./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6497de01 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 222be94abfdbb514b1917b4bfb3a2a13389b64e1e049c782003790d790f6753f --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 01:54:51,913 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 01:54:52,006 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-24 01:54:52,013 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 01:54:52,013 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 01:54:52,044 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 01:54:52,045 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 01:54:52,045 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 01:54:52,045 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 01:54:52,046 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 01:54:52,046 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 01:54:52,046 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 01:54:52,046 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 01:54:52,046 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 01:54:52,047 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 01:54:52,047 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 01:54:52,048 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 01:54:52,048 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 01:54:52,049 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 01:54:52,049 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 01:54:52,049 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 01:54:52,050 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 222be94abfdbb514b1917b4bfb3a2a13389b64e1e049c782003790d790f6753f [2024-11-24 01:54:52,382 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 01:54:52,391 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 01:54:52,394 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 01:54:52,395 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 01:54:52,396 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 01:54:52,397 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 01:54:55,453 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/b53505ad9/b4b4519c715e44d3974d4aa2e335f5de/FLAG708214ca0 [2024-11-24 01:54:55,917 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 01:54:55,918 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 01:54:55,933 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/b53505ad9/b4b4519c715e44d3974d4aa2e335f5de/FLAG708214ca0 [2024-11-24 01:54:55,953 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/b53505ad9/b4b4519c715e44d3974d4aa2e335f5de [2024-11-24 01:54:55,958 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 01:54:55,961 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 01:54:55,965 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 01:54:55,965 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 01:54:55,970 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 01:54:55,972 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 01:54:55" (1/1) ... [2024-11-24 01:54:55,973 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5395310d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:55, skipping insertion in model container [2024-11-24 01:54:55,975 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 01:54:55" (1/1) ... [2024-11-24 01:54:56,050 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 01:54:56,311 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c[1280,1293] [2024-11-24 01:54:56,611 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 01:54:56,634 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 01:54:56,647 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c[1280,1293] [2024-11-24 01:54:56,839 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 01:54:56,855 INFO L204 MainTranslator]: Completed translation [2024-11-24 01:54:56,856 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56 WrapperNode [2024-11-24 01:54:56,856 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 01:54:56,857 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 01:54:56,858 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 01:54:56,858 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 01:54:56,866 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:56,899 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,186 INFO L138 Inliner]: procedures = 17, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1976 [2024-11-24 01:54:57,186 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 01:54:57,187 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 01:54:57,189 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 01:54:57,189 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 01:54:57,201 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,202 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,258 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,440 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-24 01:54:57,440 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,441 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,544 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,555 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,587 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,609 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,624 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,689 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 01:54:57,694 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 01:54:57,694 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 01:54:57,694 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 01:54:57,695 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (1/1) ... [2024-11-24 01:54:57,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 01:54:57,728 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:54:57,745 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 01:54:57,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 01:54:57,795 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 01:54:57,796 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 01:54:57,796 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 01:54:57,796 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-24 01:54:57,796 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 01:54:57,796 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 01:54:58,204 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 01:54:58,207 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 01:55:01,574 INFO L? ?]: Removed 1091 outVars from TransFormulas that were not future-live. [2024-11-24 01:55:01,574 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 01:55:01,595 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 01:55:01,595 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-24 01:55:01,595 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 01:55:01 BoogieIcfgContainer [2024-11-24 01:55:01,595 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 01:55:01,597 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 01:55:01,598 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 01:55:01,602 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 01:55:01,602 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 01:54:55" (1/3) ... [2024-11-24 01:55:01,603 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@d917eb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 01:55:01, skipping insertion in model container [2024-11-24 01:55:01,603 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 01:54:56" (2/3) ... [2024-11-24 01:55:01,603 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@d917eb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 01:55:01, skipping insertion in model container [2024-11-24 01:55:01,603 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 01:55:01" (3/3) ... [2024-11-24 01:55:01,604 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 01:55:01,619 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 01:55:01,620 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c that has 2 procedures, 552 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-24 01:55:01,682 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 01:55:01,694 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@72c5ff5d, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 01:55:01,695 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 01:55:01,700 INFO L276 IsEmpty]: Start isEmpty. Operand has 552 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 547 states have internal predecessors, (816), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:01,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2024-11-24 01:55:01,714 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:01,715 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:01,715 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:01,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:01,720 INFO L85 PathProgramCache]: Analyzing trace with hash 105595379, now seen corresponding path program 1 times [2024-11-24 01:55:01,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:01,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535120916] [2024-11-24 01:55:01,728 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:01,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:01,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:02,311 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-24 01:55:02,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:02,315 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535120916] [2024-11-24 01:55:02,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535120916] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:55:02,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [395398313] [2024-11-24 01:55:02,317 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:02,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:55:02,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:55:02,322 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:55:02,323 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 01:55:02,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:02,868 INFO L256 TraceCheckSpWp]: Trace formula consists of 929 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-24 01:55:02,878 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:55:02,913 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-24 01:55:02,913 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 01:55:02,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [395398313] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:02,913 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 01:55:02,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-24 01:55:02,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561968394] [2024-11-24 01:55:02,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:02,920 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-24 01:55:02,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:02,946 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-24 01:55:02,946 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 01:55:02,949 INFO L87 Difference]: Start difference. First operand has 552 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 547 states have internal predecessors, (816), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:03,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:03,045 INFO L93 Difference]: Finished difference Result 999 states and 1493 transitions. [2024-11-24 01:55:03,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-24 01:55:03,047 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) Word has length 149 [2024-11-24 01:55:03,047 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:03,065 INFO L225 Difference]: With dead ends: 999 [2024-11-24 01:55:03,065 INFO L226 Difference]: Without dead ends: 549 [2024-11-24 01:55:03,074 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 150 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 01:55:03,078 INFO L435 NwaCegarLoop]: 817 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 817 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:03,079 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 817 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:55:03,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states. [2024-11-24 01:55:03,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 549. [2024-11-24 01:55:03,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 549 states, 544 states have (on average 1.4908088235294117) internal successors, (811), 544 states have internal predecessors, (811), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:03,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 817 transitions. [2024-11-24 01:55:03,162 INFO L78 Accepts]: Start accepts. Automaton has 549 states and 817 transitions. Word has length 149 [2024-11-24 01:55:03,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:03,163 INFO L471 AbstractCegarLoop]: Abstraction has 549 states and 817 transitions. [2024-11-24 01:55:03,163 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:03,164 INFO L276 IsEmpty]: Start isEmpty. Operand 549 states and 817 transitions. [2024-11-24 01:55:03,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2024-11-24 01:55:03,174 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:03,174 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:03,187 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-24 01:55:03,375 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-11-24 01:55:03,375 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:03,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:03,376 INFO L85 PathProgramCache]: Analyzing trace with hash 677396781, now seen corresponding path program 1 times [2024-11-24 01:55:03,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:03,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549246184] [2024-11-24 01:55:03,376 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:03,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:03,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:04,944 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:04,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:04,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549246184] [2024-11-24 01:55:04,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549246184] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:04,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:04,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:04,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893747936] [2024-11-24 01:55:04,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:04,946 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:04,946 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:04,951 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:04,951 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:04,952 INFO L87 Difference]: Start difference. First operand 549 states and 817 transitions. Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:05,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:05,053 INFO L93 Difference]: Finished difference Result 553 states and 821 transitions. [2024-11-24 01:55:05,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:05,053 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 149 [2024-11-24 01:55:05,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:05,056 INFO L225 Difference]: With dead ends: 553 [2024-11-24 01:55:05,058 INFO L226 Difference]: Without dead ends: 551 [2024-11-24 01:55:05,059 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:05,060 INFO L435 NwaCegarLoop]: 815 mSDtfsCounter, 0 mSDsluCounter, 1624 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2439 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:05,061 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2439 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:55:05,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2024-11-24 01:55:05,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2024-11-24 01:55:05,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 546 states have (on average 1.489010989010989) internal successors, (813), 546 states have internal predecessors, (813), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:05,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 819 transitions. [2024-11-24 01:55:05,101 INFO L78 Accepts]: Start accepts. Automaton has 551 states and 819 transitions. Word has length 149 [2024-11-24 01:55:05,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:05,104 INFO L471 AbstractCegarLoop]: Abstraction has 551 states and 819 transitions. [2024-11-24 01:55:05,104 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:05,104 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 819 transitions. [2024-11-24 01:55:05,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2024-11-24 01:55:05,110 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:05,111 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:05,111 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-24 01:55:05,112 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:05,112 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:05,116 INFO L85 PathProgramCache]: Analyzing trace with hash -473840291, now seen corresponding path program 1 times [2024-11-24 01:55:05,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:05,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [634388824] [2024-11-24 01:55:05,116 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:05,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:05,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:05,991 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:05,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:05,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [634388824] [2024-11-24 01:55:05,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [634388824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:05,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:05,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:05,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1129412909] [2024-11-24 01:55:05,994 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:05,995 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:05,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:05,996 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:05,996 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:05,996 INFO L87 Difference]: Start difference. First operand 551 states and 819 transitions. Second operand has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:06,648 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:06,648 INFO L93 Difference]: Finished difference Result 1371 states and 2041 transitions. [2024-11-24 01:55:06,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:55:06,649 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 150 [2024-11-24 01:55:06,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:06,652 INFO L225 Difference]: With dead ends: 1371 [2024-11-24 01:55:06,652 INFO L226 Difference]: Without dead ends: 551 [2024-11-24 01:55:06,654 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2024-11-24 01:55:06,655 INFO L435 NwaCegarLoop]: 861 mSDtfsCounter, 1618 mSDsluCounter, 1490 mSDsCounter, 0 mSdLazyCounter, 302 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1618 SdHoareTripleChecker+Valid, 2351 SdHoareTripleChecker+Invalid, 339 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 302 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:06,655 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1618 Valid, 2351 Invalid, 339 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 302 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 01:55:06,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2024-11-24 01:55:06,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2024-11-24 01:55:06,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 546 states have (on average 1.4871794871794872) internal successors, (812), 546 states have internal predecessors, (812), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:06,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 818 transitions. [2024-11-24 01:55:06,671 INFO L78 Accepts]: Start accepts. Automaton has 551 states and 818 transitions. Word has length 150 [2024-11-24 01:55:06,672 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:06,672 INFO L471 AbstractCegarLoop]: Abstraction has 551 states and 818 transitions. [2024-11-24 01:55:06,672 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:06,672 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 818 transitions. [2024-11-24 01:55:06,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2024-11-24 01:55:06,674 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:06,674 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:06,675 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-24 01:55:06,675 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:06,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:06,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1290588625, now seen corresponding path program 1 times [2024-11-24 01:55:06,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:06,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672402083] [2024-11-24 01:55:06,676 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:06,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:06,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:07,254 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:07,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:07,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672402083] [2024-11-24 01:55:07,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672402083] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:07,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:07,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:07,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800796083] [2024-11-24 01:55:07,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:07,256 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:07,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:07,257 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:07,257 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:07,257 INFO L87 Difference]: Start difference. First operand 551 states and 818 transitions. Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:07,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:07,312 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2024-11-24 01:55:07,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:07,313 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 151 [2024-11-24 01:55:07,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:07,317 INFO L225 Difference]: With dead ends: 1002 [2024-11-24 01:55:07,317 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:07,318 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:07,319 INFO L435 NwaCegarLoop]: 814 mSDtfsCounter, 0 mSDsluCounter, 1618 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2432 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:07,319 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2432 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:55:07,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:07,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:07,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4854014598540146) internal successors, (814), 548 states have internal predecessors, (814), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:07,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 820 transitions. [2024-11-24 01:55:07,336 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 820 transitions. Word has length 151 [2024-11-24 01:55:07,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:07,337 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 820 transitions. [2024-11-24 01:55:07,337 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:07,337 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 820 transitions. [2024-11-24 01:55:07,339 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2024-11-24 01:55:07,339 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:07,340 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:07,340 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-24 01:55:07,340 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:07,340 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:07,341 INFO L85 PathProgramCache]: Analyzing trace with hash 1843460468, now seen corresponding path program 1 times [2024-11-24 01:55:07,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:07,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280950197] [2024-11-24 01:55:07,341 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:07,341 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:07,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:08,083 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:08,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:08,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280950197] [2024-11-24 01:55:08,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280950197] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:08,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:08,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:08,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336909591] [2024-11-24 01:55:08,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:08,088 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:08,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:08,088 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:08,088 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:08,089 INFO L87 Difference]: Start difference. First operand 553 states and 820 transitions. Second operand has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:08,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:08,356 INFO L93 Difference]: Finished difference Result 1004 states and 1488 transitions. [2024-11-24 01:55:08,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:08,357 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 152 [2024-11-24 01:55:08,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:08,359 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:08,359 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:08,362 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:08,363 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 694 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 164 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 694 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 164 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:08,365 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [694 Valid, 1470 Invalid, 164 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 164 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:08,369 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:08,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:08,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4835766423357664) internal successors, (813), 548 states have internal predecessors, (813), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:08,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 819 transitions. [2024-11-24 01:55:08,401 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 819 transitions. Word has length 152 [2024-11-24 01:55:08,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:08,402 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 819 transitions. [2024-11-24 01:55:08,402 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:08,402 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 819 transitions. [2024-11-24 01:55:08,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2024-11-24 01:55:08,404 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:08,405 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:08,405 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-24 01:55:08,405 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:08,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:08,406 INFO L85 PathProgramCache]: Analyzing trace with hash -954896960, now seen corresponding path program 1 times [2024-11-24 01:55:08,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:08,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1557911638] [2024-11-24 01:55:08,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:08,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:08,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:08,907 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:08,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:08,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1557911638] [2024-11-24 01:55:08,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1557911638] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:08,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:08,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:08,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [525629341] [2024-11-24 01:55:08,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:08,910 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:08,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:08,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:08,914 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:08,914 INFO L87 Difference]: Start difference. First operand 553 states and 819 transitions. Second operand has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:09,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:09,142 INFO L93 Difference]: Finished difference Result 1010 states and 1494 transitions. [2024-11-24 01:55:09,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 01:55:09,143 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 153 [2024-11-24 01:55:09,143 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:09,145 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:09,146 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:09,146 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:55:09,147 INFO L435 NwaCegarLoop]: 806 mSDtfsCounter, 705 mSDsluCounter, 1544 mSDsCounter, 0 mSdLazyCounter, 98 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 705 SdHoareTripleChecker+Valid, 2350 SdHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 98 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:09,147 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [705 Valid, 2350 Invalid, 100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 98 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:09,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:09,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:09,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4817518248175183) internal successors, (812), 548 states have internal predecessors, (812), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:09,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 818 transitions. [2024-11-24 01:55:09,165 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 818 transitions. Word has length 153 [2024-11-24 01:55:09,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:09,165 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 818 transitions. [2024-11-24 01:55:09,166 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:09,166 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 818 transitions. [2024-11-24 01:55:09,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2024-11-24 01:55:09,167 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:09,168 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:09,168 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-24 01:55:09,168 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:09,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:09,169 INFO L85 PathProgramCache]: Analyzing trace with hash 690807295, now seen corresponding path program 1 times [2024-11-24 01:55:09,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:09,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792045382] [2024-11-24 01:55:09,169 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:09,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:09,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:09,634 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:09,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:09,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792045382] [2024-11-24 01:55:09,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792045382] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:09,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:09,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:09,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1365739866] [2024-11-24 01:55:09,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:09,635 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:09,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:09,636 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:09,636 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:09,636 INFO L87 Difference]: Start difference. First operand 553 states and 818 transitions. Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:09,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:09,884 INFO L93 Difference]: Finished difference Result 1004 states and 1484 transitions. [2024-11-24 01:55:09,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:09,885 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 154 [2024-11-24 01:55:09,885 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:09,887 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:09,888 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:09,888 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:09,889 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 802 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 160 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 805 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 161 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 160 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:09,889 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [805 Valid, 1477 Invalid, 161 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 160 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:09,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:09,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:09,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.47992700729927) internal successors, (811), 548 states have internal predecessors, (811), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:09,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 817 transitions. [2024-11-24 01:55:09,910 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 817 transitions. Word has length 154 [2024-11-24 01:55:09,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:09,911 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 817 transitions. [2024-11-24 01:55:09,911 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:09,911 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 817 transitions. [2024-11-24 01:55:09,913 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2024-11-24 01:55:09,913 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:09,913 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:09,913 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-24 01:55:09,914 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:09,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:09,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1444639353, now seen corresponding path program 1 times [2024-11-24 01:55:09,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:09,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [855621360] [2024-11-24 01:55:09,914 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:09,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:10,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:10,410 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:10,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:10,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [855621360] [2024-11-24 01:55:10,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [855621360] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:10,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:10,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:10,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131357770] [2024-11-24 01:55:10,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:10,411 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:10,411 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:10,412 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:10,412 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:10,412 INFO L87 Difference]: Start difference. First operand 553 states and 817 transitions. Second operand has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:10,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:10,659 INFO L93 Difference]: Finished difference Result 1004 states and 1482 transitions. [2024-11-24 01:55:10,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:10,660 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 155 [2024-11-24 01:55:10,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:10,662 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:10,663 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:10,664 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:10,664 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 798 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 158 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 801 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 158 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:10,665 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [801 Valid, 1477 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 158 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:10,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:10,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:10,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4781021897810218) internal successors, (810), 548 states have internal predecessors, (810), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:10,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 816 transitions. [2024-11-24 01:55:10,683 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 816 transitions. Word has length 155 [2024-11-24 01:55:10,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:10,685 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 816 transitions. [2024-11-24 01:55:10,686 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:10,686 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 816 transitions. [2024-11-24 01:55:10,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2024-11-24 01:55:10,691 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:10,691 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:10,691 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-24 01:55:10,691 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:10,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:10,692 INFO L85 PathProgramCache]: Analyzing trace with hash 457554086, now seen corresponding path program 1 times [2024-11-24 01:55:10,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:10,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411177659] [2024-11-24 01:55:10,692 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:10,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:10,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:11,167 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:11,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:11,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411177659] [2024-11-24 01:55:11,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411177659] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:11,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:11,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:11,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979083780] [2024-11-24 01:55:11,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:11,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:11,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:11,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:11,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:11,170 INFO L87 Difference]: Start difference. First operand 553 states and 816 transitions. Second operand has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:11,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:11,409 INFO L93 Difference]: Finished difference Result 1004 states and 1480 transitions. [2024-11-24 01:55:11,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:11,410 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 156 [2024-11-24 01:55:11,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:11,414 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:11,415 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:11,416 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:11,418 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 791 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 794 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:11,418 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [794 Valid, 1477 Invalid, 157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 156 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:11,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:11,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:11,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4762773722627738) internal successors, (809), 548 states have internal predecessors, (809), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:11,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 815 transitions. [2024-11-24 01:55:11,438 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 815 transitions. Word has length 156 [2024-11-24 01:55:11,438 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:11,438 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 815 transitions. [2024-11-24 01:55:11,438 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:11,439 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 815 transitions. [2024-11-24 01:55:11,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2024-11-24 01:55:11,442 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:11,442 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:11,442 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-24 01:55:11,443 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:11,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:11,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1750596921, now seen corresponding path program 1 times [2024-11-24 01:55:11,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:11,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666055148] [2024-11-24 01:55:11,444 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:11,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:11,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:12,098 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:12,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:12,099 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666055148] [2024-11-24 01:55:12,099 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666055148] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:12,099 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:12,099 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:12,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746112943] [2024-11-24 01:55:12,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:12,099 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:12,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:12,100 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:12,100 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:12,101 INFO L87 Difference]: Start difference. First operand 553 states and 815 transitions. Second operand has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:12,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:12,353 INFO L93 Difference]: Finished difference Result 1004 states and 1478 transitions. [2024-11-24 01:55:12,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:12,354 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 157 [2024-11-24 01:55:12,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:12,356 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:12,357 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:12,358 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:12,358 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 1465 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1468 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:12,359 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1468 Valid, 1470 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:12,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:12,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:12,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4744525547445255) internal successors, (808), 548 states have internal predecessors, (808), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:12,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 814 transitions. [2024-11-24 01:55:12,377 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 814 transitions. Word has length 157 [2024-11-24 01:55:12,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:12,378 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 814 transitions. [2024-11-24 01:55:12,378 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:12,378 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 814 transitions. [2024-11-24 01:55:12,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2024-11-24 01:55:12,380 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:12,380 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:12,381 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-24 01:55:12,381 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:12,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:12,381 INFO L85 PathProgramCache]: Analyzing trace with hash -273443585, now seen corresponding path program 1 times [2024-11-24 01:55:12,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:12,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871504773] [2024-11-24 01:55:12,382 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:12,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:12,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:12,801 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:12,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:12,802 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871504773] [2024-11-24 01:55:12,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [871504773] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:12,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:12,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:12,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812418001] [2024-11-24 01:55:12,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:12,803 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:12,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:12,803 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:12,804 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:12,804 INFO L87 Difference]: Start difference. First operand 553 states and 814 transitions. Second operand has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:13,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:13,028 INFO L93 Difference]: Finished difference Result 1004 states and 1476 transitions. [2024-11-24 01:55:13,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:13,029 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 158 [2024-11-24 01:55:13,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:13,032 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:13,032 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:13,033 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:13,033 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 1457 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 152 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1460 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 153 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:13,034 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1460 Valid, 1470 Invalid, 153 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 152 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:13,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:13,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:13,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4726277372262773) internal successors, (807), 548 states have internal predecessors, (807), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:13,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 813 transitions. [2024-11-24 01:55:13,050 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 813 transitions. Word has length 158 [2024-11-24 01:55:13,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:13,050 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 813 transitions. [2024-11-24 01:55:13,050 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:13,051 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 813 transitions. [2024-11-24 01:55:13,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2024-11-24 01:55:13,052 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:13,053 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:13,053 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-24 01:55:13,053 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:13,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:13,053 INFO L85 PathProgramCache]: Analyzing trace with hash -808870848, now seen corresponding path program 1 times [2024-11-24 01:55:13,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:13,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486694216] [2024-11-24 01:55:13,054 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:13,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:13,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:13,527 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:13,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:13,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486694216] [2024-11-24 01:55:13,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486694216] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:13,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:13,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:13,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845747488] [2024-11-24 01:55:13,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:13,529 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:13,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:13,529 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:13,529 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:13,530 INFO L87 Difference]: Start difference. First operand 553 states and 813 transitions. Second operand has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:13,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:13,751 INFO L93 Difference]: Finished difference Result 1004 states and 1474 transitions. [2024-11-24 01:55:13,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:13,752 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 159 [2024-11-24 01:55:13,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:13,755 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:13,755 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:13,756 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:13,756 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 779 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 150 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 782 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 151 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 150 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:13,756 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [782 Valid, 1477 Invalid, 151 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 150 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:13,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:13,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:13,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4708029197080292) internal successors, (806), 548 states have internal predecessors, (806), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:13,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 812 transitions. [2024-11-24 01:55:13,773 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 812 transitions. Word has length 159 [2024-11-24 01:55:13,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:13,773 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 812 transitions. [2024-11-24 01:55:13,774 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:13,774 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 812 transitions. [2024-11-24 01:55:13,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2024-11-24 01:55:13,775 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:13,776 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:13,776 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-11-24 01:55:13,776 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:13,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:13,777 INFO L85 PathProgramCache]: Analyzing trace with hash -476571176, now seen corresponding path program 1 times [2024-11-24 01:55:13,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:13,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951075398] [2024-11-24 01:55:13,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:13,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:13,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:14,371 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:14,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:14,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1951075398] [2024-11-24 01:55:14,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1951075398] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:14,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:14,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:14,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [768498195] [2024-11-24 01:55:14,372 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:14,372 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:14,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:14,373 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:14,373 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:14,374 INFO L87 Difference]: Start difference. First operand 553 states and 812 transitions. Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:14,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:14,532 INFO L93 Difference]: Finished difference Result 1004 states and 1472 transitions. [2024-11-24 01:55:14,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:14,533 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 160 [2024-11-24 01:55:14,533 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:14,535 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:14,536 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:14,537 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:14,537 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 696 mSDsluCounter, 768 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 696 SdHoareTripleChecker+Valid, 1534 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:14,538 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [696 Valid, 1534 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:14,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:14,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:14,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.468978102189781) internal successors, (805), 548 states have internal predecessors, (805), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:14,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 811 transitions. [2024-11-24 01:55:14,556 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 811 transitions. Word has length 160 [2024-11-24 01:55:14,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:14,556 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 811 transitions. [2024-11-24 01:55:14,556 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:14,557 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 811 transitions. [2024-11-24 01:55:14,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2024-11-24 01:55:14,559 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:14,559 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:14,559 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-24 01:55:14,559 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:14,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:14,560 INFO L85 PathProgramCache]: Analyzing trace with hash 2018153223, now seen corresponding path program 1 times [2024-11-24 01:55:14,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:14,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1832906478] [2024-11-24 01:55:14,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:14,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:14,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:14,988 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:14,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:14,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1832906478] [2024-11-24 01:55:14,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1832906478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:14,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:14,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:14,989 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408579579] [2024-11-24 01:55:14,989 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:14,991 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:14,991 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:14,991 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:14,991 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:14,992 INFO L87 Difference]: Start difference. First operand 553 states and 811 transitions. Second operand has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:15,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:15,135 INFO L93 Difference]: Finished difference Result 1008 states and 1475 transitions. [2024-11-24 01:55:15,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 01:55:15,136 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 161 [2024-11-24 01:55:15,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:15,138 INFO L225 Difference]: With dead ends: 1008 [2024-11-24 01:55:15,139 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:15,139 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:55:15,140 INFO L435 NwaCegarLoop]: 799 mSDtfsCounter, 703 mSDsluCounter, 1569 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 703 SdHoareTripleChecker+Valid, 2368 SdHoareTripleChecker+Invalid, 57 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:15,140 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [703 Valid, 2368 Invalid, 57 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:15,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:15,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:15,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.467153284671533) internal successors, (804), 548 states have internal predecessors, (804), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:15,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 810 transitions. [2024-11-24 01:55:15,158 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 810 transitions. Word has length 161 [2024-11-24 01:55:15,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:15,158 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 810 transitions. [2024-11-24 01:55:15,159 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:15,159 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 810 transitions. [2024-11-24 01:55:15,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2024-11-24 01:55:15,161 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:15,161 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:15,161 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-24 01:55:15,161 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:15,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:15,162 INFO L85 PathProgramCache]: Analyzing trace with hash -968614358, now seen corresponding path program 1 times [2024-11-24 01:55:15,162 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:15,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884461620] [2024-11-24 01:55:15,162 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:15,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:15,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:15,589 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:15,589 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:15,589 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884461620] [2024-11-24 01:55:15,589 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884461620] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:15,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:15,590 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:15,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700177267] [2024-11-24 01:55:15,590 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:15,590 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:15,591 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:15,591 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:15,591 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:15,592 INFO L87 Difference]: Start difference. First operand 553 states and 810 transitions. Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:15,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:15,743 INFO L93 Difference]: Finished difference Result 1004 states and 1468 transitions. [2024-11-24 01:55:15,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:15,744 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 162 [2024-11-24 01:55:15,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:15,747 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:15,747 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:15,748 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:15,749 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 794 mSDsluCounter, 775 mSDsCounter, 0 mSdLazyCounter, 80 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 797 SdHoareTripleChecker+Valid, 1541 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 80 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:15,749 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [797 Valid, 1541 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 80 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:15,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:15,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:15,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4653284671532847) internal successors, (803), 548 states have internal predecessors, (803), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:15,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 809 transitions. [2024-11-24 01:55:15,768 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 809 transitions. Word has length 162 [2024-11-24 01:55:15,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:15,768 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 809 transitions. [2024-11-24 01:55:15,769 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:15,769 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 809 transitions. [2024-11-24 01:55:15,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 164 [2024-11-24 01:55:15,771 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:15,771 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:15,771 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-24 01:55:15,771 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:15,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:15,772 INFO L85 PathProgramCache]: Analyzing trace with hash 311812430, now seen corresponding path program 1 times [2024-11-24 01:55:15,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:15,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [399122156] [2024-11-24 01:55:15,772 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:15,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:15,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:16,199 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:16,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:16,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [399122156] [2024-11-24 01:55:16,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [399122156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:16,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:16,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:16,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262814090] [2024-11-24 01:55:16,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:16,201 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:16,201 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:16,201 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:16,201 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:16,202 INFO L87 Difference]: Start difference. First operand 553 states and 809 transitions. Second operand has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:16,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:16,360 INFO L93 Difference]: Finished difference Result 1004 states and 1466 transitions. [2024-11-24 01:55:16,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:16,360 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 163 [2024-11-24 01:55:16,361 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:16,363 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:16,365 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:16,365 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:16,367 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 787 mSDsluCounter, 775 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 790 SdHoareTripleChecker+Valid, 1541 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:16,367 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [790 Valid, 1541 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:16,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:16,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:16,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4635036496350364) internal successors, (802), 548 states have internal predecessors, (802), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:16,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 808 transitions. [2024-11-24 01:55:16,386 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 808 transitions. Word has length 163 [2024-11-24 01:55:16,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:16,386 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 808 transitions. [2024-11-24 01:55:16,387 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:16,387 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 808 transitions. [2024-11-24 01:55:16,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2024-11-24 01:55:16,389 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:16,389 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:16,389 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-11-24 01:55:16,390 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:16,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:16,390 INFO L85 PathProgramCache]: Analyzing trace with hash -1761805302, now seen corresponding path program 1 times [2024-11-24 01:55:16,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:16,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728408670] [2024-11-24 01:55:16,391 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:16,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:16,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:16,960 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:16,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:16,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728408670] [2024-11-24 01:55:16,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728408670] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:16,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:16,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:16,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [616792187] [2024-11-24 01:55:16,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:16,962 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:16,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:16,962 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:16,963 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:16,963 INFO L87 Difference]: Start difference. First operand 553 states and 808 transitions. Second operand has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:17,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:17,055 INFO L93 Difference]: Finished difference Result 1004 states and 1464 transitions. [2024-11-24 01:55:17,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:17,056 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 164 [2024-11-24 01:55:17,056 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:17,058 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:17,058 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:17,059 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:17,060 INFO L435 NwaCegarLoop]: 782 mSDtfsCounter, 699 mSDsluCounter, 784 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 699 SdHoareTripleChecker+Valid, 1566 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:17,060 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [699 Valid, 1566 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:17,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:17,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:17,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4598540145985401) internal successors, (800), 548 states have internal predecessors, (800), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:17,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 806 transitions. [2024-11-24 01:55:17,079 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 806 transitions. Word has length 164 [2024-11-24 01:55:17,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:17,079 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 806 transitions. [2024-11-24 01:55:17,079 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:17,079 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 806 transitions. [2024-11-24 01:55:17,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2024-11-24 01:55:17,082 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:17,082 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:17,082 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-11-24 01:55:17,083 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:17,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:17,083 INFO L85 PathProgramCache]: Analyzing trace with hash -540920697, now seen corresponding path program 1 times [2024-11-24 01:55:17,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:17,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1496402889] [2024-11-24 01:55:17,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:17,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:17,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:17,609 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:17,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:17,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1496402889] [2024-11-24 01:55:17,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1496402889] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:17,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:17,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:17,610 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443773285] [2024-11-24 01:55:17,610 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:17,611 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:17,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:17,611 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:17,611 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:17,611 INFO L87 Difference]: Start difference. First operand 553 states and 806 transitions. Second operand has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:17,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:17,722 INFO L93 Difference]: Finished difference Result 1004 states and 1460 transitions. [2024-11-24 01:55:17,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:17,722 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 166 [2024-11-24 01:55:17,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:17,725 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:17,725 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:17,726 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:17,727 INFO L435 NwaCegarLoop]: 782 mSDtfsCounter, 1481 mSDsluCounter, 784 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1484 SdHoareTripleChecker+Valid, 1566 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:17,727 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1484 Valid, 1566 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:17,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:17,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:17,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4580291970802919) internal successors, (799), 548 states have internal predecessors, (799), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:17,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 805 transitions. [2024-11-24 01:55:17,751 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 805 transitions. Word has length 166 [2024-11-24 01:55:17,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:17,751 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 805 transitions. [2024-11-24 01:55:17,752 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:17,752 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 805 transitions. [2024-11-24 01:55:17,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2024-11-24 01:55:17,754 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:17,754 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:17,755 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-11-24 01:55:17,755 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:17,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:17,755 INFO L85 PathProgramCache]: Analyzing trace with hash 430318257, now seen corresponding path program 1 times [2024-11-24 01:55:17,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:17,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [784726702] [2024-11-24 01:55:17,756 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:17,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:17,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:18,483 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:18,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:18,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [784726702] [2024-11-24 01:55:18,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [784726702] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:18,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:18,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:18,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [746870677] [2024-11-24 01:55:18,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:18,484 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:18,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:18,486 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:18,486 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:18,486 INFO L87 Difference]: Start difference. First operand 553 states and 805 transitions. Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:18,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:18,585 INFO L93 Difference]: Finished difference Result 1004 states and 1458 transitions. [2024-11-24 01:55:18,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:18,586 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 167 [2024-11-24 01:55:18,586 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:18,589 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:18,589 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:18,590 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:18,590 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 734 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 736 SdHoareTripleChecker+Valid, 1572 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:18,591 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [736 Valid, 1572 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:18,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:18,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:18,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4562043795620438) internal successors, (798), 548 states have internal predecessors, (798), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:18,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 804 transitions. [2024-11-24 01:55:18,613 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 804 transitions. Word has length 167 [2024-11-24 01:55:18,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:18,614 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 804 transitions. [2024-11-24 01:55:18,614 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:18,614 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 804 transitions. [2024-11-24 01:55:18,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2024-11-24 01:55:18,616 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:18,617 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:18,617 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-11-24 01:55:18,617 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:18,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:18,618 INFO L85 PathProgramCache]: Analyzing trace with hash -274414691, now seen corresponding path program 1 times [2024-11-24 01:55:18,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:18,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093192060] [2024-11-24 01:55:18,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:18,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:18,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:19,290 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:19,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:19,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093192060] [2024-11-24 01:55:19,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093192060] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:19,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:19,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:19,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806115986] [2024-11-24 01:55:19,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:19,293 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:19,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:19,293 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:19,294 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:19,294 INFO L87 Difference]: Start difference. First operand 553 states and 804 transitions. Second operand has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:19,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:19,396 INFO L93 Difference]: Finished difference Result 1004 states and 1456 transitions. [2024-11-24 01:55:19,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:19,397 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 168 [2024-11-24 01:55:19,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:19,400 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:19,400 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:19,401 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:19,401 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 732 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 734 SdHoareTripleChecker+Valid, 1572 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:19,402 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [734 Valid, 1572 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:19,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:19,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:19,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4543795620437956) internal successors, (797), 548 states have internal predecessors, (797), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:19,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 803 transitions. [2024-11-24 01:55:19,421 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 803 transitions. Word has length 168 [2024-11-24 01:55:19,425 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:19,425 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 803 transitions. [2024-11-24 01:55:19,426 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 01:55:19,426 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 803 transitions. [2024-11-24 01:55:19,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2024-11-24 01:55:19,428 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:19,428 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:19,428 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-11-24 01:55:19,429 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:19,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:19,429 INFO L85 PathProgramCache]: Analyzing trace with hash 848604686, now seen corresponding path program 1 times [2024-11-24 01:55:19,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:19,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487449721] [2024-11-24 01:55:19,429 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:19,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:19,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:20,134 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:20,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:20,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487449721] [2024-11-24 01:55:20,136 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487449721] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:20,136 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:20,136 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:20,136 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208656400] [2024-11-24 01:55:20,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:20,137 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:20,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:20,139 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:20,139 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:20,140 INFO L87 Difference]: Start difference. First operand 553 states and 803 transitions. Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 4 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:20,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:20,310 INFO L93 Difference]: Finished difference Result 1004 states and 1454 transitions. [2024-11-24 01:55:20,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:20,311 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 39.25) internal successors, (157), 4 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 169 [2024-11-24 01:55:20,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:20,314 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:20,314 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:20,315 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:20,316 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 685 mSDsluCounter, 763 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 685 SdHoareTripleChecker+Valid, 1524 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:20,317 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [685 Valid, 1524 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 76 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:20,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:20,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:20,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4525547445255473) internal successors, (796), 548 states have internal predecessors, (796), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:20,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 802 transitions. [2024-11-24 01:55:20,337 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 802 transitions. Word has length 169 [2024-11-24 01:55:20,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:20,337 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 802 transitions. [2024-11-24 01:55:20,338 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 39.25) internal successors, (157), 4 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:20,338 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 802 transitions. [2024-11-24 01:55:20,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2024-11-24 01:55:20,341 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:20,341 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:20,341 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-11-24 01:55:20,342 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:20,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:20,343 INFO L85 PathProgramCache]: Analyzing trace with hash -781157562, now seen corresponding path program 1 times [2024-11-24 01:55:20,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:20,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186004600] [2024-11-24 01:55:20,343 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:20,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:20,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:21,016 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:21,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:21,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186004600] [2024-11-24 01:55:21,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186004600] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:21,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:21,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:21,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369130279] [2024-11-24 01:55:21,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:21,019 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:21,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:21,020 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:21,020 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:21,021 INFO L87 Difference]: Start difference. First operand 553 states and 802 transitions. Second operand has 5 states, 5 states have (on average 31.6) internal successors, (158), 5 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:21,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:21,217 INFO L93 Difference]: Finished difference Result 1004 states and 1452 transitions. [2024-11-24 01:55:21,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:21,218 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 31.6) internal successors, (158), 5 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 170 [2024-11-24 01:55:21,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:21,220 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:21,221 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:21,222 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:21,223 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 683 mSDsluCounter, 770 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 683 SdHoareTripleChecker+Valid, 1531 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:21,224 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [683 Valid, 1531 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:21,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:21,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:21,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4507299270072993) internal successors, (795), 548 states have internal predecessors, (795), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:21,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 801 transitions. [2024-11-24 01:55:21,244 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 801 transitions. Word has length 170 [2024-11-24 01:55:21,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:21,245 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 801 transitions. [2024-11-24 01:55:21,245 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 31.6) internal successors, (158), 5 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:21,245 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 801 transitions. [2024-11-24 01:55:21,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 172 [2024-11-24 01:55:21,247 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:21,248 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:21,248 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-11-24 01:55:21,248 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:21,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:21,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1923885711, now seen corresponding path program 1 times [2024-11-24 01:55:21,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:21,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277411637] [2024-11-24 01:55:21,249 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:21,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:21,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:21,914 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:21,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:21,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277411637] [2024-11-24 01:55:21,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277411637] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:21,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:21,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:21,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842955345] [2024-11-24 01:55:21,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:21,916 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:21,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:21,916 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:21,917 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:21,917 INFO L87 Difference]: Start difference. First operand 553 states and 801 transitions. Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:22,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:22,091 INFO L93 Difference]: Finished difference Result 1004 states and 1450 transitions. [2024-11-24 01:55:22,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:22,091 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 171 [2024-11-24 01:55:22,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:22,094 INFO L225 Difference]: With dead ends: 1004 [2024-11-24 01:55:22,094 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:22,095 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:22,095 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 682 mSDsluCounter, 770 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 682 SdHoareTripleChecker+Valid, 1531 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:22,096 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [682 Valid, 1531 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:22,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:22,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:22,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.448905109489051) internal successors, (794), 548 states have internal predecessors, (794), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:22,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 800 transitions. [2024-11-24 01:55:22,114 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 800 transitions. Word has length 171 [2024-11-24 01:55:22,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:22,114 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 800 transitions. [2024-11-24 01:55:22,115 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:22,115 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 800 transitions. [2024-11-24 01:55:22,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2024-11-24 01:55:22,117 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:22,117 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:22,117 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-11-24 01:55:22,117 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:22,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:22,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1902156155, now seen corresponding path program 1 times [2024-11-24 01:55:22,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:22,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950522277] [2024-11-24 01:55:22,118 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:22,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:22,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:22,703 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:22,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:22,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950522277] [2024-11-24 01:55:22,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950522277] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:22,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:22,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:22,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586315276] [2024-11-24 01:55:22,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:22,705 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:22,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:22,705 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:22,706 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:22,706 INFO L87 Difference]: Start difference. First operand 553 states and 800 transitions. Second operand has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:23,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:23,050 INFO L93 Difference]: Finished difference Result 1006 states and 1450 transitions. [2024-11-24 01:55:23,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:23,051 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 172 [2024-11-24 01:55:23,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:23,054 INFO L225 Difference]: With dead ends: 1006 [2024-11-24 01:55:23,054 INFO L226 Difference]: Without dead ends: 553 [2024-11-24 01:55:23,055 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:23,056 INFO L435 NwaCegarLoop]: 791 mSDtfsCounter, 2 mSDsluCounter, 1392 mSDsCounter, 0 mSdLazyCounter, 201 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 2183 SdHoareTripleChecker+Invalid, 201 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 201 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:23,057 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 2183 Invalid, 201 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 201 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 01:55:23,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-11-24 01:55:23,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-11-24 01:55:23,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.447080291970803) internal successors, (793), 548 states have internal predecessors, (793), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:23,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 799 transitions. [2024-11-24 01:55:23,078 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 799 transitions. Word has length 172 [2024-11-24 01:55:23,078 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:23,078 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 799 transitions. [2024-11-24 01:55:23,079 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:23,079 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 799 transitions. [2024-11-24 01:55:23,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2024-11-24 01:55:23,081 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:23,081 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:23,081 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2024-11-24 01:55:23,082 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:23,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:23,082 INFO L85 PathProgramCache]: Analyzing trace with hash -63304310, now seen corresponding path program 1 times [2024-11-24 01:55:23,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:23,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162859643] [2024-11-24 01:55:23,083 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:23,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:23,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:24,337 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:24,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:24,338 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162859643] [2024-11-24 01:55:24,338 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162859643] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:24,338 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:24,338 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:24,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174881113] [2024-11-24 01:55:24,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:24,339 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:24,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:24,340 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:24,340 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:24,341 INFO L87 Difference]: Start difference. First operand 553 states and 799 transitions. Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:24,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:24,942 INFO L93 Difference]: Finished difference Result 1008 states and 1451 transitions. [2024-11-24 01:55:24,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 01:55:24,943 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 173 [2024-11-24 01:55:24,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:24,946 INFO L225 Difference]: With dead ends: 1008 [2024-11-24 01:55:24,946 INFO L226 Difference]: Without dead ends: 557 [2024-11-24 01:55:24,947 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:24,947 INFO L435 NwaCegarLoop]: 606 mSDtfsCounter, 695 mSDsluCounter, 1205 mSDsCounter, 0 mSdLazyCounter, 580 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 695 SdHoareTripleChecker+Valid, 1811 SdHoareTripleChecker+Invalid, 580 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 580 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:24,947 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [695 Valid, 1811 Invalid, 580 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 580 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 01:55:24,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2024-11-24 01:55:24,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 556. [2024-11-24 01:55:24,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4446460980036298) internal successors, (796), 551 states have internal predecessors, (796), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:24,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 802 transitions. [2024-11-24 01:55:24,977 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 802 transitions. Word has length 173 [2024-11-24 01:55:24,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:24,977 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 802 transitions. [2024-11-24 01:55:24,978 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:24,978 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 802 transitions. [2024-11-24 01:55:24,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2024-11-24 01:55:24,980 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:24,980 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:24,981 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2024-11-24 01:55:24,981 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:24,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:24,981 INFO L85 PathProgramCache]: Analyzing trace with hash 480433128, now seen corresponding path program 1 times [2024-11-24 01:55:24,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:24,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254764881] [2024-11-24 01:55:24,982 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:24,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:25,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:25,595 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:25,596 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:25,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254764881] [2024-11-24 01:55:25,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254764881] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:25,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:25,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:25,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375346597] [2024-11-24 01:55:25,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:25,597 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:25,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:25,598 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:25,598 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:25,599 INFO L87 Difference]: Start difference. First operand 556 states and 802 transitions. Second operand has 4 states, 4 states have (on average 40.5) internal successors, (162), 4 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:25,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:25,867 INFO L93 Difference]: Finished difference Result 1010 states and 1452 transitions. [2024-11-24 01:55:25,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:25,867 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 40.5) internal successors, (162), 4 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 174 [2024-11-24 01:55:25,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:25,870 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:25,870 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:25,872 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:25,873 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 664 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 148 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 664 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 148 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 148 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:25,874 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [664 Valid, 1444 Invalid, 148 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 148 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:25,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:25,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:25,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.442831215970962) internal successors, (795), 551 states have internal predecessors, (795), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:25,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 801 transitions. [2024-11-24 01:55:25,901 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 801 transitions. Word has length 174 [2024-11-24 01:55:25,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:25,901 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 801 transitions. [2024-11-24 01:55:25,902 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 40.5) internal successors, (162), 4 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:25,902 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 801 transitions. [2024-11-24 01:55:25,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2024-11-24 01:55:25,905 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:25,905 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:25,905 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2024-11-24 01:55:25,907 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:25,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:25,908 INFO L85 PathProgramCache]: Analyzing trace with hash -13174804, now seen corresponding path program 1 times [2024-11-24 01:55:25,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:25,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144413123] [2024-11-24 01:55:25,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:25,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:26,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:26,554 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:26,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:26,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144413123] [2024-11-24 01:55:26,555 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144413123] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:26,555 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:26,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:26,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876056048] [2024-11-24 01:55:26,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:26,556 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:26,556 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:26,557 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:26,557 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:26,558 INFO L87 Difference]: Start difference. First operand 556 states and 801 transitions. Second operand has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:26,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:26,820 INFO L93 Difference]: Finished difference Result 1010 states and 1450 transitions. [2024-11-24 01:55:26,821 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:26,821 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 175 [2024-11-24 01:55:26,822 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:26,824 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:26,824 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:26,825 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:26,825 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 662 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 146 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 662 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 146 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 146 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:26,826 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [662 Valid, 1451 Invalid, 146 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 146 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:26,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:26,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:26,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.441016333938294) internal successors, (794), 551 states have internal predecessors, (794), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:26,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 800 transitions. [2024-11-24 01:55:26,850 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 800 transitions. Word has length 175 [2024-11-24 01:55:26,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:26,851 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 800 transitions. [2024-11-24 01:55:26,851 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:26,851 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 800 transitions. [2024-11-24 01:55:26,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2024-11-24 01:55:26,853 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:26,853 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:26,853 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2024-11-24 01:55:26,854 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:26,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:26,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1816091799, now seen corresponding path program 1 times [2024-11-24 01:55:26,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:26,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735885717] [2024-11-24 01:55:26,855 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:26,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:27,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:27,524 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:27,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:27,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [735885717] [2024-11-24 01:55:27,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [735885717] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:27,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:27,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:27,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072508683] [2024-11-24 01:55:27,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:27,526 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:27,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:27,526 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:27,526 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:27,527 INFO L87 Difference]: Start difference. First operand 556 states and 800 transitions. Second operand has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:27,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:27,790 INFO L93 Difference]: Finished difference Result 1010 states and 1448 transitions. [2024-11-24 01:55:27,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:27,792 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 176 [2024-11-24 01:55:27,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:27,795 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:27,795 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:27,796 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:27,798 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 661 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 144 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 661 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 144 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 144 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:27,798 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [661 Valid, 1451 Invalid, 144 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 144 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:27,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:27,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:27,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4392014519056262) internal successors, (793), 551 states have internal predecessors, (793), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:27,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 799 transitions. [2024-11-24 01:55:27,818 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 799 transitions. Word has length 176 [2024-11-24 01:55:27,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:27,819 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 799 transitions. [2024-11-24 01:55:27,819 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:27,819 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 799 transitions. [2024-11-24 01:55:27,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2024-11-24 01:55:27,821 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:27,821 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:27,822 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2024-11-24 01:55:27,822 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:27,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:27,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1929879509, now seen corresponding path program 1 times [2024-11-24 01:55:27,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:27,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349058084] [2024-11-24 01:55:27,823 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:27,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:28,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:28,406 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:28,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:28,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349058084] [2024-11-24 01:55:28,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349058084] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:28,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:28,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:28,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709539666] [2024-11-24 01:55:28,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:28,407 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:28,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:28,408 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:28,408 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:28,408 INFO L87 Difference]: Start difference. First operand 556 states and 799 transitions. Second operand has 5 states, 5 states have (on average 33.0) internal successors, (165), 5 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:28,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:28,647 INFO L93 Difference]: Finished difference Result 1010 states and 1446 transitions. [2024-11-24 01:55:28,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:28,648 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.0) internal successors, (165), 5 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 177 [2024-11-24 01:55:28,649 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:28,651 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:28,651 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:28,651 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:28,657 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 1308 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 142 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1308 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 142 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 142 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:28,657 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1308 Valid, 1444 Invalid, 142 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 142 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:28,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:28,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:28,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4373865698729582) internal successors, (792), 551 states have internal predecessors, (792), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:28,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 798 transitions. [2024-11-24 01:55:28,676 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 798 transitions. Word has length 177 [2024-11-24 01:55:28,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:28,677 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 798 transitions. [2024-11-24 01:55:28,677 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.0) internal successors, (165), 5 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:28,677 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 798 transitions. [2024-11-24 01:55:28,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2024-11-24 01:55:28,679 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:28,679 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:28,680 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2024-11-24 01:55:28,680 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:28,680 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:28,680 INFO L85 PathProgramCache]: Analyzing trace with hash -466280598, now seen corresponding path program 1 times [2024-11-24 01:55:28,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:28,680 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024645781] [2024-11-24 01:55:28,681 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:28,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:28,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:29,307 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:29,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:29,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024645781] [2024-11-24 01:55:29,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024645781] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:29,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:29,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:29,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400220752] [2024-11-24 01:55:29,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:29,309 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:29,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:29,310 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:29,310 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:29,311 INFO L87 Difference]: Start difference. First operand 556 states and 798 transitions. Second operand has 4 states, 4 states have (on average 41.5) internal successors, (166), 4 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:29,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:29,514 INFO L93 Difference]: Finished difference Result 1010 states and 1444 transitions. [2024-11-24 01:55:29,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:29,515 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 41.5) internal successors, (166), 4 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 178 [2024-11-24 01:55:29,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:29,518 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:29,518 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:29,519 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:29,520 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 644 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 140 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 644 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 140 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 140 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:29,520 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [644 Valid, 1444 Invalid, 140 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 140 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:29,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:29,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:29,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4355716878402904) internal successors, (791), 551 states have internal predecessors, (791), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:29,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 797 transitions. [2024-11-24 01:55:29,541 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 797 transitions. Word has length 178 [2024-11-24 01:55:29,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:29,542 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 797 transitions. [2024-11-24 01:55:29,542 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 41.5) internal successors, (166), 4 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:29,542 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 797 transitions. [2024-11-24 01:55:29,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2024-11-24 01:55:29,544 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:29,544 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:29,545 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2024-11-24 01:55:29,545 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:29,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:29,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1697571818, now seen corresponding path program 1 times [2024-11-24 01:55:29,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:29,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88543769] [2024-11-24 01:55:29,545 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:29,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:29,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:30,181 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:30,181 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:30,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88543769] [2024-11-24 01:55:30,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88543769] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:30,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:30,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:30,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50639037] [2024-11-24 01:55:30,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:30,182 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:30,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:30,183 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:30,183 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:30,185 INFO L87 Difference]: Start difference. First operand 556 states and 797 transitions. Second operand has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:30,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:30,420 INFO L93 Difference]: Finished difference Result 1010 states and 1442 transitions. [2024-11-24 01:55:30,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:30,421 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 179 [2024-11-24 01:55:30,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:30,423 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:30,423 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:30,424 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:30,427 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 658 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 138 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 658 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 138 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 138 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:30,427 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [658 Valid, 1451 Invalid, 138 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 138 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:30,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:30,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:30,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4337568058076224) internal successors, (790), 551 states have internal predecessors, (790), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:30,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 796 transitions. [2024-11-24 01:55:30,443 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 796 transitions. Word has length 179 [2024-11-24 01:55:30,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:30,444 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 796 transitions. [2024-11-24 01:55:30,444 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:30,445 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 796 transitions. [2024-11-24 01:55:30,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2024-11-24 01:55:30,446 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:30,446 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:30,446 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2024-11-24 01:55:30,446 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:30,447 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:30,447 INFO L85 PathProgramCache]: Analyzing trace with hash 910997483, now seen corresponding path program 1 times [2024-11-24 01:55:30,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:30,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600779168] [2024-11-24 01:55:30,447 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:30,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:30,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:31,015 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:31,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:31,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600779168] [2024-11-24 01:55:31,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600779168] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:31,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:31,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:31,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217280395] [2024-11-24 01:55:31,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:31,016 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:31,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:31,017 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:31,017 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:31,018 INFO L87 Difference]: Start difference. First operand 556 states and 796 transitions. Second operand has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:31,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:31,255 INFO L93 Difference]: Finished difference Result 1010 states and 1440 transitions. [2024-11-24 01:55:31,255 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:31,255 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 180 [2024-11-24 01:55:31,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:31,258 INFO L225 Difference]: With dead ends: 1010 [2024-11-24 01:55:31,258 INFO L226 Difference]: Without dead ends: 556 [2024-11-24 01:55:31,262 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:31,263 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 657 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 136 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 657 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 136 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 136 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:31,263 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [657 Valid, 1451 Invalid, 136 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 136 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:31,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-11-24 01:55:31,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-11-24 01:55:31,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4319419237749547) internal successors, (789), 551 states have internal predecessors, (789), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 01:55:31,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 795 transitions. [2024-11-24 01:55:31,288 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 795 transitions. Word has length 180 [2024-11-24 01:55:31,288 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:31,289 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 795 transitions. [2024-11-24 01:55:31,289 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:31,289 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 795 transitions. [2024-11-24 01:55:31,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2024-11-24 01:55:31,291 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:31,291 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:31,291 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31 [2024-11-24 01:55:31,291 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:31,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:31,292 INFO L85 PathProgramCache]: Analyzing trace with hash 203821865, now seen corresponding path program 1 times [2024-11-24 01:55:31,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:31,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932901404] [2024-11-24 01:55:31,292 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:31,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:31,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:32,467 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 01:55:32,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:32,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932901404] [2024-11-24 01:55:32,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932901404] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:32,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:32,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:55:32,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410827351] [2024-11-24 01:55:32,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:32,469 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:55:32,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:32,470 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:55:32,470 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:32,470 INFO L87 Difference]: Start difference. First operand 556 states and 795 transitions. Second operand has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:32,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:32,637 INFO L93 Difference]: Finished difference Result 1165 states and 1640 transitions. [2024-11-24 01:55:32,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:55:32,638 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 181 [2024-11-24 01:55:32,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:32,641 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:32,641 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:32,642 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:55:32,642 INFO L435 NwaCegarLoop]: 776 mSDtfsCounter, 1134 mSDsluCounter, 2322 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1137 SdHoareTripleChecker+Valid, 3098 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:32,643 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1137 Valid, 3098 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:32,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:32,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:32,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.399715504978663) internal successors, (984), 703 states have internal predecessors, (984), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:32,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 996 transitions. [2024-11-24 01:55:32,670 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 996 transitions. Word has length 181 [2024-11-24 01:55:32,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:32,671 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 996 transitions. [2024-11-24 01:55:32,671 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:55:32,671 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 996 transitions. [2024-11-24 01:55:32,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 449 [2024-11-24 01:55:32,674 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:32,674 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:32,674 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2024-11-24 01:55:32,674 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:32,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:32,675 INFO L85 PathProgramCache]: Analyzing trace with hash -1787257894, now seen corresponding path program 1 times [2024-11-24 01:55:32,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:32,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586294629] [2024-11-24 01:55:32,675 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:32,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:33,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:34,043 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:34,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:34,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586294629] [2024-11-24 01:55:34,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586294629] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:34,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:34,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:34,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [68171703] [2024-11-24 01:55:34,044 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:34,045 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:34,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:34,047 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:34,047 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:34,051 INFO L87 Difference]: Start difference. First operand 711 states and 996 transitions. Second operand has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:34,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:34,286 INFO L93 Difference]: Finished difference Result 1165 states and 1639 transitions. [2024-11-24 01:55:34,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:34,287 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 448 [2024-11-24 01:55:34,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:34,290 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:34,291 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:34,292 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:34,292 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 724 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 134 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 727 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 135 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 134 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:34,292 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [727 Valid, 1451 Invalid, 135 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 134 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:34,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:34,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:34,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3982930298719773) internal successors, (983), 703 states have internal predecessors, (983), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:34,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 995 transitions. [2024-11-24 01:55:34,324 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 995 transitions. Word has length 448 [2024-11-24 01:55:34,325 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:34,325 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 995 transitions. [2024-11-24 01:55:34,325 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:34,325 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 995 transitions. [2024-11-24 01:55:34,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 450 [2024-11-24 01:55:34,329 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:34,329 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:34,329 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2024-11-24 01:55:34,329 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:34,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:34,330 INFO L85 PathProgramCache]: Analyzing trace with hash 2025497410, now seen corresponding path program 1 times [2024-11-24 01:55:34,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:34,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24672345] [2024-11-24 01:55:34,330 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:34,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:34,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:35,442 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:35,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:35,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24672345] [2024-11-24 01:55:35,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24672345] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:35,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:35,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:35,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916656081] [2024-11-24 01:55:35,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:35,445 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:35,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:35,446 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:35,446 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:35,446 INFO L87 Difference]: Start difference. First operand 711 states and 995 transitions. Second operand has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:35,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:35,650 INFO L93 Difference]: Finished difference Result 1165 states and 1637 transitions. [2024-11-24 01:55:35,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:35,651 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 449 [2024-11-24 01:55:35,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:35,654 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:35,654 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:35,655 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:35,655 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 716 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 719 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 133 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:35,656 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [719 Valid, 1451 Invalid, 133 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:35,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:35,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:35,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3968705547652915) internal successors, (982), 703 states have internal predecessors, (982), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:35,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 994 transitions. [2024-11-24 01:55:35,684 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 994 transitions. Word has length 449 [2024-11-24 01:55:35,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:35,685 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 994 transitions. [2024-11-24 01:55:35,685 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:35,686 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 994 transitions. [2024-11-24 01:55:35,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 451 [2024-11-24 01:55:35,689 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:35,690 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:35,690 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2024-11-24 01:55:35,690 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:35,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:35,691 INFO L85 PathProgramCache]: Analyzing trace with hash -19188593, now seen corresponding path program 1 times [2024-11-24 01:55:35,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:35,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826715866] [2024-11-24 01:55:35,691 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:35,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:36,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:36,817 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:36,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:36,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826715866] [2024-11-24 01:55:36,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826715866] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:36,817 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:36,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:36,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758510081] [2024-11-24 01:55:36,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:36,818 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:36,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:36,820 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:36,821 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:36,821 INFO L87 Difference]: Start difference. First operand 711 states and 994 transitions. Second operand has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:37,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:37,015 INFO L93 Difference]: Finished difference Result 1165 states and 1635 transitions. [2024-11-24 01:55:37,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:37,016 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 450 [2024-11-24 01:55:37,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:37,019 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:37,019 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:37,020 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:37,021 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 708 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 130 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 711 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 131 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 130 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:37,021 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [711 Valid, 1451 Invalid, 131 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 130 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:37,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:37,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:37,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.395448079658606) internal successors, (981), 703 states have internal predecessors, (981), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:37,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 993 transitions. [2024-11-24 01:55:37,047 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 993 transitions. Word has length 450 [2024-11-24 01:55:37,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:37,048 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 993 transitions. [2024-11-24 01:55:37,048 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:37,048 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 993 transitions. [2024-11-24 01:55:37,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 452 [2024-11-24 01:55:37,051 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:37,052 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:37,052 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2024-11-24 01:55:37,052 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:37,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:37,053 INFO L85 PathProgramCache]: Analyzing trace with hash -189619113, now seen corresponding path program 1 times [2024-11-24 01:55:37,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:37,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1426575652] [2024-11-24 01:55:37,053 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:37,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:37,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:38,422 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:38,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:38,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1426575652] [2024-11-24 01:55:38,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1426575652] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:38,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:38,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:38,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288587037] [2024-11-24 01:55:38,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:38,424 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:38,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:38,425 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:38,426 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:38,426 INFO L87 Difference]: Start difference. First operand 711 states and 993 transitions. Second operand has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:38,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:38,611 INFO L93 Difference]: Finished difference Result 1165 states and 1633 transitions. [2024-11-24 01:55:38,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:38,612 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 451 [2024-11-24 01:55:38,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:38,615 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:38,615 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:38,616 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:38,617 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 700 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 128 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 703 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 128 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:38,617 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [703 Valid, 1451 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 128 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:38,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:38,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:38,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3940256045519204) internal successors, (980), 703 states have internal predecessors, (980), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:38,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 992 transitions. [2024-11-24 01:55:38,642 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 992 transitions. Word has length 451 [2024-11-24 01:55:38,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:38,643 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 992 transitions. [2024-11-24 01:55:38,643 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:38,644 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 992 transitions. [2024-11-24 01:55:38,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 453 [2024-11-24 01:55:38,647 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:38,647 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:38,647 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable36 [2024-11-24 01:55:38,648 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:38,648 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:38,648 INFO L85 PathProgramCache]: Analyzing trace with hash -353435452, now seen corresponding path program 1 times [2024-11-24 01:55:38,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:38,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1429065522] [2024-11-24 01:55:38,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:38,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:38,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:39,835 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:39,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:39,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1429065522] [2024-11-24 01:55:39,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1429065522] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:39,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:39,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:39,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646742689] [2024-11-24 01:55:39,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:39,838 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:39,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:39,840 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:39,840 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:39,841 INFO L87 Difference]: Start difference. First operand 711 states and 992 transitions. Second operand has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:40,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:40,165 INFO L93 Difference]: Finished difference Result 1165 states and 1631 transitions. [2024-11-24 01:55:40,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:40,166 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 452 [2024-11-24 01:55:40,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:40,170 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:40,170 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:40,171 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:40,173 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 1261 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1264 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:40,173 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1264 Valid, 1444 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 01:55:40,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:40,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:40,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3926031294452348) internal successors, (979), 703 states have internal predecessors, (979), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:40,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 991 transitions. [2024-11-24 01:55:40,206 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 991 transitions. Word has length 452 [2024-11-24 01:55:40,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:40,206 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 991 transitions. [2024-11-24 01:55:40,207 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:40,207 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 991 transitions. [2024-11-24 01:55:40,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 454 [2024-11-24 01:55:40,212 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:40,213 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:40,213 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable37 [2024-11-24 01:55:40,213 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:40,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:40,214 INFO L85 PathProgramCache]: Analyzing trace with hash 1715196140, now seen corresponding path program 1 times [2024-11-24 01:55:40,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:40,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931906809] [2024-11-24 01:55:40,214 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:40,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:40,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:41,336 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:41,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:41,337 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [931906809] [2024-11-24 01:55:41,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [931906809] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:41,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:41,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:41,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418780222] [2024-11-24 01:55:41,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:41,338 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:41,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:41,339 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:41,339 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:41,340 INFO L87 Difference]: Start difference. First operand 711 states and 991 transitions. Second operand has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:41,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:41,518 INFO L93 Difference]: Finished difference Result 1165 states and 1629 transitions. [2024-11-24 01:55:41,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:41,519 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 453 [2024-11-24 01:55:41,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:41,523 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:41,523 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:41,524 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:41,525 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 684 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 687 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:41,525 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [687 Valid, 1451 Invalid, 125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:41,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:41,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:41,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.391180654338549) internal successors, (978), 703 states have internal predecessors, (978), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:41,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 990 transitions. [2024-11-24 01:55:41,560 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 990 transitions. Word has length 453 [2024-11-24 01:55:41,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:41,561 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 990 transitions. [2024-11-24 01:55:41,562 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:41,562 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 990 transitions. [2024-11-24 01:55:41,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 455 [2024-11-24 01:55:41,568 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:41,569 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:41,569 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2024-11-24 01:55:41,569 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:41,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:41,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1189986183, now seen corresponding path program 1 times [2024-11-24 01:55:41,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:41,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723428189] [2024-11-24 01:55:41,571 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:41,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:41,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:42,856 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:42,857 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:42,857 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723428189] [2024-11-24 01:55:42,857 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723428189] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:42,857 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:42,857 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:42,857 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875590456] [2024-11-24 01:55:42,857 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:42,858 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:42,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:42,859 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:42,859 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:42,859 INFO L87 Difference]: Start difference. First operand 711 states and 990 transitions. Second operand has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:43,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:43,035 INFO L93 Difference]: Finished difference Result 1165 states and 1627 transitions. [2024-11-24 01:55:43,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:43,036 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 454 [2024-11-24 01:55:43,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:43,039 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:43,040 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:43,041 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:43,042 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 676 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 122 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 679 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 123 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 122 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:43,042 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [679 Valid, 1451 Invalid, 123 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 122 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:43,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:43,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:43,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3897581792318634) internal successors, (977), 703 states have internal predecessors, (977), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:43,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 989 transitions. [2024-11-24 01:55:43,066 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 989 transitions. Word has length 454 [2024-11-24 01:55:43,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:43,066 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 989 transitions. [2024-11-24 01:55:43,067 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:43,067 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 989 transitions. [2024-11-24 01:55:43,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 456 [2024-11-24 01:55:43,071 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:43,073 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:43,073 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable39 [2024-11-24 01:55:43,073 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:43,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:43,075 INFO L85 PathProgramCache]: Analyzing trace with hash 686713089, now seen corresponding path program 1 times [2024-11-24 01:55:43,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:43,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936938633] [2024-11-24 01:55:43,075 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:43,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:43,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:44,410 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:44,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:44,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936938633] [2024-11-24 01:55:44,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936938633] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:44,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:44,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:44,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [528526740] [2024-11-24 01:55:44,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:44,412 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:44,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:44,412 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:44,413 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:44,413 INFO L87 Difference]: Start difference. First operand 711 states and 989 transitions. Second operand has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:44,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:44,608 INFO L93 Difference]: Finished difference Result 1165 states and 1625 transitions. [2024-11-24 01:55:44,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:44,609 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 455 [2024-11-24 01:55:44,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:44,612 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:44,613 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:44,614 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:44,614 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 1213 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 120 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1216 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 120 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:44,615 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1216 Valid, 1444 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 120 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:55:44,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:44,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:44,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3883357041251778) internal successors, (976), 703 states have internal predecessors, (976), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:44,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 988 transitions. [2024-11-24 01:55:44,640 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 988 transitions. Word has length 455 [2024-11-24 01:55:44,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:44,640 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 988 transitions. [2024-11-24 01:55:44,641 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:44,641 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 988 transitions. [2024-11-24 01:55:44,645 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 457 [2024-11-24 01:55:44,645 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:44,645 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:44,645 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40 [2024-11-24 01:55:44,645 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:44,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:44,646 INFO L85 PathProgramCache]: Analyzing trace with hash -188533842, now seen corresponding path program 1 times [2024-11-24 01:55:44,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:44,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300549297] [2024-11-24 01:55:44,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:44,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:45,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:45,763 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:45,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:45,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300549297] [2024-11-24 01:55:45,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300549297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:45,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:45,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:45,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170556558] [2024-11-24 01:55:45,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:45,765 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:45,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:45,766 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:45,766 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:45,766 INFO L87 Difference]: Start difference. First operand 711 states and 988 transitions. Second operand has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:45,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:45,900 INFO L93 Difference]: Finished difference Result 1165 states and 1623 transitions. [2024-11-24 01:55:45,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:45,901 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 456 [2024-11-24 01:55:45,901 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:45,903 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:45,904 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:45,904 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:45,905 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 645 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 648 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:45,905 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [648 Valid, 1499 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:45,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:45,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:45,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3869132290184922) internal successors, (975), 703 states have internal predecessors, (975), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:45,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 987 transitions. [2024-11-24 01:55:45,927 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 987 transitions. Word has length 456 [2024-11-24 01:55:45,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:45,928 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 987 transitions. [2024-11-24 01:55:45,928 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:45,928 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 987 transitions. [2024-11-24 01:55:45,931 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 458 [2024-11-24 01:55:45,932 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:45,932 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:45,932 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41 [2024-11-24 01:55:45,932 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:45,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:45,933 INFO L85 PathProgramCache]: Analyzing trace with hash 1644342422, now seen corresponding path program 1 times [2024-11-24 01:55:45,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:45,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865327194] [2024-11-24 01:55:45,934 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:45,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:46,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:46,941 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:46,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:46,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865327194] [2024-11-24 01:55:46,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865327194] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:46,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:46,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:46,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566831873] [2024-11-24 01:55:46,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:46,942 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:46,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:46,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:46,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:46,944 INFO L87 Difference]: Start difference. First operand 711 states and 987 transitions. Second operand has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:47,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:47,048 INFO L93 Difference]: Finished difference Result 1165 states and 1621 transitions. [2024-11-24 01:55:47,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:47,049 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 457 [2024-11-24 01:55:47,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:47,052 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:47,052 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:47,052 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:47,057 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 637 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 640 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 69 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:47,058 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [640 Valid, 1499 Invalid, 69 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 68 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:47,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:47,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:47,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3854907539118066) internal successors, (974), 703 states have internal predecessors, (974), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:47,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 986 transitions. [2024-11-24 01:55:47,079 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 986 transitions. Word has length 457 [2024-11-24 01:55:47,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:47,079 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 986 transitions. [2024-11-24 01:55:47,079 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:47,080 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 986 transitions. [2024-11-24 01:55:47,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 459 [2024-11-24 01:55:47,083 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:47,083 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:47,083 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-11-24 01:55:47,084 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:47,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:47,084 INFO L85 PathProgramCache]: Analyzing trace with hash 1436555875, now seen corresponding path program 1 times [2024-11-24 01:55:47,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:47,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639017420] [2024-11-24 01:55:47,085 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:47,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:47,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:48,301 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:48,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:48,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639017420] [2024-11-24 01:55:48,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639017420] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:48,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:48,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:48,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163960544] [2024-11-24 01:55:48,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:48,303 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:48,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:48,304 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:48,304 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:48,305 INFO L87 Difference]: Start difference. First operand 711 states and 986 transitions. Second operand has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:48,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:48,457 INFO L93 Difference]: Finished difference Result 1165 states and 1619 transitions. [2024-11-24 01:55:48,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:48,458 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 458 [2024-11-24 01:55:48,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:48,461 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:48,462 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:48,462 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:48,463 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 629 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 632 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:48,463 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [632 Valid, 1499 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:48,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:48,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:48,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3840682788051208) internal successors, (973), 703 states have internal predecessors, (973), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:48,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 985 transitions. [2024-11-24 01:55:48,485 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 985 transitions. Word has length 458 [2024-11-24 01:55:48,486 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:48,486 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 985 transitions. [2024-11-24 01:55:48,486 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:48,486 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 985 transitions. [2024-11-24 01:55:48,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 460 [2024-11-24 01:55:48,490 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:48,490 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:48,491 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43 [2024-11-24 01:55:48,491 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:48,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:48,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1605313621, now seen corresponding path program 1 times [2024-11-24 01:55:48,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:48,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [765904121] [2024-11-24 01:55:48,493 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:48,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:48,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:49,640 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:49,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:49,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [765904121] [2024-11-24 01:55:49,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [765904121] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:49,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:49,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:49,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059170020] [2024-11-24 01:55:49,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:49,642 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:49,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:49,643 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:49,643 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:49,643 INFO L87 Difference]: Start difference. First operand 711 states and 985 transitions. Second operand has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:49,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:49,753 INFO L93 Difference]: Finished difference Result 1165 states and 1617 transitions. [2024-11-24 01:55:49,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:49,754 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 459 [2024-11-24 01:55:49,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:49,757 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:49,757 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:49,757 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:49,758 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 621 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 624 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:49,758 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [624 Valid, 1499 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:49,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:49,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:49,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3826458036984353) internal successors, (972), 703 states have internal predecessors, (972), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:49,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 984 transitions. [2024-11-24 01:55:49,778 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 984 transitions. Word has length 459 [2024-11-24 01:55:49,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:49,778 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 984 transitions. [2024-11-24 01:55:49,779 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:49,779 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 984 transitions. [2024-11-24 01:55:49,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 461 [2024-11-24 01:55:49,782 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:49,783 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:49,783 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44 [2024-11-24 01:55:49,783 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:49,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:49,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1083755368, now seen corresponding path program 1 times [2024-11-24 01:55:49,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:49,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592148229] [2024-11-24 01:55:49,785 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:49,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:50,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:50,853 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:50,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:50,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592148229] [2024-11-24 01:55:50,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592148229] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:50,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:50,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:50,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335828528] [2024-11-24 01:55:50,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:50,855 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:50,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:50,856 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:50,856 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:50,856 INFO L87 Difference]: Start difference. First operand 711 states and 984 transitions. Second operand has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:50,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:50,946 INFO L93 Difference]: Finished difference Result 1165 states and 1615 transitions. [2024-11-24 01:55:50,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:50,947 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 460 [2024-11-24 01:55:50,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:50,950 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:50,950 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:50,951 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:50,951 INFO L435 NwaCegarLoop]: 757 mSDtfsCounter, 606 mSDsluCounter, 766 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 609 SdHoareTripleChecker+Valid, 1523 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:50,952 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [609 Valid, 1523 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:50,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:50,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:50,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3812233285917497) internal successors, (971), 703 states have internal predecessors, (971), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:50,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 983 transitions. [2024-11-24 01:55:50,972 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 983 transitions. Word has length 460 [2024-11-24 01:55:50,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:50,972 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 983 transitions. [2024-11-24 01:55:50,973 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:50,973 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 983 transitions. [2024-11-24 01:55:50,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 462 [2024-11-24 01:55:50,977 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:50,977 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:50,978 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45 [2024-11-24 01:55:50,978 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:50,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:50,979 INFO L85 PathProgramCache]: Analyzing trace with hash 2085697088, now seen corresponding path program 1 times [2024-11-24 01:55:50,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:50,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817881705] [2024-11-24 01:55:50,979 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:50,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:51,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:52,121 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:52,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:52,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817881705] [2024-11-24 01:55:52,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817881705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:52,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:52,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:52,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169215823] [2024-11-24 01:55:52,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:52,122 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:52,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:52,123 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:52,123 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:52,124 INFO L87 Difference]: Start difference. First operand 711 states and 983 transitions. Second operand has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:52,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:52,206 INFO L93 Difference]: Finished difference Result 1165 states and 1613 transitions. [2024-11-24 01:55:52,207 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:52,207 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 461 [2024-11-24 01:55:52,208 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:52,210 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:52,210 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:52,211 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:52,211 INFO L435 NwaCegarLoop]: 757 mSDtfsCounter, 598 mSDsluCounter, 766 mSDsCounter, 0 mSdLazyCounter, 36 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 601 SdHoareTripleChecker+Valid, 1523 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 36 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:52,212 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [601 Valid, 1523 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 36 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:52,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:52,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:52,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.379800853485064) internal successors, (970), 703 states have internal predecessors, (970), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:52,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 982 transitions. [2024-11-24 01:55:52,232 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 982 transitions. Word has length 461 [2024-11-24 01:55:52,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:52,233 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 982 transitions. [2024-11-24 01:55:52,233 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:52,233 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 982 transitions. [2024-11-24 01:55:52,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 463 [2024-11-24 01:55:52,237 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:52,238 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:52,238 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46 [2024-11-24 01:55:52,238 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:52,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:52,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1106690637, now seen corresponding path program 1 times [2024-11-24 01:55:52,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:52,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572201043] [2024-11-24 01:55:52,239 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:52,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:52,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:53,433 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:53,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:53,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572201043] [2024-11-24 01:55:53,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572201043] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:53,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:53,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:53,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404750553] [2024-11-24 01:55:53,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:53,435 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:53,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:53,436 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:53,436 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:53,436 INFO L87 Difference]: Start difference. First operand 711 states and 982 transitions. Second operand has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:53,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:53,842 INFO L93 Difference]: Finished difference Result 1165 states and 1611 transitions. [2024-11-24 01:55:53,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:53,842 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 462 [2024-11-24 01:55:53,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:53,845 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:53,845 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:53,846 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:53,847 INFO L435 NwaCegarLoop]: 578 mSDtfsCounter, 583 mSDsluCounter, 587 mSDsCounter, 0 mSdLazyCounter, 392 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 586 SdHoareTripleChecker+Valid, 1165 SdHoareTripleChecker+Invalid, 393 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 392 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:53,847 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [586 Valid, 1165 Invalid, 393 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 392 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 01:55:53,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:53,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:53,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3783783783783783) internal successors, (969), 703 states have internal predecessors, (969), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:53,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 981 transitions. [2024-11-24 01:55:53,869 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 981 transitions. Word has length 462 [2024-11-24 01:55:53,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:53,869 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 981 transitions. [2024-11-24 01:55:53,869 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:53,870 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 981 transitions. [2024-11-24 01:55:53,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 464 [2024-11-24 01:55:53,873 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:53,873 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:53,873 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable47 [2024-11-24 01:55:53,874 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:53,874 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:53,875 INFO L85 PathProgramCache]: Analyzing trace with hash 941358165, now seen corresponding path program 1 times [2024-11-24 01:55:53,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:53,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894730018] [2024-11-24 01:55:53,875 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:53,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:55,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:56,252 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:56,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:56,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894730018] [2024-11-24 01:55:56,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894730018] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:56,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:56,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:55:56,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [151871895] [2024-11-24 01:55:56,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:56,253 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:55:56,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:56,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:55:56,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:55:56,255 INFO L87 Difference]: Start difference. First operand 711 states and 981 transitions. Second operand has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:56,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:56,326 INFO L93 Difference]: Finished difference Result 1165 states and 1609 transitions. [2024-11-24 01:55:56,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:56,327 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 463 [2024-11-24 01:55:56,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:56,329 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:56,329 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:56,330 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:56,331 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 496 mSDsluCounter, 758 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 496 SdHoareTripleChecker+Valid, 1514 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:56,331 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [496 Valid, 1514 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:55:56,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:56,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:56,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3769559032716927) internal successors, (968), 703 states have internal predecessors, (968), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:56,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 980 transitions. [2024-11-24 01:55:56,352 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 980 transitions. Word has length 463 [2024-11-24 01:55:56,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:56,353 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 980 transitions. [2024-11-24 01:55:56,353 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:56,353 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 980 transitions. [2024-11-24 01:55:56,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 465 [2024-11-24 01:55:56,356 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:56,357 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:56,357 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable48 [2024-11-24 01:55:56,357 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:56,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:56,358 INFO L85 PathProgramCache]: Analyzing trace with hash 2059983743, now seen corresponding path program 1 times [2024-11-24 01:55:56,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:56,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [141617589] [2024-11-24 01:55:56,359 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:56,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:55:57,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:55:58,873 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:55:58,873 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:55:58,873 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [141617589] [2024-11-24 01:55:58,873 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [141617589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:55:58,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:55:58,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:55:58,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757553263] [2024-11-24 01:55:58,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:55:58,874 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:55:58,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:55:58,875 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:55:58,875 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:55:58,875 INFO L87 Difference]: Start difference. First operand 711 states and 980 transitions. Second operand has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:59,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:55:59,022 INFO L93 Difference]: Finished difference Result 1165 states and 1607 transitions. [2024-11-24 01:55:59,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:55:59,023 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 464 [2024-11-24 01:55:59,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:55:59,026 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:55:59,026 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:55:59,026 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:55:59,028 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 1177 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1177 SdHoareTripleChecker+Valid, 1484 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:55:59,028 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1177 Valid, 1484 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 62 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:55:59,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:55:59,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:55:59,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3755334281650071) internal successors, (967), 703 states have internal predecessors, (967), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:55:59,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 979 transitions. [2024-11-24 01:55:59,057 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 979 transitions. Word has length 464 [2024-11-24 01:55:59,057 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:55:59,057 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 979 transitions. [2024-11-24 01:55:59,058 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:55:59,058 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 979 transitions. [2024-11-24 01:55:59,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 466 [2024-11-24 01:55:59,061 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:55:59,062 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:55:59,062 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable49 [2024-11-24 01:55:59,062 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:55:59,063 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:55:59,063 INFO L85 PathProgramCache]: Analyzing trace with hash 2072196053, now seen corresponding path program 1 times [2024-11-24 01:55:59,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:55:59,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668303818] [2024-11-24 01:55:59,063 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:55:59,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:00,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:00,954 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:00,954 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:00,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668303818] [2024-11-24 01:56:00,955 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668303818] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:00,955 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:00,955 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:00,955 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1902588743] [2024-11-24 01:56:00,955 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:00,956 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:00,956 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:00,956 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:00,956 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:00,957 INFO L87 Difference]: Start difference. First operand 711 states and 979 transitions. Second operand has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:01,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:01,090 INFO L93 Difference]: Finished difference Result 1165 states and 1605 transitions. [2024-11-24 01:56:01,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:01,091 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 465 [2024-11-24 01:56:01,091 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:01,093 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:01,094 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:01,095 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:01,096 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 1167 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1167 SdHoareTripleChecker+Valid, 1484 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:01,096 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1167 Valid, 1484 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:01,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:01,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:01,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3741109530583215) internal successors, (966), 703 states have internal predecessors, (966), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:01,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 978 transitions. [2024-11-24 01:56:01,114 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 978 transitions. Word has length 465 [2024-11-24 01:56:01,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:01,114 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 978 transitions. [2024-11-24 01:56:01,114 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:01,115 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 978 transitions. [2024-11-24 01:56:01,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 467 [2024-11-24 01:56:01,118 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:01,118 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:01,118 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-11-24 01:56:01,118 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:01,119 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:01,119 INFO L85 PathProgramCache]: Analyzing trace with hash 512722894, now seen corresponding path program 1 times [2024-11-24 01:56:01,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:01,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741666837] [2024-11-24 01:56:01,120 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:01,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:02,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:02,673 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:02,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:02,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741666837] [2024-11-24 01:56:02,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741666837] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:02,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:02,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:56:02,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194147151] [2024-11-24 01:56:02,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:02,674 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:56:02,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:02,675 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:56:02,675 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:56:02,675 INFO L87 Difference]: Start difference. First operand 711 states and 978 transitions. Second operand has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:02,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:02,758 INFO L93 Difference]: Finished difference Result 1165 states and 1603 transitions. [2024-11-24 01:56:02,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:02,759 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 466 [2024-11-24 01:56:02,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:02,761 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:02,761 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:02,761 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:02,762 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 505 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 505 SdHoareTripleChecker+Valid, 1484 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:02,762 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [505 Valid, 1484 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:02,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:02,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:02,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.372688477951636) internal successors, (965), 703 states have internal predecessors, (965), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:02,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 977 transitions. [2024-11-24 01:56:02,779 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 977 transitions. Word has length 466 [2024-11-24 01:56:02,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:02,780 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 977 transitions. [2024-11-24 01:56:02,780 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:02,780 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 977 transitions. [2024-11-24 01:56:02,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 468 [2024-11-24 01:56:02,783 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:02,784 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:02,784 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51 [2024-11-24 01:56:02,784 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:02,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:02,785 INFO L85 PathProgramCache]: Analyzing trace with hash 861938758, now seen corresponding path program 1 times [2024-11-24 01:56:02,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:02,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797772421] [2024-11-24 01:56:02,785 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:02,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:03,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:04,669 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:04,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:04,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797772421] [2024-11-24 01:56:04,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797772421] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:04,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:04,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:04,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2063481444] [2024-11-24 01:56:04,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:04,671 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:04,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:04,672 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:04,672 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:04,672 INFO L87 Difference]: Start difference. First operand 711 states and 977 transitions. Second operand has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:04,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:04,909 INFO L93 Difference]: Finished difference Result 1165 states and 1601 transitions. [2024-11-24 01:56:04,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:04,910 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 467 [2024-11-24 01:56:04,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:04,912 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:04,912 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:04,912 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:04,913 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 1212 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 118 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1212 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 118 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 118 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:04,913 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1212 Valid, 1422 Invalid, 118 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 118 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 01:56:04,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:04,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:04,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3712660028449501) internal successors, (964), 703 states have internal predecessors, (964), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:04,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 976 transitions. [2024-11-24 01:56:04,936 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 976 transitions. Word has length 467 [2024-11-24 01:56:04,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:04,937 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 976 transitions. [2024-11-24 01:56:04,937 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:04,937 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 976 transitions. [2024-11-24 01:56:04,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 469 [2024-11-24 01:56:04,943 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:04,943 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:04,943 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-11-24 01:56:04,944 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:04,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:04,944 INFO L85 PathProgramCache]: Analyzing trace with hash 1901367216, now seen corresponding path program 1 times [2024-11-24 01:56:04,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:04,945 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483121974] [2024-11-24 01:56:04,945 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:04,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:05,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:06,642 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:06,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:06,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483121974] [2024-11-24 01:56:06,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483121974] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:06,643 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:06,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:06,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1673151649] [2024-11-24 01:56:06,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:06,643 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:06,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:06,644 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:06,644 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:06,645 INFO L87 Difference]: Start difference. First operand 711 states and 976 transitions. Second operand has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:06,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:06,824 INFO L93 Difference]: Finished difference Result 1165 states and 1599 transitions. [2024-11-24 01:56:06,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:06,824 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 468 [2024-11-24 01:56:06,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:06,826 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:06,826 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:06,826 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:06,826 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 636 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 636 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 116 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:06,827 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [636 Valid, 1429 Invalid, 116 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 116 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:06,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:06,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:06,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3698435277382646) internal successors, (963), 703 states have internal predecessors, (963), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:06,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 975 transitions. [2024-11-24 01:56:06,837 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 975 transitions. Word has length 468 [2024-11-24 01:56:06,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:06,837 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 975 transitions. [2024-11-24 01:56:06,837 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:06,837 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 975 transitions. [2024-11-24 01:56:06,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 470 [2024-11-24 01:56:06,840 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:06,840 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:06,840 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-11-24 01:56:06,841 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:06,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:06,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1536682647, now seen corresponding path program 1 times [2024-11-24 01:56:06,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:06,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767412234] [2024-11-24 01:56:06,842 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:06,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:07,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:08,584 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:08,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:08,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767412234] [2024-11-24 01:56:08,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767412234] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:08,584 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:08,584 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:56:08,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2241932] [2024-11-24 01:56:08,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:08,585 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:56:08,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:08,586 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:56:08,586 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:56:08,586 INFO L87 Difference]: Start difference. First operand 711 states and 975 transitions. Second operand has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:08,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:08,728 INFO L93 Difference]: Finished difference Result 1165 states and 1597 transitions. [2024-11-24 01:56:08,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:08,728 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 469 [2024-11-24 01:56:08,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:08,730 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:08,730 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:08,730 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:08,731 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 558 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 114 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 558 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 114 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:08,731 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [558 Valid, 1422 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 114 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:08,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:08,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:08,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.368421052631579) internal successors, (962), 703 states have internal predecessors, (962), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:08,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 974 transitions. [2024-11-24 01:56:08,743 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 974 transitions. Word has length 469 [2024-11-24 01:56:08,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:08,743 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 974 transitions. [2024-11-24 01:56:08,743 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:08,743 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 974 transitions. [2024-11-24 01:56:08,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 471 [2024-11-24 01:56:08,745 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:08,745 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:08,745 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-11-24 01:56:08,745 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:08,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:08,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1546007711, now seen corresponding path program 1 times [2024-11-24 01:56:08,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:08,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431867001] [2024-11-24 01:56:08,746 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:08,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:09,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:10,125 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:10,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:10,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431867001] [2024-11-24 01:56:10,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431867001] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:10,125 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:10,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:10,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831346894] [2024-11-24 01:56:10,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:10,126 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:10,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:10,126 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:10,126 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:10,127 INFO L87 Difference]: Start difference. First operand 711 states and 974 transitions. Second operand has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:10,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:10,273 INFO L93 Difference]: Finished difference Result 1165 states and 1595 transitions. [2024-11-24 01:56:10,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:10,273 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 470 [2024-11-24 01:56:10,273 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:10,275 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:10,275 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:10,275 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:10,275 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 634 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 634 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:10,275 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [634 Valid, 1429 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 112 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:10,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:10,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:10,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3669985775248934) internal successors, (961), 703 states have internal predecessors, (961), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:10,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 973 transitions. [2024-11-24 01:56:10,285 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 973 transitions. Word has length 470 [2024-11-24 01:56:10,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:10,285 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 973 transitions. [2024-11-24 01:56:10,286 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:10,286 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 973 transitions. [2024-11-24 01:56:10,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 472 [2024-11-24 01:56:10,287 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:10,287 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:10,288 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-11-24 01:56:10,288 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:10,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:10,288 INFO L85 PathProgramCache]: Analyzing trace with hash 916407912, now seen corresponding path program 1 times [2024-11-24 01:56:10,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:10,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424678143] [2024-11-24 01:56:10,288 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:10,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:11,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:11,858 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:11,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:11,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424678143] [2024-11-24 01:56:11,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424678143] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:11,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:11,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:11,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232449836] [2024-11-24 01:56:11,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:11,859 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:11,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:11,860 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:11,860 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:11,860 INFO L87 Difference]: Start difference. First operand 711 states and 973 transitions. Second operand has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:12,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:12,019 INFO L93 Difference]: Finished difference Result 1165 states and 1593 transitions. [2024-11-24 01:56:12,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:12,019 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 471 [2024-11-24 01:56:12,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:12,021 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:12,021 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:12,022 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:12,022 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 633 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 633 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:12,023 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [633 Valid, 1429 Invalid, 110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:12,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:12,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:12,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3655761024182076) internal successors, (960), 703 states have internal predecessors, (960), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:12,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 972 transitions. [2024-11-24 01:56:12,040 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 972 transitions. Word has length 471 [2024-11-24 01:56:12,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:12,040 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 972 transitions. [2024-11-24 01:56:12,041 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:12,041 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 972 transitions. [2024-11-24 01:56:12,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 473 [2024-11-24 01:56:12,044 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:12,044 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:12,044 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-11-24 01:56:12,045 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:12,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:12,045 INFO L85 PathProgramCache]: Analyzing trace with hash -426939378, now seen corresponding path program 1 times [2024-11-24 01:56:12,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:12,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1288811523] [2024-11-24 01:56:12,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:12,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:13,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:13,653 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:13,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:13,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1288811523] [2024-11-24 01:56:13,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1288811523] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:13,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:13,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:13,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838384268] [2024-11-24 01:56:13,653 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:13,654 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:13,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:13,654 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:13,655 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:13,655 INFO L87 Difference]: Start difference. First operand 711 states and 972 transitions. Second operand has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:13,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:13,797 INFO L93 Difference]: Finished difference Result 1165 states and 1591 transitions. [2024-11-24 01:56:13,798 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:13,798 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 472 [2024-11-24 01:56:13,798 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:13,800 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:13,800 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:13,800 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:13,800 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 632 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 108 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 632 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 108 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:13,801 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [632 Valid, 1429 Invalid, 108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 108 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:13,801 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:13,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:13,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.364153627311522) internal successors, (959), 703 states have internal predecessors, (959), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:13,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 971 transitions. [2024-11-24 01:56:13,811 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 971 transitions. Word has length 472 [2024-11-24 01:56:13,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:13,811 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 971 transitions. [2024-11-24 01:56:13,811 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:13,811 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 971 transitions. [2024-11-24 01:56:13,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 474 [2024-11-24 01:56:13,814 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:13,814 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:13,815 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-11-24 01:56:13,815 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:13,815 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:13,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1135077305, now seen corresponding path program 1 times [2024-11-24 01:56:13,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:13,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859891191] [2024-11-24 01:56:13,816 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:13,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:14,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:15,112 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:15,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:15,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859891191] [2024-11-24 01:56:15,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859891191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:15,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:15,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 01:56:15,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1580424174] [2024-11-24 01:56:15,113 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:15,113 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 01:56:15,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:15,114 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 01:56:15,114 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 01:56:15,114 INFO L87 Difference]: Start difference. First operand 711 states and 971 transitions. Second operand has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:15,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:15,237 INFO L93 Difference]: Finished difference Result 1165 states and 1589 transitions. [2024-11-24 01:56:15,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 01:56:15,237 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 473 [2024-11-24 01:56:15,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:15,239 INFO L225 Difference]: With dead ends: 1165 [2024-11-24 01:56:15,239 INFO L226 Difference]: Without dead ends: 711 [2024-11-24 01:56:15,240 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:15,240 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 522 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 522 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 106 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:15,240 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [522 Valid, 1422 Invalid, 106 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 106 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:15,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-11-24 01:56:15,250 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-11-24 01:56:15,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3627311522048364) internal successors, (958), 703 states have internal predecessors, (958), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 01:56:15,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 970 transitions. [2024-11-24 01:56:15,252 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 970 transitions. Word has length 473 [2024-11-24 01:56:15,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:15,253 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 970 transitions. [2024-11-24 01:56:15,253 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:15,253 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 970 transitions. [2024-11-24 01:56:15,255 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 475 [2024-11-24 01:56:15,255 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:15,255 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:15,255 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-11-24 01:56:15,255 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:15,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:15,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1287685629, now seen corresponding path program 1 times [2024-11-24 01:56:15,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:15,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786483340] [2024-11-24 01:56:15,256 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:15,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:16,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:17,051 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:17,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:17,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786483340] [2024-11-24 01:56:17,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786483340] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:17,052 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:17,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:56:17,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774648013] [2024-11-24 01:56:17,052 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:17,052 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:56:17,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:17,053 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:56:17,053 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:17,053 INFO L87 Difference]: Start difference. First operand 711 states and 970 transitions. Second operand has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:17,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:17,613 INFO L93 Difference]: Finished difference Result 1683 states and 2299 transitions. [2024-11-24 01:56:17,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:56:17,614 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 474 [2024-11-24 01:56:17,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:17,617 INFO L225 Difference]: With dead ends: 1683 [2024-11-24 01:56:17,617 INFO L226 Difference]: Without dead ends: 1229 [2024-11-24 01:56:17,618 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:56:17,618 INFO L435 NwaCegarLoop]: 631 mSDtfsCounter, 725 mSDsluCounter, 2070 mSDsCounter, 0 mSdLazyCounter, 567 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 728 SdHoareTripleChecker+Valid, 2701 SdHoareTripleChecker+Invalid, 575 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 567 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:17,618 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [728 Valid, 2701 Invalid, 575 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 567 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 01:56:17,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1229 states. [2024-11-24 01:56:17,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1229 to 1121. [2024-11-24 01:56:17,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1121 states, 1110 states have (on average 1.3567567567567567) internal successors, (1506), 1110 states have internal predecessors, (1506), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 01:56:17,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1524 transitions. [2024-11-24 01:56:17,647 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1524 transitions. Word has length 474 [2024-11-24 01:56:17,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:17,647 INFO L471 AbstractCegarLoop]: Abstraction has 1121 states and 1524 transitions. [2024-11-24 01:56:17,647 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:17,648 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1524 transitions. [2024-11-24 01:56:17,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 476 [2024-11-24 01:56:17,651 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:17,651 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:17,651 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-11-24 01:56:17,652 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:17,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:17,652 INFO L85 PathProgramCache]: Analyzing trace with hash -642634531, now seen corresponding path program 1 times [2024-11-24 01:56:17,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:17,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880718425] [2024-11-24 01:56:17,653 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:17,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:19,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:20,771 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2024-11-24 01:56:20,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:20,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [880718425] [2024-11-24 01:56:20,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [880718425] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:20,772 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:20,772 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 01:56:20,772 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1325179140] [2024-11-24 01:56:20,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:20,772 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 01:56:20,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:20,773 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 01:56:20,773 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:20,774 INFO L87 Difference]: Start difference. First operand 1121 states and 1524 transitions. Second operand has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:20,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:20,826 INFO L93 Difference]: Finished difference Result 2050 states and 2737 transitions. [2024-11-24 01:56:20,826 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 01:56:20,826 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 475 [2024-11-24 01:56:20,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:20,829 INFO L225 Difference]: With dead ends: 2050 [2024-11-24 01:56:20,829 INFO L226 Difference]: Without dead ends: 1358 [2024-11-24 01:56:20,830 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 01:56:20,830 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 19 mSDsluCounter, 2259 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 3015 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:20,830 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 3015 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:56:20,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1358 states. [2024-11-24 01:56:20,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1358 to 1352. [2024-11-24 01:56:20,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1352 states, 1341 states have (on average 1.3154362416107384) internal successors, (1764), 1341 states have internal predecessors, (1764), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 01:56:20,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1352 states to 1352 states and 1782 transitions. [2024-11-24 01:56:20,856 INFO L78 Accepts]: Start accepts. Automaton has 1352 states and 1782 transitions. Word has length 475 [2024-11-24 01:56:20,856 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:20,856 INFO L471 AbstractCegarLoop]: Abstraction has 1352 states and 1782 transitions. [2024-11-24 01:56:20,856 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:20,856 INFO L276 IsEmpty]: Start isEmpty. Operand 1352 states and 1782 transitions. [2024-11-24 01:56:20,858 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 478 [2024-11-24 01:56:20,858 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:20,858 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:20,858 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-11-24 01:56:20,859 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:20,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:20,859 INFO L85 PathProgramCache]: Analyzing trace with hash 557524213, now seen corresponding path program 1 times [2024-11-24 01:56:20,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:20,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635223770] [2024-11-24 01:56:20,859 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:20,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:22,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:23,598 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 115 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:56:23,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:23,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635223770] [2024-11-24 01:56:23,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635223770] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:23,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:23,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:56:23,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265251140] [2024-11-24 01:56:23,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:23,599 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:56:23,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:23,600 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:56:23,600 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:23,600 INFO L87 Difference]: Start difference. First operand 1352 states and 1782 transitions. Second operand has 6 states, 6 states have (on average 75.0) internal successors, (450), 6 states have internal predecessors, (450), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:24,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:24,234 INFO L93 Difference]: Finished difference Result 1906 states and 2519 transitions. [2024-11-24 01:56:24,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:56:24,235 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 75.0) internal successors, (450), 6 states have internal predecessors, (450), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 477 [2024-11-24 01:56:24,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:24,237 INFO L225 Difference]: With dead ends: 1906 [2024-11-24 01:56:24,237 INFO L226 Difference]: Without dead ends: 1375 [2024-11-24 01:56:24,238 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:56:24,238 INFO L435 NwaCegarLoop]: 568 mSDtfsCounter, 1339 mSDsluCounter, 1681 mSDsCounter, 0 mSdLazyCounter, 791 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1342 SdHoareTripleChecker+Valid, 2249 SdHoareTripleChecker+Invalid, 791 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 791 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:24,239 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1342 Valid, 2249 Invalid, 791 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 791 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 01:56:24,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1375 states. [2024-11-24 01:56:24,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1375 to 1353. [2024-11-24 01:56:24,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1353 states, 1342 states have (on average 1.3152011922503726) internal successors, (1765), 1342 states have internal predecessors, (1765), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 01:56:24,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1353 states to 1353 states and 1783 transitions. [2024-11-24 01:56:24,258 INFO L78 Accepts]: Start accepts. Automaton has 1353 states and 1783 transitions. Word has length 477 [2024-11-24 01:56:24,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:24,258 INFO L471 AbstractCegarLoop]: Abstraction has 1353 states and 1783 transitions. [2024-11-24 01:56:24,258 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 75.0) internal successors, (450), 6 states have internal predecessors, (450), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:24,258 INFO L276 IsEmpty]: Start isEmpty. Operand 1353 states and 1783 transitions. [2024-11-24 01:56:24,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 478 [2024-11-24 01:56:24,261 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:24,261 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:24,261 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-11-24 01:56:24,261 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:24,262 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:24,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1156124924, now seen corresponding path program 1 times [2024-11-24 01:56:24,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:24,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849048237] [2024-11-24 01:56:24,262 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:24,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:25,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:26,635 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-11-24 01:56:26,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:26,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1849048237] [2024-11-24 01:56:26,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1849048237] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:26,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:26,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 01:56:26,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1341310882] [2024-11-24 01:56:26,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:26,636 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 01:56:26,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:26,637 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 01:56:26,637 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 01:56:26,637 INFO L87 Difference]: Start difference. First operand 1353 states and 1783 transitions. Second operand has 8 states, 8 states have (on average 46.0) internal successors, (368), 8 states have internal predecessors, (368), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:26,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:26,829 INFO L93 Difference]: Finished difference Result 3074 states and 4032 transitions. [2024-11-24 01:56:26,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 01:56:26,829 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 46.0) internal successors, (368), 8 states have internal predecessors, (368), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 477 [2024-11-24 01:56:26,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:26,834 INFO L225 Difference]: With dead ends: 3074 [2024-11-24 01:56:26,835 INFO L226 Difference]: Without dead ends: 2361 [2024-11-24 01:56:26,836 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:56:26,836 INFO L435 NwaCegarLoop]: 1801 mSDtfsCounter, 1158 mSDsluCounter, 7740 mSDsCounter, 0 mSdLazyCounter, 147 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1161 SdHoareTripleChecker+Valid, 9541 SdHoareTripleChecker+Invalid, 147 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 147 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:26,837 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1161 Valid, 9541 Invalid, 147 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 147 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:56:26,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2361 states. [2024-11-24 01:56:26,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2361 to 1420. [2024-11-24 01:56:26,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1420 states, 1406 states have (on average 1.3200568990042674) internal successors, (1856), 1406 states have internal predecessors, (1856), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 01:56:26,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1420 states to 1420 states and 1880 transitions. [2024-11-24 01:56:26,883 INFO L78 Accepts]: Start accepts. Automaton has 1420 states and 1880 transitions. Word has length 477 [2024-11-24 01:56:26,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:26,883 INFO L471 AbstractCegarLoop]: Abstraction has 1420 states and 1880 transitions. [2024-11-24 01:56:26,883 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 46.0) internal successors, (368), 8 states have internal predecessors, (368), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:56:26,884 INFO L276 IsEmpty]: Start isEmpty. Operand 1420 states and 1880 transitions. [2024-11-24 01:56:26,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 479 [2024-11-24 01:56:26,887 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:26,888 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:26,888 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-11-24 01:56:26,888 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:26,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:26,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1031637214, now seen corresponding path program 1 times [2024-11-24 01:56:26,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:26,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1369752362] [2024-11-24 01:56:26,889 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:26,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:28,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:29,692 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 129 trivial. 0 not checked. [2024-11-24 01:56:29,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:29,692 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1369752362] [2024-11-24 01:56:29,692 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1369752362] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:29,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:29,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 01:56:29,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182938185] [2024-11-24 01:56:29,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:29,693 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 01:56:29,693 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:29,694 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 01:56:29,694 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:56:29,694 INFO L87 Difference]: Start difference. First operand 1420 states and 1880 transitions. Second operand has 7 states, 7 states have (on average 55.0) internal successors, (385), 7 states have internal predecessors, (385), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:30,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:30,108 INFO L93 Difference]: Finished difference Result 2814 states and 3716 transitions. [2024-11-24 01:56:30,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 01:56:30,109 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 55.0) internal successors, (385), 7 states have internal predecessors, (385), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 478 [2024-11-24 01:56:30,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:30,113 INFO L225 Difference]: With dead ends: 2814 [2024-11-24 01:56:30,113 INFO L226 Difference]: Without dead ends: 1436 [2024-11-24 01:56:30,116 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-24 01:56:30,116 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 771 mSDsluCounter, 2832 mSDsCounter, 0 mSdLazyCounter, 290 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 773 SdHoareTripleChecker+Valid, 3588 SdHoareTripleChecker+Invalid, 295 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 290 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:30,116 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [773 Valid, 3588 Invalid, 295 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 290 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 01:56:30,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1436 states. [2024-11-24 01:56:30,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1436 to 1428. [2024-11-24 01:56:30,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1428 states, 1414 states have (on average 1.3154172560113153) internal successors, (1860), 1414 states have internal predecessors, (1860), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 01:56:30,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1428 states to 1428 states and 1884 transitions. [2024-11-24 01:56:30,158 INFO L78 Accepts]: Start accepts. Automaton has 1428 states and 1884 transitions. Word has length 478 [2024-11-24 01:56:30,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:30,158 INFO L471 AbstractCegarLoop]: Abstraction has 1428 states and 1884 transitions. [2024-11-24 01:56:30,158 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 55.0) internal successors, (385), 7 states have internal predecessors, (385), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:30,158 INFO L276 IsEmpty]: Start isEmpty. Operand 1428 states and 1884 transitions. [2024-11-24 01:56:30,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 481 [2024-11-24 01:56:30,162 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:30,163 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:30,163 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable63 [2024-11-24 01:56:30,163 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:30,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:30,164 INFO L85 PathProgramCache]: Analyzing trace with hash 529696992, now seen corresponding path program 1 times [2024-11-24 01:56:30,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:30,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760226314] [2024-11-24 01:56:30,164 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:30,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:32,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:33,376 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 52 proven. 0 refuted. 0 times theorem prover too weak. 124 trivial. 0 not checked. [2024-11-24 01:56:33,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:33,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760226314] [2024-11-24 01:56:33,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760226314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:33,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:33,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 01:56:33,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1385210015] [2024-11-24 01:56:33,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:33,377 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 01:56:33,378 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:33,379 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 01:56:33,379 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-24 01:56:33,379 INFO L87 Difference]: Start difference. First operand 1428 states and 1884 transitions. Second operand has 8 states, 8 states have (on average 49.0) internal successors, (392), 8 states have internal predecessors, (392), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:34,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:34,534 INFO L93 Difference]: Finished difference Result 3648 states and 4744 transitions. [2024-11-24 01:56:34,534 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-11-24 01:56:34,534 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 49.0) internal successors, (392), 8 states have internal predecessors, (392), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 480 [2024-11-24 01:56:34,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:34,541 INFO L225 Difference]: With dead ends: 3648 [2024-11-24 01:56:34,542 INFO L226 Difference]: Without dead ends: 2624 [2024-11-24 01:56:34,544 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2024-11-24 01:56:34,544 INFO L435 NwaCegarLoop]: 1144 mSDtfsCounter, 1278 mSDsluCounter, 4903 mSDsCounter, 0 mSdLazyCounter, 1395 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1281 SdHoareTripleChecker+Valid, 6047 SdHoareTripleChecker+Invalid, 1395 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1395 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:34,545 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1281 Valid, 6047 Invalid, 1395 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1395 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-24 01:56:34,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2624 states. [2024-11-24 01:56:34,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2624 to 2616. [2024-11-24 01:56:34,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2616 states, 2593 states have (on average 1.303895102198226) internal successors, (3381), 2593 states have internal predecessors, (3381), 21 states have call successors, (21), 1 states have call predecessors, (21), 1 states have return successors, (21), 21 states have call predecessors, (21), 21 states have call successors, (21) [2024-11-24 01:56:34,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2616 states to 2616 states and 3423 transitions. [2024-11-24 01:56:34,616 INFO L78 Accepts]: Start accepts. Automaton has 2616 states and 3423 transitions. Word has length 480 [2024-11-24 01:56:34,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:34,616 INFO L471 AbstractCegarLoop]: Abstraction has 2616 states and 3423 transitions. [2024-11-24 01:56:34,616 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 49.0) internal successors, (392), 8 states have internal predecessors, (392), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:34,617 INFO L276 IsEmpty]: Start isEmpty. Operand 2616 states and 3423 transitions. [2024-11-24 01:56:34,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 483 [2024-11-24 01:56:34,623 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:34,623 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:34,623 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64 [2024-11-24 01:56:34,623 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:34,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:34,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1940933154, now seen corresponding path program 1 times [2024-11-24 01:56:34,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:34,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410160820] [2024-11-24 01:56:34,625 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:34,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:36,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:37,324 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 27 proven. 0 refuted. 0 times theorem prover too weak. 150 trivial. 0 not checked. [2024-11-24 01:56:37,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:37,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410160820] [2024-11-24 01:56:37,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410160820] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:37,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:37,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 01:56:37,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1156038983] [2024-11-24 01:56:37,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:37,325 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 01:56:37,325 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:37,326 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 01:56:37,326 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:56:37,326 INFO L87 Difference]: Start difference. First operand 2616 states and 3423 transitions. Second operand has 7 states, 7 states have (on average 52.714285714285715) internal successors, (369), 7 states have internal predecessors, (369), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 01:56:37,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:37,916 INFO L93 Difference]: Finished difference Result 4963 states and 6455 transitions. [2024-11-24 01:56:37,917 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:56:37,917 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 52.714285714285715) internal successors, (369), 7 states have internal predecessors, (369), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 482 [2024-11-24 01:56:37,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:37,921 INFO L225 Difference]: With dead ends: 4963 [2024-11-24 01:56:37,921 INFO L226 Difference]: Without dead ends: 2648 [2024-11-24 01:56:37,924 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-11-24 01:56:37,924 INFO L435 NwaCegarLoop]: 560 mSDtfsCounter, 753 mSDsluCounter, 1680 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 755 SdHoareTripleChecker+Valid, 2240 SdHoareTripleChecker+Invalid, 812 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:37,924 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [755 Valid, 2240 Invalid, 812 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 01:56:37,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2648 states. [2024-11-24 01:56:37,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2648 to 2632. [2024-11-24 01:56:37,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2632 states, 2609 states have (on average 1.298965120735914) internal successors, (3389), 2609 states have internal predecessors, (3389), 21 states have call successors, (21), 1 states have call predecessors, (21), 1 states have return successors, (21), 21 states have call predecessors, (21), 21 states have call successors, (21) [2024-11-24 01:56:37,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2632 states to 2632 states and 3431 transitions. [2024-11-24 01:56:37,983 INFO L78 Accepts]: Start accepts. Automaton has 2632 states and 3431 transitions. Word has length 482 [2024-11-24 01:56:37,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:37,983 INFO L471 AbstractCegarLoop]: Abstraction has 2632 states and 3431 transitions. [2024-11-24 01:56:37,983 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 52.714285714285715) internal successors, (369), 7 states have internal predecessors, (369), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 01:56:37,984 INFO L276 IsEmpty]: Start isEmpty. Operand 2632 states and 3431 transitions. [2024-11-24 01:56:37,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 485 [2024-11-24 01:56:37,989 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:37,989 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:37,989 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65 [2024-11-24 01:56:37,989 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:37,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:37,990 INFO L85 PathProgramCache]: Analyzing trace with hash -616963008, now seen corresponding path program 1 times [2024-11-24 01:56:37,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:37,990 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242404181] [2024-11-24 01:56:37,990 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:37,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:39,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:40,607 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 150 trivial. 0 not checked. [2024-11-24 01:56:40,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:40,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242404181] [2024-11-24 01:56:40,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242404181] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:40,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:40,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:56:40,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [288968816] [2024-11-24 01:56:40,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:40,609 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:56:40,609 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:40,609 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:56:40,609 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:40,609 INFO L87 Difference]: Start difference. First operand 2632 states and 3431 transitions. Second operand has 6 states, 6 states have (on average 61.833333333333336) internal successors, (371), 6 states have internal predecessors, (371), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 01:56:41,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:41,201 INFO L93 Difference]: Finished difference Result 4943 states and 6405 transitions. [2024-11-24 01:56:41,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:56:41,202 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 61.833333333333336) internal successors, (371), 6 states have internal predecessors, (371), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 484 [2024-11-24 01:56:41,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:41,205 INFO L225 Difference]: With dead ends: 4943 [2024-11-24 01:56:41,205 INFO L226 Difference]: Without dead ends: 2648 [2024-11-24 01:56:41,207 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:56:41,207 INFO L435 NwaCegarLoop]: 560 mSDtfsCounter, 685 mSDsluCounter, 1673 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 686 SdHoareTripleChecker+Valid, 2233 SdHoareTripleChecker+Invalid, 810 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:41,207 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [686 Valid, 2233 Invalid, 810 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 01:56:41,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2648 states. [2024-11-24 01:56:41,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2648 to 2640. [2024-11-24 01:56:41,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2640 states, 2617 states have (on average 1.2980512036683225) internal successors, (3397), 2617 states have internal predecessors, (3397), 21 states have call successors, (21), 1 states have call predecessors, (21), 1 states have return successors, (21), 21 states have call predecessors, (21), 21 states have call successors, (21) [2024-11-24 01:56:41,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2640 states to 2640 states and 3439 transitions. [2024-11-24 01:56:41,272 INFO L78 Accepts]: Start accepts. Automaton has 2640 states and 3439 transitions. Word has length 484 [2024-11-24 01:56:41,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:41,272 INFO L471 AbstractCegarLoop]: Abstraction has 2640 states and 3439 transitions. [2024-11-24 01:56:41,272 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 61.833333333333336) internal successors, (371), 6 states have internal predecessors, (371), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 01:56:41,272 INFO L276 IsEmpty]: Start isEmpty. Operand 2640 states and 3439 transitions. [2024-11-24 01:56:41,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 487 [2024-11-24 01:56:41,277 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:41,278 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:41,278 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-11-24 01:56:41,278 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:41,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:41,279 INFO L85 PathProgramCache]: Analyzing trace with hash 196482588, now seen corresponding path program 1 times [2024-11-24 01:56:41,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:41,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147388903] [2024-11-24 01:56:41,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:41,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:43,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:44,422 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-24 01:56:44,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:44,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147388903] [2024-11-24 01:56:44,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147388903] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:44,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:44,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:56:44,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983168451] [2024-11-24 01:56:44,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:44,424 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:56:44,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:44,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:56:44,424 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:56:44,425 INFO L87 Difference]: Start difference. First operand 2640 states and 3439 transitions. Second operand has 6 states, 6 states have (on average 60.666666666666664) internal successors, (364), 6 states have internal predecessors, (364), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-24 01:56:45,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:45,020 INFO L93 Difference]: Finished difference Result 2650 states and 3447 transitions. [2024-11-24 01:56:45,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:56:45,021 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 60.666666666666664) internal successors, (364), 6 states have internal predecessors, (364), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 486 [2024-11-24 01:56:45,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:45,024 INFO L225 Difference]: With dead ends: 2650 [2024-11-24 01:56:45,024 INFO L226 Difference]: Without dead ends: 1448 [2024-11-24 01:56:45,025 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:56:45,026 INFO L435 NwaCegarLoop]: 560 mSDtfsCounter, 693 mSDsluCounter, 1673 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 695 SdHoareTripleChecker+Valid, 2233 SdHoareTripleChecker+Invalid, 810 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:45,026 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [695 Valid, 2233 Invalid, 810 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 01:56:45,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1448 states. [2024-11-24 01:56:45,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1448 to 1444. [2024-11-24 01:56:45,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1444 states, 1430 states have (on average 1.309090909090909) internal successors, (1872), 1430 states have internal predecessors, (1872), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 01:56:45,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1444 states to 1444 states and 1896 transitions. [2024-11-24 01:56:45,062 INFO L78 Accepts]: Start accepts. Automaton has 1444 states and 1896 transitions. Word has length 486 [2024-11-24 01:56:45,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:45,062 INFO L471 AbstractCegarLoop]: Abstraction has 1444 states and 1896 transitions. [2024-11-24 01:56:45,062 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 60.666666666666664) internal successors, (364), 6 states have internal predecessors, (364), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-24 01:56:45,062 INFO L276 IsEmpty]: Start isEmpty. Operand 1444 states and 1896 transitions. [2024-11-24 01:56:45,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 487 [2024-11-24 01:56:45,066 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:45,067 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:45,067 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable67 [2024-11-24 01:56:45,067 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:45,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:45,068 INFO L85 PathProgramCache]: Analyzing trace with hash -1224288658, now seen corresponding path program 1 times [2024-11-24 01:56:45,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:45,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694044500] [2024-11-24 01:56:45,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:45,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:47,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:49,687 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 141 trivial. 0 not checked. [2024-11-24 01:56:49,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:49,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694044500] [2024-11-24 01:56:49,688 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694044500] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:49,688 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:49,688 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-24 01:56:49,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085631999] [2024-11-24 01:56:49,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:49,689 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-24 01:56:49,689 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:49,689 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-24 01:56:49,689 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-11-24 01:56:49,689 INFO L87 Difference]: Start difference. First operand 1444 states and 1896 transitions. Second operand has 10 states, 10 states have (on average 38.1) internal successors, (381), 10 states have internal predecessors, (381), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:50,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:50,209 INFO L93 Difference]: Finished difference Result 2889 states and 3780 transitions. [2024-11-24 01:56:50,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-24 01:56:50,210 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 38.1) internal successors, (381), 10 states have internal predecessors, (381), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 486 [2024-11-24 01:56:50,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:50,212 INFO L225 Difference]: With dead ends: 2889 [2024-11-24 01:56:50,212 INFO L226 Difference]: Without dead ends: 1943 [2024-11-24 01:56:50,213 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2024-11-24 01:56:50,213 INFO L435 NwaCegarLoop]: 1176 mSDtfsCounter, 2402 mSDsluCounter, 7053 mSDsCounter, 0 mSdLazyCounter, 507 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2407 SdHoareTripleChecker+Valid, 8229 SdHoareTripleChecker+Invalid, 515 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 507 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:50,214 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2407 Valid, 8229 Invalid, 515 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 507 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 01:56:50,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1943 states. [2024-11-24 01:56:50,249 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1943 to 1486. [2024-11-24 01:56:50,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1486 states, 1470 states have (on average 1.3095238095238095) internal successors, (1925), 1470 states have internal predecessors, (1925), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-11-24 01:56:50,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1486 states to 1486 states and 1953 transitions. [2024-11-24 01:56:50,253 INFO L78 Accepts]: Start accepts. Automaton has 1486 states and 1953 transitions. Word has length 486 [2024-11-24 01:56:50,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:50,254 INFO L471 AbstractCegarLoop]: Abstraction has 1486 states and 1953 transitions. [2024-11-24 01:56:50,254 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 38.1) internal successors, (381), 10 states have internal predecessors, (381), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:56:50,254 INFO L276 IsEmpty]: Start isEmpty. Operand 1486 states and 1953 transitions. [2024-11-24 01:56:50,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 487 [2024-11-24 01:56:50,258 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:50,258 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:50,258 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-11-24 01:56:50,258 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:50,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:50,259 INFO L85 PathProgramCache]: Analyzing trace with hash 538858702, now seen corresponding path program 1 times [2024-11-24 01:56:50,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:50,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549405113] [2024-11-24 01:56:50,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:50,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:54,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:54,737 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 26 proven. 0 refuted. 0 times theorem prover too weak. 151 trivial. 0 not checked. [2024-11-24 01:56:54,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:54,737 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549405113] [2024-11-24 01:56:54,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549405113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:56:54,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:56:54,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 01:56:54,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148404914] [2024-11-24 01:56:54,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:56:54,738 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 01:56:54,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:56:54,739 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 01:56:54,739 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:56:54,739 INFO L87 Difference]: Start difference. First operand 1486 states and 1953 transitions. Second operand has 7 states, 7 states have (on average 53.142857142857146) internal successors, (372), 7 states have internal predecessors, (372), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 01:56:55,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:56:55,106 INFO L93 Difference]: Finished difference Result 3116 states and 4082 transitions. [2024-11-24 01:56:55,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 01:56:55,107 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 53.142857142857146) internal successors, (372), 7 states have internal predecessors, (372), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 486 [2024-11-24 01:56:55,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:56:55,109 INFO L225 Difference]: With dead ends: 3116 [2024-11-24 01:56:55,109 INFO L226 Difference]: Without dead ends: 1502 [2024-11-24 01:56:55,111 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-24 01:56:55,111 INFO L435 NwaCegarLoop]: 737 mSDtfsCounter, 835 mSDsluCounter, 2771 mSDsCounter, 0 mSdLazyCounter, 290 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 838 SdHoareTripleChecker+Valid, 3508 SdHoareTripleChecker+Invalid, 299 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 290 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 01:56:55,112 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [838 Valid, 3508 Invalid, 299 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 290 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 01:56:55,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1502 states. [2024-11-24 01:56:55,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1502 to 1494. [2024-11-24 01:56:55,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1494 states, 1478 states have (on average 1.3051420838971584) internal successors, (1929), 1478 states have internal predecessors, (1929), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-11-24 01:56:55,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1494 states to 1494 states and 1957 transitions. [2024-11-24 01:56:55,151 INFO L78 Accepts]: Start accepts. Automaton has 1494 states and 1957 transitions. Word has length 486 [2024-11-24 01:56:55,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:56:55,152 INFO L471 AbstractCegarLoop]: Abstraction has 1494 states and 1957 transitions. [2024-11-24 01:56:55,152 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 53.142857142857146) internal successors, (372), 7 states have internal predecessors, (372), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 01:56:55,152 INFO L276 IsEmpty]: Start isEmpty. Operand 1494 states and 1957 transitions. [2024-11-24 01:56:55,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 489 [2024-11-24 01:56:55,156 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:56:55,157 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:56:55,157 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-11-24 01:56:55,157 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:56:55,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:56:55,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1555488832, now seen corresponding path program 1 times [2024-11-24 01:56:55,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:56:55,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771007321] [2024-11-24 01:56:55,158 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:55,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:56:57,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:56:59,373 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 85 proven. 17 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-11-24 01:56:59,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:56:59,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771007321] [2024-11-24 01:56:59,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771007321] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:56:59,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1319861676] [2024-11-24 01:56:59,373 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:56:59,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:56:59,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:56:59,379 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:56:59,381 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-24 01:57:01,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:02,015 INFO L256 TraceCheckSpWp]: Trace formula consists of 2974 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-11-24 01:57:02,046 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:57:02,397 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 171 trivial. 0 not checked. [2024-11-24 01:57:02,398 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 01:57:02,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1319861676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:02,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 01:57:02,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [9] total 13 [2024-11-24 01:57:02,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1913030665] [2024-11-24 01:57:02,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:02,399 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:02,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:02,400 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:02,400 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2024-11-24 01:57:02,401 INFO L87 Difference]: Start difference. First operand 1494 states and 1957 transitions. Second operand has 6 states, 6 states have (on average 59.666666666666664) internal successors, (358), 6 states have internal predecessors, (358), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:57:03,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:03,025 INFO L93 Difference]: Finished difference Result 2812 states and 3658 transitions. [2024-11-24 01:57:03,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:57:03,025 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 59.666666666666664) internal successors, (358), 6 states have internal predecessors, (358), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 488 [2024-11-24 01:57:03,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:03,027 INFO L225 Difference]: With dead ends: 2812 [2024-11-24 01:57:03,027 INFO L226 Difference]: Without dead ends: 1502 [2024-11-24 01:57:03,029 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 496 GetRequests, 485 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2024-11-24 01:57:03,029 INFO L435 NwaCegarLoop]: 559 mSDtfsCounter, 699 mSDsluCounter, 1649 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 702 SdHoareTripleChecker+Valid, 2208 SdHoareTripleChecker+Invalid, 810 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:03,029 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [702 Valid, 2208 Invalid, 810 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 01:57:03,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1502 states. [2024-11-24 01:57:03,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1502 to 1498. [2024-11-24 01:57:03,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1498 states, 1482 states have (on average 1.3043184885290149) internal successors, (1933), 1482 states have internal predecessors, (1933), 14 states have call successors, (14), 1 states have call predecessors, (14), 1 states have return successors, (14), 14 states have call predecessors, (14), 14 states have call successors, (14) [2024-11-24 01:57:03,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1498 states to 1498 states and 1961 transitions. [2024-11-24 01:57:03,066 INFO L78 Accepts]: Start accepts. Automaton has 1498 states and 1961 transitions. Word has length 488 [2024-11-24 01:57:03,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:03,066 INFO L471 AbstractCegarLoop]: Abstraction has 1498 states and 1961 transitions. [2024-11-24 01:57:03,066 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 59.666666666666664) internal successors, (358), 6 states have internal predecessors, (358), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:57:03,066 INFO L276 IsEmpty]: Start isEmpty. Operand 1498 states and 1961 transitions. [2024-11-24 01:57:03,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2024-11-24 01:57:03,070 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:03,071 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:03,094 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-24 01:57:03,271 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:03,271 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:03,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:03,272 INFO L85 PathProgramCache]: Analyzing trace with hash 540170644, now seen corresponding path program 1 times [2024-11-24 01:57:03,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:03,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332439201] [2024-11-24 01:57:03,272 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:03,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:05,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:08,089 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 137 trivial. 0 not checked. [2024-11-24 01:57:08,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:08,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332439201] [2024-11-24 01:57:08,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332439201] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:08,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:57:08,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 01:57:08,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737097406] [2024-11-24 01:57:08,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:08,090 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 01:57:08,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:08,091 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 01:57:08,091 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:57:08,091 INFO L87 Difference]: Start difference. First operand 1498 states and 1961 transitions. Second operand has 9 states, 9 states have (on average 43.22222222222222) internal successors, (389), 9 states have internal predecessors, (389), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:09,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:09,881 INFO L93 Difference]: Finished difference Result 3719 states and 4791 transitions. [2024-11-24 01:57:09,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 01:57:09,881 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 43.22222222222222) internal successors, (389), 9 states have internal predecessors, (389), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 490 [2024-11-24 01:57:09,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:09,884 INFO L225 Difference]: With dead ends: 3719 [2024-11-24 01:57:09,884 INFO L226 Difference]: Without dead ends: 2612 [2024-11-24 01:57:09,886 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2024-11-24 01:57:09,886 INFO L435 NwaCegarLoop]: 897 mSDtfsCounter, 1900 mSDsluCounter, 4099 mSDsCounter, 0 mSdLazyCounter, 1987 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1901 SdHoareTripleChecker+Valid, 4996 SdHoareTripleChecker+Invalid, 1990 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1987 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:09,886 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1901 Valid, 4996 Invalid, 1990 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1987 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2024-11-24 01:57:09,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2612 states. [2024-11-24 01:57:09,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2612 to 1604. [2024-11-24 01:57:09,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1604 states, 1583 states have (on average 1.3057485786481364) internal successors, (2067), 1583 states have internal predecessors, (2067), 19 states have call successors, (19), 1 states have call predecessors, (19), 1 states have return successors, (19), 19 states have call predecessors, (19), 19 states have call successors, (19) [2024-11-24 01:57:09,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1604 states to 1604 states and 2105 transitions. [2024-11-24 01:57:09,921 INFO L78 Accepts]: Start accepts. Automaton has 1604 states and 2105 transitions. Word has length 490 [2024-11-24 01:57:09,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:09,921 INFO L471 AbstractCegarLoop]: Abstraction has 1604 states and 2105 transitions. [2024-11-24 01:57:09,921 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 43.22222222222222) internal successors, (389), 9 states have internal predecessors, (389), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:09,921 INFO L276 IsEmpty]: Start isEmpty. Operand 1604 states and 2105 transitions. [2024-11-24 01:57:09,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2024-11-24 01:57:09,923 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:09,924 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:09,924 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-11-24 01:57:09,924 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:09,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:09,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1888656980, now seen corresponding path program 1 times [2024-11-24 01:57:09,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:09,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223667493] [2024-11-24 01:57:09,924 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:09,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:13,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:15,570 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 4 proven. 115 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:15,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:15,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223667493] [2024-11-24 01:57:15,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223667493] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:57:15,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1335097065] [2024-11-24 01:57:15,570 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:15,571 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:15,571 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:57:15,572 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:57:15,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 01:57:18,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:18,655 INFO L256 TraceCheckSpWp]: Trace formula consists of 2976 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 01:57:18,664 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:57:18,748 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 74 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2024-11-24 01:57:18,748 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 01:57:18,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1335097065] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:18,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 01:57:18,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 15 [2024-11-24 01:57:18,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629963779] [2024-11-24 01:57:18,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:18,749 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:18,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:18,750 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:18,750 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 01:57:18,750 INFO L87 Difference]: Start difference. First operand 1604 states and 2105 transitions. Second operand has 6 states, 5 states have (on average 77.0) internal successors, (385), 6 states have internal predecessors, (385), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:18,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:18,845 INFO L93 Difference]: Finished difference Result 2799 states and 3644 transitions. [2024-11-24 01:57:18,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:57:18,846 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 77.0) internal successors, (385), 6 states have internal predecessors, (385), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 490 [2024-11-24 01:57:18,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:18,848 INFO L225 Difference]: With dead ends: 2799 [2024-11-24 01:57:18,848 INFO L226 Difference]: Without dead ends: 1604 [2024-11-24 01:57:18,849 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 487 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 01:57:18,850 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 0 mSDsluCounter, 3005 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3761 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:18,850 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3761 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:57:18,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2024-11-24 01:57:18,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1604. [2024-11-24 01:57:18,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1604 states, 1583 states have (on average 1.3025900189513582) internal successors, (2062), 1583 states have internal predecessors, (2062), 19 states have call successors, (19), 1 states have call predecessors, (19), 1 states have return successors, (19), 19 states have call predecessors, (19), 19 states have call successors, (19) [2024-11-24 01:57:18,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1604 states to 1604 states and 2100 transitions. [2024-11-24 01:57:18,957 INFO L78 Accepts]: Start accepts. Automaton has 1604 states and 2100 transitions. Word has length 490 [2024-11-24 01:57:18,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:18,958 INFO L471 AbstractCegarLoop]: Abstraction has 1604 states and 2100 transitions. [2024-11-24 01:57:18,958 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 77.0) internal successors, (385), 6 states have internal predecessors, (385), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:18,958 INFO L276 IsEmpty]: Start isEmpty. Operand 1604 states and 2100 transitions. [2024-11-24 01:57:18,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 493 [2024-11-24 01:57:18,962 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:18,963 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:18,990 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-24 01:57:19,163 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:19,164 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:19,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:19,164 INFO L85 PathProgramCache]: Analyzing trace with hash 149817504, now seen corresponding path program 1 times [2024-11-24 01:57:19,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:19,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115138123] [2024-11-24 01:57:19,164 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:19,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:20,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:23,004 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 4 proven. 116 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:23,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:23,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2115138123] [2024-11-24 01:57:23,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2115138123] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:57:23,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1656028701] [2024-11-24 01:57:23,004 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:23,004 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:23,004 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:57:23,006 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:57:23,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-24 01:57:26,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:26,043 INFO L256 TraceCheckSpWp]: Trace formula consists of 2982 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 01:57:26,051 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:57:26,136 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 57 proven. 0 refuted. 0 times theorem prover too weak. 123 trivial. 0 not checked. [2024-11-24 01:57:26,139 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 01:57:26,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1656028701] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:26,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 01:57:26,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 15 [2024-11-24 01:57:26,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [449306935] [2024-11-24 01:57:26,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:26,140 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:26,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:26,141 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:26,141 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 01:57:26,142 INFO L87 Difference]: Start difference. First operand 1604 states and 2100 transitions. Second operand has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 01:57:26,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:26,237 INFO L93 Difference]: Finished difference Result 2947 states and 3834 transitions. [2024-11-24 01:57:26,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:57:26,238 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) Word has length 492 [2024-11-24 01:57:26,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:26,240 INFO L225 Difference]: With dead ends: 2947 [2024-11-24 01:57:26,240 INFO L226 Difference]: Without dead ends: 1604 [2024-11-24 01:57:26,243 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 489 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 01:57:26,244 INFO L435 NwaCegarLoop]: 755 mSDtfsCounter, 0 mSDsluCounter, 3001 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3756 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:26,244 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3756 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:57:26,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1604 states. [2024-11-24 01:57:26,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1604 to 1604. [2024-11-24 01:57:26,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1604 states, 1583 states have (on average 1.29943145925458) internal successors, (2057), 1583 states have internal predecessors, (2057), 19 states have call successors, (19), 1 states have call predecessors, (19), 1 states have return successors, (19), 19 states have call predecessors, (19), 19 states have call successors, (19) [2024-11-24 01:57:26,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1604 states to 1604 states and 2095 transitions. [2024-11-24 01:57:26,294 INFO L78 Accepts]: Start accepts. Automaton has 1604 states and 2095 transitions. Word has length 492 [2024-11-24 01:57:26,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:26,295 INFO L471 AbstractCegarLoop]: Abstraction has 1604 states and 2095 transitions. [2024-11-24 01:57:26,295 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 01:57:26,295 INFO L276 IsEmpty]: Start isEmpty. Operand 1604 states and 2095 transitions. [2024-11-24 01:57:26,299 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 493 [2024-11-24 01:57:26,299 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:26,300 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:26,329 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-11-24 01:57:26,500 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:26,500 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:26,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:26,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1492645889, now seen corresponding path program 1 times [2024-11-24 01:57:26,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:26,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271385440] [2024-11-24 01:57:26,501 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:26,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:27,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:28,864 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 122 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:28,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:28,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271385440] [2024-11-24 01:57:28,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271385440] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:28,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:57:28,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:57:28,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982288335] [2024-11-24 01:57:28,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:28,865 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:28,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:28,866 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:28,866 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:57:28,866 INFO L87 Difference]: Start difference. First operand 1604 states and 2095 transitions. Second operand has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:29,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:29,612 INFO L93 Difference]: Finished difference Result 2427 states and 3195 transitions. [2024-11-24 01:57:29,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:57:29,612 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 492 [2024-11-24 01:57:29,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:29,615 INFO L225 Difference]: With dead ends: 2427 [2024-11-24 01:57:29,615 INFO L226 Difference]: Without dead ends: 1861 [2024-11-24 01:57:29,616 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-11-24 01:57:29,616 INFO L435 NwaCegarLoop]: 565 mSDtfsCounter, 979 mSDsluCounter, 1652 mSDsCounter, 0 mSdLazyCounter, 770 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 982 SdHoareTripleChecker+Valid, 2217 SdHoareTripleChecker+Invalid, 773 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 770 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:29,616 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [982 Valid, 2217 Invalid, 773 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 770 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 01:57:29,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1861 states. [2024-11-24 01:57:29,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1861 to 1361. [2024-11-24 01:57:29,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1361 states, 1343 states have (on average 1.3164556962025316) internal successors, (1768), 1343 states have internal predecessors, (1768), 16 states have call successors, (16), 1 states have call predecessors, (16), 1 states have return successors, (16), 16 states have call predecessors, (16), 16 states have call successors, (16) [2024-11-24 01:57:29,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1361 states to 1361 states and 1800 transitions. [2024-11-24 01:57:29,643 INFO L78 Accepts]: Start accepts. Automaton has 1361 states and 1800 transitions. Word has length 492 [2024-11-24 01:57:29,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:29,643 INFO L471 AbstractCegarLoop]: Abstraction has 1361 states and 1800 transitions. [2024-11-24 01:57:29,643 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:29,643 INFO L276 IsEmpty]: Start isEmpty. Operand 1361 states and 1800 transitions. [2024-11-24 01:57:29,646 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-11-24 01:57:29,646 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:29,646 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:29,646 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-11-24 01:57:29,646 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:29,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:29,647 INFO L85 PathProgramCache]: Analyzing trace with hash -540853783, now seen corresponding path program 1 times [2024-11-24 01:57:29,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:29,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396122091] [2024-11-24 01:57:29,647 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:29,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:29,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:31,010 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 140 trivial. 0 not checked. [2024-11-24 01:57:31,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:31,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396122091] [2024-11-24 01:57:31,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396122091] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:31,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:57:31,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:57:31,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360053982] [2024-11-24 01:57:31,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:31,011 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:31,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:31,012 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:31,012 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:57:31,013 INFO L87 Difference]: Start difference. First operand 1361 states and 1800 transitions. Second operand has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:31,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:31,674 INFO L93 Difference]: Finished difference Result 2350 states and 3088 transitions. [2024-11-24 01:57:31,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 01:57:31,675 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 493 [2024-11-24 01:57:31,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:31,676 INFO L225 Difference]: With dead ends: 2350 [2024-11-24 01:57:31,676 INFO L226 Difference]: Without dead ends: 1377 [2024-11-24 01:57:31,677 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:57:31,678 INFO L435 NwaCegarLoop]: 569 mSDtfsCounter, 715 mSDsluCounter, 1680 mSDsCounter, 0 mSdLazyCounter, 786 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 715 SdHoareTripleChecker+Valid, 2249 SdHoareTripleChecker+Invalid, 787 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 786 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:31,678 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [715 Valid, 2249 Invalid, 787 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 786 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 01:57:31,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1377 states. [2024-11-24 01:57:31,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1377 to 1369. [2024-11-24 01:57:31,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1369 states, 1351 states have (on average 1.3145817912657292) internal successors, (1776), 1351 states have internal predecessors, (1776), 16 states have call successors, (16), 1 states have call predecessors, (16), 1 states have return successors, (16), 16 states have call predecessors, (16), 16 states have call successors, (16) [2024-11-24 01:57:31,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1369 states to 1369 states and 1808 transitions. [2024-11-24 01:57:31,721 INFO L78 Accepts]: Start accepts. Automaton has 1369 states and 1808 transitions. Word has length 493 [2024-11-24 01:57:31,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:31,721 INFO L471 AbstractCegarLoop]: Abstraction has 1369 states and 1808 transitions. [2024-11-24 01:57:31,721 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:31,722 INFO L276 IsEmpty]: Start isEmpty. Operand 1369 states and 1808 transitions. [2024-11-24 01:57:31,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-11-24 01:57:31,726 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:31,726 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:31,726 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75 [2024-11-24 01:57:31,726 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:31,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:31,727 INFO L85 PathProgramCache]: Analyzing trace with hash -1811427721, now seen corresponding path program 1 times [2024-11-24 01:57:31,727 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:31,727 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026689169] [2024-11-24 01:57:31,727 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:31,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:35,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:37,639 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 121 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:37,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:37,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026689169] [2024-11-24 01:57:37,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026689169] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:37,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:57:37,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 01:57:37,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1227891595] [2024-11-24 01:57:37,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:37,640 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 01:57:37,640 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:37,641 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 01:57:37,641 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 01:57:37,641 INFO L87 Difference]: Start difference. First operand 1369 states and 1808 transitions. Second operand has 9 states, 9 states have (on average 51.77777777777778) internal successors, (466), 9 states have internal predecessors, (466), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:39,133 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:39,133 INFO L93 Difference]: Finished difference Result 3084 states and 4046 transitions. [2024-11-24 01:57:39,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 01:57:39,134 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 51.77777777777778) internal successors, (466), 9 states have internal predecessors, (466), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 493 [2024-11-24 01:57:39,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:39,136 INFO L225 Difference]: With dead ends: 3084 [2024-11-24 01:57:39,136 INFO L226 Difference]: Without dead ends: 2311 [2024-11-24 01:57:39,137 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2024-11-24 01:57:39,137 INFO L435 NwaCegarLoop]: 776 mSDtfsCounter, 1297 mSDsluCounter, 3614 mSDsCounter, 0 mSdLazyCounter, 1808 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1298 SdHoareTripleChecker+Valid, 4390 SdHoareTripleChecker+Invalid, 1811 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1808 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:39,137 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1298 Valid, 4390 Invalid, 1811 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1808 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-24 01:57:39,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2311 states. [2024-11-24 01:57:39,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2311 to 1877. [2024-11-24 01:57:39,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1877 states, 1855 states have (on average 1.2878706199460916) internal successors, (2389), 1855 states have internal predecessors, (2389), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 01:57:39,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1877 states to 1877 states and 2429 transitions. [2024-11-24 01:57:39,183 INFO L78 Accepts]: Start accepts. Automaton has 1877 states and 2429 transitions. Word has length 493 [2024-11-24 01:57:39,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:39,183 INFO L471 AbstractCegarLoop]: Abstraction has 1877 states and 2429 transitions. [2024-11-24 01:57:39,184 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 51.77777777777778) internal successors, (466), 9 states have internal predecessors, (466), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 01:57:39,184 INFO L276 IsEmpty]: Start isEmpty. Operand 1877 states and 2429 transitions. [2024-11-24 01:57:39,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-11-24 01:57:39,188 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:39,188 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:39,189 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76 [2024-11-24 01:57:39,189 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:39,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:39,189 INFO L85 PathProgramCache]: Analyzing trace with hash 189873430, now seen corresponding path program 1 times [2024-11-24 01:57:39,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:39,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564242084] [2024-11-24 01:57:39,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:39,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:42,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:44,399 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 4 proven. 115 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:44,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:44,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1564242084] [2024-11-24 01:57:44,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1564242084] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:57:44,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [472996401] [2024-11-24 01:57:44,400 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:44,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:44,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:57:44,401 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:57:44,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 01:57:48,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:48,028 INFO L256 TraceCheckSpWp]: Trace formula consists of 2985 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-24 01:57:48,038 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:57:48,385 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 113 proven. 6 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:48,385 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 01:57:48,871 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 119 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:48,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [472996401] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 01:57:48,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 01:57:48,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11, 8] total 22 [2024-11-24 01:57:48,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113701585] [2024-11-24 01:57:48,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:48,873 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 01:57:48,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:48,874 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 01:57:48,874 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2024-11-24 01:57:48,874 INFO L87 Difference]: Start difference. First operand 1877 states and 2429 transitions. Second operand has 7 states, 7 states have (on average 66.57142857142857) internal successors, (466), 7 states have internal predecessors, (466), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:49,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:49,075 INFO L93 Difference]: Finished difference Result 3498 states and 4515 transitions. [2024-11-24 01:57:49,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 01:57:49,076 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 66.57142857142857) internal successors, (466), 7 states have internal predecessors, (466), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 493 [2024-11-24 01:57:49,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:49,080 INFO L225 Difference]: With dead ends: 3498 [2024-11-24 01:57:49,080 INFO L226 Difference]: Without dead ends: 2689 [2024-11-24 01:57:49,082 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 998 GetRequests, 976 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2024-11-24 01:57:49,083 INFO L435 NwaCegarLoop]: 1328 mSDtfsCounter, 482 mSDsluCounter, 6040 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 482 SdHoareTripleChecker+Valid, 7368 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:49,083 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [482 Valid, 7368 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 01:57:49,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2689 states. [2024-11-24 01:57:49,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2689 to 2340. [2024-11-24 01:57:49,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2340 states, 2313 states have (on average 1.2689148292261132) internal successors, (2935), 2313 states have internal predecessors, (2935), 25 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 25 states have call predecessors, (25), 25 states have call successors, (25) [2024-11-24 01:57:49,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2340 states to 2340 states and 2985 transitions. [2024-11-24 01:57:49,153 INFO L78 Accepts]: Start accepts. Automaton has 2340 states and 2985 transitions. Word has length 493 [2024-11-24 01:57:49,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:49,153 INFO L471 AbstractCegarLoop]: Abstraction has 2340 states and 2985 transitions. [2024-11-24 01:57:49,153 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 66.57142857142857) internal successors, (466), 7 states have internal predecessors, (466), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:49,154 INFO L276 IsEmpty]: Start isEmpty. Operand 2340 states and 2985 transitions. [2024-11-24 01:57:49,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-11-24 01:57:49,161 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:49,161 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:49,192 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-24 01:57:49,362 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:49,362 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:49,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:49,363 INFO L85 PathProgramCache]: Analyzing trace with hash -74270233, now seen corresponding path program 1 times [2024-11-24 01:57:49,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:49,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210987508] [2024-11-24 01:57:49,363 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:49,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:49,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:50,237 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-24 01:57:50,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:50,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [210987508] [2024-11-24 01:57:50,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [210987508] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:50,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 01:57:50,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 01:57:50,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1387706556] [2024-11-24 01:57:50,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:50,238 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 01:57:50,238 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:50,238 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 01:57:50,239 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:57:50,239 INFO L87 Difference]: Start difference. First operand 2340 states and 2985 transitions. Second operand has 6 states, 6 states have (on average 73.0) internal successors, (438), 6 states have internal predecessors, (438), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:57:50,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:50,323 INFO L93 Difference]: Finished difference Result 4205 states and 5364 transitions. [2024-11-24 01:57:50,323 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 01:57:50,324 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 73.0) internal successors, (438), 6 states have internal predecessors, (438), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 493 [2024-11-24 01:57:50,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:50,326 INFO L225 Difference]: With dead ends: 4205 [2024-11-24 01:57:50,326 INFO L226 Difference]: Without dead ends: 2502 [2024-11-24 01:57:50,328 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 01:57:50,328 INFO L435 NwaCegarLoop]: 754 mSDtfsCounter, 15 mSDsluCounter, 2998 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 3752 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:50,328 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 3752 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 01:57:50,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2502 states. [2024-11-24 01:57:50,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2502 to 2502. [2024-11-24 01:57:50,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2502 states, 2475 states have (on average 1.2755555555555556) internal successors, (3157), 2475 states have internal predecessors, (3157), 25 states have call successors, (25), 1 states have call predecessors, (25), 1 states have return successors, (25), 25 states have call predecessors, (25), 25 states have call successors, (25) [2024-11-24 01:57:50,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2502 states to 2502 states and 3207 transitions. [2024-11-24 01:57:50,387 INFO L78 Accepts]: Start accepts. Automaton has 2502 states and 3207 transitions. Word has length 493 [2024-11-24 01:57:50,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:50,387 INFO L471 AbstractCegarLoop]: Abstraction has 2502 states and 3207 transitions. [2024-11-24 01:57:50,387 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 73.0) internal successors, (438), 6 states have internal predecessors, (438), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 01:57:50,388 INFO L276 IsEmpty]: Start isEmpty. Operand 2502 states and 3207 transitions. [2024-11-24 01:57:50,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 495 [2024-11-24 01:57:50,392 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:50,392 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:50,392 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78 [2024-11-24 01:57:50,392 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:50,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:50,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1589664243, now seen corresponding path program 1 times [2024-11-24 01:57:50,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:50,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499097007] [2024-11-24 01:57:50,393 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:50,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:57:52,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:54,473 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 4 proven. 115 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:57:54,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:57:54,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499097007] [2024-11-24 01:57:54,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499097007] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:57:54,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [622659173] [2024-11-24 01:57:54,473 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:54,473 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:57:54,473 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:57:54,478 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:57:54,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-24 01:57:57,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:57:57,898 INFO L256 TraceCheckSpWp]: Trace formula consists of 2988 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-24 01:57:57,907 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:57:58,241 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 149 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-11-24 01:57:58,241 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 01:57:58,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [622659173] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 01:57:58,241 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 01:57:58,241 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [11] total 17 [2024-11-24 01:57:58,241 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82726958] [2024-11-24 01:57:58,241 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 01:57:58,242 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 01:57:58,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:57:58,243 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 01:57:58,243 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2024-11-24 01:57:58,243 INFO L87 Difference]: Start difference. First operand 2502 states and 3207 transitions. Second operand has 8 states, 8 states have (on average 58.375) internal successors, (467), 8 states have internal predecessors, (467), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:59,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:57:59,032 INFO L93 Difference]: Finished difference Result 5212 states and 6689 transitions. [2024-11-24 01:57:59,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 01:57:59,032 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 58.375) internal successors, (467), 8 states have internal predecessors, (467), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 494 [2024-11-24 01:57:59,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:57:59,035 INFO L225 Difference]: With dead ends: 5212 [2024-11-24 01:57:59,035 INFO L226 Difference]: Without dead ends: 3567 [2024-11-24 01:57:59,037 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 489 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2024-11-24 01:57:59,037 INFO L435 NwaCegarLoop]: 565 mSDtfsCounter, 1755 mSDsluCounter, 2105 mSDsCounter, 0 mSdLazyCounter, 950 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1761 SdHoareTripleChecker+Valid, 2670 SdHoareTripleChecker+Invalid, 950 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 950 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 01:57:59,037 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1761 Valid, 2670 Invalid, 950 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 950 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 01:57:59,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3567 states. [2024-11-24 01:57:59,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3567 to 3234. [2024-11-24 01:57:59,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3234 states, 3192 states have (on average 1.2647243107769424) internal successors, (4037), 3192 states have internal predecessors, (4037), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-11-24 01:57:59,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3234 states to 3234 states and 4117 transitions. [2024-11-24 01:57:59,096 INFO L78 Accepts]: Start accepts. Automaton has 3234 states and 4117 transitions. Word has length 494 [2024-11-24 01:57:59,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:57:59,096 INFO L471 AbstractCegarLoop]: Abstraction has 3234 states and 4117 transitions. [2024-11-24 01:57:59,096 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 58.375) internal successors, (467), 8 states have internal predecessors, (467), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 01:57:59,096 INFO L276 IsEmpty]: Start isEmpty. Operand 3234 states and 4117 transitions. [2024-11-24 01:57:59,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 496 [2024-11-24 01:57:59,099 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:57:59,100 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:57:59,122 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-24 01:57:59,300 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable79 [2024-11-24 01:57:59,300 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:57:59,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:57:59,301 INFO L85 PathProgramCache]: Analyzing trace with hash -1556336006, now seen corresponding path program 1 times [2024-11-24 01:57:59,301 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:57:59,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457522570] [2024-11-24 01:57:59,301 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:57:59,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:58:02,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:58:07,388 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 82 proven. 38 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:58:07,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:58:07,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457522570] [2024-11-24 01:58:07,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457522570] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:58:07,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [666884071] [2024-11-24 01:58:07,389 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:58:07,389 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:58:07,389 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:58:07,391 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:58:07,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-24 01:58:11,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:58:11,692 INFO L256 TraceCheckSpWp]: Trace formula consists of 2991 conjuncts, 169 conjuncts are in the unsatisfiable core [2024-11-24 01:58:11,712 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:58:18,486 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 82 proven. 38 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:58:18,486 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 01:58:33,825 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 80 proven. 40 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:58:33,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [666884071] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 01:58:33,826 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 01:58:33,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 27, 28] total 69 [2024-11-24 01:58:33,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148586575] [2024-11-24 01:58:33,826 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 01:58:33,827 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 69 states [2024-11-24 01:58:33,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:58:33,828 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2024-11-24 01:58:33,828 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=428, Invalid=4264, Unknown=0, NotChecked=0, Total=4692 [2024-11-24 01:58:33,829 INFO L87 Difference]: Start difference. First operand 3234 states and 4117 transitions. Second operand has 69 states, 69 states have (on average 17.782608695652176) internal successors, (1227), 69 states have internal predecessors, (1227), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 01:59:38,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 01:59:38,358 INFO L93 Difference]: Finished difference Result 54514 states and 68654 transitions. [2024-11-24 01:59:38,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 301 states. [2024-11-24 01:59:38,359 INFO L78 Accepts]: Start accepts. Automaton has has 69 states, 69 states have (on average 17.782608695652176) internal successors, (1227), 69 states have internal predecessors, (1227), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) Word has length 495 [2024-11-24 01:59:38,359 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 01:59:38,387 INFO L225 Difference]: With dead ends: 54514 [2024-11-24 01:59:38,388 INFO L226 Difference]: Without dead ends: 52003 [2024-11-24 01:59:38,402 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1294 GetRequests, 939 SyntacticMatches, 0 SemanticMatches, 355 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48678 ImplicationChecksByTransitivity, 30.7s TimeCoverageRelationStatistics Valid=13819, Invalid=113273, Unknown=0, NotChecked=0, Total=127092 [2024-11-24 01:59:38,402 INFO L435 NwaCegarLoop]: 1579 mSDtfsCounter, 38803 mSDsluCounter, 63027 mSDsCounter, 0 mSdLazyCounter, 38453 mSolverCounterSat, 260 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 27.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 38808 SdHoareTripleChecker+Valid, 64606 SdHoareTripleChecker+Invalid, 38713 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.3s SdHoareTripleChecker+Time, 260 IncrementalHoareTripleChecker+Valid, 38453 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 31.4s IncrementalHoareTripleChecker+Time [2024-11-24 01:59:38,402 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [38808 Valid, 64606 Invalid, 38713 Unknown, 0 Unchecked, 0.3s Time], IncrementalHoareTripleChecker [260 Valid, 38453 Invalid, 0 Unknown, 0 Unchecked, 31.4s Time] [2024-11-24 01:59:38,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52003 states. [2024-11-24 01:59:38,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52003 to 19847. [2024-11-24 01:59:38,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19847 states, 19643 states have (on average 1.2565290434251388) internal successors, (24682), 19643 states have internal predecessors, (24682), 202 states have call successors, (202), 1 states have call predecessors, (202), 1 states have return successors, (202), 202 states have call predecessors, (202), 202 states have call successors, (202) [2024-11-24 01:59:39,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19847 states to 19847 states and 25086 transitions. [2024-11-24 01:59:39,013 INFO L78 Accepts]: Start accepts. Automaton has 19847 states and 25086 transitions. Word has length 495 [2024-11-24 01:59:39,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 01:59:39,014 INFO L471 AbstractCegarLoop]: Abstraction has 19847 states and 25086 transitions. [2024-11-24 01:59:39,014 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 69 states, 69 states have (on average 17.782608695652176) internal successors, (1227), 69 states have internal predecessors, (1227), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 01:59:39,015 INFO L276 IsEmpty]: Start isEmpty. Operand 19847 states and 25086 transitions. [2024-11-24 01:59:39,033 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-11-24 01:59:39,034 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 01:59:39,034 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 01:59:39,064 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-24 01:59:39,235 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:59:39,235 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 01:59:39,235 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 01:59:39,235 INFO L85 PathProgramCache]: Analyzing trace with hash 577744513, now seen corresponding path program 1 times [2024-11-24 01:59:39,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 01:59:39,235 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471873248] [2024-11-24 01:59:39,235 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:59:39,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 01:59:45,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:59:46,941 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 4 proven. 118 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:59:46,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 01:59:46,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1471873248] [2024-11-24 01:59:46,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1471873248] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:59:46,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1693148374] [2024-11-24 01:59:46,942 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 01:59:46,942 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 01:59:46,942 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 01:59:46,943 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 01:59:46,945 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-24 01:59:52,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 01:59:52,461 INFO L256 TraceCheckSpWp]: Trace formula consists of 2994 conjuncts, 74 conjuncts are in the unsatisfiable core [2024-11-24 01:59:52,477 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 01:59:54,730 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 154 proven. 4 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-24 01:59:54,730 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 01:59:57,972 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 118 proven. 4 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 01:59:57,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1693148374] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 01:59:57,972 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 01:59:57,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 12] total 31 [2024-11-24 01:59:57,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1157897254] [2024-11-24 01:59:57,972 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 01:59:57,973 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2024-11-24 01:59:57,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 01:59:57,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2024-11-24 01:59:57,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=125, Invalid=805, Unknown=0, NotChecked=0, Total=930 [2024-11-24 01:59:57,975 INFO L87 Difference]: Start difference. First operand 19847 states and 25086 transitions. Second operand has 31 states, 31 states have (on average 41.16129032258065) internal successors, (1276), 31 states have internal predecessors, (1276), 5 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 5 states have call predecessors, (18), 5 states have call successors, (18) [2024-11-24 02:00:01,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:00:01,652 INFO L93 Difference]: Finished difference Result 30717 states and 38834 transitions. [2024-11-24 02:00:01,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2024-11-24 02:00:01,653 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 31 states have (on average 41.16129032258065) internal successors, (1276), 31 states have internal predecessors, (1276), 5 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 5 states have call predecessors, (18), 5 states have call successors, (18) Word has length 496 [2024-11-24 02:00:01,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:00:01,669 INFO L225 Difference]: With dead ends: 30717 [2024-11-24 02:00:01,669 INFO L226 Difference]: Without dead ends: 20093 [2024-11-24 02:00:01,680 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1018 GetRequests, 972 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 415 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=381, Invalid=1875, Unknown=0, NotChecked=0, Total=2256 [2024-11-24 02:00:01,680 INFO L435 NwaCegarLoop]: 694 mSDtfsCounter, 888 mSDsluCounter, 11690 mSDsCounter, 0 mSdLazyCounter, 4731 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 888 SdHoareTripleChecker+Valid, 12384 SdHoareTripleChecker+Invalid, 4736 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 4731 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:00:01,681 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [888 Valid, 12384 Invalid, 4736 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 4731 Invalid, 0 Unknown, 0 Unchecked, 2.9s Time] [2024-11-24 02:00:01,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20093 states. [2024-11-24 02:00:02,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20093 to 19895. [2024-11-24 02:00:02,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19895 states, 19691 states have (on average 1.2563099893352292) internal successors, (24738), 19691 states have internal predecessors, (24738), 202 states have call successors, (202), 1 states have call predecessors, (202), 1 states have return successors, (202), 202 states have call predecessors, (202), 202 states have call successors, (202) [2024-11-24 02:00:02,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19895 states to 19895 states and 25142 transitions. [2024-11-24 02:00:02,094 INFO L78 Accepts]: Start accepts. Automaton has 19895 states and 25142 transitions. Word has length 496 [2024-11-24 02:00:02,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:00:02,094 INFO L471 AbstractCegarLoop]: Abstraction has 19895 states and 25142 transitions. [2024-11-24 02:00:02,094 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 31 states have (on average 41.16129032258065) internal successors, (1276), 31 states have internal predecessors, (1276), 5 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 5 states have call predecessors, (18), 5 states have call successors, (18) [2024-11-24 02:00:02,094 INFO L276 IsEmpty]: Start isEmpty. Operand 19895 states and 25142 transitions. [2024-11-24 02:00:02,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-11-24 02:00:02,110 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:00:02,110 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:00:02,142 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-24 02:00:02,311 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable81 [2024-11-24 02:00:02,311 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:00:02,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:00:02,311 INFO L85 PathProgramCache]: Analyzing trace with hash 790787429, now seen corresponding path program 1 times [2024-11-24 02:00:02,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:00:02,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403207931] [2024-11-24 02:00:02,312 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:00:02,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:00:04,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:00:07,492 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 2 proven. 117 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:00:07,492 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:00:07,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403207931] [2024-11-24 02:00:07,492 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403207931] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:00:07,492 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1515071351] [2024-11-24 02:00:07,492 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:00:07,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:00:07,493 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:00:07,494 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:00:07,495 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-24 02:00:11,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:00:11,674 INFO L256 TraceCheckSpWp]: Trace formula consists of 2992 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 02:00:11,681 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:00:11,761 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 154 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2024-11-24 02:00:11,761 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:00:11,761 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1515071351] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:00:11,762 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:00:11,762 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [13] total 17 [2024-11-24 02:00:11,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421483461] [2024-11-24 02:00:11,762 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:00:11,763 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:00:11,763 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:00:11,763 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:00:11,764 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2024-11-24 02:00:11,764 INFO L87 Difference]: Start difference. First operand 19895 states and 25142 transitions. Second operand has 6 states, 5 states have (on average 94.2) internal successors, (471), 6 states have internal predecessors, (471), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 02:00:12,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:00:12,183 INFO L93 Difference]: Finished difference Result 39399 states and 49738 transitions. [2024-11-24 02:00:12,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:00:12,184 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 94.2) internal successors, (471), 6 states have internal predecessors, (471), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 496 [2024-11-24 02:00:12,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:00:12,197 INFO L225 Difference]: With dead ends: 39399 [2024-11-24 02:00:12,197 INFO L226 Difference]: Without dead ends: 19895 [2024-11-24 02:00:12,205 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 511 GetRequests, 495 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2024-11-24 02:00:12,206 INFO L435 NwaCegarLoop]: 754 mSDtfsCounter, 0 mSDsluCounter, 2997 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3751 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:00:12,206 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3751 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:00:12,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19895 states. [2024-11-24 02:00:12,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19895 to 19895. [2024-11-24 02:00:12,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19895 states, 19691 states have (on average 1.2549895891524045) internal successors, (24712), 19691 states have internal predecessors, (24712), 202 states have call successors, (202), 1 states have call predecessors, (202), 1 states have return successors, (202), 202 states have call predecessors, (202), 202 states have call successors, (202) [2024-11-24 02:00:12,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19895 states to 19895 states and 25116 transitions. [2024-11-24 02:00:12,562 INFO L78 Accepts]: Start accepts. Automaton has 19895 states and 25116 transitions. Word has length 496 [2024-11-24 02:00:12,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:00:12,563 INFO L471 AbstractCegarLoop]: Abstraction has 19895 states and 25116 transitions. [2024-11-24 02:00:12,563 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 94.2) internal successors, (471), 6 states have internal predecessors, (471), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 02:00:12,563 INFO L276 IsEmpty]: Start isEmpty. Operand 19895 states and 25116 transitions. [2024-11-24 02:00:12,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2024-11-24 02:00:12,584 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:00:12,585 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:00:12,616 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-24 02:00:12,785 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable82 [2024-11-24 02:00:12,786 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:00:12,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:00:12,786 INFO L85 PathProgramCache]: Analyzing trace with hash 768773700, now seen corresponding path program 1 times [2024-11-24 02:00:12,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:00:12,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949096786] [2024-11-24 02:00:12,787 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:00:12,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:00:15,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:00:18,715 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 2 proven. 119 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:00:18,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:00:18,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949096786] [2024-11-24 02:00:18,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949096786] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:00:18,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [903605205] [2024-11-24 02:00:18,715 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:00:18,716 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:00:18,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:00:18,717 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:00:18,718 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-24 02:00:24,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:00:24,659 INFO L256 TraceCheckSpWp]: Trace formula consists of 2995 conjuncts, 242 conjuncts are in the unsatisfiable core [2024-11-24 02:00:24,673 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:00:29,256 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 8 proven. 128 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 02:00:29,256 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:00:39,711 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 8 proven. 128 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 02:00:39,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [903605205] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:00:39,711 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:00:39,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 50, 43] total 99 [2024-11-24 02:00:39,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1443296084] [2024-11-24 02:00:39,712 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:00:39,712 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 99 states [2024-11-24 02:00:39,713 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:00:39,714 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2024-11-24 02:00:39,715 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1016, Invalid=8686, Unknown=0, NotChecked=0, Total=9702 [2024-11-24 02:00:39,715 INFO L87 Difference]: Start difference. First operand 19895 states and 25116 transitions. Second operand has 99 states, 96 states have (on average 14.5625) internal successors, (1398), 99 states have internal predecessors, (1398), 11 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 9 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 02:01:04,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:01:04,468 INFO L93 Difference]: Finished difference Result 92603 states and 116076 transitions. [2024-11-24 02:01:04,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2024-11-24 02:01:04,469 INFO L78 Accepts]: Start accepts. Automaton has has 99 states, 96 states have (on average 14.5625) internal successors, (1398), 99 states have internal predecessors, (1398), 11 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 9 states have call predecessors, (18), 11 states have call successors, (18) Word has length 497 [2024-11-24 02:01:04,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:01:04,527 INFO L225 Difference]: With dead ends: 92603 [2024-11-24 02:01:04,528 INFO L226 Difference]: Without dead ends: 77369 [2024-11-24 02:01:04,542 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1187 GetRequests, 910 SyntacticMatches, 1 SemanticMatches, 276 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24163 ImplicationChecksByTransitivity, 14.8s TimeCoverageRelationStatistics Valid=7814, Invalid=69192, Unknown=0, NotChecked=0, Total=77006 [2024-11-24 02:01:04,543 INFO L435 NwaCegarLoop]: 1171 mSDtfsCounter, 9492 mSDsluCounter, 48786 mSDsCounter, 0 mSdLazyCounter, 20504 mSolverCounterSat, 54 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 11.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9500 SdHoareTripleChecker+Valid, 49957 SdHoareTripleChecker+Invalid, 20558 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.2s SdHoareTripleChecker+Time, 54 IncrementalHoareTripleChecker+Valid, 20504 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 12.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:01:04,543 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [9500 Valid, 49957 Invalid, 20558 Unknown, 0 Unchecked, 0.2s Time], IncrementalHoareTripleChecker [54 Valid, 20504 Invalid, 0 Unknown, 0 Unchecked, 12.9s Time] [2024-11-24 02:01:04,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77369 states. [2024-11-24 02:01:05,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77369 to 20701. [2024-11-24 02:01:05,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20701 states, 20473 states have (on average 1.2507204610951008) internal successors, (25606), 20473 states have internal predecessors, (25606), 226 states have call successors, (226), 1 states have call predecessors, (226), 1 states have return successors, (226), 226 states have call predecessors, (226), 226 states have call successors, (226) [2024-11-24 02:01:05,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20701 states to 20701 states and 26058 transitions. [2024-11-24 02:01:05,139 INFO L78 Accepts]: Start accepts. Automaton has 20701 states and 26058 transitions. Word has length 497 [2024-11-24 02:01:05,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:01:05,139 INFO L471 AbstractCegarLoop]: Abstraction has 20701 states and 26058 transitions. [2024-11-24 02:01:05,139 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 99 states, 96 states have (on average 14.5625) internal successors, (1398), 99 states have internal predecessors, (1398), 11 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 9 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 02:01:05,139 INFO L276 IsEmpty]: Start isEmpty. Operand 20701 states and 26058 transitions. [2024-11-24 02:01:05,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2024-11-24 02:01:05,153 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:01:05,153 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:01:05,179 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-24 02:01:05,354 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable83 [2024-11-24 02:01:05,354 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:01:05,354 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:01:05,354 INFO L85 PathProgramCache]: Analyzing trace with hash -1385373554, now seen corresponding path program 1 times [2024-11-24 02:01:05,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:01:05,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561912778] [2024-11-24 02:01:05,355 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:01:05,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:01:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:01:06,444 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-24 02:01:06,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:01:06,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561912778] [2024-11-24 02:01:06,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561912778] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:01:06,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:01:06,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:01:06,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1635401325] [2024-11-24 02:01:06,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:01:06,445 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:01:06,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:01:06,446 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:01:06,446 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:01:06,446 INFO L87 Difference]: Start difference. First operand 20701 states and 26058 transitions. Second operand has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 02:01:06,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:01:06,744 INFO L93 Difference]: Finished difference Result 37487 states and 47166 transitions. [2024-11-24 02:01:06,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:01:06,744 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 497 [2024-11-24 02:01:06,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:01:06,768 INFO L225 Difference]: With dead ends: 37487 [2024-11-24 02:01:06,768 INFO L226 Difference]: Without dead ends: 19405 [2024-11-24 02:01:06,783 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:01:06,784 INFO L435 NwaCegarLoop]: 754 mSDtfsCounter, 0 mSDsluCounter, 1498 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2252 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:01:06,784 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2252 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:01:06,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19405 states. [2024-11-24 02:01:07,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19405 to 19405. [2024-11-24 02:01:07,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19405 states, 19177 states have (on average 1.2504562757469886) internal successors, (23980), 19177 states have internal predecessors, (23980), 226 states have call successors, (226), 1 states have call predecessors, (226), 1 states have return successors, (226), 226 states have call predecessors, (226), 226 states have call successors, (226) [2024-11-24 02:01:07,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19405 states to 19405 states and 24432 transitions. [2024-11-24 02:01:07,402 INFO L78 Accepts]: Start accepts. Automaton has 19405 states and 24432 transitions. Word has length 497 [2024-11-24 02:01:07,403 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:01:07,403 INFO L471 AbstractCegarLoop]: Abstraction has 19405 states and 24432 transitions. [2024-11-24 02:01:07,403 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 02:01:07,403 INFO L276 IsEmpty]: Start isEmpty. Operand 19405 states and 24432 transitions. [2024-11-24 02:01:07,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 499 [2024-11-24 02:01:07,418 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:01:07,418 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:01:07,419 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84 [2024-11-24 02:01:07,419 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:01:07,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:01:07,419 INFO L85 PathProgramCache]: Analyzing trace with hash -415707967, now seen corresponding path program 1 times [2024-11-24 02:01:07,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:01:07,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984206337] [2024-11-24 02:01:07,420 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:01:07,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:01:07,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:01:09,805 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 119 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:01:09,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:01:09,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984206337] [2024-11-24 02:01:09,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984206337] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:01:09,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:01:09,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:01:09,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398103660] [2024-11-24 02:01:09,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:01:09,806 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:01:09,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:01:09,807 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:01:09,807 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:01:09,807 INFO L87 Difference]: Start difference. First operand 19405 states and 24432 transitions. Second operand has 6 states, 6 states have (on average 78.5) internal successors, (471), 6 states have internal predecessors, (471), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:01:10,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:01:10,238 INFO L93 Difference]: Finished difference Result 37963 states and 47866 transitions. [2024-11-24 02:01:10,239 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:01:10,239 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 78.5) internal successors, (471), 6 states have internal predecessors, (471), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 498 [2024-11-24 02:01:10,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:01:10,260 INFO L225 Difference]: With dead ends: 37963 [2024-11-24 02:01:10,260 INFO L226 Difference]: Without dead ends: 27009 [2024-11-24 02:01:10,270 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:01:10,271 INFO L435 NwaCegarLoop]: 1310 mSDtfsCounter, 534 mSDsluCounter, 4670 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 534 SdHoareTripleChecker+Valid, 5980 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:01:10,271 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [534 Valid, 5980 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:01:10,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27009 states. [2024-11-24 02:01:10,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27009 to 21109. [2024-11-24 02:01:10,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21109 states, 20793 states have (on average 1.2511903044293753) internal successors, (26016), 20793 states have internal predecessors, (26016), 314 states have call successors, (314), 1 states have call predecessors, (314), 1 states have return successors, (314), 314 states have call predecessors, (314), 314 states have call successors, (314) [2024-11-24 02:01:10,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21109 states to 21109 states and 26644 transitions. [2024-11-24 02:01:10,822 INFO L78 Accepts]: Start accepts. Automaton has 21109 states and 26644 transitions. Word has length 498 [2024-11-24 02:01:10,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:01:10,822 INFO L471 AbstractCegarLoop]: Abstraction has 21109 states and 26644 transitions. [2024-11-24 02:01:10,823 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 78.5) internal successors, (471), 6 states have internal predecessors, (471), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:01:10,823 INFO L276 IsEmpty]: Start isEmpty. Operand 21109 states and 26644 transitions. [2024-11-24 02:01:10,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 499 [2024-11-24 02:01:10,844 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:01:10,844 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:01:10,845 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-11-24 02:01:10,845 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:01:10,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:01:10,845 INFO L85 PathProgramCache]: Analyzing trace with hash -1936033725, now seen corresponding path program 1 times [2024-11-24 02:01:10,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:01:10,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582722154] [2024-11-24 02:01:10,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:01:10,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:01:14,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:01:18,095 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 39 proven. 82 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:01:18,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:01:18,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582722154] [2024-11-24 02:01:18,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582722154] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:01:18,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [996334081] [2024-11-24 02:01:18,096 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:01:18,096 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:01:18,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:01:18,097 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:01:18,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-24 02:01:24,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:01:24,080 INFO L256 TraceCheckSpWp]: Trace formula consists of 2996 conjuncts, 196 conjuncts are in the unsatisfiable core [2024-11-24 02:01:24,098 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:01:31,139 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 2 proven. 119 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:01:31,139 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:01:38,705 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 34 proven. 87 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 02:01:38,705 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [996334081] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:01:38,705 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:01:38,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 36, 21] total 65 [2024-11-24 02:01:38,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822570266] [2024-11-24 02:01:38,705 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:01:38,706 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 65 states [2024-11-24 02:01:38,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:01:38,707 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2024-11-24 02:01:38,707 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=564, Invalid=3596, Unknown=0, NotChecked=0, Total=4160 [2024-11-24 02:01:38,708 INFO L87 Difference]: Start difference. First operand 21109 states and 26644 transitions. Second operand has 65 states, 65 states have (on average 21.49230769230769) internal successors, (1397), 65 states have internal predecessors, (1397), 7 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) [2024-11-24 02:02:12,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:02:12,242 INFO L93 Difference]: Finished difference Result 80811 states and 100283 transitions. [2024-11-24 02:02:12,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 163 states. [2024-11-24 02:02:12,243 INFO L78 Accepts]: Start accepts. Automaton has has 65 states, 65 states have (on average 21.49230769230769) internal successors, (1397), 65 states have internal predecessors, (1397), 7 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) Word has length 498 [2024-11-24 02:02:12,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:02:12,286 INFO L225 Difference]: With dead ends: 80811 [2024-11-24 02:02:12,286 INFO L226 Difference]: Without dead ends: 66553 [2024-11-24 02:02:12,298 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1168 GetRequests, 944 SyntacticMatches, 0 SemanticMatches, 224 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14961 ImplicationChecksByTransitivity, 13.3s TimeCoverageRelationStatistics Valid=5507, Invalid=45343, Unknown=0, NotChecked=0, Total=50850 [2024-11-24 02:02:12,298 INFO L435 NwaCegarLoop]: 864 mSDtfsCounter, 9956 mSDsluCounter, 33724 mSDsCounter, 0 mSdLazyCounter, 33569 mSolverCounterSat, 33 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 18.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9956 SdHoareTripleChecker+Valid, 34588 SdHoareTripleChecker+Invalid, 33602 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.2s SdHoareTripleChecker+Time, 33 IncrementalHoareTripleChecker+Valid, 33569 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 20.7s IncrementalHoareTripleChecker+Time [2024-11-24 02:02:12,299 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [9956 Valid, 34588 Invalid, 33602 Unknown, 0 Unchecked, 0.2s Time], IncrementalHoareTripleChecker [33 Valid, 33569 Invalid, 0 Unknown, 0 Unchecked, 20.7s Time] [2024-11-24 02:02:12,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66553 states. [2024-11-24 02:02:12,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66553 to 24320. [2024-11-24 02:02:12,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24320 states, 24004 states have (on average 1.265830694884186) internal successors, (30385), 24004 states have internal predecessors, (30385), 314 states have call successors, (314), 1 states have call predecessors, (314), 1 states have return successors, (314), 314 states have call predecessors, (314), 314 states have call successors, (314) [2024-11-24 02:02:12,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24320 states to 24320 states and 31013 transitions. [2024-11-24 02:02:12,956 INFO L78 Accepts]: Start accepts. Automaton has 24320 states and 31013 transitions. Word has length 498 [2024-11-24 02:02:12,957 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:02:12,957 INFO L471 AbstractCegarLoop]: Abstraction has 24320 states and 31013 transitions. [2024-11-24 02:02:12,957 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 65 states, 65 states have (on average 21.49230769230769) internal successors, (1397), 65 states have internal predecessors, (1397), 7 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) [2024-11-24 02:02:12,957 INFO L276 IsEmpty]: Start isEmpty. Operand 24320 states and 31013 transitions. [2024-11-24 02:02:12,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 499 [2024-11-24 02:02:12,982 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:02:12,982 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:02:13,018 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-11-24 02:02:13,183 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:02:13,184 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:02:13,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:02:13,185 INFO L85 PathProgramCache]: Analyzing trace with hash -373273150, now seen corresponding path program 1 times [2024-11-24 02:02:13,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:02:13,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2041388427] [2024-11-24 02:02:13,185 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:02:13,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:02:21,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 02:02:21,101 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-24 02:02:29,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 02:02:30,119 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-24 02:02:30,119 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-24 02:02:30,120 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-24 02:02:30,122 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-11-24 02:02:30,125 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:02:30,572 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-24 02:02:30,575 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.11 02:02:30 BoogieIcfgContainer [2024-11-24 02:02:30,576 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-24 02:02:30,576 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-24 02:02:30,577 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-24 02:02:30,577 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-24 02:02:30,578 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 01:55:01" (3/4) ... [2024-11-24 02:02:30,580 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-11-24 02:02:30,582 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-24 02:02:30,584 INFO L158 Benchmark]: Toolchain (without parser) took 454622.24ms. Allocated memory was 117.4MB in the beginning and 3.2GB in the end (delta: 3.1GB). Free memory was 93.2MB in the beginning and 2.1GB in the end (delta: -2.0GB). Peak memory consumption was 1.0GB. Max. memory is 16.1GB. [2024-11-24 02:02:30,584 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 78.3MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 02:02:30,584 INFO L158 Benchmark]: CACSL2BoogieTranslator took 892.03ms. Allocated memory is still 117.4MB. Free memory was 92.9MB in the beginning and 54.3MB in the end (delta: 38.6MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-11-24 02:02:30,584 INFO L158 Benchmark]: Boogie Procedure Inliner took 329.32ms. Allocated memory is still 117.4MB. Free memory was 54.3MB in the beginning and 52.9MB in the end (delta: 1.4MB). Peak memory consumption was 30.7MB. Max. memory is 16.1GB. [2024-11-24 02:02:30,585 INFO L158 Benchmark]: Boogie Preprocessor took 505.35ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 52.9MB in the beginning and 282.9MB in the end (delta: -230.0MB). Peak memory consumption was 37.6MB. Max. memory is 16.1GB. [2024-11-24 02:02:30,585 INFO L158 Benchmark]: RCFGBuilder took 3901.98ms. Allocated memory is still 352.3MB. Free memory was 282.9MB in the beginning and 209.9MB in the end (delta: 73.0MB). Peak memory consumption was 177.0MB. Max. memory is 16.1GB. [2024-11-24 02:02:30,586 INFO L158 Benchmark]: TraceAbstraction took 448978.23ms. Allocated memory was 352.3MB in the beginning and 3.2GB in the end (delta: 2.8GB). Free memory was 209.9MB in the beginning and 2.1GB in the end (delta: -1.9GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2024-11-24 02:02:30,586 INFO L158 Benchmark]: Witness Printer took 5.71ms. Allocated memory is still 3.2GB. Free memory was 2.1GB in the beginning and 2.1GB in the end (delta: 169.8kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-24 02:02:30,587 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 78.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 892.03ms. Allocated memory is still 117.4MB. Free memory was 92.9MB in the beginning and 54.3MB in the end (delta: 38.6MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 329.32ms. Allocated memory is still 117.4MB. Free memory was 54.3MB in the beginning and 52.9MB in the end (delta: 1.4MB). Peak memory consumption was 30.7MB. Max. memory is 16.1GB. * Boogie Preprocessor took 505.35ms. Allocated memory was 117.4MB in the beginning and 352.3MB in the end (delta: 234.9MB). Free memory was 52.9MB in the beginning and 282.9MB in the end (delta: -230.0MB). Peak memory consumption was 37.6MB. Max. memory is 16.1GB. * RCFGBuilder took 3901.98ms. Allocated memory is still 352.3MB. Free memory was 282.9MB in the beginning and 209.9MB in the end (delta: 73.0MB). Peak memory consumption was 177.0MB. Max. memory is 16.1GB. * TraceAbstraction took 448978.23ms. Allocated memory was 352.3MB in the beginning and 3.2GB in the end (delta: 2.8GB). Free memory was 209.9MB in the beginning and 2.1GB in the end (delta: -1.9GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. * Witness Printer took 5.71ms. Allocated memory is still 3.2GB. Free memory was 2.1GB in the beginning and 2.1GB in the end (delta: 169.8kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 164, overapproximation of bitwiseOr at line 389, overapproximation of bitwiseOr at line 145, overapproximation of bitwiseAnd at line 221, overapproximation of bitwiseAnd at line 253, overapproximation of bitwiseAnd at line 635, overapproximation of bitwiseAnd at line 265, overapproximation of bitwiseAnd at line 692, overapproximation of bitwiseAnd at line 559, overapproximation of bitwiseAnd at line 165, overapproximation of bitwiseAnd at line 521, overapproximation of bitwiseAnd at line 277, overapproximation of bitwiseAnd at line 241, overapproximation of bitwiseAnd at line 301, overapproximation of bitwiseAnd at line 398, overapproximation of bitwiseAnd at line 129, overapproximation of bitwiseAnd at line 502, overapproximation of bitwiseAnd at line 289, overapproximation of bitwiseAnd at line 483, overapproximation of bitwiseAnd at line 654, overapproximation of bitwiseAnd at line 464, overapproximation of bitwiseAnd at line 766, overapproximation of bitwiseAnd at line 247, overapproximation of bitwiseAnd at line 540, overapproximation of bitwiseAnd at line 295, overapproximation of bitwiseAnd at line 229, overapproximation of bitwiseAnd at line 125, overapproximation of bitwiseAnd at line 271, overapproximation of bitwiseAnd at line 283, overapproximation of bitwiseAnd at line 616, overapproximation of bitwiseAnd at line 578. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 6); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (6 - 1); [L35] const SORT_13 mask_SORT_13 = (SORT_13)-1 >> (sizeof(SORT_13) * 8 - 5); [L36] const SORT_13 msb_SORT_13 = (SORT_13)1 << (5 - 1); [L38] const SORT_19 mask_SORT_19 = (SORT_19)-1 >> (sizeof(SORT_19) * 8 - 4); [L39] const SORT_19 msb_SORT_19 = (SORT_19)1 << (4 - 1); [L41] const SORT_60 mask_SORT_60 = (SORT_60)-1 >> (sizeof(SORT_60) * 8 - 3); [L42] const SORT_60 msb_SORT_60 = (SORT_60)1 << (3 - 1); [L44] const SORT_81 mask_SORT_81 = (SORT_81)-1 >> (sizeof(SORT_81) * 8 - 2); [L45] const SORT_81 msb_SORT_81 = (SORT_81)1 << (2 - 1); [L47] const SORT_13 var_15 = 16; [L48] const SORT_19 var_20 = 15; [L49] const SORT_19 var_25 = 14; [L50] const SORT_19 var_30 = 13; [L51] const SORT_19 var_35 = 12; [L52] const SORT_19 var_40 = 11; [L53] const SORT_19 var_45 = 10; [L54] const SORT_19 var_50 = 9; [L55] const SORT_19 var_55 = 8; [L56] const SORT_60 var_61 = 7; [L57] const SORT_60 var_66 = 6; [L58] const SORT_60 var_71 = 5; [L59] const SORT_60 var_76 = 4; [L60] const SORT_81 var_82 = 3; [L61] const SORT_81 var_87 = 2; [L62] const SORT_1 var_92 = 1; [L63] const SORT_13 var_105 = 17; [L64] const SORT_11 var_122 = 0; [L65] const SORT_1 var_152 = 0; [L66] const SORT_3 var_373 = 0; [L68] SORT_1 input_2; [L69] SORT_3 input_4; [L70] SORT_1 input_5; [L71] SORT_1 input_6; [L72] SORT_1 input_7; [L73] SORT_1 input_8; [L74] SORT_3 input_9; [L75] SORT_1 input_150; [L77] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L77] SORT_3 state_10 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L78] SORT_11 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L79] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L79] SORT_3 state_18 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L80] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L80] SORT_3 state_24 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L81] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L81] SORT_3 state_29 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L82] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L82] SORT_3 state_34 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L83] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L83] SORT_3 state_39 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L84] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L84] SORT_3 state_44 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L85] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L85] SORT_3 state_49 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L86] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L86] SORT_3 state_54 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L87] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L87] SORT_3 state_59 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L88] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L88] SORT_3 state_65 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L89] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L89] SORT_3 state_70 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L90] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L90] SORT_3 state_75 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L91] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L91] SORT_3 state_80 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L92] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L92] SORT_3 state_86 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L93] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L93] SORT_3 state_91 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L94] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L94] SORT_3 state_96 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L95] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L95] SORT_11 state_101 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L96] SORT_1 state_109 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L97] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L97] SORT_1 state_110 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L98] SORT_11 state_113 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L99] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L99] SORT_3 state_128 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L100] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L100] SORT_1 state_132 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L101] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L101] SORT_11 state_185 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L103] SORT_1 init_133_arg_1 = var_92; [L104] state_132 = init_133_arg_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L107] input_2 = __VERIFIER_nondet_uchar() [L108] input_4 = __VERIFIER_nondet_ushort() [L109] input_5 = __VERIFIER_nondet_uchar() [L110] input_6 = __VERIFIER_nondet_uchar() [L111] input_7 = __VERIFIER_nondet_uchar() [L112] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L112] input_7 = input_7 & mask_SORT_1 [L113] input_8 = __VERIFIER_nondet_uchar() [L114] input_9 = __VERIFIER_nondet_ushort() [L115] input_150 = __VERIFIER_nondet_uchar() [L117] SORT_1 var_134_arg_0 = input_7; [L118] SORT_1 var_134_arg_1 = state_132; [L119] SORT_1 var_134 = var_134_arg_0 == var_134_arg_1; [L120] SORT_1 var_135_arg_0 = var_92; [L121] SORT_1 var_135 = ~var_135_arg_0; [L122] SORT_1 var_136_arg_0 = var_134; [L123] SORT_1 var_136_arg_1 = var_135; VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_136_arg_0=0, var_136_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L124] EXPR var_136_arg_0 | var_136_arg_1 VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L124] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L125] EXPR var_136 & mask_SORT_1 VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] var_136 = var_136 & mask_SORT_1 [L126] SORT_1 constr_137_arg_0 = var_136; VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L127] CALL assume_abort_if_not(constr_137_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L127] RET assume_abort_if_not(constr_137_arg_0) VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L128] SORT_13 var_106_arg_0 = var_105; VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_106_arg_0=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] EXPR var_106_arg_0 & mask_SORT_13 VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] var_106_arg_0 = var_106_arg_0 & mask_SORT_13 [L130] SORT_11 var_106 = var_106_arg_0; [L131] SORT_11 var_107_arg_0 = state_101; [L132] SORT_11 var_107_arg_1 = var_106; [L133] SORT_1 var_107 = var_107_arg_0 == var_107_arg_1; [L134] SORT_1 var_138_arg_0 = var_107; [L135] SORT_1 var_138 = ~var_138_arg_0; [L136] SORT_1 var_139_arg_0 = input_6; [L137] SORT_1 var_139 = ~var_139_arg_0; [L138] SORT_1 var_140_arg_0 = var_138; [L139] SORT_1 var_140_arg_1 = var_139; VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_140_arg_0=-1, var_140_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L140] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L140] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L141] SORT_1 var_141_arg_0 = var_92; [L142] SORT_1 var_141 = ~var_141_arg_0; [L143] SORT_1 var_142_arg_0 = var_140; [L144] SORT_1 var_142_arg_1 = var_141; VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_142_arg_0=255, var_142_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L145] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L145] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L146] EXPR var_142 & mask_SORT_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] var_142 = var_142 & mask_SORT_1 [L147] SORT_1 constr_143_arg_0 = var_142; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L148] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L148] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L149] SORT_11 var_102_arg_0 = state_101; [L150] SORT_1 var_102 = var_102_arg_0 != 0; [L151] SORT_1 var_103_arg_0 = var_102; [L152] SORT_1 var_103 = ~var_103_arg_0; [L153] SORT_1 var_144_arg_0 = var_103; [L154] SORT_1 var_144 = ~var_144_arg_0; [L155] SORT_1 var_145_arg_0 = input_5; [L156] SORT_1 var_145 = ~var_145_arg_0; [L157] SORT_1 var_146_arg_0 = var_144; [L158] SORT_1 var_146_arg_1 = var_145; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_146_arg_0=-256, var_146_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L159] EXPR var_146_arg_0 | var_146_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L159] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L160] SORT_1 var_147_arg_0 = var_92; [L161] SORT_1 var_147 = ~var_147_arg_0; [L162] SORT_1 var_148_arg_0 = var_146; [L163] SORT_1 var_148_arg_1 = var_147; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_148_arg_0=255, var_148_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L164] EXPR var_148_arg_0 | var_148_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L164] SORT_1 var_148 = var_148_arg_0 | var_148_arg_1; [L165] EXPR var_148 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] var_148 = var_148 & mask_SORT_1 [L166] SORT_1 constr_149_arg_0 = var_148; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L167] CALL assume_abort_if_not(constr_149_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L167] RET assume_abort_if_not(constr_149_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L169] SORT_1 var_153_arg_0 = state_132; [L170] SORT_1 var_153_arg_1 = var_152; [L171] SORT_1 var_153_arg_2 = var_92; [L172] SORT_1 var_153 = var_153_arg_0 ? var_153_arg_1 : var_153_arg_2; [L173] SORT_1 var_111_arg_0 = state_110; [L174] SORT_1 var_111 = ~var_111_arg_0; [L175] SORT_1 var_112_arg_0 = state_109; [L176] SORT_1 var_112_arg_1 = var_111; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_112_arg_0=0, var_112_arg_1=-1, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L177] EXPR var_112_arg_0 & var_112_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L177] SORT_1 var_112 = var_112_arg_0 & var_112_arg_1; [L178] SORT_11 var_114_arg_0 = state_113; [L179] SORT_1 var_114 = var_114_arg_0 != 0; [L180] SORT_1 var_115_arg_0 = var_112; [L181] SORT_1 var_115_arg_1 = var_114; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115_arg_0=0, var_115_arg_1=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L182] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L182] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L183] SORT_1 var_116_arg_0 = state_109; [L184] SORT_1 var_116 = ~var_116_arg_0; [L185] SORT_1 var_117_arg_0 = input_6; [L186] SORT_1 var_117_arg_1 = var_116; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_117_arg_0=0, var_117_arg_1=-1, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L187] EXPR var_117_arg_0 & var_117_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L187] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L188] SORT_1 var_118_arg_0 = var_117; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_118_arg_0=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L189] EXPR var_118_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L189] var_118_arg_0 = var_118_arg_0 & mask_SORT_1 [L190] SORT_11 var_118 = var_118_arg_0; [L191] SORT_11 var_119_arg_0 = state_113; [L192] SORT_11 var_119_arg_1 = var_118; [L193] SORT_11 var_119 = var_119_arg_0 + var_119_arg_1; [L194] SORT_1 var_120_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_120_arg_0=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L195] EXPR var_120_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L195] var_120_arg_0 = var_120_arg_0 & mask_SORT_1 [L196] SORT_11 var_120 = var_120_arg_0; [L197] SORT_11 var_121_arg_0 = var_119; [L198] SORT_11 var_121_arg_1 = var_120; [L199] SORT_11 var_121 = var_121_arg_0 - var_121_arg_1; [L200] SORT_1 var_123_arg_0 = input_7; [L201] SORT_11 var_123_arg_1 = var_122; [L202] SORT_11 var_123_arg_2 = var_121; [L203] SORT_11 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_123=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L204] EXPR var_123 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L204] var_123 = var_123 & mask_SORT_11 [L205] SORT_11 var_124_arg_0 = var_123; [L206] SORT_1 var_124 = var_124_arg_0 != 0; [L207] SORT_1 var_125_arg_0 = var_124; [L208] SORT_1 var_125 = ~var_125_arg_0; [L209] SORT_1 var_126_arg_0 = var_115; [L210] SORT_1 var_126_arg_1 = var_125; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126_arg_0=0, var_126_arg_1=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L211] EXPR var_126_arg_0 & var_126_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L211] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L212] SORT_1 var_127_arg_0 = var_126; [L213] SORT_1 var_127 = ~var_127_arg_0; [L214] SORT_11 var_14_arg_0 = state_12; [L215] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L216] EXPR var_14 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L216] var_14 = var_14 & mask_SORT_13 [L217] SORT_13 var_97_arg_0 = var_14; [L218] SORT_1 var_97 = var_97_arg_0 != 0; [L219] SORT_1 var_98_arg_0 = var_97; [L220] SORT_1 var_98 = ~var_98_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=-1] [L221] EXPR var_98 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L221] var_98 = var_98 & mask_SORT_1 [L222] SORT_1 var_93_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_93_arg_0=1, var_98=0] [L223] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=0] [L223] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L224] SORT_13 var_93 = var_93_arg_0; [L225] SORT_13 var_94_arg_0 = var_14; [L226] SORT_13 var_94_arg_1 = var_93; [L227] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L228] SORT_81 var_88_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_88_arg_0=2, var_92=1, var_94=0, var_98=0] [L229] EXPR var_88_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_94=0, var_98=0] [L229] var_88_arg_0 = var_88_arg_0 & mask_SORT_81 [L230] SORT_13 var_88 = var_88_arg_0; [L231] SORT_13 var_89_arg_0 = var_14; [L232] SORT_13 var_89_arg_1 = var_88; [L233] SORT_1 var_89 = var_89_arg_0 == var_89_arg_1; [L234] SORT_81 var_83_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_83_arg_0=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L235] EXPR var_83_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L235] var_83_arg_0 = var_83_arg_0 & mask_SORT_81 [L236] SORT_13 var_83 = var_83_arg_0; [L237] SORT_13 var_84_arg_0 = var_14; [L238] SORT_13 var_84_arg_1 = var_83; [L239] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L240] SORT_60 var_77_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_77_arg_0=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L241] EXPR var_77_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L241] var_77_arg_0 = var_77_arg_0 & mask_SORT_60 [L242] SORT_13 var_77 = var_77_arg_0; [L243] SORT_13 var_78_arg_0 = var_14; [L244] SORT_13 var_78_arg_1 = var_77; [L245] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L246] SORT_60 var_72_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_72_arg_0=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L247] EXPR var_72_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L247] var_72_arg_0 = var_72_arg_0 & mask_SORT_60 [L248] SORT_13 var_72 = var_72_arg_0; [L249] SORT_13 var_73_arg_0 = var_14; [L250] SORT_13 var_73_arg_1 = var_72; [L251] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L252] SORT_60 var_67_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_67_arg_0=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L253] EXPR var_67_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L253] var_67_arg_0 = var_67_arg_0 & mask_SORT_60 [L254] SORT_13 var_67 = var_67_arg_0; [L255] SORT_13 var_68_arg_0 = var_14; [L256] SORT_13 var_68_arg_1 = var_67; [L257] SORT_1 var_68 = var_68_arg_0 == var_68_arg_1; [L258] SORT_60 var_62_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_62_arg_0=7, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L259] EXPR var_62_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L259] var_62_arg_0 = var_62_arg_0 & mask_SORT_60 [L260] SORT_13 var_62 = var_62_arg_0; [L261] SORT_13 var_63_arg_0 = var_14; [L262] SORT_13 var_63_arg_1 = var_62; [L263] SORT_1 var_63 = var_63_arg_0 == var_63_arg_1; [L264] SORT_19 var_56_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_56_arg_0=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L265] EXPR var_56_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L265] var_56_arg_0 = var_56_arg_0 & mask_SORT_19 [L266] SORT_13 var_56 = var_56_arg_0; [L267] SORT_13 var_57_arg_0 = var_14; [L268] SORT_13 var_57_arg_1 = var_56; [L269] SORT_1 var_57 = var_57_arg_0 == var_57_arg_1; [L270] SORT_19 var_51_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_51_arg_0=9, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L271] EXPR var_51_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L271] var_51_arg_0 = var_51_arg_0 & mask_SORT_19 [L272] SORT_13 var_51 = var_51_arg_0; [L273] SORT_13 var_52_arg_0 = var_14; [L274] SORT_13 var_52_arg_1 = var_51; [L275] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L276] SORT_19 var_46_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_46_arg_0=10, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L277] EXPR var_46_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L277] var_46_arg_0 = var_46_arg_0 & mask_SORT_19 [L278] SORT_13 var_46 = var_46_arg_0; [L279] SORT_13 var_47_arg_0 = var_14; [L280] SORT_13 var_47_arg_1 = var_46; [L281] SORT_1 var_47 = var_47_arg_0 == var_47_arg_1; [L282] SORT_19 var_41_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_41_arg_0=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L283] EXPR var_41_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L283] var_41_arg_0 = var_41_arg_0 & mask_SORT_19 [L284] SORT_13 var_41 = var_41_arg_0; [L285] SORT_13 var_42_arg_0 = var_14; [L286] SORT_13 var_42_arg_1 = var_41; [L287] SORT_1 var_42 = var_42_arg_0 == var_42_arg_1; [L288] SORT_19 var_36_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_36_arg_0=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L289] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L289] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L290] SORT_13 var_36 = var_36_arg_0; [L291] SORT_13 var_37_arg_0 = var_14; [L292] SORT_13 var_37_arg_1 = var_36; [L293] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L294] SORT_19 var_31_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_31_arg_0=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L295] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L295] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L296] SORT_13 var_31 = var_31_arg_0; [L297] SORT_13 var_32_arg_0 = var_14; [L298] SORT_13 var_32_arg_1 = var_31; [L299] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L300] SORT_19 var_26_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_26_arg_0=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L301] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L301] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L302] SORT_13 var_26 = var_26_arg_0; [L303] SORT_13 var_27_arg_0 = var_14; [L304] SORT_13 var_27_arg_1 = var_26; [L305] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L306] SORT_19 var_21_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_21_arg_0=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L307] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L307] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L308] SORT_13 var_21 = var_21_arg_0; [L309] SORT_13 var_22_arg_0 = var_14; [L310] SORT_13 var_22_arg_1 = var_21; [L311] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L312] SORT_13 var_16_arg_0 = var_14; [L313] SORT_13 var_16_arg_1 = var_15; [L314] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L315] SORT_1 var_17_arg_0 = var_16; [L316] SORT_3 var_17_arg_1 = state_10; [L317] SORT_3 var_17_arg_2 = input_9; [L318] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L319] SORT_1 var_23_arg_0 = var_22; [L320] SORT_3 var_23_arg_1 = state_18; [L321] SORT_3 var_23_arg_2 = var_17; [L322] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L323] SORT_1 var_28_arg_0 = var_27; [L324] SORT_3 var_28_arg_1 = state_24; [L325] SORT_3 var_28_arg_2 = var_23; [L326] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L327] SORT_1 var_33_arg_0 = var_32; [L328] SORT_3 var_33_arg_1 = state_29; [L329] SORT_3 var_33_arg_2 = var_28; [L330] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L331] SORT_1 var_38_arg_0 = var_37; [L332] SORT_3 var_38_arg_1 = state_34; [L333] SORT_3 var_38_arg_2 = var_33; [L334] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L335] SORT_1 var_43_arg_0 = var_42; [L336] SORT_3 var_43_arg_1 = state_39; [L337] SORT_3 var_43_arg_2 = var_38; [L338] SORT_3 var_43 = var_43_arg_0 ? var_43_arg_1 : var_43_arg_2; [L339] SORT_1 var_48_arg_0 = var_47; [L340] SORT_3 var_48_arg_1 = state_44; [L341] SORT_3 var_48_arg_2 = var_43; [L342] SORT_3 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L343] SORT_1 var_53_arg_0 = var_52; [L344] SORT_3 var_53_arg_1 = state_49; [L345] SORT_3 var_53_arg_2 = var_48; [L346] SORT_3 var_53 = var_53_arg_0 ? var_53_arg_1 : var_53_arg_2; [L347] SORT_1 var_58_arg_0 = var_57; [L348] SORT_3 var_58_arg_1 = state_54; [L349] SORT_3 var_58_arg_2 = var_53; [L350] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; [L351] SORT_1 var_64_arg_0 = var_63; [L352] SORT_3 var_64_arg_1 = state_59; [L353] SORT_3 var_64_arg_2 = var_58; [L354] SORT_3 var_64 = var_64_arg_0 ? var_64_arg_1 : var_64_arg_2; [L355] SORT_1 var_69_arg_0 = var_68; [L356] SORT_3 var_69_arg_1 = state_65; [L357] SORT_3 var_69_arg_2 = var_64; [L358] SORT_3 var_69 = var_69_arg_0 ? var_69_arg_1 : var_69_arg_2; [L359] SORT_1 var_74_arg_0 = var_73; [L360] SORT_3 var_74_arg_1 = state_70; [L361] SORT_3 var_74_arg_2 = var_69; [L362] SORT_3 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L363] SORT_1 var_79_arg_0 = var_78; [L364] SORT_3 var_79_arg_1 = state_75; [L365] SORT_3 var_79_arg_2 = var_74; [L366] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L367] SORT_1 var_85_arg_0 = var_84; [L368] SORT_3 var_85_arg_1 = state_80; [L369] SORT_3 var_85_arg_2 = var_79; [L370] SORT_3 var_85 = var_85_arg_0 ? var_85_arg_1 : var_85_arg_2; [L371] SORT_1 var_90_arg_0 = var_89; [L372] SORT_3 var_90_arg_1 = state_86; [L373] SORT_3 var_90_arg_2 = var_85; [L374] SORT_3 var_90 = var_90_arg_0 ? var_90_arg_1 : var_90_arg_2; [L375] SORT_1 var_95_arg_0 = var_94; [L376] SORT_3 var_95_arg_1 = state_91; [L377] SORT_3 var_95_arg_2 = var_90; [L378] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L379] SORT_1 var_99_arg_0 = var_98; [L380] SORT_3 var_99_arg_1 = state_96; [L381] SORT_3 var_99_arg_2 = var_95; [L382] SORT_3 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_99=65535] [L383] EXPR var_99 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L383] var_99 = var_99 & mask_SORT_3 [L384] SORT_3 var_129_arg_0 = state_128; [L385] SORT_3 var_129_arg_1 = var_99; [L386] SORT_1 var_129 = var_129_arg_0 == var_129_arg_1; [L387] SORT_1 var_130_arg_0 = var_127; [L388] SORT_1 var_130_arg_1 = var_129; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_130_arg_0=-1, var_130_arg_1=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L389] EXPR var_130_arg_0 | var_130_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L389] SORT_1 var_130 = var_130_arg_0 | var_130_arg_1; [L390] SORT_1 var_151_arg_0 = state_132; [L391] SORT_1 var_151_arg_1 = input_150; [L392] SORT_1 var_151_arg_2 = var_130; [L393] SORT_1 var_151 = var_151_arg_0 ? var_151_arg_1 : var_151_arg_2; [L394] SORT_1 var_154_arg_0 = var_151; [L395] SORT_1 var_154 = ~var_154_arg_0; [L396] SORT_1 var_155_arg_0 = var_153; [L397] SORT_1 var_155_arg_1 = var_154; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_155_arg_0=0, var_155_arg_1=-256, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L398] EXPR var_155_arg_0 & var_155_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L398] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L399] EXPR var_155 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] var_155 = var_155 & mask_SORT_1 [L400] SORT_1 bad_156_arg_0 = var_155; [L401] CALL __VERIFIER_assert(!(bad_156_arg_0)) [L21] COND FALSE !(!(cond)) [L401] RET __VERIFIER_assert(!(bad_156_arg_0)) [L403] SORT_11 var_186_arg_0 = state_185; [L404] SORT_13 var_186 = var_186_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L405] EXPR var_186 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L405] var_186 = var_186 & mask_SORT_13 [L406] SORT_13 var_236_arg_0 = var_186; [L407] SORT_13 var_236_arg_1 = var_15; [L408] SORT_1 var_236 = var_236_arg_0 == var_236_arg_1; [L409] SORT_1 var_237_arg_0 = input_6; [L410] SORT_1 var_237_arg_1 = var_236; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_237_arg_0=0, var_237_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L411] EXPR var_237_arg_0 & var_237_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L411] SORT_1 var_237 = var_237_arg_0 & var_237_arg_1; [L412] EXPR var_237 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L412] var_237 = var_237 & mask_SORT_1 [L413] SORT_1 var_372_arg_0 = var_237; [L414] SORT_3 var_372_arg_1 = input_4; [L415] SORT_3 var_372_arg_2 = state_10; [L416] SORT_3 var_372 = var_372_arg_0 ? var_372_arg_1 : var_372_arg_2; [L417] SORT_1 var_374_arg_0 = input_7; [L418] SORT_3 var_374_arg_1 = var_373; [L419] SORT_3 var_374_arg_2 = var_372; [L420] SORT_3 var_374 = var_374_arg_0 ? var_374_arg_1 : var_374_arg_2; [L421] SORT_3 next_375_arg_1 = var_374; [L422] SORT_1 var_160_arg_0 = input_6; [L423] SORT_1 var_160_arg_1 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_160_arg_0=0, var_160_arg_1=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L424] EXPR var_160_arg_0 | var_160_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L424] SORT_1 var_160 = var_160_arg_0 | var_160_arg_1; [L425] SORT_1 var_161_arg_0 = var_160; [L426] SORT_1 var_161_arg_1 = input_7; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161_arg_0=0, var_161_arg_1=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L427] EXPR var_161_arg_0 | var_161_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L427] SORT_1 var_161 = var_161_arg_0 | var_161_arg_1; [L428] EXPR var_161 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L428] var_161 = var_161 & mask_SORT_1 [L429] SORT_1 var_303_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_303_arg_0=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L430] EXPR var_303_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L430] var_303_arg_0 = var_303_arg_0 & mask_SORT_1 [L431] SORT_11 var_303 = var_303_arg_0; [L432] SORT_11 var_304_arg_0 = state_12; [L433] SORT_11 var_304_arg_1 = var_303; [L434] SORT_11 var_304 = var_304_arg_0 + var_304_arg_1; [L435] SORT_1 var_376_arg_0 = var_161; [L436] SORT_11 var_376_arg_1 = var_304; [L437] SORT_11 var_376_arg_2 = state_12; [L438] SORT_11 var_376 = var_376_arg_0 ? var_376_arg_1 : var_376_arg_2; [L439] SORT_1 var_377_arg_0 = input_7; [L440] SORT_11 var_377_arg_1 = var_122; [L441] SORT_11 var_377_arg_2 = var_376; [L442] SORT_11 var_377 = var_377_arg_0 ? var_377_arg_1 : var_377_arg_2; [L443] SORT_11 next_378_arg_1 = var_377; [L444] SORT_19 var_229_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_229_arg_0=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L445] EXPR var_229_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L445] var_229_arg_0 = var_229_arg_0 & mask_SORT_19 [L446] SORT_13 var_229 = var_229_arg_0; [L447] SORT_13 var_230_arg_0 = var_186; [L448] SORT_13 var_230_arg_1 = var_229; [L449] SORT_1 var_230 = var_230_arg_0 == var_230_arg_1; [L450] SORT_1 var_231_arg_0 = input_6; [L451] SORT_1 var_231_arg_1 = var_230; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_231_arg_0=0, var_231_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L452] EXPR var_231_arg_0 & var_231_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L452] SORT_1 var_231 = var_231_arg_0 & var_231_arg_1; [L453] EXPR var_231 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L453] var_231 = var_231 & mask_SORT_1 [L454] SORT_1 var_379_arg_0 = var_231; [L455] SORT_3 var_379_arg_1 = input_4; [L456] SORT_3 var_379_arg_2 = state_18; [L457] SORT_3 var_379 = var_379_arg_0 ? var_379_arg_1 : var_379_arg_2; [L458] SORT_1 var_380_arg_0 = input_7; [L459] SORT_3 var_380_arg_1 = var_373; [L460] SORT_3 var_380_arg_2 = var_379; [L461] SORT_3 var_380 = var_380_arg_0 ? var_380_arg_1 : var_380_arg_2; [L462] SORT_3 next_381_arg_1 = var_380; [L463] SORT_19 var_222_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_222_arg_0=14, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L464] EXPR var_222_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L464] var_222_arg_0 = var_222_arg_0 & mask_SORT_19 [L465] SORT_13 var_222 = var_222_arg_0; [L466] SORT_13 var_223_arg_0 = var_186; [L467] SORT_13 var_223_arg_1 = var_222; [L468] SORT_1 var_223 = var_223_arg_0 == var_223_arg_1; [L469] SORT_1 var_224_arg_0 = input_6; [L470] SORT_1 var_224_arg_1 = var_223; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_224_arg_0=0, var_224_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L471] EXPR var_224_arg_0 & var_224_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L471] SORT_1 var_224 = var_224_arg_0 & var_224_arg_1; [L472] EXPR var_224 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L472] var_224 = var_224 & mask_SORT_1 [L473] SORT_1 var_382_arg_0 = var_224; [L474] SORT_3 var_382_arg_1 = input_4; [L475] SORT_3 var_382_arg_2 = state_24; [L476] SORT_3 var_382 = var_382_arg_0 ? var_382_arg_1 : var_382_arg_2; [L477] SORT_1 var_383_arg_0 = input_7; [L478] SORT_3 var_383_arg_1 = var_373; [L479] SORT_3 var_383_arg_2 = var_382; [L480] SORT_3 var_383 = var_383_arg_0 ? var_383_arg_1 : var_383_arg_2; [L481] SORT_3 next_384_arg_1 = var_383; [L482] SORT_19 var_215_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_215_arg_0=13, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L483] EXPR var_215_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L483] var_215_arg_0 = var_215_arg_0 & mask_SORT_19 [L484] SORT_13 var_215 = var_215_arg_0; [L485] SORT_13 var_216_arg_0 = var_186; [L486] SORT_13 var_216_arg_1 = var_215; [L487] SORT_1 var_216 = var_216_arg_0 == var_216_arg_1; [L488] SORT_1 var_217_arg_0 = input_6; [L489] SORT_1 var_217_arg_1 = var_216; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_217_arg_0=0, var_217_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L490] EXPR var_217_arg_0 & var_217_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L490] SORT_1 var_217 = var_217_arg_0 & var_217_arg_1; [L491] EXPR var_217 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L491] var_217 = var_217 & mask_SORT_1 [L492] SORT_1 var_385_arg_0 = var_217; [L493] SORT_3 var_385_arg_1 = input_4; [L494] SORT_3 var_385_arg_2 = state_29; [L495] SORT_3 var_385 = var_385_arg_0 ? var_385_arg_1 : var_385_arg_2; [L496] SORT_1 var_386_arg_0 = input_7; [L497] SORT_3 var_386_arg_1 = var_373; [L498] SORT_3 var_386_arg_2 = var_385; [L499] SORT_3 var_386 = var_386_arg_0 ? var_386_arg_1 : var_386_arg_2; [L500] SORT_3 next_387_arg_1 = var_386; [L501] SORT_19 var_208_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_208_arg_0=12, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L502] EXPR var_208_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L502] var_208_arg_0 = var_208_arg_0 & mask_SORT_19 [L503] SORT_13 var_208 = var_208_arg_0; [L504] SORT_13 var_209_arg_0 = var_186; [L505] SORT_13 var_209_arg_1 = var_208; [L506] SORT_1 var_209 = var_209_arg_0 == var_209_arg_1; [L507] SORT_1 var_210_arg_0 = input_6; [L508] SORT_1 var_210_arg_1 = var_209; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_210_arg_0=0, var_210_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L509] EXPR var_210_arg_0 & var_210_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L509] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L510] EXPR var_210 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L510] var_210 = var_210 & mask_SORT_1 [L511] SORT_1 var_388_arg_0 = var_210; [L512] SORT_3 var_388_arg_1 = input_4; [L513] SORT_3 var_388_arg_2 = state_34; [L514] SORT_3 var_388 = var_388_arg_0 ? var_388_arg_1 : var_388_arg_2; [L515] SORT_1 var_389_arg_0 = input_7; [L516] SORT_3 var_389_arg_1 = var_373; [L517] SORT_3 var_389_arg_2 = var_388; [L518] SORT_3 var_389 = var_389_arg_0 ? var_389_arg_1 : var_389_arg_2; [L519] SORT_3 next_390_arg_1 = var_389; [L520] SORT_19 var_201_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_201_arg_0=11, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L521] EXPR var_201_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L521] var_201_arg_0 = var_201_arg_0 & mask_SORT_19 [L522] SORT_13 var_201 = var_201_arg_0; [L523] SORT_13 var_202_arg_0 = var_186; [L524] SORT_13 var_202_arg_1 = var_201; [L525] SORT_1 var_202 = var_202_arg_0 == var_202_arg_1; [L526] SORT_1 var_203_arg_0 = input_6; [L527] SORT_1 var_203_arg_1 = var_202; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_203_arg_0=0, var_203_arg_1=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L528] EXPR var_203_arg_0 & var_203_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L528] SORT_1 var_203 = var_203_arg_0 & var_203_arg_1; [L529] EXPR var_203 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L529] var_203 = var_203 & mask_SORT_1 [L530] SORT_1 var_391_arg_0 = var_203; [L531] SORT_3 var_391_arg_1 = input_4; [L532] SORT_3 var_391_arg_2 = state_39; [L533] SORT_3 var_391 = var_391_arg_0 ? var_391_arg_1 : var_391_arg_2; [L534] SORT_1 var_392_arg_0 = input_7; [L535] SORT_3 var_392_arg_1 = var_373; [L536] SORT_3 var_392_arg_2 = var_391; [L537] SORT_3 var_392 = var_392_arg_0 ? var_392_arg_1 : var_392_arg_2; [L538] SORT_3 next_393_arg_1 = var_392; [L539] SORT_19 var_194_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_194_arg_0=10, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L540] EXPR var_194_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L540] var_194_arg_0 = var_194_arg_0 & mask_SORT_19 [L541] SORT_13 var_194 = var_194_arg_0; [L542] SORT_13 var_195_arg_0 = var_186; [L543] SORT_13 var_195_arg_1 = var_194; [L544] SORT_1 var_195 = var_195_arg_0 == var_195_arg_1; [L545] SORT_1 var_196_arg_0 = input_6; [L546] SORT_1 var_196_arg_1 = var_195; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_196_arg_0=0, var_196_arg_1=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L547] EXPR var_196_arg_0 & var_196_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L547] SORT_1 var_196 = var_196_arg_0 & var_196_arg_1; [L548] EXPR var_196 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L548] var_196 = var_196 & mask_SORT_1 [L549] SORT_1 var_394_arg_0 = var_196; [L550] SORT_3 var_394_arg_1 = input_4; [L551] SORT_3 var_394_arg_2 = state_44; [L552] SORT_3 var_394 = var_394_arg_0 ? var_394_arg_1 : var_394_arg_2; [L553] SORT_1 var_395_arg_0 = input_7; [L554] SORT_3 var_395_arg_1 = var_373; [L555] SORT_3 var_395_arg_2 = var_394; [L556] SORT_3 var_395 = var_395_arg_0 ? var_395_arg_1 : var_395_arg_2; [L557] SORT_3 next_396_arg_1 = var_395; [L558] SORT_19 var_298_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_298_arg_0=9, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L559] EXPR var_298_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L559] var_298_arg_0 = var_298_arg_0 & mask_SORT_19 [L560] SORT_13 var_298 = var_298_arg_0; [L561] SORT_13 var_299_arg_0 = var_186; [L562] SORT_13 var_299_arg_1 = var_298; [L563] SORT_1 var_299 = var_299_arg_0 == var_299_arg_1; [L564] SORT_1 var_300_arg_0 = input_6; [L565] SORT_1 var_300_arg_1 = var_299; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_300_arg_0=0, var_300_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L566] EXPR var_300_arg_0 & var_300_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L566] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L567] EXPR var_300 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L567] var_300 = var_300 & mask_SORT_1 [L568] SORT_1 var_397_arg_0 = var_300; [L569] SORT_3 var_397_arg_1 = input_4; [L570] SORT_3 var_397_arg_2 = state_49; [L571] SORT_3 var_397 = var_397_arg_0 ? var_397_arg_1 : var_397_arg_2; [L572] SORT_1 var_398_arg_0 = input_7; [L573] SORT_3 var_398_arg_1 = var_373; [L574] SORT_3 var_398_arg_2 = var_397; [L575] SORT_3 var_398 = var_398_arg_0 ? var_398_arg_1 : var_398_arg_2; [L576] SORT_3 next_399_arg_1 = var_398; [L577] SORT_19 var_291_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_291_arg_0=8, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L578] EXPR var_291_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L578] var_291_arg_0 = var_291_arg_0 & mask_SORT_19 [L579] SORT_13 var_291 = var_291_arg_0; [L580] SORT_13 var_292_arg_0 = var_186; [L581] SORT_13 var_292_arg_1 = var_291; [L582] SORT_1 var_292 = var_292_arg_0 == var_292_arg_1; [L583] SORT_1 var_293_arg_0 = input_6; [L584] SORT_1 var_293_arg_1 = var_292; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_293_arg_0=0, var_293_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L585] EXPR var_293_arg_0 & var_293_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L585] SORT_1 var_293 = var_293_arg_0 & var_293_arg_1; [L586] EXPR var_293 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L586] var_293 = var_293 & mask_SORT_1 [L587] SORT_1 var_400_arg_0 = var_293; [L588] SORT_3 var_400_arg_1 = input_4; [L589] SORT_3 var_400_arg_2 = state_54; [L590] SORT_3 var_400 = var_400_arg_0 ? var_400_arg_1 : var_400_arg_2; [L591] SORT_1 var_401_arg_0 = input_7; [L592] SORT_3 var_401_arg_1 = var_373; [L593] SORT_3 var_401_arg_2 = var_400; [L594] SORT_3 var_401 = var_401_arg_0 ? var_401_arg_1 : var_401_arg_2; [L595] SORT_3 next_402_arg_1 = var_401; [L596] SORT_60 var_284_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_284_arg_0=7, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L597] EXPR var_284_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L597] var_284_arg_0 = var_284_arg_0 & mask_SORT_60 [L598] SORT_13 var_284 = var_284_arg_0; [L599] SORT_13 var_285_arg_0 = var_186; [L600] SORT_13 var_285_arg_1 = var_284; [L601] SORT_1 var_285 = var_285_arg_0 == var_285_arg_1; [L602] SORT_1 var_286_arg_0 = input_6; [L603] SORT_1 var_286_arg_1 = var_285; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_286_arg_0=0, var_286_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L604] EXPR var_286_arg_0 & var_286_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L604] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L605] EXPR var_286 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L605] var_286 = var_286 & mask_SORT_1 [L606] SORT_1 var_403_arg_0 = var_286; [L607] SORT_3 var_403_arg_1 = input_4; [L608] SORT_3 var_403_arg_2 = state_59; [L609] SORT_3 var_403 = var_403_arg_0 ? var_403_arg_1 : var_403_arg_2; [L610] SORT_1 var_404_arg_0 = input_7; [L611] SORT_3 var_404_arg_1 = var_373; [L612] SORT_3 var_404_arg_2 = var_403; [L613] SORT_3 var_404 = var_404_arg_0 ? var_404_arg_1 : var_404_arg_2; [L614] SORT_3 next_405_arg_1 = var_404; [L615] SORT_60 var_277_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_277_arg_0=6, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L616] EXPR var_277_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L616] var_277_arg_0 = var_277_arg_0 & mask_SORT_60 [L617] SORT_13 var_277 = var_277_arg_0; [L618] SORT_13 var_278_arg_0 = var_186; [L619] SORT_13 var_278_arg_1 = var_277; [L620] SORT_1 var_278 = var_278_arg_0 == var_278_arg_1; [L621] SORT_1 var_279_arg_0 = input_6; [L622] SORT_1 var_279_arg_1 = var_278; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_279_arg_0=0, var_279_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L623] EXPR var_279_arg_0 & var_279_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L623] SORT_1 var_279 = var_279_arg_0 & var_279_arg_1; [L624] EXPR var_279 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L624] var_279 = var_279 & mask_SORT_1 [L625] SORT_1 var_406_arg_0 = var_279; [L626] SORT_3 var_406_arg_1 = input_4; [L627] SORT_3 var_406_arg_2 = state_65; [L628] SORT_3 var_406 = var_406_arg_0 ? var_406_arg_1 : var_406_arg_2; [L629] SORT_1 var_407_arg_0 = input_7; [L630] SORT_3 var_407_arg_1 = var_373; [L631] SORT_3 var_407_arg_2 = var_406; [L632] SORT_3 var_407 = var_407_arg_0 ? var_407_arg_1 : var_407_arg_2; [L633] SORT_3 next_408_arg_1 = var_407; [L634] SORT_60 var_270_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_270_arg_0=5, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L635] EXPR var_270_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L635] var_270_arg_0 = var_270_arg_0 & mask_SORT_60 [L636] SORT_13 var_270 = var_270_arg_0; [L637] SORT_13 var_271_arg_0 = var_186; [L638] SORT_13 var_271_arg_1 = var_270; [L639] SORT_1 var_271 = var_271_arg_0 == var_271_arg_1; [L640] SORT_1 var_272_arg_0 = input_6; [L641] SORT_1 var_272_arg_1 = var_271; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_272_arg_0=0, var_272_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L642] EXPR var_272_arg_0 & var_272_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L642] SORT_1 var_272 = var_272_arg_0 & var_272_arg_1; [L643] EXPR var_272 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L643] var_272 = var_272 & mask_SORT_1 [L644] SORT_1 var_409_arg_0 = var_272; [L645] SORT_3 var_409_arg_1 = input_4; [L646] SORT_3 var_409_arg_2 = state_70; [L647] SORT_3 var_409 = var_409_arg_0 ? var_409_arg_1 : var_409_arg_2; [L648] SORT_1 var_410_arg_0 = input_7; [L649] SORT_3 var_410_arg_1 = var_373; [L650] SORT_3 var_410_arg_2 = var_409; [L651] SORT_3 var_410 = var_410_arg_0 ? var_410_arg_1 : var_410_arg_2; [L652] SORT_3 next_411_arg_1 = var_410; [L653] SORT_60 var_263_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_263_arg_0=4, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L654] EXPR var_263_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L654] var_263_arg_0 = var_263_arg_0 & mask_SORT_60 [L655] SORT_13 var_263 = var_263_arg_0; [L656] SORT_13 var_264_arg_0 = var_186; [L657] SORT_13 var_264_arg_1 = var_263; [L658] SORT_1 var_264 = var_264_arg_0 == var_264_arg_1; [L659] SORT_1 var_265_arg_0 = input_6; [L660] SORT_1 var_265_arg_1 = var_264; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_265_arg_0=0, var_265_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L661] EXPR var_265_arg_0 & var_265_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L661] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L662] EXPR var_265 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L662] var_265 = var_265 & mask_SORT_1 [L663] SORT_1 var_412_arg_0 = var_265; [L664] SORT_3 var_412_arg_1 = input_4; [L665] SORT_3 var_412_arg_2 = state_75; [L666] SORT_3 var_412 = var_412_arg_0 ? var_412_arg_1 : var_412_arg_2; [L667] SORT_1 var_413_arg_0 = input_7; [L668] SORT_3 var_413_arg_1 = var_373; [L669] SORT_3 var_413_arg_2 = var_412; [L670] SORT_3 var_413 = var_413_arg_0 ? var_413_arg_1 : var_413_arg_2; [L671] SORT_3 next_414_arg_1 = var_413; [L672] SORT_81 var_256_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_256_arg_0=3, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L673] EXPR var_256_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L673] var_256_arg_0 = var_256_arg_0 & mask_SORT_81 [L674] SORT_13 var_256 = var_256_arg_0; [L675] SORT_13 var_257_arg_0 = var_186; [L676] SORT_13 var_257_arg_1 = var_256; [L677] SORT_1 var_257 = var_257_arg_0 == var_257_arg_1; [L678] SORT_1 var_258_arg_0 = input_6; [L679] SORT_1 var_258_arg_1 = var_257; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_258_arg_0=0, var_258_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L680] EXPR var_258_arg_0 & var_258_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L680] SORT_1 var_258 = var_258_arg_0 & var_258_arg_1; [L681] EXPR var_258 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L681] var_258 = var_258 & mask_SORT_1 [L682] SORT_1 var_415_arg_0 = var_258; [L683] SORT_3 var_415_arg_1 = input_4; [L684] SORT_3 var_415_arg_2 = state_80; [L685] SORT_3 var_415 = var_415_arg_0 ? var_415_arg_1 : var_415_arg_2; [L686] SORT_1 var_416_arg_0 = input_7; [L687] SORT_3 var_416_arg_1 = var_373; [L688] SORT_3 var_416_arg_2 = var_415; [L689] SORT_3 var_416 = var_416_arg_0 ? var_416_arg_1 : var_416_arg_2; [L690] SORT_3 next_417_arg_1 = var_416; [L691] SORT_81 var_249_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_249_arg_0=2, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L692] EXPR var_249_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L692] var_249_arg_0 = var_249_arg_0 & mask_SORT_81 [L693] SORT_13 var_249 = var_249_arg_0; [L694] SORT_13 var_250_arg_0 = var_186; [L695] SORT_13 var_250_arg_1 = var_249; [L696] SORT_1 var_250 = var_250_arg_0 == var_250_arg_1; [L697] SORT_1 var_251_arg_0 = input_6; [L698] SORT_1 var_251_arg_1 = var_250; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_251_arg_0=0, var_251_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L699] EXPR var_251_arg_0 & var_251_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L699] SORT_1 var_251 = var_251_arg_0 & var_251_arg_1; [L700] EXPR var_251 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L700] var_251 = var_251 & mask_SORT_1 [L701] SORT_1 var_418_arg_0 = var_251; [L702] SORT_3 var_418_arg_1 = input_4; [L703] SORT_3 var_418_arg_2 = state_86; [L704] SORT_3 var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L705] SORT_1 var_419_arg_0 = input_7; [L706] SORT_3 var_419_arg_1 = var_373; [L707] SORT_3 var_419_arg_2 = var_418; [L708] SORT_3 var_419 = var_419_arg_0 ? var_419_arg_1 : var_419_arg_2; [L709] SORT_3 next_420_arg_1 = var_419; [L710] SORT_1 var_242_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_242_arg_0=1, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L711] EXPR var_242_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L711] var_242_arg_0 = var_242_arg_0 & mask_SORT_1 [L712] SORT_13 var_242 = var_242_arg_0; [L713] SORT_13 var_243_arg_0 = var_186; [L714] SORT_13 var_243_arg_1 = var_242; [L715] SORT_1 var_243 = var_243_arg_0 == var_243_arg_1; [L716] SORT_1 var_244_arg_0 = input_6; [L717] SORT_1 var_244_arg_1 = var_243; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_244_arg_0=0, var_244_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L718] EXPR var_244_arg_0 & var_244_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L718] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L719] EXPR var_244 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L719] var_244 = var_244 & mask_SORT_1 [L720] SORT_1 var_421_arg_0 = var_244; [L721] SORT_3 var_421_arg_1 = input_4; [L722] SORT_3 var_421_arg_2 = state_91; [L723] SORT_3 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; [L724] SORT_1 var_422_arg_0 = input_7; [L725] SORT_3 var_422_arg_1 = var_373; [L726] SORT_3 var_422_arg_2 = var_421; [L727] SORT_3 var_422 = var_422_arg_0 ? var_422_arg_1 : var_422_arg_2; [L728] SORT_3 next_423_arg_1 = var_422; [L729] SORT_13 var_187_arg_0 = var_186; [L730] SORT_1 var_187 = var_187_arg_0 != 0; [L731] SORT_1 var_188_arg_0 = var_187; [L732] SORT_1 var_188 = ~var_188_arg_0; [L733] SORT_1 var_189_arg_0 = input_6; [L734] SORT_1 var_189_arg_1 = var_188; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_189_arg_0=0, var_189_arg_1=-1, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L735] EXPR var_189_arg_0 & var_189_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L735] SORT_1 var_189 = var_189_arg_0 & var_189_arg_1; [L736] EXPR var_189 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L736] var_189 = var_189 & mask_SORT_1 [L737] SORT_1 var_424_arg_0 = var_189; [L738] SORT_3 var_424_arg_1 = input_4; [L739] SORT_3 var_424_arg_2 = state_96; [L740] SORT_3 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; [L741] SORT_1 var_425_arg_0 = input_7; [L742] SORT_3 var_425_arg_1 = var_373; [L743] SORT_3 var_425_arg_2 = var_424; [L744] SORT_3 var_425 = var_425_arg_0 ? var_425_arg_1 : var_425_arg_2; [L745] SORT_3 next_426_arg_1 = var_425; [L746] SORT_1 var_427_arg_0 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_427_arg_0=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L747] EXPR var_427_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L747] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L748] SORT_11 var_427 = var_427_arg_0; [L749] SORT_11 var_428_arg_0 = state_101; [L750] SORT_11 var_428_arg_1 = var_427; [L751] SORT_11 var_428 = var_428_arg_0 + var_428_arg_1; [L752] SORT_1 var_429_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_428=0, var_429_arg_0=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L753] EXPR var_429_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_428=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L753] var_429_arg_0 = var_429_arg_0 & mask_SORT_1 [L754] SORT_11 var_429 = var_429_arg_0; [L755] SORT_11 var_430_arg_0 = var_428; [L756] SORT_11 var_430_arg_1 = var_429; [L757] SORT_11 var_430 = var_430_arg_0 - var_430_arg_1; [L758] SORT_1 var_431_arg_0 = input_7; [L759] SORT_11 var_431_arg_1 = var_122; [L760] SORT_11 var_431_arg_2 = var_430; [L761] SORT_11 var_431 = var_431_arg_0 ? var_431_arg_1 : var_431_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_431=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L762] EXPR var_431 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L762] var_431 = var_431 & mask_SORT_11 [L763] SORT_11 next_432_arg_1 = var_431; [L764] SORT_1 var_333_arg_0 = state_109; [L765] SORT_1 var_333 = ~var_333_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_333=-1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L766] EXPR var_333 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L766] var_333 = var_333 & mask_SORT_1 [L767] SORT_1 var_329_arg_0 = input_8; [L768] SORT_1 var_329_arg_1 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329_arg_0=0, var_329_arg_1=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L769] EXPR var_329_arg_0 & var_329_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L769] SORT_1 var_329 = var_329_arg_0 & var_329_arg_1; [L770] SORT_1 var_330_arg_0 = state_109; [L771] SORT_1 var_330_arg_1 = var_329; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_330_arg_0=0, var_330_arg_1=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L772] EXPR var_330_arg_0 | var_330_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L772] SORT_1 var_330 = var_330_arg_0 | var_330_arg_1; [L773] SORT_1 var_433_arg_0 = var_333; [L774] SORT_1 var_433_arg_1 = var_330; [L775] SORT_1 var_433_arg_2 = state_109; [L776] SORT_1 var_433 = var_433_arg_0 ? var_433_arg_1 : var_433_arg_2; [L777] SORT_1 var_434_arg_0 = input_7; [L778] SORT_1 var_434_arg_1 = var_152; [L779] SORT_1 var_434_arg_2 = var_433; [L780] SORT_1 var_434 = var_434_arg_0 ? var_434_arg_1 : var_434_arg_2; [L781] SORT_1 next_435_arg_1 = var_434; [L782] SORT_1 var_341_arg_0 = var_126; [L783] SORT_1 var_341_arg_1 = state_110; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_341_arg_0=0, var_341_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L784] EXPR var_341_arg_0 | var_341_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L784] SORT_1 var_341 = var_341_arg_0 | var_341_arg_1; [L785] SORT_1 var_436_arg_0 = var_92; [L786] SORT_1 var_436_arg_1 = var_341; [L787] SORT_1 var_436_arg_2 = state_110; [L788] SORT_1 var_436 = var_436_arg_0 ? var_436_arg_1 : var_436_arg_2; [L789] SORT_1 var_437_arg_0 = input_7; [L790] SORT_1 var_437_arg_1 = var_152; [L791] SORT_1 var_437_arg_2 = var_436; [L792] SORT_1 var_437 = var_437_arg_0 ? var_437_arg_1 : var_437_arg_2; [L793] SORT_1 next_438_arg_1 = var_437; [L794] SORT_1 var_353_arg_0 = input_6; [L795] SORT_1 var_353_arg_1 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_353_arg_0=0, var_353_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L796] EXPR var_353_arg_0 | var_353_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L796] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L797] SORT_1 var_354_arg_0 = var_353; [L798] SORT_1 var_354_arg_1 = input_7; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_354_arg_0=0, var_354_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L799] EXPR var_354_arg_0 | var_354_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L799] SORT_1 var_354 = var_354_arg_0 | var_354_arg_1; [L800] SORT_1 var_355_arg_0 = var_354; [L801] SORT_1 var_355_arg_1 = state_109; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_355_arg_0=0, var_355_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L802] EXPR var_355_arg_0 | var_355_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L802] SORT_1 var_355 = var_355_arg_0 | var_355_arg_1; [L803] EXPR var_355 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L803] var_355 = var_355 & mask_SORT_1 [L804] SORT_1 var_439_arg_0 = var_355; [L805] SORT_11 var_439_arg_1 = var_123; [L806] SORT_11 var_439_arg_2 = state_113; [L807] SORT_11 var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L808] SORT_1 var_440_arg_0 = input_7; [L809] SORT_11 var_440_arg_1 = var_122; [L810] SORT_11 var_440_arg_2 = var_439; [L811] SORT_11 var_440 = var_440_arg_0 ? var_440_arg_1 : var_440_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_440=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L812] EXPR var_440 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L812] var_440 = var_440 & mask_SORT_11 [L813] SORT_11 next_441_arg_1 = var_440; [L814] SORT_1 var_338_arg_0 = var_329; [L815] SORT_1 var_338_arg_1 = var_333; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_338_arg_0=0, var_338_arg_1=1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L816] EXPR var_338_arg_0 & var_338_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L816] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L817] EXPR var_338 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L817] var_338 = var_338 & mask_SORT_1 [L818] SORT_1 var_442_arg_0 = var_338; [L819] SORT_3 var_442_arg_1 = input_4; [L820] SORT_3 var_442_arg_2 = state_128; [L821] SORT_3 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; [L822] SORT_1 var_443_arg_0 = input_7; [L823] SORT_3 var_443_arg_1 = var_373; [L824] SORT_3 var_443_arg_2 = var_442; [L825] SORT_3 var_443 = var_443_arg_0 ? var_443_arg_1 : var_443_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_443=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L826] EXPR var_443 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L826] var_443 = var_443 & mask_SORT_3 [L827] SORT_3 next_444_arg_1 = var_443; [L828] SORT_1 next_445_arg_1 = var_152; [L829] SORT_1 var_309_arg_0 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, next_444_arg_1=0, next_445_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_309_arg_0=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L830] EXPR var_309_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, next_444_arg_1=0, next_445_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L830] var_309_arg_0 = var_309_arg_0 & mask_SORT_1 [L831] SORT_11 var_309 = var_309_arg_0; [L832] SORT_11 var_310_arg_0 = state_185; [L833] SORT_11 var_310_arg_1 = var_309; [L834] SORT_11 var_310 = var_310_arg_0 + var_310_arg_1; [L835] SORT_1 var_446_arg_0 = var_161; [L836] SORT_11 var_446_arg_1 = var_310; [L837] SORT_11 var_446_arg_2 = state_185; [L838] SORT_11 var_446 = var_446_arg_0 ? var_446_arg_1 : var_446_arg_2; [L839] SORT_1 var_447_arg_0 = input_7; [L840] SORT_11 var_447_arg_1 = var_122; [L841] SORT_11 var_447_arg_2 = var_446; [L842] SORT_11 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L843] SORT_11 next_448_arg_1 = var_447; [L845] state_10 = next_375_arg_1 [L846] state_12 = next_378_arg_1 [L847] state_18 = next_381_arg_1 [L848] state_24 = next_384_arg_1 [L849] state_29 = next_387_arg_1 [L850] state_34 = next_390_arg_1 [L851] state_39 = next_393_arg_1 [L852] state_44 = next_396_arg_1 [L853] state_49 = next_399_arg_1 [L854] state_54 = next_402_arg_1 [L855] state_59 = next_405_arg_1 [L856] state_65 = next_408_arg_1 [L857] state_70 = next_411_arg_1 [L858] state_75 = next_414_arg_1 [L859] state_80 = next_417_arg_1 [L860] state_86 = next_420_arg_1 [L861] state_91 = next_423_arg_1 [L862] state_96 = next_426_arg_1 [L863] state_101 = next_432_arg_1 [L864] state_109 = next_435_arg_1 [L865] state_110 = next_438_arg_1 [L866] state_113 = next_441_arg_1 [L867] state_128 = next_444_arg_1 [L868] state_132 = next_445_arg_1 [L869] state_185 = next_448_arg_1 [L107] input_2 = __VERIFIER_nondet_uchar() [L108] input_4 = __VERIFIER_nondet_ushort() [L109] input_5 = __VERIFIER_nondet_uchar() [L110] input_6 = __VERIFIER_nondet_uchar() [L111] input_7 = __VERIFIER_nondet_uchar() [L112] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L112] input_7 = input_7 & mask_SORT_1 [L113] input_8 = __VERIFIER_nondet_uchar() [L114] input_9 = __VERIFIER_nondet_ushort() [L115] input_150 = __VERIFIER_nondet_uchar() [L117] SORT_1 var_134_arg_0 = input_7; [L118] SORT_1 var_134_arg_1 = state_132; [L119] SORT_1 var_134 = var_134_arg_0 == var_134_arg_1; [L120] SORT_1 var_135_arg_0 = var_92; [L121] SORT_1 var_135 = ~var_135_arg_0; [L122] SORT_1 var_136_arg_0 = var_134; [L123] SORT_1 var_136_arg_1 = var_135; VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_136_arg_0=0, var_136_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L124] EXPR var_136_arg_0 | var_136_arg_1 VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L124] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L125] EXPR var_136 & mask_SORT_1 VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] var_136 = var_136 & mask_SORT_1 [L126] SORT_1 constr_137_arg_0 = var_136; VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L127] CALL assume_abort_if_not(constr_137_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L127] RET assume_abort_if_not(constr_137_arg_0) VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L128] SORT_13 var_106_arg_0 = var_105; VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_106_arg_0=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] EXPR var_106_arg_0 & mask_SORT_13 VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] var_106_arg_0 = var_106_arg_0 & mask_SORT_13 [L130] SORT_11 var_106 = var_106_arg_0; [L131] SORT_11 var_107_arg_0 = state_101; [L132] SORT_11 var_107_arg_1 = var_106; [L133] SORT_1 var_107 = var_107_arg_0 == var_107_arg_1; [L134] SORT_1 var_138_arg_0 = var_107; [L135] SORT_1 var_138 = ~var_138_arg_0; [L136] SORT_1 var_139_arg_0 = input_6; [L137] SORT_1 var_139 = ~var_139_arg_0; [L138] SORT_1 var_140_arg_0 = var_138; [L139] SORT_1 var_140_arg_1 = var_139; VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_140_arg_0=-1, var_140_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L140] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L140] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L141] SORT_1 var_141_arg_0 = var_92; [L142] SORT_1 var_141 = ~var_141_arg_0; [L143] SORT_1 var_142_arg_0 = var_140; [L144] SORT_1 var_142_arg_1 = var_141; VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_142_arg_0=255, var_142_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L145] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L145] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L146] EXPR var_142 & mask_SORT_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] var_142 = var_142 & mask_SORT_1 [L147] SORT_1 constr_143_arg_0 = var_142; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L148] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L148] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L149] SORT_11 var_102_arg_0 = state_101; [L150] SORT_1 var_102 = var_102_arg_0 != 0; [L151] SORT_1 var_103_arg_0 = var_102; [L152] SORT_1 var_103 = ~var_103_arg_0; [L153] SORT_1 var_144_arg_0 = var_103; [L154] SORT_1 var_144 = ~var_144_arg_0; [L155] SORT_1 var_145_arg_0 = input_5; [L156] SORT_1 var_145 = ~var_145_arg_0; [L157] SORT_1 var_146_arg_0 = var_144; [L158] SORT_1 var_146_arg_1 = var_145; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_146_arg_0=-256, var_146_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L159] EXPR var_146_arg_0 | var_146_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L159] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L160] SORT_1 var_147_arg_0 = var_92; [L161] SORT_1 var_147 = ~var_147_arg_0; [L162] SORT_1 var_148_arg_0 = var_146; [L163] SORT_1 var_148_arg_1 = var_147; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_148_arg_0=254, var_148_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L164] EXPR var_148_arg_0 | var_148_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L164] SORT_1 var_148 = var_148_arg_0 | var_148_arg_1; [L165] EXPR var_148 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] var_148 = var_148 & mask_SORT_1 [L166] SORT_1 constr_149_arg_0 = var_148; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L167] CALL assume_abort_if_not(constr_149_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L167] RET assume_abort_if_not(constr_149_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L169] SORT_1 var_153_arg_0 = state_132; [L170] SORT_1 var_153_arg_1 = var_152; [L171] SORT_1 var_153_arg_2 = var_92; [L172] SORT_1 var_153 = var_153_arg_0 ? var_153_arg_1 : var_153_arg_2; [L173] SORT_1 var_111_arg_0 = state_110; [L174] SORT_1 var_111 = ~var_111_arg_0; [L175] SORT_1 var_112_arg_0 = state_109; [L176] SORT_1 var_112_arg_1 = var_111; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_112_arg_0=0, var_112_arg_1=-1, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L177] EXPR var_112_arg_0 & var_112_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L177] SORT_1 var_112 = var_112_arg_0 & var_112_arg_1; [L178] SORT_11 var_114_arg_0 = state_113; [L179] SORT_1 var_114 = var_114_arg_0 != 0; [L180] SORT_1 var_115_arg_0 = var_112; [L181] SORT_1 var_115_arg_1 = var_114; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115_arg_0=0, var_115_arg_1=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L182] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L182] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L183] SORT_1 var_116_arg_0 = state_109; [L184] SORT_1 var_116 = ~var_116_arg_0; [L185] SORT_1 var_117_arg_0 = input_6; [L186] SORT_1 var_117_arg_1 = var_116; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_117_arg_0=0, var_117_arg_1=-1, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L187] EXPR var_117_arg_0 & var_117_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L187] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L188] SORT_1 var_118_arg_0 = var_117; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_118_arg_0=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L189] EXPR var_118_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L189] var_118_arg_0 = var_118_arg_0 & mask_SORT_1 [L190] SORT_11 var_118 = var_118_arg_0; [L191] SORT_11 var_119_arg_0 = state_113; [L192] SORT_11 var_119_arg_1 = var_118; [L193] SORT_11 var_119 = var_119_arg_0 + var_119_arg_1; [L194] SORT_1 var_120_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_120_arg_0=257, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L195] EXPR var_120_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L195] var_120_arg_0 = var_120_arg_0 & mask_SORT_1 [L196] SORT_11 var_120 = var_120_arg_0; [L197] SORT_11 var_121_arg_0 = var_119; [L198] SORT_11 var_121_arg_1 = var_120; [L199] SORT_11 var_121 = var_121_arg_0 - var_121_arg_1; [L200] SORT_1 var_123_arg_0 = input_7; [L201] SORT_11 var_123_arg_1 = var_122; [L202] SORT_11 var_123_arg_2 = var_121; [L203] SORT_11 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_123=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L204] EXPR var_123 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L204] var_123 = var_123 & mask_SORT_11 [L205] SORT_11 var_124_arg_0 = var_123; [L206] SORT_1 var_124 = var_124_arg_0 != 0; [L207] SORT_1 var_125_arg_0 = var_124; [L208] SORT_1 var_125 = ~var_125_arg_0; [L209] SORT_1 var_126_arg_0 = var_115; [L210] SORT_1 var_126_arg_1 = var_125; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126_arg_0=0, var_126_arg_1=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L211] EXPR var_126_arg_0 & var_126_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L211] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L212] SORT_1 var_127_arg_0 = var_126; [L213] SORT_1 var_127 = ~var_127_arg_0; [L214] SORT_11 var_14_arg_0 = state_12; [L215] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L216] EXPR var_14 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L216] var_14 = var_14 & mask_SORT_13 [L217] SORT_13 var_97_arg_0 = var_14; [L218] SORT_1 var_97 = var_97_arg_0 != 0; [L219] SORT_1 var_98_arg_0 = var_97; [L220] SORT_1 var_98 = ~var_98_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=-1] [L221] EXPR var_98 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L221] var_98 = var_98 & mask_SORT_1 [L222] SORT_1 var_93_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_93_arg_0=1, var_98=1] [L223] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=1] [L223] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L224] SORT_13 var_93 = var_93_arg_0; [L225] SORT_13 var_94_arg_0 = var_14; [L226] SORT_13 var_94_arg_1 = var_93; [L227] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L228] SORT_81 var_88_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_88_arg_0=2, var_92=1, var_94=0, var_98=1] [L229] EXPR var_88_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_94=0, var_98=1] [L229] var_88_arg_0 = var_88_arg_0 & mask_SORT_81 [L230] SORT_13 var_88 = var_88_arg_0; [L231] SORT_13 var_89_arg_0 = var_14; [L232] SORT_13 var_89_arg_1 = var_88; [L233] SORT_1 var_89 = var_89_arg_0 == var_89_arg_1; [L234] SORT_81 var_83_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_83_arg_0=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L235] EXPR var_83_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L235] var_83_arg_0 = var_83_arg_0 & mask_SORT_81 [L236] SORT_13 var_83 = var_83_arg_0; [L237] SORT_13 var_84_arg_0 = var_14; [L238] SORT_13 var_84_arg_1 = var_83; [L239] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L240] SORT_60 var_77_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_77_arg_0=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L241] EXPR var_77_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L241] var_77_arg_0 = var_77_arg_0 & mask_SORT_60 [L242] SORT_13 var_77 = var_77_arg_0; [L243] SORT_13 var_78_arg_0 = var_14; [L244] SORT_13 var_78_arg_1 = var_77; [L245] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L246] SORT_60 var_72_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_72_arg_0=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L247] EXPR var_72_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L247] var_72_arg_0 = var_72_arg_0 & mask_SORT_60 [L248] SORT_13 var_72 = var_72_arg_0; [L249] SORT_13 var_73_arg_0 = var_14; [L250] SORT_13 var_73_arg_1 = var_72; [L251] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L252] SORT_60 var_67_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_67_arg_0=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L253] EXPR var_67_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L253] var_67_arg_0 = var_67_arg_0 & mask_SORT_60 [L254] SORT_13 var_67 = var_67_arg_0; [L255] SORT_13 var_68_arg_0 = var_14; [L256] SORT_13 var_68_arg_1 = var_67; [L257] SORT_1 var_68 = var_68_arg_0 == var_68_arg_1; [L258] SORT_60 var_62_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_62_arg_0=7, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L259] EXPR var_62_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L259] var_62_arg_0 = var_62_arg_0 & mask_SORT_60 [L260] SORT_13 var_62 = var_62_arg_0; [L261] SORT_13 var_63_arg_0 = var_14; [L262] SORT_13 var_63_arg_1 = var_62; [L263] SORT_1 var_63 = var_63_arg_0 == var_63_arg_1; [L264] SORT_19 var_56_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_56_arg_0=8, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L265] EXPR var_56_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L265] var_56_arg_0 = var_56_arg_0 & mask_SORT_19 [L266] SORT_13 var_56 = var_56_arg_0; [L267] SORT_13 var_57_arg_0 = var_14; [L268] SORT_13 var_57_arg_1 = var_56; [L269] SORT_1 var_57 = var_57_arg_0 == var_57_arg_1; [L270] SORT_19 var_51_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_51_arg_0=9, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L271] EXPR var_51_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L271] var_51_arg_0 = var_51_arg_0 & mask_SORT_19 [L272] SORT_13 var_51 = var_51_arg_0; [L273] SORT_13 var_52_arg_0 = var_14; [L274] SORT_13 var_52_arg_1 = var_51; [L275] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L276] SORT_19 var_46_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_46_arg_0=10, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L277] EXPR var_46_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L277] var_46_arg_0 = var_46_arg_0 & mask_SORT_19 [L278] SORT_13 var_46 = var_46_arg_0; [L279] SORT_13 var_47_arg_0 = var_14; [L280] SORT_13 var_47_arg_1 = var_46; [L281] SORT_1 var_47 = var_47_arg_0 == var_47_arg_1; [L282] SORT_19 var_41_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_41_arg_0=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L283] EXPR var_41_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L283] var_41_arg_0 = var_41_arg_0 & mask_SORT_19 [L284] SORT_13 var_41 = var_41_arg_0; [L285] SORT_13 var_42_arg_0 = var_14; [L286] SORT_13 var_42_arg_1 = var_41; [L287] SORT_1 var_42 = var_42_arg_0 == var_42_arg_1; [L288] SORT_19 var_36_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_36_arg_0=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L289] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L289] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L290] SORT_13 var_36 = var_36_arg_0; [L291] SORT_13 var_37_arg_0 = var_14; [L292] SORT_13 var_37_arg_1 = var_36; [L293] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L294] SORT_19 var_31_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_31_arg_0=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L295] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L295] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L296] SORT_13 var_31 = var_31_arg_0; [L297] SORT_13 var_32_arg_0 = var_14; [L298] SORT_13 var_32_arg_1 = var_31; [L299] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L300] SORT_19 var_26_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_26_arg_0=14, var_30=13, var_32=1, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L301] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_32=1, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L301] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L302] SORT_13 var_26 = var_26_arg_0; [L303] SORT_13 var_27_arg_0 = var_14; [L304] SORT_13 var_27_arg_1 = var_26; [L305] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L306] SORT_19 var_21_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_21_arg_0=15, var_25=14, var_27=0, var_30=13, var_32=1, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L307] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_27=0, var_30=13, var_32=1, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=1, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=1] [L307] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L308] SORT_13 var_21 = var_21_arg_0; [L309] SORT_13 var_22_arg_0 = var_14; [L310] SORT_13 var_22_arg_1 = var_21; [L311] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L312] SORT_13 var_16_arg_0 = var_14; [L313] SORT_13 var_16_arg_1 = var_15; [L314] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L315] SORT_1 var_17_arg_0 = var_16; [L316] SORT_3 var_17_arg_1 = state_10; [L317] SORT_3 var_17_arg_2 = input_9; [L318] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L319] SORT_1 var_23_arg_0 = var_22; [L320] SORT_3 var_23_arg_1 = state_18; [L321] SORT_3 var_23_arg_2 = var_17; [L322] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L323] SORT_1 var_28_arg_0 = var_27; [L324] SORT_3 var_28_arg_1 = state_24; [L325] SORT_3 var_28_arg_2 = var_23; [L326] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L327] SORT_1 var_33_arg_0 = var_32; [L328] SORT_3 var_33_arg_1 = state_29; [L329] SORT_3 var_33_arg_2 = var_28; [L330] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L331] SORT_1 var_38_arg_0 = var_37; [L332] SORT_3 var_38_arg_1 = state_34; [L333] SORT_3 var_38_arg_2 = var_33; [L334] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L335] SORT_1 var_43_arg_0 = var_42; [L336] SORT_3 var_43_arg_1 = state_39; [L337] SORT_3 var_43_arg_2 = var_38; [L338] SORT_3 var_43 = var_43_arg_0 ? var_43_arg_1 : var_43_arg_2; [L339] SORT_1 var_48_arg_0 = var_47; [L340] SORT_3 var_48_arg_1 = state_44; [L341] SORT_3 var_48_arg_2 = var_43; [L342] SORT_3 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L343] SORT_1 var_53_arg_0 = var_52; [L344] SORT_3 var_53_arg_1 = state_49; [L345] SORT_3 var_53_arg_2 = var_48; [L346] SORT_3 var_53 = var_53_arg_0 ? var_53_arg_1 : var_53_arg_2; [L347] SORT_1 var_58_arg_0 = var_57; [L348] SORT_3 var_58_arg_1 = state_54; [L349] SORT_3 var_58_arg_2 = var_53; [L350] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; [L351] SORT_1 var_64_arg_0 = var_63; [L352] SORT_3 var_64_arg_1 = state_59; [L353] SORT_3 var_64_arg_2 = var_58; [L354] SORT_3 var_64 = var_64_arg_0 ? var_64_arg_1 : var_64_arg_2; [L355] SORT_1 var_69_arg_0 = var_68; [L356] SORT_3 var_69_arg_1 = state_65; [L357] SORT_3 var_69_arg_2 = var_64; [L358] SORT_3 var_69 = var_69_arg_0 ? var_69_arg_1 : var_69_arg_2; [L359] SORT_1 var_74_arg_0 = var_73; [L360] SORT_3 var_74_arg_1 = state_70; [L361] SORT_3 var_74_arg_2 = var_69; [L362] SORT_3 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L363] SORT_1 var_79_arg_0 = var_78; [L364] SORT_3 var_79_arg_1 = state_75; [L365] SORT_3 var_79_arg_2 = var_74; [L366] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L367] SORT_1 var_85_arg_0 = var_84; [L368] SORT_3 var_85_arg_1 = state_80; [L369] SORT_3 var_85_arg_2 = var_79; [L370] SORT_3 var_85 = var_85_arg_0 ? var_85_arg_1 : var_85_arg_2; [L371] SORT_1 var_90_arg_0 = var_89; [L372] SORT_3 var_90_arg_1 = state_86; [L373] SORT_3 var_90_arg_2 = var_85; [L374] SORT_3 var_90 = var_90_arg_0 ? var_90_arg_1 : var_90_arg_2; [L375] SORT_1 var_95_arg_0 = var_94; [L376] SORT_3 var_95_arg_1 = state_91; [L377] SORT_3 var_95_arg_2 = var_90; [L378] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L379] SORT_1 var_99_arg_0 = var_98; [L380] SORT_3 var_99_arg_1 = state_96; [L381] SORT_3 var_99_arg_2 = var_95; [L382] SORT_3 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_99=0] [L383] EXPR var_99 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L383] var_99 = var_99 & mask_SORT_3 [L384] SORT_3 var_129_arg_0 = state_128; [L385] SORT_3 var_129_arg_1 = var_99; [L386] SORT_1 var_129 = var_129_arg_0 == var_129_arg_1; [L387] SORT_1 var_130_arg_0 = var_127; [L388] SORT_1 var_130_arg_1 = var_129; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_130_arg_0=-1, var_130_arg_1=1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L389] EXPR var_130_arg_0 | var_130_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L389] SORT_1 var_130 = var_130_arg_0 | var_130_arg_1; [L390] SORT_1 var_151_arg_0 = state_132; [L391] SORT_1 var_151_arg_1 = input_150; [L392] SORT_1 var_151_arg_2 = var_130; [L393] SORT_1 var_151 = var_151_arg_0 ? var_151_arg_1 : var_151_arg_2; [L394] SORT_1 var_154_arg_0 = var_151; [L395] SORT_1 var_154 = ~var_154_arg_0; [L396] SORT_1 var_155_arg_0 = var_153; [L397] SORT_1 var_155_arg_1 = var_154; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_155_arg_0=1, var_155_arg_1=-1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L398] EXPR var_155_arg_0 & var_155_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L398] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L399] EXPR var_155 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] var_155 = var_155 & mask_SORT_1 [L400] SORT_1 bad_156_arg_0 = var_155; [L401] CALL __VERIFIER_assert(!(bad_156_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 552 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 448.5s, OverallIterations: 88, TraceHistogramMax: 6, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.4s, AutomataDifference: 152.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 122349 SdHoareTripleChecker+Valid, 87.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 122216 mSDsluCounter, 349999 SdHoareTripleChecker+Invalid, 75.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 282326 mSDsCounter, 466 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 117865 IncrementalHoareTripleChecker+Invalid, 118331 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 466 mSolverCounterUnsat, 67673 mSDtfsCounter, 117865 mSolverCounterSat, 1.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 8876 GetRequests, 7536 SyntacticMatches, 2 SemanticMatches, 1338 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88573 ImplicationChecksByTransitivity, 64.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=24320occurred in iteration=87, InterpolantAutomatonStates: 1096, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 6.0s AutomataMinimizationTime, 87 MinimizatonAttempts, 141378 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 4.0s SsaConstructionTime, 99.7s SatisfiabilityAnalysisTime, 141.1s InterpolantComputationTime, 36668 NumberOfCodeBlocks, 36668 NumberOfCodeBlocksAsserted, 99 NumberOfCheckSat, 38546 ConstructedInterpolants, 0 QuantifiedInterpolants, 236116 SizeOfPredicates, 86 NumberOfNonLiveVariables, 30802 ConjunctsInSsa, 792 ConjunctsInUnsatCore, 103 InterpolantComputations, 83 PerfectInterpolantSequences, 11121/12631 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-24 02:02:30,659 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 222be94abfdbb514b1917b4bfb3a2a13389b64e1e049c782003790d790f6753f --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 02:02:33,544 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 02:02:33,655 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-24 02:02:33,662 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 02:02:33,662 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 02:02:33,693 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 02:02:33,694 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 02:02:33,694 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 02:02:33,695 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 02:02:33,695 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 02:02:33,695 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 02:02:33,695 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 02:02:33,695 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 02:02:33,696 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 02:02:33,696 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 02:02:33,696 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 02:02:33,696 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 02:02:33,696 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 02:02:33,696 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 02:02:33,697 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 02:02:33,698 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 02:02:33,698 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 02:02:33,698 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:02:33,698 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:02:33,698 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:02:33,698 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:02:33,699 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 02:02:33,699 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:02:33,699 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:02:33,699 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:02:33,699 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:02:33,699 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 02:02:33,699 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 02:02:33,700 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 02:02:33,701 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 02:02:33,701 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 222be94abfdbb514b1917b4bfb3a2a13389b64e1e049c782003790d790f6753f [2024-11-24 02:02:34,002 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 02:02:34,011 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 02:02:34,014 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 02:02:34,015 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 02:02:34,016 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 02:02:34,017 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 02:02:37,074 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/246dbb511/82f8b1a27fdb4a39864ed698bd3d7e9d/FLAG27d87a5f6 [2024-11-24 02:02:37,369 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 02:02:37,370 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 02:02:37,383 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/246dbb511/82f8b1a27fdb4a39864ed698bd3d7e9d/FLAG27d87a5f6 [2024-11-24 02:02:37,398 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/data/246dbb511/82f8b1a27fdb4a39864ed698bd3d7e9d [2024-11-24 02:02:37,401 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 02:02:37,403 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 02:02:37,404 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 02:02:37,404 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 02:02:37,409 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 02:02:37,410 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:02:37" (1/1) ... [2024-11-24 02:02:37,411 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60ba5469 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:37, skipping insertion in model container [2024-11-24 02:02:37,412 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:02:37" (1/1) ... [2024-11-24 02:02:37,450 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 02:02:37,626 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c[1280,1293] [2024-11-24 02:02:37,923 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:02:37,935 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 02:02:37,946 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c[1280,1293] [2024-11-24 02:02:38,036 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:02:38,051 INFO L204 MainTranslator]: Completed translation [2024-11-24 02:02:38,052 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38 WrapperNode [2024-11-24 02:02:38,052 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 02:02:38,053 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 02:02:38,053 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 02:02:38,053 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 02:02:38,060 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,094 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,195 INFO L138 Inliner]: procedures = 17, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 912 [2024-11-24 02:02:38,196 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 02:02:38,196 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 02:02:38,196 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 02:02:38,196 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 02:02:38,209 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,209 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,222 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,255 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-24 02:02:38,259 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,259 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,296 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,298 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,302 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,304 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,308 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,315 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 02:02:38,315 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 02:02:38,316 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 02:02:38,316 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 02:02:38,317 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (1/1) ... [2024-11-24 02:02:38,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:02:38,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:02:38,354 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 02:02:38,359 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 02:02:38,391 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 02:02:38,391 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-24 02:02:38,391 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 02:02:38,391 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 02:02:38,392 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 02:02:38,392 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 02:02:38,720 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 02:02:38,722 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 02:02:39,758 INFO L? ?]: Removed 271 outVars from TransFormulas that were not future-live. [2024-11-24 02:02:39,758 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 02:02:39,768 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 02:02:39,769 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-24 02:02:39,769 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:02:39 BoogieIcfgContainer [2024-11-24 02:02:39,769 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 02:02:39,776 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 02:02:39,778 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 02:02:39,784 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 02:02:39,784 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 02:02:37" (1/3) ... [2024-11-24 02:02:39,785 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@68564d85 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:02:39, skipping insertion in model container [2024-11-24 02:02:39,786 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:02:38" (2/3) ... [2024-11-24 02:02:39,786 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@68564d85 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:02:39, skipping insertion in model container [2024-11-24 02:02:39,786 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:02:39" (3/3) ... [2024-11-24 02:02:39,789 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c [2024-11-24 02:02:39,807 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 02:02:39,810 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w16_d16_e0.c that has 2 procedures, 20 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-24 02:02:39,869 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 02:02:39,884 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@7105f8e9, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 02:02:39,884 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 02:02:39,889 INFO L276 IsEmpty]: Start isEmpty. Operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 02:02:39,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2024-11-24 02:02:39,895 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:02:39,895 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:02:39,896 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:02:39,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:02:39,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1676994902, now seen corresponding path program 1 times [2024-11-24 02:02:39,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:02:39,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [875413678] [2024-11-24 02:02:39,912 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:02:39,913 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:02:39,913 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:02:39,915 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:02:39,919 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 02:02:40,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:02:40,463 INFO L256 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-24 02:02:40,482 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:02:40,918 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-24 02:02:40,918 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:02:41,174 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:02:41,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [875413678] [2024-11-24 02:02:41,175 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [875413678] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:02:41,175 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1330758811] [2024-11-24 02:02:41,175 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:02:41,176 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:41,176 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 02:02:41,179 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 02:02:41,182 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (3)] Waiting until timeout for monitored process [2024-11-24 02:02:41,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:02:41,909 INFO L256 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-24 02:02:41,916 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:02:42,107 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 02:02:42,109 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:02:42,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1330758811] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:02:42,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:02:42,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-11-24 02:02:42,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701851608] [2024-11-24 02:02:42,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:02:42,118 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:02:42,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:02:42,144 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:02:42,145 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:02:42,148 INFO L87 Difference]: Start difference. First operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 02:02:42,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:02:42,318 INFO L93 Difference]: Finished difference Result 43 states and 63 transitions. [2024-11-24 02:02:42,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:02:42,321 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 23 [2024-11-24 02:02:42,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:02:42,327 INFO L225 Difference]: With dead ends: 43 [2024-11-24 02:02:42,328 INFO L226 Difference]: Without dead ends: 25 [2024-11-24 02:02:42,331 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:02:42,335 INFO L435 NwaCegarLoop]: 14 mSDtfsCounter, 0 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:02:42,336 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 38 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:02:42,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2024-11-24 02:02:42,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-11-24 02:02:42,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 02:02:42,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 30 transitions. [2024-11-24 02:02:42,379 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 30 transitions. Word has length 23 [2024-11-24 02:02:42,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:02:42,382 INFO L471 AbstractCegarLoop]: Abstraction has 25 states and 30 transitions. [2024-11-24 02:02:42,382 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 02:02:42,382 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 30 transitions. [2024-11-24 02:02:42,384 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2024-11-24 02:02:42,385 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:02:42,385 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-11-24 02:02:42,398 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-24 02:02:42,592 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (3)] Ended with exit code 0 [2024-11-24 02:02:42,790 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:42,790 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:02:42,791 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:02:42,791 INFO L85 PathProgramCache]: Analyzing trace with hash -1294995197, now seen corresponding path program 1 times [2024-11-24 02:02:42,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:02:42,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1104519610] [2024-11-24 02:02:42,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:02:42,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:02:42,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:02:42,795 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:02:42,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 02:02:43,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:02:43,470 INFO L256 TraceCheckSpWp]: Trace formula consists of 656 conjuncts, 43 conjuncts are in the unsatisfiable core [2024-11-24 02:02:43,484 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:02:44,276 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 02:02:44,276 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:02:44,502 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:02:44,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1104519610] [2024-11-24 02:02:44,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1104519610] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:02:44,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1752202249] [2024-11-24 02:02:44,502 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:02:44,503 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:44,503 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 02:02:44,505 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 02:02:44,508 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (5)] Waiting until timeout for monitored process [2024-11-24 02:02:45,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:02:45,895 INFO L256 TraceCheckSpWp]: Trace formula consists of 656 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-11-24 02:02:45,920 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:02:46,413 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 02:02:46,414 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:02:46,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1752202249] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:02:46,633 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:02:46,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-11-24 02:02:46,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686955132] [2024-11-24 02:02:46,633 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:02:46,634 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-24 02:02:46,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:02:46,636 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-24 02:02:46,637 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2024-11-24 02:02:46,637 INFO L87 Difference]: Start difference. First operand 25 states and 30 transitions. Second operand has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 02:02:47,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:02:47,228 INFO L93 Difference]: Finished difference Result 36 states and 44 transitions. [2024-11-24 02:02:47,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-11-24 02:02:47,228 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 44 [2024-11-24 02:02:47,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:02:47,230 INFO L225 Difference]: With dead ends: 36 [2024-11-24 02:02:47,230 INFO L226 Difference]: Without dead ends: 34 [2024-11-24 02:02:47,230 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=47, Invalid=193, Unknown=0, NotChecked=0, Total=240 [2024-11-24 02:02:47,231 INFO L435 NwaCegarLoop]: 12 mSDtfsCounter, 7 mSDsluCounter, 64 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 139 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 02:02:47,232 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 76 Invalid, 139 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 02:02:47,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2024-11-24 02:02:47,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2024-11-24 02:02:47,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 02:02:47,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 42 transitions. [2024-11-24 02:02:47,250 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 42 transitions. Word has length 44 [2024-11-24 02:02:47,250 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:02:47,250 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 42 transitions. [2024-11-24 02:02:47,250 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 02:02:47,251 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 42 transitions. [2024-11-24 02:02:47,252 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2024-11-24 02:02:47,252 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:02:47,252 INFO L218 NwaCegarLoop]: trace histogram [9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-11-24 02:02:47,267 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-24 02:02:47,460 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (5)] Forceful destruction successful, exit code 0 [2024-11-24 02:02:47,653 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:47,653 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:02:47,654 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:02:47,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1531864950, now seen corresponding path program 2 times [2024-11-24 02:02:47,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:02:47,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2119002580] [2024-11-24 02:02:47,656 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:02:47,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:02:47,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:02:47,660 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:02:47,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 02:02:48,564 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:02:48,565 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:02:48,580 INFO L256 TraceCheckSpWp]: Trace formula consists of 960 conjuncts, 88 conjuncts are in the unsatisfiable core [2024-11-24 02:02:48,606 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:02:53,740 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 12 proven. 55 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-11-24 02:02:53,740 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:02:58,239 WARN L851 $PredicateComparison]: unable to prove that (let ((.cse0 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|))) (let ((.cse7 (forall ((|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_151_arg_1~0#1_17| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_151_arg_1~0#1_17|)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|)))) .cse0))))) (.cse8 (= (_ bv0 8) |c_ULTIMATE.start_main_~state_132~0#1|))) (let ((.cse12 (or .cse7 .cse8)) (.cse10 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_109~0#1|)) (.cse11 (not .cse8))) (let ((.cse4 (and .cse12 (or (forall ((|v_ULTIMATE.start_main_~var_115_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_126_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse0 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_115_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_1~0#1_17|) .cse10)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_126_arg_1~0#1_17|))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|)))))))) .cse11))) (.cse6 ((_ zero_extend 16) |c_ULTIMATE.start_main_~state_128~0#1|)) (.cse5 ((_ zero_extend 16) |c_ULTIMATE.start_main_~mask_SORT_3~0#1|))) (let ((.cse2 (let ((.cse9 (= .cse6 ((_ zero_extend 16) ((_ extract 15 0) (bvand ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |c_ULTIMATE.start_main_~state_96~0#1|))) .cse5)))))) (and (or .cse4 .cse9) (or (not .cse9) (and (or (forall ((|v_ULTIMATE.start_main_~var_115_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_126_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv1 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_115_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_1~0#1_17|) .cse10)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_126_arg_1~0#1_17|)))))))))))))))))) .cse0)))) .cse11) .cse12))))) (.cse1 (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_13~0#1|) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_12~0#1|))))))))) (and (or (= (_ bv0 8) ((_ extract 7 0) (bvand .cse0 (_ bv255 32)))) (not .cse1) .cse2) (or (let ((.cse3 (= ((_ extract 7 0) (bvand .cse0 (_ bv254 32))) (_ bv0 8)))) (and (or .cse3 .cse2) (or (not .cse3) (and (or .cse4 (forall ((|v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| (_ BitVec 16))) (= ((_ zero_extend 16) ((_ extract 15 0) (bvand ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |v_ULTIMATE.start_main_~var_99_arg_2~0#1_15|))) .cse5))) .cse6))) (or .cse7 (forall ((|v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| (_ BitVec 16))) (not (= ((_ zero_extend 16) ((_ extract 15 0) (bvand ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |v_ULTIMATE.start_main_~var_99_arg_2~0#1_15|))) .cse5))) .cse6))) .cse8))))) .cse1))))))) is different from false [2024-11-24 02:02:58,456 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:02:58,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2119002580] [2024-11-24 02:02:58,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2119002580] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:02:58,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1356647179] [2024-11-24 02:02:58,457 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:02:58,457 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 02:02:58,457 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 02:02:58,460 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 02:02:58,462 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (7)] Waiting until timeout for monitored process [2024-11-24 02:03:00,009 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:03:00,010 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:03:00,055 INFO L256 TraceCheckSpWp]: Trace formula consists of 960 conjuncts, 87 conjuncts are in the unsatisfiable core [2024-11-24 02:03:00,070 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:03:15,201 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 12 proven. 55 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-11-24 02:03:15,201 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:03:20,935 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 101 [2024-11-24 02:03:20,935 WARN L249 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) stderr output: (error "out of memory") [2024-11-24 02:03:20,936 WARN L320 FreeRefinementEngine]: Global settings require throwing the following exception [2024-11-24 02:03:20,946 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (7)] Forceful destruction successful, exit code 0 [2024-11-24 02:03:21,150 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-24 02:03:21,337 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:03:21,338 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:281) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.smtlibutils.ManagedScript.checkSat(ManagedScript.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:85) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:842) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:786) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:374) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:323) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:555) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:416) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:395) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:267) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:325) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:181) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:160) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getOrConstruct(IpTcStrategyModuleBase.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getInterpolantComputationStatus(IpTcStrategyModuleBase.java:77) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.tryExecuteInterpolantGenerator(AutomatonFreeRefinementEngine.java:267) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.generateProof(AutomatonFreeRefinementEngine.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.executeStrategy(AutomatonFreeRefinementEngine.java:137) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.(AutomatonFreeRefinementEngine.java:85) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:82) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:317) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:407) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.startCegar(AbstractCegarLoop.java:342) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.runCegar(AbstractCegarLoop.java:324) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:428) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:314) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseSequentialProgram(TraceAbstractionStarter.java:275) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:167) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:140) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:132) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:150) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:127) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:233) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:227) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:144) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:106) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:319) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1518) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:701) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:258) ... 46 more [2024-11-24 02:03:21,342 INFO L158 Benchmark]: Toolchain (without parser) took 43939.74ms. Allocated memory was 83.9MB in the beginning and 637.5MB in the end (delta: 553.6MB). Free memory was 58.9MB in the beginning and 309.6MB in the end (delta: -250.8MB). Peak memory consumption was 303.6MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,343 INFO L158 Benchmark]: CDTParser took 0.43ms. Allocated memory is still 83.9MB. Free memory is still 63.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 02:03:21,343 INFO L158 Benchmark]: CACSL2BoogieTranslator took 648.20ms. Allocated memory is still 83.9MB. Free memory was 58.9MB in the beginning and 26.7MB in the end (delta: 32.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,343 INFO L158 Benchmark]: Boogie Procedure Inliner took 142.65ms. Allocated memory is still 83.9MB. Free memory was 26.7MB in the beginning and 55.8MB in the end (delta: -29.1MB). Peak memory consumption was 14.2MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,345 INFO L158 Benchmark]: Boogie Preprocessor took 118.74ms. Allocated memory is still 83.9MB. Free memory was 55.8MB in the beginning and 47.3MB in the end (delta: 8.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,345 INFO L158 Benchmark]: RCFGBuilder took 1454.31ms. Allocated memory is still 83.9MB. Free memory was 47.3MB in the beginning and 27.1MB in the end (delta: 20.2MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,346 INFO L158 Benchmark]: TraceAbstraction took 41565.36ms. Allocated memory was 100.7MB in the beginning and 637.5MB in the end (delta: 536.9MB). Free memory was 67.6MB in the beginning and 309.6MB in the end (delta: -242.0MB). Peak memory consumption was 291.3MB. Max. memory is 16.1GB. [2024-11-24 02:03:21,349 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.43ms. Allocated memory is still 83.9MB. Free memory is still 63.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 648.20ms. Allocated memory is still 83.9MB. Free memory was 58.9MB in the beginning and 26.7MB in the end (delta: 32.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 142.65ms. Allocated memory is still 83.9MB. Free memory was 26.7MB in the beginning and 55.8MB in the end (delta: -29.1MB). Peak memory consumption was 14.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 118.74ms. Allocated memory is still 83.9MB. Free memory was 55.8MB in the beginning and 47.3MB in the end (delta: 8.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 1454.31ms. Allocated memory is still 83.9MB. Free memory was 47.3MB in the beginning and 27.1MB in the end (delta: 20.2MB). Peak memory consumption was 38.5MB. Max. memory is 16.1GB. * TraceAbstraction took 41565.36ms. Allocated memory was 100.7MB in the beginning and 637.5MB in the end (delta: 536.9MB). Free memory was 67.6MB in the beginning and 309.6MB in the end (delta: -242.0MB). Peak memory consumption was 291.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_fe124c54-0311-40d5-bebb-8f0eea6ac759/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory")