./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6497de01 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 4d887e46d9e1781030c0b6aae8069b6bddec306ee6a48cba2aa303ff66f408ca --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 00:47:18,314 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 00:47:18,422 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-24 00:47:18,431 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 00:47:18,435 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 00:47:18,473 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 00:47:18,475 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 00:47:18,475 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 00:47:18,476 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 00:47:18,476 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 00:47:18,477 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 00:47:18,477 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 00:47:18,478 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 00:47:18,478 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 00:47:18,478 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 00:47:18,479 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 00:47:18,479 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 00:47:18,479 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-24 00:47:18,479 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 00:47:18,480 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:47:18,480 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:47:18,481 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:47:18,481 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:47:18,481 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 00:47:18,482 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:47:18,482 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:47:18,482 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:47:18,482 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:47:18,482 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 00:47:18,483 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 00:47:18,484 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 00:47:18,484 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d887e46d9e1781030c0b6aae8069b6bddec306ee6a48cba2aa303ff66f408ca [2024-11-24 00:47:18,887 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 00:47:18,902 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 00:47:18,905 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 00:47:18,906 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 00:47:18,907 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 00:47:18,908 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:47:22,301 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/6403ca55e/6ee1745f3d484699beff73a1c1c4f065/FLAG5717873e2 [2024-11-24 00:47:22,771 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 00:47:22,774 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:47:22,792 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/6403ca55e/6ee1745f3d484699beff73a1c1c4f065/FLAG5717873e2 [2024-11-24 00:47:22,819 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/6403ca55e/6ee1745f3d484699beff73a1c1c4f065 [2024-11-24 00:47:22,824 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 00:47:22,826 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 00:47:22,829 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 00:47:22,829 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 00:47:22,839 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 00:47:22,840 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:47:22" (1/1) ... [2024-11-24 00:47:22,842 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@22994f32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:22, skipping insertion in model container [2024-11-24 00:47:22,842 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:47:22" (1/1) ... [2024-11-24 00:47:22,906 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 00:47:23,109 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c[1279,1292] [2024-11-24 00:47:23,331 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:47:23,348 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 00:47:23,359 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c[1279,1292] [2024-11-24 00:47:23,505 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:47:23,520 INFO L204 MainTranslator]: Completed translation [2024-11-24 00:47:23,521 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23 WrapperNode [2024-11-24 00:47:23,521 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 00:47:23,522 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 00:47:23,522 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 00:47:23,522 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 00:47:23,531 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,573 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,795 INFO L138 Inliner]: procedures = 17, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1382 [2024-11-24 00:47:23,796 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 00:47:23,796 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 00:47:23,797 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 00:47:23,797 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 00:47:23,808 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,810 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,855 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,946 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-24 00:47:23,948 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:23,948 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,051 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,066 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,084 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,118 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,130 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,169 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 00:47:24,171 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 00:47:24,171 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 00:47:24,172 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 00:47:24,173 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (1/1) ... [2024-11-24 00:47:24,183 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:47:24,199 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:47:24,216 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 00:47:24,222 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 00:47:24,253 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 00:47:24,254 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 00:47:24,254 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 00:47:24,254 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-24 00:47:24,254 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 00:47:24,254 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 00:47:24,571 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 00:47:24,574 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 00:47:26,867 INFO L? ?]: Removed 754 outVars from TransFormulas that were not future-live. [2024-11-24 00:47:26,867 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 00:47:26,896 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 00:47:26,899 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-24 00:47:26,899 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:47:26 BoogieIcfgContainer [2024-11-24 00:47:26,899 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 00:47:26,902 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 00:47:26,902 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 00:47:26,909 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 00:47:26,909 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 12:47:22" (1/3) ... [2024-11-24 00:47:26,910 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ef7cd49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:47:26, skipping insertion in model container [2024-11-24 00:47:26,910 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:47:23" (2/3) ... [2024-11-24 00:47:26,910 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ef7cd49 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:47:26, skipping insertion in model container [2024-11-24 00:47:26,911 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:47:26" (3/3) ... [2024-11-24 00:47:26,913 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:47:26,931 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 00:47:26,932 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c that has 2 procedures, 392 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-24 00:47:27,019 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 00:47:27,035 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@1f9ad270, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 00:47:27,036 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 00:47:27,042 INFO L276 IsEmpty]: Start isEmpty. Operand has 392 states, 386 states have (on average 1.4922279792746114) internal successors, (576), 387 states have internal predecessors, (576), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:27,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2024-11-24 00:47:27,058 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:27,059 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:27,059 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:27,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:27,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1934366869, now seen corresponding path program 1 times [2024-11-24 00:47:27,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:27,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833257668] [2024-11-24 00:47:27,071 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:27,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:27,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:27,629 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-24 00:47:27,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:27,630 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833257668] [2024-11-24 00:47:27,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833257668] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:47:27,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [614296386] [2024-11-24 00:47:27,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:27,631 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:47:27,632 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:47:27,634 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:47:27,637 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 00:47:28,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:28,093 INFO L256 TraceCheckSpWp]: Trace formula consists of 685 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-24 00:47:28,103 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:47:28,133 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-24 00:47:28,133 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:47:28,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [614296386] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:28,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:47:28,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-24 00:47:28,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1197877532] [2024-11-24 00:47:28,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:28,142 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-24 00:47:28,144 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:28,167 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-24 00:47:28,168 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 00:47:28,172 INFO L87 Difference]: Start difference. First operand has 392 states, 386 states have (on average 1.4922279792746114) internal successors, (576), 387 states have internal predecessors, (576), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 53.5) internal successors, (107), 2 states have internal predecessors, (107), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:28,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:28,258 INFO L93 Difference]: Finished difference Result 711 states and 1061 transitions. [2024-11-24 00:47:28,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-24 00:47:28,260 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 53.5) internal successors, (107), 2 states have internal predecessors, (107), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) Word has length 117 [2024-11-24 00:47:28,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:28,277 INFO L225 Difference]: With dead ends: 711 [2024-11-24 00:47:28,278 INFO L226 Difference]: Without dead ends: 389 [2024-11-24 00:47:28,283 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 00:47:28,288 INFO L435 NwaCegarLoop]: 577 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 577 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:28,289 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 577 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:47:28,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 389 states. [2024-11-24 00:47:28,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 389 to 389. [2024-11-24 00:47:28,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 389 states, 384 states have (on average 1.4869791666666667) internal successors, (571), 384 states have internal predecessors, (571), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:28,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 577 transitions. [2024-11-24 00:47:28,363 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 577 transitions. Word has length 117 [2024-11-24 00:47:28,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:28,364 INFO L471 AbstractCegarLoop]: Abstraction has 389 states and 577 transitions. [2024-11-24 00:47:28,365 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 53.5) internal successors, (107), 2 states have internal predecessors, (107), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:28,365 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 577 transitions. [2024-11-24 00:47:28,372 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2024-11-24 00:47:28,372 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:28,372 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:28,385 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-24 00:47:28,573 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:47:28,573 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:28,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:28,574 INFO L85 PathProgramCache]: Analyzing trace with hash 504535717, now seen corresponding path program 1 times [2024-11-24 00:47:28,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:28,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764847410] [2024-11-24 00:47:28,574 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:28,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:28,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:30,257 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:30,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:30,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764847410] [2024-11-24 00:47:30,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764847410] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:30,259 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:30,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:30,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104452778] [2024-11-24 00:47:30,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:30,261 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:30,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:30,262 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:30,263 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:30,264 INFO L87 Difference]: Start difference. First operand 389 states and 577 transitions. Second operand has 4 states, 4 states have (on average 26.25) internal successors, (105), 4 states have internal predecessors, (105), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:30,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:30,345 INFO L93 Difference]: Finished difference Result 393 states and 581 transitions. [2024-11-24 00:47:30,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:30,348 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 26.25) internal successors, (105), 4 states have internal predecessors, (105), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 117 [2024-11-24 00:47:30,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:30,351 INFO L225 Difference]: With dead ends: 393 [2024-11-24 00:47:30,351 INFO L226 Difference]: Without dead ends: 391 [2024-11-24 00:47:30,351 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:30,357 INFO L435 NwaCegarLoop]: 575 mSDtfsCounter, 0 mSDsluCounter, 1144 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1719 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:30,358 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1719 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:47:30,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2024-11-24 00:47:30,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 391. [2024-11-24 00:47:30,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 391 states, 386 states have (on average 1.4844559585492227) internal successors, (573), 386 states have internal predecessors, (573), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:30,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 579 transitions. [2024-11-24 00:47:30,394 INFO L78 Accepts]: Start accepts. Automaton has 391 states and 579 transitions. Word has length 117 [2024-11-24 00:47:30,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:30,397 INFO L471 AbstractCegarLoop]: Abstraction has 391 states and 579 transitions. [2024-11-24 00:47:30,397 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 26.25) internal successors, (105), 4 states have internal predecessors, (105), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:30,398 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 579 transitions. [2024-11-24 00:47:30,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2024-11-24 00:47:30,403 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:30,403 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:30,403 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-24 00:47:30,404 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:30,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:30,404 INFO L85 PathProgramCache]: Analyzing trace with hash -1537566187, now seen corresponding path program 1 times [2024-11-24 00:47:30,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:30,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969359609] [2024-11-24 00:47:30,405 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:30,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:30,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:31,173 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:31,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:31,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [969359609] [2024-11-24 00:47:31,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [969359609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:31,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:31,176 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:31,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297858686] [2024-11-24 00:47:31,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:31,177 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:31,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:31,178 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:31,178 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:31,179 INFO L87 Difference]: Start difference. First operand 391 states and 579 transitions. Second operand has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:31,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:31,884 INFO L93 Difference]: Finished difference Result 971 states and 1441 transitions. [2024-11-24 00:47:31,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:47:31,885 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 118 [2024-11-24 00:47:31,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:31,889 INFO L225 Difference]: With dead ends: 971 [2024-11-24 00:47:31,891 INFO L226 Difference]: Without dead ends: 391 [2024-11-24 00:47:31,894 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2024-11-24 00:47:31,897 INFO L435 NwaCegarLoop]: 629 mSDtfsCounter, 1090 mSDsluCounter, 1058 mSDsCounter, 0 mSdLazyCounter, 246 mSolverCounterSat, 29 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1090 SdHoareTripleChecker+Valid, 1687 SdHoareTripleChecker+Invalid, 275 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 29 IncrementalHoareTripleChecker+Valid, 246 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:31,898 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1090 Valid, 1687 Invalid, 275 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [29 Valid, 246 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 00:47:31,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states. [2024-11-24 00:47:31,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 391. [2024-11-24 00:47:31,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 391 states, 386 states have (on average 1.4818652849740932) internal successors, (572), 386 states have internal predecessors, (572), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:31,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 578 transitions. [2024-11-24 00:47:31,923 INFO L78 Accepts]: Start accepts. Automaton has 391 states and 578 transitions. Word has length 118 [2024-11-24 00:47:31,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:31,924 INFO L471 AbstractCegarLoop]: Abstraction has 391 states and 578 transitions. [2024-11-24 00:47:31,924 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 21.2) internal successors, (106), 5 states have internal predecessors, (106), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:31,924 INFO L276 IsEmpty]: Start isEmpty. Operand 391 states and 578 transitions. [2024-11-24 00:47:31,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2024-11-24 00:47:31,926 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:31,927 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:31,927 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-24 00:47:31,927 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:31,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:31,928 INFO L85 PathProgramCache]: Analyzing trace with hash 930225119, now seen corresponding path program 1 times [2024-11-24 00:47:31,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:31,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9832117] [2024-11-24 00:47:31,928 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:31,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:32,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:32,452 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:32,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:32,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [9832117] [2024-11-24 00:47:32,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [9832117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:32,453 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:32,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:32,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [480318545] [2024-11-24 00:47:32,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:32,454 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:32,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:32,457 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:32,458 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:32,458 INFO L87 Difference]: Start difference. First operand 391 states and 578 transitions. Second operand has 4 states, 4 states have (on average 26.75) internal successors, (107), 4 states have internal predecessors, (107), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:32,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:32,525 INFO L93 Difference]: Finished difference Result 714 states and 1055 transitions. [2024-11-24 00:47:32,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:32,526 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 26.75) internal successors, (107), 4 states have internal predecessors, (107), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 119 [2024-11-24 00:47:32,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:32,531 INFO L225 Difference]: With dead ends: 714 [2024-11-24 00:47:32,533 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:32,534 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:32,535 INFO L435 NwaCegarLoop]: 574 mSDtfsCounter, 0 mSDsluCounter, 1138 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1712 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:32,535 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1712 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:47:32,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:32,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:32,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4793814432989691) internal successors, (574), 388 states have internal predecessors, (574), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:32,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 580 transitions. [2024-11-24 00:47:32,557 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 580 transitions. Word has length 119 [2024-11-24 00:47:32,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:32,558 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 580 transitions. [2024-11-24 00:47:32,559 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 26.75) internal successors, (107), 4 states have internal predecessors, (107), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:32,559 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 580 transitions. [2024-11-24 00:47:32,560 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2024-11-24 00:47:32,562 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:32,562 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:32,563 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-24 00:47:32,563 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:32,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:32,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1969209588, now seen corresponding path program 1 times [2024-11-24 00:47:32,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:32,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [695864925] [2024-11-24 00:47:32,564 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:32,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:32,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:33,572 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:33,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:33,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [695864925] [2024-11-24 00:47:33,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [695864925] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:33,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:33,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:33,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40289760] [2024-11-24 00:47:33,576 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:33,577 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:33,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:33,578 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:33,578 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:33,578 INFO L87 Difference]: Start difference. First operand 393 states and 580 transitions. Second operand has 4 states, 4 states have (on average 27.0) internal successors, (108), 4 states have internal predecessors, (108), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:33,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:33,770 INFO L93 Difference]: Finished difference Result 716 states and 1056 transitions. [2024-11-24 00:47:33,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:33,771 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 27.0) internal successors, (108), 4 states have internal predecessors, (108), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 120 [2024-11-24 00:47:33,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:33,773 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:33,773 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:33,774 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:33,775 INFO L435 NwaCegarLoop]: 534 mSDtfsCounter, 484 mSDsluCounter, 536 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 484 SdHoareTripleChecker+Valid, 1070 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:33,775 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [484 Valid, 1070 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:33,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:33,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:33,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4768041237113403) internal successors, (573), 388 states have internal predecessors, (573), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:33,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 579 transitions. [2024-11-24 00:47:33,792 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 579 transitions. Word has length 120 [2024-11-24 00:47:33,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:33,792 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 579 transitions. [2024-11-24 00:47:33,793 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 27.0) internal successors, (108), 4 states have internal predecessors, (108), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:33,793 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 579 transitions. [2024-11-24 00:47:33,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2024-11-24 00:47:33,795 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:33,795 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:33,795 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-24 00:47:33,795 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:33,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:33,796 INFO L85 PathProgramCache]: Analyzing trace with hash -2133916823, now seen corresponding path program 1 times [2024-11-24 00:47:33,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:33,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88697589] [2024-11-24 00:47:33,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:33,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:33,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:34,407 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:34,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:34,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88697589] [2024-11-24 00:47:34,408 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88697589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:34,408 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:34,408 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:34,408 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599850468] [2024-11-24 00:47:34,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:34,409 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:34,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:34,409 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:34,410 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:34,410 INFO L87 Difference]: Start difference. First operand 393 states and 579 transitions. Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:34,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:34,591 INFO L93 Difference]: Finished difference Result 716 states and 1054 transitions. [2024-11-24 00:47:34,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:34,592 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 121 [2024-11-24 00:47:34,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:34,594 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:34,594 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:34,595 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:34,595 INFO L435 NwaCegarLoop]: 534 mSDtfsCounter, 1041 mSDsluCounter, 536 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1044 SdHoareTripleChecker+Valid, 1070 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:34,596 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1044 Valid, 1070 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:34,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:34,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:34,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4742268041237114) internal successors, (572), 388 states have internal predecessors, (572), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:34,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 578 transitions. [2024-11-24 00:47:34,610 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 578 transitions. Word has length 121 [2024-11-24 00:47:34,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:34,611 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 578 transitions. [2024-11-24 00:47:34,611 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:34,611 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 578 transitions. [2024-11-24 00:47:34,612 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2024-11-24 00:47:34,613 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:34,613 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:34,613 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-24 00:47:34,613 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:34,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:34,614 INFO L85 PathProgramCache]: Analyzing trace with hash 728541133, now seen corresponding path program 1 times [2024-11-24 00:47:34,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:34,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364837421] [2024-11-24 00:47:34,614 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:34,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:34,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:35,077 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:35,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:35,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364837421] [2024-11-24 00:47:35,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364837421] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:35,078 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:35,078 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:35,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949057993] [2024-11-24 00:47:35,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:35,078 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:35,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:35,079 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:35,079 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:35,079 INFO L87 Difference]: Start difference. First operand 393 states and 578 transitions. Second operand has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:35,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:35,250 INFO L93 Difference]: Finished difference Result 716 states and 1052 transitions. [2024-11-24 00:47:35,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:35,251 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 122 [2024-11-24 00:47:35,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:35,254 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:35,254 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:35,254 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:35,255 INFO L435 NwaCegarLoop]: 534 mSDtfsCounter, 559 mSDsluCounter, 543 mSDsCounter, 0 mSdLazyCounter, 80 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 562 SdHoareTripleChecker+Valid, 1077 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 80 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:35,256 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [562 Valid, 1077 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 80 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:35,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:35,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:35,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4716494845360826) internal successors, (571), 388 states have internal predecessors, (571), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:35,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 577 transitions. [2024-11-24 00:47:35,270 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 577 transitions. Word has length 122 [2024-11-24 00:47:35,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:35,271 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 577 transitions. [2024-11-24 00:47:35,271 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:35,271 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 577 transitions. [2024-11-24 00:47:35,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2024-11-24 00:47:35,272 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:35,272 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:35,272 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-24 00:47:35,273 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:35,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:35,273 INFO L85 PathProgramCache]: Analyzing trace with hash 187884130, now seen corresponding path program 1 times [2024-11-24 00:47:35,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:35,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1605232245] [2024-11-24 00:47:35,273 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:35,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:35,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:35,703 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:35,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:35,703 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1605232245] [2024-11-24 00:47:35,703 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1605232245] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:35,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:35,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:35,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757340886] [2024-11-24 00:47:35,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:35,704 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:35,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:35,705 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:35,705 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:35,706 INFO L87 Difference]: Start difference. First operand 393 states and 577 transitions. Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:35,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:35,875 INFO L93 Difference]: Finished difference Result 716 states and 1050 transitions. [2024-11-24 00:47:35,875 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:35,876 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 123 [2024-11-24 00:47:35,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:35,878 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:35,878 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:35,878 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:35,879 INFO L435 NwaCegarLoop]: 534 mSDtfsCounter, 1025 mSDsluCounter, 536 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1028 SdHoareTripleChecker+Valid, 1070 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:35,879 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1028 Valid, 1070 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:35,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:35,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:35,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4690721649484537) internal successors, (570), 388 states have internal predecessors, (570), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:35,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 576 transitions. [2024-11-24 00:47:35,899 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 576 transitions. Word has length 123 [2024-11-24 00:47:35,899 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:35,900 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 576 transitions. [2024-11-24 00:47:35,900 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:35,901 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 576 transitions. [2024-11-24 00:47:35,903 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2024-11-24 00:47:35,903 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:35,903 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:35,903 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-24 00:47:35,904 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:35,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:35,904 INFO L85 PathProgramCache]: Analyzing trace with hash 358061862, now seen corresponding path program 1 times [2024-11-24 00:47:35,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:35,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325743801] [2024-11-24 00:47:35,904 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:35,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:36,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:36,523 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:36,524 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:36,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325743801] [2024-11-24 00:47:36,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325743801] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:36,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:36,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:36,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818679261] [2024-11-24 00:47:36,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:36,527 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:36,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:36,528 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:36,528 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:36,529 INFO L87 Difference]: Start difference. First operand 393 states and 576 transitions. Second operand has 4 states, 4 states have (on average 28.0) internal successors, (112), 4 states have internal predecessors, (112), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:36,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:36,637 INFO L93 Difference]: Finished difference Result 716 states and 1048 transitions. [2024-11-24 00:47:36,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:36,638 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 28.0) internal successors, (112), 4 states have internal predecessors, (112), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 124 [2024-11-24 00:47:36,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:36,640 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:36,640 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:36,642 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:36,645 INFO L435 NwaCegarLoop]: 550 mSDtfsCounter, 483 mSDsluCounter, 552 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 483 SdHoareTripleChecker+Valid, 1102 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:36,645 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [483 Valid, 1102 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:36,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:36,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:36,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4639175257731958) internal successors, (568), 388 states have internal predecessors, (568), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:36,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 574 transitions. [2024-11-24 00:47:36,662 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 574 transitions. Word has length 124 [2024-11-24 00:47:36,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:36,663 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 574 transitions. [2024-11-24 00:47:36,663 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 28.0) internal successors, (112), 4 states have internal predecessors, (112), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:36,663 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 574 transitions. [2024-11-24 00:47:36,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2024-11-24 00:47:36,668 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:36,668 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:36,668 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-11-24 00:47:36,669 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:36,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:36,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1506252195, now seen corresponding path program 1 times [2024-11-24 00:47:36,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:36,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713439911] [2024-11-24 00:47:36,669 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:36,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:36,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:37,371 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:37,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:37,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713439911] [2024-11-24 00:47:37,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713439911] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:37,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:37,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:37,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1903089006] [2024-11-24 00:47:37,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:37,375 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:37,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:37,376 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:37,376 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:37,376 INFO L87 Difference]: Start difference. First operand 393 states and 574 transitions. Second operand has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:37,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:37,501 INFO L93 Difference]: Finished difference Result 716 states and 1044 transitions. [2024-11-24 00:47:37,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:37,501 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 126 [2024-11-24 00:47:37,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:37,506 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:37,506 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:37,507 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:37,508 INFO L435 NwaCegarLoop]: 550 mSDtfsCounter, 557 mSDsluCounter, 559 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 560 SdHoareTripleChecker+Valid, 1109 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:37,508 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [560 Valid, 1109 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:37,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:37,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:37,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.461340206185567) internal successors, (567), 388 states have internal predecessors, (567), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:37,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 573 transitions. [2024-11-24 00:47:37,526 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 573 transitions. Word has length 126 [2024-11-24 00:47:37,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:37,527 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 573 transitions. [2024-11-24 00:47:37,527 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 22.8) internal successors, (114), 5 states have internal predecessors, (114), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:37,527 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 573 transitions. [2024-11-24 00:47:37,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2024-11-24 00:47:37,529 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:37,530 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:37,530 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-24 00:47:37,531 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:37,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:37,532 INFO L85 PathProgramCache]: Analyzing trace with hash -1413439803, now seen corresponding path program 1 times [2024-11-24 00:47:37,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:37,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770754192] [2024-11-24 00:47:37,532 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:37,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:37,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:38,139 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:38,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:38,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770754192] [2024-11-24 00:47:38,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770754192] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:38,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:38,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:38,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767171412] [2024-11-24 00:47:38,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:38,140 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:38,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:38,141 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:38,141 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:38,141 INFO L87 Difference]: Start difference. First operand 393 states and 573 transitions. Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:38,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:38,249 INFO L93 Difference]: Finished difference Result 716 states and 1042 transitions. [2024-11-24 00:47:38,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:38,250 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 127 [2024-11-24 00:47:38,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:38,252 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:38,252 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:38,253 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:38,254 INFO L435 NwaCegarLoop]: 553 mSDtfsCounter, 518 mSDsluCounter, 555 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 520 SdHoareTripleChecker+Valid, 1108 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:38,255 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [520 Valid, 1108 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:38,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:38,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:38,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.458762886597938) internal successors, (566), 388 states have internal predecessors, (566), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:38,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 572 transitions. [2024-11-24 00:47:38,273 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 572 transitions. Word has length 127 [2024-11-24 00:47:38,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:38,273 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 572 transitions. [2024-11-24 00:47:38,274 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:38,274 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 572 transitions. [2024-11-24 00:47:38,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-11-24 00:47:38,277 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:38,277 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:38,279 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-24 00:47:38,279 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:38,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:38,279 INFO L85 PathProgramCache]: Analyzing trace with hash -12372935, now seen corresponding path program 1 times [2024-11-24 00:47:38,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:38,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761661783] [2024-11-24 00:47:38,280 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:38,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:38,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:39,086 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:39,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:39,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761661783] [2024-11-24 00:47:39,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761661783] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:39,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:39,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:39,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602401211] [2024-11-24 00:47:39,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:39,090 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:39,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:39,091 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:39,091 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:39,091 INFO L87 Difference]: Start difference. First operand 393 states and 572 transitions. Second operand has 5 states, 5 states have (on average 23.2) internal successors, (116), 5 states have internal predecessors, (116), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:39,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:39,317 INFO L93 Difference]: Finished difference Result 716 states and 1040 transitions. [2024-11-24 00:47:39,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:39,318 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.2) internal successors, (116), 5 states have internal predecessors, (116), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 128 [2024-11-24 00:47:39,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:39,320 INFO L225 Difference]: With dead ends: 716 [2024-11-24 00:47:39,320 INFO L226 Difference]: Without dead ends: 393 [2024-11-24 00:47:39,321 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:39,322 INFO L435 NwaCegarLoop]: 530 mSDtfsCounter, 472 mSDsluCounter, 1057 mSDsCounter, 0 mSdLazyCounter, 115 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 472 SdHoareTripleChecker+Valid, 1587 SdHoareTripleChecker+Invalid, 115 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 115 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:39,322 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [472 Valid, 1587 Invalid, 115 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 115 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 00:47:39,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 393 states. [2024-11-24 00:47:39,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 393 to 393. [2024-11-24 00:47:39,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 388 states have (on average 1.4561855670103092) internal successors, (565), 388 states have internal predecessors, (565), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:39,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 571 transitions. [2024-11-24 00:47:39,338 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 571 transitions. Word has length 128 [2024-11-24 00:47:39,338 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:39,339 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 571 transitions. [2024-11-24 00:47:39,339 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.2) internal successors, (116), 5 states have internal predecessors, (116), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:39,339 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 571 transitions. [2024-11-24 00:47:39,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 130 [2024-11-24 00:47:39,341 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:39,341 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:39,341 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-11-24 00:47:39,341 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:39,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:39,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1411160021, now seen corresponding path program 1 times [2024-11-24 00:47:39,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:39,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692943480] [2024-11-24 00:47:39,342 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:39,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:39,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:40,271 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:40,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:40,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692943480] [2024-11-24 00:47:40,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692943480] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:40,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:40,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:40,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74232708] [2024-11-24 00:47:40,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:40,273 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:40,273 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:40,273 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:40,273 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:40,274 INFO L87 Difference]: Start difference. First operand 393 states and 571 transitions. Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:40,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:40,674 INFO L93 Difference]: Finished difference Result 722 states and 1046 transitions. [2024-11-24 00:47:40,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 00:47:40,675 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 129 [2024-11-24 00:47:40,675 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:40,678 INFO L225 Difference]: With dead ends: 722 [2024-11-24 00:47:40,678 INFO L226 Difference]: Without dead ends: 397 [2024-11-24 00:47:40,679 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:40,679 INFO L435 NwaCegarLoop]: 561 mSDtfsCounter, 2 mSDsluCounter, 1530 mSDsCounter, 0 mSdLazyCounter, 176 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 2091 SdHoareTripleChecker+Invalid, 176 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 176 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:40,680 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 2091 Invalid, 176 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 176 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 00:47:40,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2024-11-24 00:47:40,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 395. [2024-11-24 00:47:40,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 395 states, 390 states have (on average 1.4538461538461538) internal successors, (567), 390 states have internal predecessors, (567), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:40,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 573 transitions. [2024-11-24 00:47:40,701 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 573 transitions. Word has length 129 [2024-11-24 00:47:40,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:40,703 INFO L471 AbstractCegarLoop]: Abstraction has 395 states and 573 transitions. [2024-11-24 00:47:40,703 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:40,703 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 573 transitions. [2024-11-24 00:47:40,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2024-11-24 00:47:40,705 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:40,705 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:40,706 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-24 00:47:40,706 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:40,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:40,706 INFO L85 PathProgramCache]: Analyzing trace with hash -1039408138, now seen corresponding path program 1 times [2024-11-24 00:47:40,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:40,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1243924589] [2024-11-24 00:47:40,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:40,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:40,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:41,520 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:41,521 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:41,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1243924589] [2024-11-24 00:47:41,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1243924589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:41,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:41,522 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:41,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908075619] [2024-11-24 00:47:41,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:41,523 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:41,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:41,524 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:41,524 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:41,524 INFO L87 Difference]: Start difference. First operand 395 states and 573 transitions. Second operand has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:41,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:41,750 INFO L93 Difference]: Finished difference Result 720 states and 1042 transitions. [2024-11-24 00:47:41,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:41,751 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 130 [2024-11-24 00:47:41,752 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:41,754 INFO L225 Difference]: With dead ends: 720 [2024-11-24 00:47:41,754 INFO L226 Difference]: Without dead ends: 395 [2024-11-24 00:47:41,755 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:41,756 INFO L435 NwaCegarLoop]: 530 mSDtfsCounter, 932 mSDsluCounter, 532 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 932 SdHoareTripleChecker+Valid, 1062 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:41,756 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [932 Valid, 1062 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:41,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2024-11-24 00:47:41,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2024-11-24 00:47:41,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 395 states, 390 states have (on average 1.4512820512820512) internal successors, (566), 390 states have internal predecessors, (566), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:41,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 572 transitions. [2024-11-24 00:47:41,772 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 572 transitions. Word has length 130 [2024-11-24 00:47:41,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:41,773 INFO L471 AbstractCegarLoop]: Abstraction has 395 states and 572 transitions. [2024-11-24 00:47:41,773 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:41,773 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 572 transitions. [2024-11-24 00:47:41,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2024-11-24 00:47:41,775 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:41,775 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:41,775 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-24 00:47:41,775 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:41,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:41,776 INFO L85 PathProgramCache]: Analyzing trace with hash 1963964559, now seen corresponding path program 1 times [2024-11-24 00:47:41,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:41,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889831381] [2024-11-24 00:47:41,776 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:41,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:41,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:42,386 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:42,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:42,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889831381] [2024-11-24 00:47:42,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889831381] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:42,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:42,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:42,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160909180] [2024-11-24 00:47:42,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:42,387 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:42,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:42,388 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:42,388 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:42,388 INFO L87 Difference]: Start difference. First operand 395 states and 572 transitions. Second operand has 5 states, 5 states have (on average 23.8) internal successors, (119), 5 states have internal predecessors, (119), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:42,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:42,575 INFO L93 Difference]: Finished difference Result 720 states and 1040 transitions. [2024-11-24 00:47:42,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:42,576 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.8) internal successors, (119), 5 states have internal predecessors, (119), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 131 [2024-11-24 00:47:42,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:42,578 INFO L225 Difference]: With dead ends: 720 [2024-11-24 00:47:42,578 INFO L226 Difference]: Without dead ends: 395 [2024-11-24 00:47:42,579 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:42,580 INFO L435 NwaCegarLoop]: 530 mSDtfsCounter, 467 mSDsluCounter, 539 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 467 SdHoareTripleChecker+Valid, 1069 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:42,580 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [467 Valid, 1069 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:42,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2024-11-24 00:47:42,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2024-11-24 00:47:42,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 395 states, 390 states have (on average 1.4487179487179487) internal successors, (565), 390 states have internal predecessors, (565), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:42,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 571 transitions. [2024-11-24 00:47:42,599 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 571 transitions. Word has length 131 [2024-11-24 00:47:42,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:42,600 INFO L471 AbstractCegarLoop]: Abstraction has 395 states and 571 transitions. [2024-11-24 00:47:42,600 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.8) internal successors, (119), 5 states have internal predecessors, (119), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:42,601 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 571 transitions. [2024-11-24 00:47:42,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 133 [2024-11-24 00:47:42,603 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:42,603 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:42,603 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-24 00:47:42,603 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:42,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:42,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1513937355, now seen corresponding path program 1 times [2024-11-24 00:47:42,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:42,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405353088] [2024-11-24 00:47:42,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:42,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:42,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:43,071 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:43,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:43,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405353088] [2024-11-24 00:47:43,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405353088] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:43,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:43,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:43,073 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927158008] [2024-11-24 00:47:43,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:43,074 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:43,074 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:43,075 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:43,075 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:43,075 INFO L87 Difference]: Start difference. First operand 395 states and 571 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:43,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:43,181 INFO L93 Difference]: Finished difference Result 720 states and 1038 transitions. [2024-11-24 00:47:43,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:43,182 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 132 [2024-11-24 00:47:43,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:43,184 INFO L225 Difference]: With dead ends: 720 [2024-11-24 00:47:43,184 INFO L226 Difference]: Without dead ends: 395 [2024-11-24 00:47:43,185 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:43,186 INFO L435 NwaCegarLoop]: 550 mSDtfsCounter, 513 mSDsluCounter, 552 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 515 SdHoareTripleChecker+Valid, 1102 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:43,187 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [515 Valid, 1102 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:43,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2024-11-24 00:47:43,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 395. [2024-11-24 00:47:43,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 395 states, 390 states have (on average 1.4461538461538461) internal successors, (564), 390 states have internal predecessors, (564), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:43,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 395 states to 395 states and 570 transitions. [2024-11-24 00:47:43,203 INFO L78 Accepts]: Start accepts. Automaton has 395 states and 570 transitions. Word has length 132 [2024-11-24 00:47:43,203 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:43,204 INFO L471 AbstractCegarLoop]: Abstraction has 395 states and 570 transitions. [2024-11-24 00:47:43,204 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-24 00:47:43,204 INFO L276 IsEmpty]: Start isEmpty. Operand 395 states and 570 transitions. [2024-11-24 00:47:43,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2024-11-24 00:47:43,206 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:43,207 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:43,207 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-11-24 00:47:43,207 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:43,208 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:43,208 INFO L85 PathProgramCache]: Analyzing trace with hash -946071650, now seen corresponding path program 1 times [2024-11-24 00:47:43,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:43,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047608044] [2024-11-24 00:47:43,208 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:43,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:43,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:44,555 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:44,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:44,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047608044] [2024-11-24 00:47:44,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047608044] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:44,556 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:44,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 00:47:44,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278332075] [2024-11-24 00:47:44,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:44,557 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 00:47:44,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:44,557 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 00:47:44,558 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-24 00:47:44,558 INFO L87 Difference]: Start difference. First operand 395 states and 570 transitions. Second operand has 7 states, 7 states have (on average 17.285714285714285) internal successors, (121), 7 states have internal predecessors, (121), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:45,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:45,248 INFO L93 Difference]: Finished difference Result 788 states and 1134 transitions. [2024-11-24 00:47:45,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 00:47:45,248 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.285714285714285) internal successors, (121), 7 states have internal predecessors, (121), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 133 [2024-11-24 00:47:45,249 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:45,251 INFO L225 Difference]: With dead ends: 788 [2024-11-24 00:47:45,251 INFO L226 Difference]: Without dead ends: 399 [2024-11-24 00:47:45,252 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-24 00:47:45,253 INFO L435 NwaCegarLoop]: 540 mSDtfsCounter, 647 mSDsluCounter, 2022 mSDsCounter, 0 mSdLazyCounter, 260 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 650 SdHoareTripleChecker+Valid, 2562 SdHoareTripleChecker+Invalid, 269 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 260 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:45,253 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [650 Valid, 2562 Invalid, 269 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 260 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 00:47:45,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 399 states. [2024-11-24 00:47:45,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 399 to 397. [2024-11-24 00:47:45,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 397 states, 392 states have (on average 1.4438775510204083) internal successors, (566), 392 states have internal predecessors, (566), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:47:45,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 397 states and 572 transitions. [2024-11-24 00:47:45,270 INFO L78 Accepts]: Start accepts. Automaton has 397 states and 572 transitions. Word has length 133 [2024-11-24 00:47:45,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:45,270 INFO L471 AbstractCegarLoop]: Abstraction has 397 states and 572 transitions. [2024-11-24 00:47:45,271 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.285714285714285) internal successors, (121), 7 states have internal predecessors, (121), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:45,271 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 572 transitions. [2024-11-24 00:47:45,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2024-11-24 00:47:45,273 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:45,273 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:45,273 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-11-24 00:47:45,273 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:45,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:45,274 INFO L85 PathProgramCache]: Analyzing trace with hash 2020339687, now seen corresponding path program 1 times [2024-11-24 00:47:45,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:45,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290386437] [2024-11-24 00:47:45,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:45,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:45,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:46,390 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:47:46,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:46,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290386437] [2024-11-24 00:47:46,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290386437] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:46,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:46,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:47:46,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1287756039] [2024-11-24 00:47:46,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:46,391 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:47:46,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:46,392 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:47:46,392 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:46,395 INFO L87 Difference]: Start difference. First operand 397 states and 572 transitions. Second operand has 6 states, 6 states have (on average 20.333333333333332) internal successors, (122), 6 states have internal predecessors, (122), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:46,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:46,597 INFO L93 Difference]: Finished difference Result 848 states and 1211 transitions. [2024-11-24 00:47:46,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:47:46,598 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 20.333333333333332) internal successors, (122), 6 states have internal predecessors, (122), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 134 [2024-11-24 00:47:46,598 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:46,601 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:46,601 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:46,602 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:47:46,602 INFO L435 NwaCegarLoop]: 552 mSDtfsCounter, 861 mSDsluCounter, 1650 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 864 SdHoareTripleChecker+Valid, 2202 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:46,603 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [864 Valid, 2202 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:46,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:46,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:46,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4230019493177388) internal successors, (730), 513 states have internal predecessors, (730), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:46,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 742 transitions. [2024-11-24 00:47:46,628 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 742 transitions. Word has length 134 [2024-11-24 00:47:46,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:46,629 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 742 transitions. [2024-11-24 00:47:46,629 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 20.333333333333332) internal successors, (122), 6 states have internal predecessors, (122), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:47:46,629 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 742 transitions. [2024-11-24 00:47:46,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 323 [2024-11-24 00:47:46,635 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:46,635 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:46,636 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-11-24 00:47:46,636 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:46,636 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:46,636 INFO L85 PathProgramCache]: Analyzing trace with hash -545067660, now seen corresponding path program 1 times [2024-11-24 00:47:46,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:46,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069625474] [2024-11-24 00:47:46,637 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:46,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:47,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:47,700 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:47,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:47,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069625474] [2024-11-24 00:47:47,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069625474] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:47,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:47,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:47,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1521252468] [2024-11-24 00:47:47,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:47,701 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:47,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:47,703 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:47,703 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:47,704 INFO L87 Difference]: Start difference. First operand 521 states and 742 transitions. Second operand has 5 states, 5 states have (on average 59.0) internal successors, (295), 5 states have internal predecessors, (295), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:47,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:47,842 INFO L93 Difference]: Finished difference Result 848 states and 1210 transitions. [2024-11-24 00:47:47,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:47,843 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 59.0) internal successors, (295), 5 states have internal predecessors, (295), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 322 [2024-11-24 00:47:47,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:47,846 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:47,847 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:47,848 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:47,848 INFO L435 NwaCegarLoop]: 529 mSDtfsCounter, 940 mSDsluCounter, 531 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 943 SdHoareTripleChecker+Valid, 1060 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:47,849 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [943 Valid, 1060 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:47,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:47,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:47,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4210526315789473) internal successors, (729), 513 states have internal predecessors, (729), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:47,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 741 transitions. [2024-11-24 00:47:47,880 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 741 transitions. Word has length 322 [2024-11-24 00:47:47,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:47,881 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 741 transitions. [2024-11-24 00:47:47,881 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 59.0) internal successors, (295), 5 states have internal predecessors, (295), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:47,881 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 741 transitions. [2024-11-24 00:47:47,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 324 [2024-11-24 00:47:47,887 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:47,887 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:47,887 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-11-24 00:47:47,887 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:47,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:47,888 INFO L85 PathProgramCache]: Analyzing trace with hash 344496768, now seen corresponding path program 1 times [2024-11-24 00:47:47,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:47,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1620007612] [2024-11-24 00:47:47,889 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:47,889 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:48,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:49,000 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:49,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:49,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1620007612] [2024-11-24 00:47:49,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1620007612] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:49,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:49,002 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:49,002 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531739468] [2024-11-24 00:47:49,002 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:49,003 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:49,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:49,005 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:49,005 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:49,005 INFO L87 Difference]: Start difference. First operand 521 states and 741 transitions. Second operand has 5 states, 5 states have (on average 59.2) internal successors, (296), 5 states have internal predecessors, (296), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:49,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:49,177 INFO L93 Difference]: Finished difference Result 848 states and 1208 transitions. [2024-11-24 00:47:49,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:49,178 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 59.2) internal successors, (296), 5 states have internal predecessors, (296), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 323 [2024-11-24 00:47:49,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:49,181 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:49,181 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:49,182 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:49,183 INFO L435 NwaCegarLoop]: 529 mSDtfsCounter, 508 mSDsluCounter, 538 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 511 SdHoareTripleChecker+Valid, 1067 SdHoareTripleChecker+Invalid, 69 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:49,183 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [511 Valid, 1067 Invalid, 69 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 68 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:49,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:49,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:49,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4191033138401559) internal successors, (728), 513 states have internal predecessors, (728), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:49,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 740 transitions. [2024-11-24 00:47:49,215 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 740 transitions. Word has length 323 [2024-11-24 00:47:49,216 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:49,216 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 740 transitions. [2024-11-24 00:47:49,216 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 59.2) internal successors, (296), 5 states have internal predecessors, (296), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:49,217 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 740 transitions. [2024-11-24 00:47:49,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 325 [2024-11-24 00:47:49,224 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:49,224 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:49,224 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-11-24 00:47:49,225 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:49,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:49,225 INFO L85 PathProgramCache]: Analyzing trace with hash 492464095, now seen corresponding path program 1 times [2024-11-24 00:47:49,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:49,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155907731] [2024-11-24 00:47:49,226 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:49,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:49,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:50,179 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:50,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:50,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155907731] [2024-11-24 00:47:50,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [155907731] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:50,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:50,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:50,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510324344] [2024-11-24 00:47:50,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:50,181 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:50,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:50,183 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:50,183 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:50,184 INFO L87 Difference]: Start difference. First operand 521 states and 740 transitions. Second operand has 5 states, 5 states have (on average 59.4) internal successors, (297), 5 states have internal predecessors, (297), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:50,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:50,351 INFO L93 Difference]: Finished difference Result 848 states and 1206 transitions. [2024-11-24 00:47:50,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:50,352 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 59.4) internal successors, (297), 5 states have internal predecessors, (297), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 324 [2024-11-24 00:47:50,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:50,356 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:50,356 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:50,357 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:50,358 INFO L435 NwaCegarLoop]: 529 mSDtfsCounter, 500 mSDsluCounter, 538 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 503 SdHoareTripleChecker+Valid, 1067 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:50,359 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [503 Valid, 1067 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:50,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:50,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:50,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4171539961013646) internal successors, (727), 513 states have internal predecessors, (727), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:50,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 739 transitions. [2024-11-24 00:47:50,388 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 739 transitions. Word has length 324 [2024-11-24 00:47:50,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:50,389 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 739 transitions. [2024-11-24 00:47:50,389 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 59.4) internal successors, (297), 5 states have internal predecessors, (297), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:50,389 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 739 transitions. [2024-11-24 00:47:50,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 326 [2024-11-24 00:47:50,395 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:50,395 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:50,395 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-11-24 00:47:50,395 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:50,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:50,396 INFO L85 PathProgramCache]: Analyzing trace with hash -590877813, now seen corresponding path program 1 times [2024-11-24 00:47:50,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:50,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798570437] [2024-11-24 00:47:50,397 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:50,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:50,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:51,375 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:51,375 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:51,375 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798570437] [2024-11-24 00:47:51,375 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798570437] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:51,375 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:51,376 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:51,376 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967724450] [2024-11-24 00:47:51,376 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:51,376 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:51,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:51,377 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:51,378 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:51,378 INFO L87 Difference]: Start difference. First operand 521 states and 739 transitions. Second operand has 5 states, 5 states have (on average 59.6) internal successors, (298), 5 states have internal predecessors, (298), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:51,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:51,514 INFO L93 Difference]: Finished difference Result 848 states and 1204 transitions. [2024-11-24 00:47:51,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:51,515 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 59.6) internal successors, (298), 5 states have internal predecessors, (298), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 325 [2024-11-24 00:47:51,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:51,518 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:51,518 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:51,519 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:51,520 INFO L435 NwaCegarLoop]: 529 mSDtfsCounter, 892 mSDsluCounter, 531 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 895 SdHoareTripleChecker+Valid, 1060 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:51,520 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [895 Valid, 1060 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:51,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:51,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:51,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4152046783625731) internal successors, (726), 513 states have internal predecessors, (726), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:51,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 738 transitions. [2024-11-24 00:47:51,547 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 738 transitions. Word has length 325 [2024-11-24 00:47:51,548 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:51,549 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 738 transitions. [2024-11-24 00:47:51,549 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 59.6) internal successors, (298), 5 states have internal predecessors, (298), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:51,549 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 738 transitions. [2024-11-24 00:47:51,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 327 [2024-11-24 00:47:51,555 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:51,555 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:51,555 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-11-24 00:47:51,556 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:51,556 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:51,556 INFO L85 PathProgramCache]: Analyzing trace with hash 47349450, now seen corresponding path program 1 times [2024-11-24 00:47:51,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:51,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [739208467] [2024-11-24 00:47:51,556 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:51,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:51,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:52,643 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:52,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:52,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [739208467] [2024-11-24 00:47:52,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [739208467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:52,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:52,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:52,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105710051] [2024-11-24 00:47:52,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:52,645 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:52,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:52,646 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:52,647 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:52,647 INFO L87 Difference]: Start difference. First operand 521 states and 738 transitions. Second operand has 5 states, 5 states have (on average 59.8) internal successors, (299), 5 states have internal predecessors, (299), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:52,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:52,762 INFO L93 Difference]: Finished difference Result 848 states and 1202 transitions. [2024-11-24 00:47:52,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:52,763 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 59.8) internal successors, (299), 5 states have internal predecessors, (299), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 326 [2024-11-24 00:47:52,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:52,766 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:52,766 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:52,767 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:52,768 INFO L435 NwaCegarLoop]: 541 mSDtfsCounter, 869 mSDsluCounter, 543 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 872 SdHoareTripleChecker+Valid, 1084 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:52,769 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [872 Valid, 1084 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:52,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:52,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:52,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4132553606237817) internal successors, (725), 513 states have internal predecessors, (725), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:52,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 737 transitions. [2024-11-24 00:47:52,794 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 737 transitions. Word has length 326 [2024-11-24 00:47:52,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:52,795 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 737 transitions. [2024-11-24 00:47:52,795 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 59.8) internal successors, (299), 5 states have internal predecessors, (299), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:52,795 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 737 transitions. [2024-11-24 00:47:52,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 328 [2024-11-24 00:47:52,801 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:52,801 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:52,801 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-11-24 00:47:52,801 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:52,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:52,803 INFO L85 PathProgramCache]: Analyzing trace with hash -421125866, now seen corresponding path program 1 times [2024-11-24 00:47:52,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:52,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741398651] [2024-11-24 00:47:52,803 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:52,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:53,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:53,723 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:53,724 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:53,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741398651] [2024-11-24 00:47:53,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741398651] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:53,724 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:53,724 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:53,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360205477] [2024-11-24 00:47:53,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:53,727 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:53,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:53,728 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:53,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:53,728 INFO L87 Difference]: Start difference. First operand 521 states and 737 transitions. Second operand has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:53,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:53,831 INFO L93 Difference]: Finished difference Result 848 states and 1200 transitions. [2024-11-24 00:47:53,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:53,832 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 327 [2024-11-24 00:47:53,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:53,835 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:53,835 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:53,836 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:53,837 INFO L435 NwaCegarLoop]: 541 mSDtfsCounter, 853 mSDsluCounter, 543 mSDsCounter, 0 mSdLazyCounter, 36 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 856 SdHoareTripleChecker+Valid, 1084 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 36 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:53,837 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [856 Valid, 1084 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 36 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:53,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:53,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:53,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4113060428849902) internal successors, (724), 513 states have internal predecessors, (724), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:53,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 736 transitions. [2024-11-24 00:47:53,865 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 736 transitions. Word has length 327 [2024-11-24 00:47:53,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:53,866 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 736 transitions. [2024-11-24 00:47:53,866 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:53,866 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 736 transitions. [2024-11-24 00:47:53,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 329 [2024-11-24 00:47:53,871 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:53,872 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:53,872 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2024-11-24 00:47:53,873 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:53,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:53,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1883442635, now seen corresponding path program 1 times [2024-11-24 00:47:53,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:53,874 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113045660] [2024-11-24 00:47:53,874 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:53,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:54,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:54,853 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:54,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:54,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113045660] [2024-11-24 00:47:54,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113045660] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:54,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:54,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:54,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575897053] [2024-11-24 00:47:54,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:54,855 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:54,856 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:54,856 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:54,856 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:54,857 INFO L87 Difference]: Start difference. First operand 521 states and 736 transitions. Second operand has 5 states, 5 states have (on average 60.2) internal successors, (301), 5 states have internal predecessors, (301), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:55,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:55,329 INFO L93 Difference]: Finished difference Result 848 states and 1198 transitions. [2024-11-24 00:47:55,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:55,330 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.2) internal successors, (301), 5 states have internal predecessors, (301), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 328 [2024-11-24 00:47:55,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:55,333 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:55,334 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:55,335 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:55,336 INFO L435 NwaCegarLoop]: 401 mSDtfsCounter, 417 mSDsluCounter, 410 mSDsCounter, 0 mSdLazyCounter, 314 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 417 SdHoareTripleChecker+Valid, 811 SdHoareTripleChecker+Invalid, 315 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 314 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:55,338 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [417 Valid, 811 Invalid, 315 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 314 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 00:47:55,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:55,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:55,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.409356725146199) internal successors, (723), 513 states have internal predecessors, (723), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:55,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 735 transitions. [2024-11-24 00:47:55,372 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 735 transitions. Word has length 328 [2024-11-24 00:47:55,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:55,373 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 735 transitions. [2024-11-24 00:47:55,374 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.2) internal successors, (301), 5 states have internal predecessors, (301), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:55,374 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 735 transitions. [2024-11-24 00:47:55,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 330 [2024-11-24 00:47:55,380 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:55,381 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:55,381 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2024-11-24 00:47:55,381 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:55,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:55,382 INFO L85 PathProgramCache]: Analyzing trace with hash -2098529503, now seen corresponding path program 1 times [2024-11-24 00:47:55,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:55,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134325164] [2024-11-24 00:47:55,383 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:55,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:56,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:57,402 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:57,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:57,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134325164] [2024-11-24 00:47:57,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134325164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:57,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:57,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:47:57,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [524618757] [2024-11-24 00:47:57,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:57,405 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:47:57,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:57,406 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:47:57,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:47:57,407 INFO L87 Difference]: Start difference. First operand 521 states and 735 transitions. Second operand has 4 states, 4 states have (on average 75.5) internal successors, (302), 4 states have internal predecessors, (302), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:57,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:57,502 INFO L93 Difference]: Finished difference Result 848 states and 1196 transitions. [2024-11-24 00:47:57,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:57,504 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 75.5) internal successors, (302), 4 states have internal predecessors, (302), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 329 [2024-11-24 00:47:57,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:57,507 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:57,507 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:57,508 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:57,509 INFO L435 NwaCegarLoop]: 540 mSDtfsCounter, 383 mSDsluCounter, 542 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 383 SdHoareTripleChecker+Valid, 1082 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:57,509 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [383 Valid, 1082 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:57,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:57,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:57,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4074074074074074) internal successors, (722), 513 states have internal predecessors, (722), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:57,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 734 transitions. [2024-11-24 00:47:57,533 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 734 transitions. Word has length 329 [2024-11-24 00:47:57,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:57,534 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 734 transitions. [2024-11-24 00:47:57,534 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 75.5) internal successors, (302), 4 states have internal predecessors, (302), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:57,534 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 734 transitions. [2024-11-24 00:47:57,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 331 [2024-11-24 00:47:57,540 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:57,540 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:57,540 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2024-11-24 00:47:57,542 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:57,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:57,543 INFO L85 PathProgramCache]: Analyzing trace with hash -33950269, now seen corresponding path program 1 times [2024-11-24 00:47:57,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:57,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1190336743] [2024-11-24 00:47:57,543 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:57,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:47:58,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:47:59,119 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:47:59,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:47:59,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1190336743] [2024-11-24 00:47:59,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1190336743] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:47:59,120 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:47:59,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:47:59,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [245913782] [2024-11-24 00:47:59,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:47:59,121 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:47:59,121 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:47:59,121 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:47:59,122 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:47:59,122 INFO L87 Difference]: Start difference. First operand 521 states and 734 transitions. Second operand has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:59,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:47:59,283 INFO L93 Difference]: Finished difference Result 848 states and 1194 transitions. [2024-11-24 00:47:59,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:47:59,284 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 330 [2024-11-24 00:47:59,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:47:59,286 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:47:59,287 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:47:59,287 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:47:59,288 INFO L435 NwaCegarLoop]: 525 mSDtfsCounter, 864 mSDsluCounter, 527 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 864 SdHoareTripleChecker+Valid, 1052 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:47:59,289 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [864 Valid, 1052 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 62 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:47:59,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:47:59,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:47:59,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.405458089668616) internal successors, (721), 513 states have internal predecessors, (721), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:47:59,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 733 transitions. [2024-11-24 00:47:59,315 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 733 transitions. Word has length 330 [2024-11-24 00:47:59,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:47:59,315 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 733 transitions. [2024-11-24 00:47:59,315 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:47:59,316 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 733 transitions. [2024-11-24 00:47:59,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 332 [2024-11-24 00:47:59,320 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:47:59,321 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:47:59,322 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2024-11-24 00:47:59,322 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:47:59,322 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:47:59,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1414511327, now seen corresponding path program 1 times [2024-11-24 00:47:59,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:47:59,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095156338] [2024-11-24 00:47:59,323 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:47:59,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:00,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:00,861 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:00,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:00,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095156338] [2024-11-24 00:48:00,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095156338] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:00,862 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:00,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:48:00,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357252473] [2024-11-24 00:48:00,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:00,862 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:48:00,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:00,863 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:48:00,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:00,864 INFO L87 Difference]: Start difference. First operand 521 states and 733 transitions. Second operand has 5 states, 5 states have (on average 60.8) internal successors, (304), 5 states have internal predecessors, (304), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:01,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:01,028 INFO L93 Difference]: Finished difference Result 848 states and 1192 transitions. [2024-11-24 00:48:01,028 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:48:01,028 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.8) internal successors, (304), 5 states have internal predecessors, (304), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 331 [2024-11-24 00:48:01,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:01,031 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:48:01,031 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:48:01,032 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:48:01,036 INFO L435 NwaCegarLoop]: 525 mSDtfsCounter, 454 mSDsluCounter, 534 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 454 SdHoareTripleChecker+Valid, 1059 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:01,037 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [454 Valid, 1059 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:48:01,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:48:01,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:48:01,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4035087719298245) internal successors, (720), 513 states have internal predecessors, (720), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:48:01,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 732 transitions. [2024-11-24 00:48:01,062 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 732 transitions. Word has length 331 [2024-11-24 00:48:01,063 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:01,063 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 732 transitions. [2024-11-24 00:48:01,067 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.8) internal successors, (304), 5 states have internal predecessors, (304), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:01,067 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 732 transitions. [2024-11-24 00:48:01,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 333 [2024-11-24 00:48:01,079 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:01,080 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:01,080 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2024-11-24 00:48:01,080 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:01,081 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:01,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1547045420, now seen corresponding path program 1 times [2024-11-24 00:48:01,081 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:01,081 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386926712] [2024-11-24 00:48:01,081 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:01,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:01,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:02,689 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:02,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:02,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386926712] [2024-11-24 00:48:02,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386926712] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:02,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:02,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:48:02,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297877592] [2024-11-24 00:48:02,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:02,691 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:48:02,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:02,693 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:48:02,693 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:02,693 INFO L87 Difference]: Start difference. First operand 521 states and 732 transitions. Second operand has 5 states, 5 states have (on average 61.0) internal successors, (305), 5 states have internal predecessors, (305), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:02,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:02,887 INFO L93 Difference]: Finished difference Result 848 states and 1190 transitions. [2024-11-24 00:48:02,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:48:02,888 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 61.0) internal successors, (305), 5 states have internal predecessors, (305), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 332 [2024-11-24 00:48:02,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:02,891 INFO L225 Difference]: With dead ends: 848 [2024-11-24 00:48:02,891 INFO L226 Difference]: Without dead ends: 521 [2024-11-24 00:48:02,892 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:48:02,894 INFO L435 NwaCegarLoop]: 525 mSDtfsCounter, 453 mSDsluCounter, 534 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 453 SdHoareTripleChecker+Valid, 1059 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:02,895 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [453 Valid, 1059 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:48:02,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states. [2024-11-24 00:48:02,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 521. [2024-11-24 00:48:02,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 521 states, 513 states have (on average 1.4015594541910332) internal successors, (719), 513 states have internal predecessors, (719), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:48:02,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 731 transitions. [2024-11-24 00:48:02,921 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 731 transitions. Word has length 332 [2024-11-24 00:48:02,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:02,922 INFO L471 AbstractCegarLoop]: Abstraction has 521 states and 731 transitions. [2024-11-24 00:48:02,922 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 61.0) internal successors, (305), 5 states have internal predecessors, (305), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:02,922 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 731 transitions. [2024-11-24 00:48:02,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 334 [2024-11-24 00:48:02,926 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:02,926 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:02,926 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2024-11-24 00:48:02,926 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:02,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:02,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1723789232, now seen corresponding path program 1 times [2024-11-24 00:48:02,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:02,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477607538] [2024-11-24 00:48:02,928 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:02,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:04,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:05,353 INFO L134 CoverageAnalysis]: Checked inductivity of 143 backedges. 77 proven. 0 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2024-11-24 00:48:05,353 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:05,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477607538] [2024-11-24 00:48:05,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477607538] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:05,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:05,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:48:05,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1725197544] [2024-11-24 00:48:05,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:05,355 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:48:05,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:05,358 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:48:05,358 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:05,358 INFO L87 Difference]: Start difference. First operand 521 states and 731 transitions. Second operand has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:05,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:05,432 INFO L93 Difference]: Finished difference Result 942 states and 1304 transitions. [2024-11-24 00:48:05,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 00:48:05,434 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 333 [2024-11-24 00:48:05,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:05,437 INFO L225 Difference]: With dead ends: 942 [2024-11-24 00:48:05,437 INFO L226 Difference]: Without dead ends: 613 [2024-11-24 00:48:05,438 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:05,439 INFO L435 NwaCegarLoop]: 547 mSDtfsCounter, 19 mSDsluCounter, 1632 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 2179 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:05,439 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 2179 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:48:05,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 613 states. [2024-11-24 00:48:05,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 613 to 609. [2024-11-24 00:48:05,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 609 states, 601 states have (on average 1.3727121464226288) internal successors, (825), 601 states have internal predecessors, (825), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:48:05,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 609 states to 609 states and 837 transitions. [2024-11-24 00:48:05,465 INFO L78 Accepts]: Start accepts. Automaton has 609 states and 837 transitions. Word has length 333 [2024-11-24 00:48:05,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:05,466 INFO L471 AbstractCegarLoop]: Abstraction has 609 states and 837 transitions. [2024-11-24 00:48:05,466 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.6) internal successors, (303), 5 states have internal predecessors, (303), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:05,466 INFO L276 IsEmpty]: Start isEmpty. Operand 609 states and 837 transitions. [2024-11-24 00:48:05,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 336 [2024-11-24 00:48:05,470 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:05,471 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:05,471 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2024-11-24 00:48:05,471 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:05,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:05,472 INFO L85 PathProgramCache]: Analyzing trace with hash -543443530, now seen corresponding path program 1 times [2024-11-24 00:48:05,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:05,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1193945086] [2024-11-24 00:48:05,473 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:05,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:06,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:07,339 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:07,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:07,339 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1193945086] [2024-11-24 00:48:07,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1193945086] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:07,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:07,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:48:07,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604758431] [2024-11-24 00:48:07,340 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:07,341 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:48:07,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:07,342 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:48:07,342 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:48:07,342 INFO L87 Difference]: Start difference. First operand 609 states and 837 transitions. Second operand has 6 states, 6 states have (on average 51.333333333333336) internal successors, (308), 6 states have internal predecessors, (308), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:08,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:08,177 INFO L93 Difference]: Finished difference Result 1429 states and 1970 transitions. [2024-11-24 00:48:08,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:48:08,178 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 51.333333333333336) internal successors, (308), 6 states have internal predecessors, (308), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 335 [2024-11-24 00:48:08,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:08,184 INFO L225 Difference]: With dead ends: 1429 [2024-11-24 00:48:08,184 INFO L226 Difference]: Without dead ends: 1058 [2024-11-24 00:48:08,185 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 00:48:08,186 INFO L435 NwaCegarLoop]: 459 mSDtfsCounter, 356 mSDsluCounter, 1865 mSDsCounter, 0 mSdLazyCounter, 602 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 359 SdHoareTripleChecker+Valid, 2324 SdHoareTripleChecker+Invalid, 611 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 602 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:08,186 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [359 Valid, 2324 Invalid, 611 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 602 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 00:48:08,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1058 states. [2024-11-24 00:48:08,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1058 to 936. [2024-11-24 00:48:08,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 936 states, 925 states have (on average 1.3686486486486487) internal successors, (1266), 925 states have internal predecessors, (1266), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 00:48:08,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1284 transitions. [2024-11-24 00:48:08,237 INFO L78 Accepts]: Start accepts. Automaton has 936 states and 1284 transitions. Word has length 335 [2024-11-24 00:48:08,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:08,238 INFO L471 AbstractCegarLoop]: Abstraction has 936 states and 1284 transitions. [2024-11-24 00:48:08,238 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 51.333333333333336) internal successors, (308), 6 states have internal predecessors, (308), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:08,238 INFO L276 IsEmpty]: Start isEmpty. Operand 936 states and 1284 transitions. [2024-11-24 00:48:08,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2024-11-24 00:48:08,244 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:08,244 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:08,244 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2024-11-24 00:48:08,245 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:08,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:08,245 INFO L85 PathProgramCache]: Analyzing trace with hash 1268661504, now seen corresponding path program 1 times [2024-11-24 00:48:08,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:08,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583768943] [2024-11-24 00:48:08,246 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:08,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:09,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:10,764 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 39 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2024-11-24 00:48:10,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:10,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583768943] [2024-11-24 00:48:10,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583768943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:10,765 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:10,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:48:10,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993609419] [2024-11-24 00:48:10,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:10,767 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:48:10,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:10,768 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:48:10,768 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:10,769 INFO L87 Difference]: Start difference. First operand 936 states and 1284 transitions. Second operand has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:48:11,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:11,279 INFO L93 Difference]: Finished difference Result 1601 states and 2173 transitions. [2024-11-24 00:48:11,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 00:48:11,279 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 336 [2024-11-24 00:48:11,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:11,283 INFO L225 Difference]: With dead ends: 1601 [2024-11-24 00:48:11,284 INFO L226 Difference]: Without dead ends: 948 [2024-11-24 00:48:11,285 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:11,285 INFO L435 NwaCegarLoop]: 404 mSDtfsCounter, 325 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 460 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 325 SdHoareTripleChecker+Valid, 1191 SdHoareTripleChecker+Invalid, 460 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:11,286 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [325 Valid, 1191 Invalid, 460 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 460 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-24 00:48:11,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 948 states. [2024-11-24 00:48:11,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 948 to 942. [2024-11-24 00:48:11,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 942 states, 931 states have (on average 1.3662728249194414) internal successors, (1272), 931 states have internal predecessors, (1272), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 00:48:11,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 942 states to 942 states and 1290 transitions. [2024-11-24 00:48:11,325 INFO L78 Accepts]: Start accepts. Automaton has 942 states and 1290 transitions. Word has length 336 [2024-11-24 00:48:11,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:11,326 INFO L471 AbstractCegarLoop]: Abstraction has 942 states and 1290 transitions. [2024-11-24 00:48:11,326 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:48:11,327 INFO L276 IsEmpty]: Start isEmpty. Operand 942 states and 1290 transitions. [2024-11-24 00:48:11,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2024-11-24 00:48:11,331 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:11,331 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:11,331 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31 [2024-11-24 00:48:11,331 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:11,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:11,332 INFO L85 PathProgramCache]: Analyzing trace with hash -730592032, now seen corresponding path program 1 times [2024-11-24 00:48:11,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:11,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148133871] [2024-11-24 00:48:11,332 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:11,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:12,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:12,837 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-24 00:48:12,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:12,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148133871] [2024-11-24 00:48:12,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148133871] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:12,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:12,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:48:12,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792978593] [2024-11-24 00:48:12,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:12,839 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:48:12,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:12,839 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:48:12,839 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:48:12,840 INFO L87 Difference]: Start difference. First operand 942 states and 1290 transitions. Second operand has 4 states, 4 states have (on average 69.0) internal successors, (276), 4 states have internal predecessors, (276), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:13,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:13,227 INFO L93 Difference]: Finished difference Result 1597 states and 2163 transitions. [2024-11-24 00:48:13,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:48:13,227 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 69.0) internal successors, (276), 4 states have internal predecessors, (276), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 336 [2024-11-24 00:48:13,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:13,231 INFO L225 Difference]: With dead ends: 1597 [2024-11-24 00:48:13,232 INFO L226 Difference]: Without dead ends: 942 [2024-11-24 00:48:13,233 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:48:13,233 INFO L435 NwaCegarLoop]: 405 mSDtfsCounter, 504 mSDsluCounter, 397 mSDsCounter, 0 mSdLazyCounter, 299 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 504 SdHoareTripleChecker+Valid, 802 SdHoareTripleChecker+Invalid, 300 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 299 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:13,234 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [504 Valid, 802 Invalid, 300 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 299 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 00:48:13,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 942 states. [2024-11-24 00:48:13,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 942 to 942. [2024-11-24 00:48:13,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 942 states, 931 states have (on average 1.359828141783029) internal successors, (1266), 931 states have internal predecessors, (1266), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 00:48:13,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 942 states to 942 states and 1284 transitions. [2024-11-24 00:48:13,266 INFO L78 Accepts]: Start accepts. Automaton has 942 states and 1284 transitions. Word has length 336 [2024-11-24 00:48:13,266 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:13,266 INFO L471 AbstractCegarLoop]: Abstraction has 942 states and 1284 transitions. [2024-11-24 00:48:13,266 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 69.0) internal successors, (276), 4 states have internal predecessors, (276), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:13,267 INFO L276 IsEmpty]: Start isEmpty. Operand 942 states and 1284 transitions. [2024-11-24 00:48:13,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 339 [2024-11-24 00:48:13,270 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:13,270 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:13,270 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2024-11-24 00:48:13,271 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:13,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:13,271 INFO L85 PathProgramCache]: Analyzing trace with hash 931392926, now seen corresponding path program 1 times [2024-11-24 00:48:13,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:13,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485212734] [2024-11-24 00:48:13,272 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:13,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:14,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:15,615 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 85 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:15,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:15,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485212734] [2024-11-24 00:48:15,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485212734] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:15,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:15,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:48:15,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590464758] [2024-11-24 00:48:15,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:15,617 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:48:15,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:15,618 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:48:15,618 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:48:15,619 INFO L87 Difference]: Start difference. First operand 942 states and 1284 transitions. Second operand has 6 states, 6 states have (on average 51.833333333333336) internal successors, (311), 6 states have internal predecessors, (311), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:16,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:16,402 INFO L93 Difference]: Finished difference Result 1338 states and 1828 transitions. [2024-11-24 00:48:16,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:48:16,403 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 51.833333333333336) internal successors, (311), 6 states have internal predecessors, (311), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 338 [2024-11-24 00:48:16,404 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:16,407 INFO L225 Difference]: With dead ends: 1338 [2024-11-24 00:48:16,407 INFO L226 Difference]: Without dead ends: 965 [2024-11-24 00:48:16,408 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-11-24 00:48:16,409 INFO L435 NwaCegarLoop]: 398 mSDtfsCounter, 765 mSDsluCounter, 1178 mSDsCounter, 0 mSdLazyCounter, 631 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 768 SdHoareTripleChecker+Valid, 1576 SdHoareTripleChecker+Invalid, 631 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 631 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:16,409 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [768 Valid, 1576 Invalid, 631 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 631 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 00:48:16,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 965 states. [2024-11-24 00:48:16,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 965 to 943. [2024-11-24 00:48:16,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 943 states, 932 states have (on average 1.359442060085837) internal successors, (1267), 932 states have internal predecessors, (1267), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 00:48:16,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 943 states to 943 states and 1285 transitions. [2024-11-24 00:48:16,449 INFO L78 Accepts]: Start accepts. Automaton has 943 states and 1285 transitions. Word has length 338 [2024-11-24 00:48:16,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:16,449 INFO L471 AbstractCegarLoop]: Abstraction has 943 states and 1285 transitions. [2024-11-24 00:48:16,450 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 51.833333333333336) internal successors, (311), 6 states have internal predecessors, (311), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:16,450 INFO L276 IsEmpty]: Start isEmpty. Operand 943 states and 1285 transitions. [2024-11-24 00:48:16,454 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 339 [2024-11-24 00:48:16,455 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:16,455 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:16,455 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2024-11-24 00:48:16,456 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:16,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:16,456 INFO L85 PathProgramCache]: Analyzing trace with hash 264224577, now seen corresponding path program 1 times [2024-11-24 00:48:16,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:16,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172261054] [2024-11-24 00:48:16,457 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:16,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:17,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:18,912 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 114 trivial. 0 not checked. [2024-11-24 00:48:18,912 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:18,912 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172261054] [2024-11-24 00:48:18,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172261054] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:18,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:18,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 00:48:18,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258435500] [2024-11-24 00:48:18,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:18,914 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 00:48:18,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:18,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 00:48:18,915 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 00:48:18,915 INFO L87 Difference]: Start difference. First operand 943 states and 1285 transitions. Second operand has 8 states, 8 states have (on average 32.5) internal successors, (260), 8 states have internal predecessors, (260), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:19,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:19,170 INFO L93 Difference]: Finished difference Result 2126 states and 2889 transitions. [2024-11-24 00:48:19,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 00:48:19,171 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 32.5) internal successors, (260), 8 states have internal predecessors, (260), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 338 [2024-11-24 00:48:19,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:19,176 INFO L225 Difference]: With dead ends: 2126 [2024-11-24 00:48:19,177 INFO L226 Difference]: Without dead ends: 1635 [2024-11-24 00:48:19,178 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:48:19,180 INFO L435 NwaCegarLoop]: 1313 mSDtfsCounter, 808 mSDsluCounter, 5624 mSDsCounter, 0 mSdLazyCounter, 149 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 811 SdHoareTripleChecker+Valid, 6937 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 149 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:19,180 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [811 Valid, 6937 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 149 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 00:48:19,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1635 states. [2024-11-24 00:48:19,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1635 to 1012. [2024-11-24 00:48:19,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1012 states, 998 states have (on average 1.3627254509018036) internal successors, (1360), 998 states have internal predecessors, (1360), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 00:48:19,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1012 states to 1012 states and 1384 transitions. [2024-11-24 00:48:19,218 INFO L78 Accepts]: Start accepts. Automaton has 1012 states and 1384 transitions. Word has length 338 [2024-11-24 00:48:19,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:19,219 INFO L471 AbstractCegarLoop]: Abstraction has 1012 states and 1384 transitions. [2024-11-24 00:48:19,219 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 32.5) internal successors, (260), 8 states have internal predecessors, (260), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:19,219 INFO L276 IsEmpty]: Start isEmpty. Operand 1012 states and 1384 transitions. [2024-11-24 00:48:19,223 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 340 [2024-11-24 00:48:19,223 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:19,224 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:19,224 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2024-11-24 00:48:19,225 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:19,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:19,226 INFO L85 PathProgramCache]: Analyzing trace with hash 2025188781, now seen corresponding path program 1 times [2024-11-24 00:48:19,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:19,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053622812] [2024-11-24 00:48:19,226 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:19,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:20,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:21,358 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 138 trivial. 0 not checked. [2024-11-24 00:48:21,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:21,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053622812] [2024-11-24 00:48:21,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053622812] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:21,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:21,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:48:21,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43229245] [2024-11-24 00:48:21,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:21,360 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:48:21,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:21,361 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:48:21,361 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:48:21,361 INFO L87 Difference]: Start difference. First operand 1012 states and 1384 transitions. Second operand has 6 states, 6 states have (on average 40.0) internal successors, (240), 6 states have internal predecessors, (240), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:48:22,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:22,022 INFO L93 Difference]: Finished difference Result 1892 states and 2572 transitions. [2024-11-24 00:48:22,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:48:22,023 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 40.0) internal successors, (240), 6 states have internal predecessors, (240), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 339 [2024-11-24 00:48:22,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:22,027 INFO L225 Difference]: With dead ends: 1892 [2024-11-24 00:48:22,027 INFO L226 Difference]: Without dead ends: 1020 [2024-11-24 00:48:22,029 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:48:22,029 INFO L435 NwaCegarLoop]: 391 mSDtfsCounter, 511 mSDsluCounter, 1166 mSDsCounter, 0 mSdLazyCounter, 650 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 514 SdHoareTripleChecker+Valid, 1557 SdHoareTripleChecker+Invalid, 651 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 650 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:22,030 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [514 Valid, 1557 Invalid, 651 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 650 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 00:48:22,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1020 states. [2024-11-24 00:48:22,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1020 to 1016. [2024-11-24 00:48:22,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1016 states, 1002 states have (on average 1.3572854291417165) internal successors, (1360), 1002 states have internal predecessors, (1360), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 00:48:22,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1016 states to 1016 states and 1384 transitions. [2024-11-24 00:48:22,062 INFO L78 Accepts]: Start accepts. Automaton has 1016 states and 1384 transitions. Word has length 339 [2024-11-24 00:48:22,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:22,062 INFO L471 AbstractCegarLoop]: Abstraction has 1016 states and 1384 transitions. [2024-11-24 00:48:22,062 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 40.0) internal successors, (240), 6 states have internal predecessors, (240), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:48:22,062 INFO L276 IsEmpty]: Start isEmpty. Operand 1016 states and 1384 transitions. [2024-11-24 00:48:22,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 342 [2024-11-24 00:48:22,066 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:22,066 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:22,067 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2024-11-24 00:48:22,067 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:22,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:22,068 INFO L85 PathProgramCache]: Analyzing trace with hash 615740921, now seen corresponding path program 1 times [2024-11-24 00:48:22,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:22,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056550359] [2024-11-24 00:48:22,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:22,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:23,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:24,934 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 4 proven. 82 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:24,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:24,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056550359] [2024-11-24 00:48:24,934 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056550359] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:24,934 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [316928179] [2024-11-24 00:48:24,934 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:24,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:24,935 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:48:24,938 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:48:24,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-24 00:48:26,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:26,515 INFO L256 TraceCheckSpWp]: Trace formula consists of 2047 conjuncts, 35 conjuncts are in the unsatisfiable core [2024-11-24 00:48:26,541 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:48:27,070 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 60 proven. 0 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2024-11-24 00:48:27,071 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:48:27,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [316928179] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:27,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:48:27,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [11] total 19 [2024-11-24 00:48:27,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295852744] [2024-11-24 00:48:27,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:27,072 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-24 00:48:27,073 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:27,073 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-24 00:48:27,073 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=299, Unknown=0, NotChecked=0, Total=342 [2024-11-24 00:48:27,074 INFO L87 Difference]: Start difference. First operand 1016 states and 1384 transitions. Second operand has 10 states, 10 states have (on average 26.3) internal successors, (263), 10 states have internal predecessors, (263), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 00:48:28,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:28,104 INFO L93 Difference]: Finished difference Result 1855 states and 2516 transitions. [2024-11-24 00:48:28,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 00:48:28,105 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 26.3) internal successors, (263), 10 states have internal predecessors, (263), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 341 [2024-11-24 00:48:28,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:28,108 INFO L225 Difference]: With dead ends: 1855 [2024-11-24 00:48:28,108 INFO L226 Difference]: Without dead ends: 1036 [2024-11-24 00:48:28,109 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 354 GetRequests, 334 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=55, Invalid=407, Unknown=0, NotChecked=0, Total=462 [2024-11-24 00:48:28,109 INFO L435 NwaCegarLoop]: 380 mSDtfsCounter, 494 mSDsluCounter, 2627 mSDsCounter, 0 mSdLazyCounter, 1374 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 495 SdHoareTripleChecker+Valid, 3007 SdHoareTripleChecker+Invalid, 1377 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1374 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:28,110 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [495 Valid, 3007 Invalid, 1377 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1374 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-24 00:48:28,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1036 states. [2024-11-24 00:48:28,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1036 to 1028. [2024-11-24 00:48:28,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1028 states, 1014 states have (on average 1.3451676528599605) internal successors, (1364), 1014 states have internal predecessors, (1364), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 00:48:28,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1388 transitions. [2024-11-24 00:48:28,137 INFO L78 Accepts]: Start accepts. Automaton has 1028 states and 1388 transitions. Word has length 341 [2024-11-24 00:48:28,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:28,138 INFO L471 AbstractCegarLoop]: Abstraction has 1028 states and 1388 transitions. [2024-11-24 00:48:28,138 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 26.3) internal successors, (263), 10 states have internal predecessors, (263), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 00:48:28,138 INFO L276 IsEmpty]: Start isEmpty. Operand 1028 states and 1388 transitions. [2024-11-24 00:48:28,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 346 [2024-11-24 00:48:28,141 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:28,141 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:28,158 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-24 00:48:28,342 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2024-11-24 00:48:28,342 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:28,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:28,343 INFO L85 PathProgramCache]: Analyzing trace with hash 545994611, now seen corresponding path program 1 times [2024-11-24 00:48:28,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:28,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132175030] [2024-11-24 00:48:28,343 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:28,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:29,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:31,159 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 4 proven. 84 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:31,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:31,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132175030] [2024-11-24 00:48:31,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132175030] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:31,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [61301228] [2024-11-24 00:48:31,160 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:31,160 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:31,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:48:31,166 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:48:31,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 00:48:32,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:32,560 INFO L256 TraceCheckSpWp]: Trace formula consists of 2055 conjuncts, 33 conjuncts are in the unsatisfiable core [2024-11-24 00:48:32,578 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:48:32,912 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2024-11-24 00:48:32,912 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:48:32,912 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [61301228] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:32,912 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:48:32,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 15 [2024-11-24 00:48:32,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50028636] [2024-11-24 00:48:32,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:32,913 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:48:32,913 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:32,914 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:48:32,914 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2024-11-24 00:48:32,914 INFO L87 Difference]: Start difference. First operand 1028 states and 1388 transitions. Second operand has 6 states, 6 states have (on average 43.0) internal successors, (258), 6 states have internal predecessors, (258), 2 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-24 00:48:33,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:33,528 INFO L93 Difference]: Finished difference Result 1863 states and 2505 transitions. [2024-11-24 00:48:33,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:48:33,529 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 43.0) internal successors, (258), 6 states have internal predecessors, (258), 2 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 345 [2024-11-24 00:48:33,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:33,533 INFO L225 Difference]: With dead ends: 1863 [2024-11-24 00:48:33,533 INFO L226 Difference]: Without dead ends: 1044 [2024-11-24 00:48:33,535 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 355 GetRequests, 342 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=34, Invalid=176, Unknown=0, NotChecked=0, Total=210 [2024-11-24 00:48:33,535 INFO L435 NwaCegarLoop]: 389 mSDtfsCounter, 494 mSDsluCounter, 1139 mSDsCounter, 0 mSdLazyCounter, 650 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 496 SdHoareTripleChecker+Valid, 1528 SdHoareTripleChecker+Invalid, 651 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 650 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:33,535 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [496 Valid, 1528 Invalid, 651 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 650 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 00:48:33,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1044 states. [2024-11-24 00:48:33,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1044 to 1040. [2024-11-24 00:48:33,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1040 states, 1026 states have (on average 1.341130604288499) internal successors, (1376), 1026 states have internal predecessors, (1376), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 00:48:33,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1400 transitions. [2024-11-24 00:48:33,571 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1400 transitions. Word has length 345 [2024-11-24 00:48:33,571 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:33,571 INFO L471 AbstractCegarLoop]: Abstraction has 1040 states and 1400 transitions. [2024-11-24 00:48:33,571 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 43.0) internal successors, (258), 6 states have internal predecessors, (258), 2 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-11-24 00:48:33,572 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1400 transitions. [2024-11-24 00:48:33,575 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 350 [2024-11-24 00:48:33,575 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:33,576 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:33,595 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-24 00:48:33,780 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2024-11-24 00:48:33,781 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:33,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:33,781 INFO L85 PathProgramCache]: Analyzing trace with hash 568587949, now seen corresponding path program 1 times [2024-11-24 00:48:33,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:33,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888598170] [2024-11-24 00:48:33,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:33,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:35,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:36,707 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 4 proven. 86 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:36,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:36,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888598170] [2024-11-24 00:48:36,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888598170] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:36,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1996586219] [2024-11-24 00:48:36,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:36,708 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:36,708 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:48:36,711 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:48:36,715 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-24 00:48:38,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:38,534 INFO L256 TraceCheckSpWp]: Trace formula consists of 2063 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-24 00:48:38,547 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:48:38,886 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 120 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-11-24 00:48:38,886 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:48:38,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1996586219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:38,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:48:38,887 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [11] total 17 [2024-11-24 00:48:38,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317066057] [2024-11-24 00:48:38,887 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:38,888 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 00:48:38,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:38,889 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 00:48:38,889 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2024-11-24 00:48:38,889 INFO L87 Difference]: Start difference. First operand 1040 states and 1400 transitions. Second operand has 8 states, 8 states have (on average 40.25) internal successors, (322), 8 states have internal predecessors, (322), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:39,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:39,737 INFO L93 Difference]: Finished difference Result 2333 states and 3148 transitions. [2024-11-24 00:48:39,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 00:48:39,738 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 40.25) internal successors, (322), 8 states have internal predecessors, (322), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 349 [2024-11-24 00:48:39,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:39,744 INFO L225 Difference]: With dead ends: 2333 [2024-11-24 00:48:39,744 INFO L226 Difference]: Without dead ends: 1810 [2024-11-24 00:48:39,745 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 344 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2024-11-24 00:48:39,747 INFO L435 NwaCegarLoop]: 395 mSDtfsCounter, 932 mSDsluCounter, 1958 mSDsCounter, 0 mSdLazyCounter, 940 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 938 SdHoareTripleChecker+Valid, 2353 SdHoareTripleChecker+Invalid, 940 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 940 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:39,747 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [938 Valid, 2353 Invalid, 940 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 940 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 00:48:39,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1810 states. [2024-11-24 00:48:39,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1810 to 1464. [2024-11-24 00:48:39,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1441 states have (on average 1.3226925746009714) internal successors, (1906), 1441 states have internal predecessors, (1906), 21 states have call successors, (21), 1 states have call predecessors, (21), 1 states have return successors, (21), 21 states have call predecessors, (21), 21 states have call successors, (21) [2024-11-24 00:48:39,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 1948 transitions. [2024-11-24 00:48:39,811 INFO L78 Accepts]: Start accepts. Automaton has 1464 states and 1948 transitions. Word has length 349 [2024-11-24 00:48:39,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:39,812 INFO L471 AbstractCegarLoop]: Abstraction has 1464 states and 1948 transitions. [2024-11-24 00:48:39,812 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 40.25) internal successors, (322), 8 states have internal predecessors, (322), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:39,812 INFO L276 IsEmpty]: Start isEmpty. Operand 1464 states and 1948 transitions. [2024-11-24 00:48:39,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 350 [2024-11-24 00:48:39,818 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:39,818 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:39,838 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-24 00:48:40,019 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable38 [2024-11-24 00:48:40,019 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:40,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:40,020 INFO L85 PathProgramCache]: Analyzing trace with hash -96894230, now seen corresponding path program 1 times [2024-11-24 00:48:40,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:40,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259971730] [2024-11-24 00:48:40,021 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:40,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:40,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:40,933 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 101 trivial. 0 not checked. [2024-11-24 00:48:40,937 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:40,937 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1259971730] [2024-11-24 00:48:40,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1259971730] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:40,937 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:40,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:48:40,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1272373709] [2024-11-24 00:48:40,937 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:40,938 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:48:40,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:40,939 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:48:40,939 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:40,940 INFO L87 Difference]: Start difference. First operand 1464 states and 1948 transitions. Second operand has 5 states, 5 states have (on average 57.0) internal successors, (285), 5 states have internal predecessors, (285), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:41,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:41,068 INFO L93 Difference]: Finished difference Result 2267 states and 3025 transitions. [2024-11-24 00:48:41,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 00:48:41,068 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 57.0) internal successors, (285), 5 states have internal predecessors, (285), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 349 [2024-11-24 00:48:41,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:41,078 INFO L225 Difference]: With dead ends: 2267 [2024-11-24 00:48:41,078 INFO L226 Difference]: Without dead ends: 1554 [2024-11-24 00:48:41,080 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:48:41,080 INFO L435 NwaCegarLoop]: 546 mSDtfsCounter, 16 mSDsluCounter, 1626 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 2172 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:41,081 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 2172 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:48:41,083 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1554 states. [2024-11-24 00:48:41,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1554 to 1554. [2024-11-24 00:48:41,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1554 states, 1531 states have (on average 1.3298497713912476) internal successors, (2036), 1531 states have internal predecessors, (2036), 21 states have call successors, (21), 1 states have call predecessors, (21), 1 states have return successors, (21), 21 states have call predecessors, (21), 21 states have call successors, (21) [2024-11-24 00:48:41,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 1554 states and 2078 transitions. [2024-11-24 00:48:41,125 INFO L78 Accepts]: Start accepts. Automaton has 1554 states and 2078 transitions. Word has length 349 [2024-11-24 00:48:41,125 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:41,125 INFO L471 AbstractCegarLoop]: Abstraction has 1554 states and 2078 transitions. [2024-11-24 00:48:41,125 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 57.0) internal successors, (285), 5 states have internal predecessors, (285), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:41,125 INFO L276 IsEmpty]: Start isEmpty. Operand 1554 states and 2078 transitions. [2024-11-24 00:48:41,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 351 [2024-11-24 00:48:41,130 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:41,130 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:41,130 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable39 [2024-11-24 00:48:41,130 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:41,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:41,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1377398202, now seen corresponding path program 1 times [2024-11-24 00:48:41,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:41,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [529927277] [2024-11-24 00:48:41,131 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:41,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:42,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:43,923 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 4 proven. 86 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:43,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:43,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [529927277] [2024-11-24 00:48:43,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [529927277] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:43,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2016487623] [2024-11-24 00:48:43,923 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:43,923 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:43,923 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:48:43,925 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:48:43,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 00:48:45,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:45,734 INFO L256 TraceCheckSpWp]: Trace formula consists of 2066 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-11-24 00:48:45,741 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:48:46,072 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 84 proven. 6 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:46,072 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:48:46,576 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 90 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:46,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2016487623] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:46,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 00:48:46,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11, 8] total 22 [2024-11-24 00:48:46,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260709741] [2024-11-24 00:48:46,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:46,577 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 00:48:46,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:46,579 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 00:48:46,579 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2024-11-24 00:48:46,579 INFO L87 Difference]: Start difference. First operand 1554 states and 2078 transitions. Second operand has 7 states, 7 states have (on average 46.142857142857146) internal successors, (323), 7 states have internal predecessors, (323), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:46,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:46,771 INFO L93 Difference]: Finished difference Result 2348 states and 3157 transitions. [2024-11-24 00:48:46,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 00:48:46,772 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 46.142857142857146) internal successors, (323), 7 states have internal predecessors, (323), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 350 [2024-11-24 00:48:46,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:46,782 INFO L225 Difference]: With dead ends: 2348 [2024-11-24 00:48:46,786 INFO L226 Difference]: Without dead ends: 1950 [2024-11-24 00:48:46,787 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 712 GetRequests, 690 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2024-11-24 00:48:46,787 INFO L435 NwaCegarLoop]: 970 mSDtfsCounter, 354 mSDsluCounter, 4400 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 354 SdHoareTripleChecker+Valid, 5370 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:46,788 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [354 Valid, 5370 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:48:46,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1950 states. [2024-11-24 00:48:46,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1950 to 1747. [2024-11-24 00:48:46,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1747 states, 1721 states have (on average 1.3248111563044742) internal successors, (2280), 1721 states have internal predecessors, (2280), 24 states have call successors, (24), 1 states have call predecessors, (24), 1 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2024-11-24 00:48:46,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1747 states to 1747 states and 2328 transitions. [2024-11-24 00:48:46,836 INFO L78 Accepts]: Start accepts. Automaton has 1747 states and 2328 transitions. Word has length 350 [2024-11-24 00:48:46,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:46,836 INFO L471 AbstractCegarLoop]: Abstraction has 1747 states and 2328 transitions. [2024-11-24 00:48:46,836 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 46.142857142857146) internal successors, (323), 7 states have internal predecessors, (323), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:48:46,837 INFO L276 IsEmpty]: Start isEmpty. Operand 1747 states and 2328 transitions. [2024-11-24 00:48:46,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 352 [2024-11-24 00:48:46,843 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:46,843 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:46,861 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-24 00:48:47,043 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:47,044 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:47,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:47,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1364522509, now seen corresponding path program 1 times [2024-11-24 00:48:47,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:47,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664206807] [2024-11-24 00:48:47,045 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:47,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:47,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:49,497 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 4 proven. 87 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:48:49,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:49,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664206807] [2024-11-24 00:48:49,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664206807] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:48:49,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [245419364] [2024-11-24 00:48:49,498 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:49,498 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:49,498 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:48:49,502 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:48:49,504 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-24 00:48:51,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:51,987 INFO L256 TraceCheckSpWp]: Trace formula consists of 2069 conjuncts, 103 conjuncts are in the unsatisfiable core [2024-11-24 00:48:52,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:48:54,432 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 127 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-24 00:48:54,433 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:48:54,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [245419364] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:54,433 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:48:54,433 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [11] total 21 [2024-11-24 00:48:54,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296877385] [2024-11-24 00:48:54,433 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:54,434 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-24 00:48:54,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:54,435 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-24 00:48:54,435 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=365, Unknown=0, NotChecked=0, Total=420 [2024-11-24 00:48:54,435 INFO L87 Difference]: Start difference. First operand 1747 states and 2328 transitions. Second operand has 12 states, 12 states have (on average 27.25) internal successors, (327), 12 states have internal predecessors, (327), 3 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:48:56,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:48:56,719 INFO L93 Difference]: Finished difference Result 3724 states and 4941 transitions. [2024-11-24 00:48:56,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-24 00:48:56,720 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 27.25) internal successors, (327), 12 states have internal predecessors, (327), 3 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 351 [2024-11-24 00:48:56,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:48:56,728 INFO L225 Difference]: With dead ends: 3724 [2024-11-24 00:48:56,728 INFO L226 Difference]: Without dead ends: 3133 [2024-11-24 00:48:56,730 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 342 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=55, Invalid=365, Unknown=0, NotChecked=0, Total=420 [2024-11-24 00:48:56,731 INFO L435 NwaCegarLoop]: 618 mSDtfsCounter, 721 mSDsluCounter, 4482 mSDsCounter, 0 mSdLazyCounter, 2634 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 723 SdHoareTripleChecker+Valid, 5100 SdHoareTripleChecker+Invalid, 2635 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2634 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.2s IncrementalHoareTripleChecker+Time [2024-11-24 00:48:56,731 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [723 Valid, 5100 Invalid, 2635 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2634 Invalid, 0 Unknown, 0 Unchecked, 2.2s Time] [2024-11-24 00:48:56,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3133 states. [2024-11-24 00:48:56,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3133 to 3107. [2024-11-24 00:48:56,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3107 states, 3065 states have (on average 1.3187601957585644) internal successors, (4042), 3065 states have internal predecessors, (4042), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-11-24 00:48:56,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3107 states to 3107 states and 4122 transitions. [2024-11-24 00:48:56,801 INFO L78 Accepts]: Start accepts. Automaton has 3107 states and 4122 transitions. Word has length 351 [2024-11-24 00:48:56,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:48:56,802 INFO L471 AbstractCegarLoop]: Abstraction has 3107 states and 4122 transitions. [2024-11-24 00:48:56,802 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 27.25) internal successors, (327), 12 states have internal predecessors, (327), 3 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:48:56,802 INFO L276 IsEmpty]: Start isEmpty. Operand 3107 states and 4122 transitions. [2024-11-24 00:48:56,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 352 [2024-11-24 00:48:56,809 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:48:56,809 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:48:56,827 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-24 00:48:57,009 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:48:57,010 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:48:57,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:48:57,010 INFO L85 PathProgramCache]: Analyzing trace with hash -1344369747, now seen corresponding path program 1 times [2024-11-24 00:48:57,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:48:57,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450869022] [2024-11-24 00:48:57,010 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:48:57,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:48:58,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:48:59,845 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 107 trivial. 0 not checked. [2024-11-24 00:48:59,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:48:59,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450869022] [2024-11-24 00:48:59,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450869022] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:48:59,846 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:48:59,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 00:48:59,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2111044040] [2024-11-24 00:48:59,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:48:59,847 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 00:48:59,847 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:48:59,848 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 00:48:59,848 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:48:59,848 INFO L87 Difference]: Start difference. First operand 3107 states and 4122 transitions. Second operand has 9 states, 9 states have (on average 31.11111111111111) internal successors, (280), 9 states have internal predecessors, (280), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:01,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:01,442 INFO L93 Difference]: Finished difference Result 7741 states and 10161 transitions. [2024-11-24 00:49:01,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 00:49:01,442 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 31.11111111111111) internal successors, (280), 9 states have internal predecessors, (280), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 351 [2024-11-24 00:49:01,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:01,456 INFO L225 Difference]: With dead ends: 7741 [2024-11-24 00:49:01,457 INFO L226 Difference]: Without dead ends: 5515 [2024-11-24 00:49:01,459 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2024-11-24 00:49:01,460 INFO L435 NwaCegarLoop]: 605 mSDtfsCounter, 1336 mSDsluCounter, 2747 mSDsCounter, 0 mSdLazyCounter, 1547 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1337 SdHoareTripleChecker+Valid, 3352 SdHoareTripleChecker+Invalid, 1550 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1547 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:01,461 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1337 Valid, 3352 Invalid, 1550 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1547 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-24 00:49:01,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5515 states. [2024-11-24 00:49:01,578 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5515 to 3579. [2024-11-24 00:49:01,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3579 states, 3521 states have (on average 1.3229196251065038) internal successors, (4658), 3521 states have internal predecessors, (4658), 56 states have call successors, (56), 1 states have call predecessors, (56), 1 states have return successors, (56), 56 states have call predecessors, (56), 56 states have call successors, (56) [2024-11-24 00:49:01,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3579 states to 3579 states and 4770 transitions. [2024-11-24 00:49:01,592 INFO L78 Accepts]: Start accepts. Automaton has 3579 states and 4770 transitions. Word has length 351 [2024-11-24 00:49:01,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:01,593 INFO L471 AbstractCegarLoop]: Abstraction has 3579 states and 4770 transitions. [2024-11-24 00:49:01,593 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 31.11111111111111) internal successors, (280), 9 states have internal predecessors, (280), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:01,593 INFO L276 IsEmpty]: Start isEmpty. Operand 3579 states and 4770 transitions. [2024-11-24 00:49:01,604 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 352 [2024-11-24 00:49:01,605 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:01,605 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:01,605 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-11-24 00:49:01,605 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:01,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:01,606 INFO L85 PathProgramCache]: Analyzing trace with hash 533469101, now seen corresponding path program 1 times [2024-11-24 00:49:01,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:01,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334776040] [2024-11-24 00:49:01,607 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:01,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:03,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:05,359 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 4 proven. 85 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:05,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:05,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1334776040] [2024-11-24 00:49:05,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1334776040] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:05,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1902832972] [2024-11-24 00:49:05,360 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:05,360 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:05,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:05,362 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:05,363 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-24 00:49:07,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:07,427 INFO L256 TraceCheckSpWp]: Trace formula consists of 2069 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 00:49:07,438 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:07,527 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 57 proven. 0 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2024-11-24 00:49:07,527 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:49:07,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1902832972] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:49:07,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:49:07,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [11] total 15 [2024-11-24 00:49:07,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686110938] [2024-11-24 00:49:07,528 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:49:07,529 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:49:07,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:07,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:49:07,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 00:49:07,530 INFO L87 Difference]: Start difference. First operand 3579 states and 4770 transitions. Second operand has 6 states, 5 states have (on average 53.4) internal successors, (267), 6 states have internal predecessors, (267), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 00:49:07,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:07,669 INFO L93 Difference]: Finished difference Result 5806 states and 7742 transitions. [2024-11-24 00:49:07,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:49:07,670 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 53.4) internal successors, (267), 6 states have internal predecessors, (267), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) Word has length 351 [2024-11-24 00:49:07,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:07,680 INFO L225 Difference]: With dead ends: 5806 [2024-11-24 00:49:07,680 INFO L226 Difference]: Without dead ends: 3579 [2024-11-24 00:49:07,684 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 361 GetRequests, 348 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=179, Unknown=0, NotChecked=0, Total=210 [2024-11-24 00:49:07,684 INFO L435 NwaCegarLoop]: 546 mSDtfsCounter, 0 mSDsluCounter, 2165 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2711 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:07,685 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2711 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:49:07,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3579 states. [2024-11-24 00:49:07,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3579 to 3579. [2024-11-24 00:49:07,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3579 states, 3521 states have (on average 1.3206475433115592) internal successors, (4650), 3521 states have internal predecessors, (4650), 56 states have call successors, (56), 1 states have call predecessors, (56), 1 states have return successors, (56), 56 states have call predecessors, (56), 56 states have call successors, (56) [2024-11-24 00:49:07,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3579 states to 3579 states and 4762 transitions. [2024-11-24 00:49:07,770 INFO L78 Accepts]: Start accepts. Automaton has 3579 states and 4762 transitions. Word has length 351 [2024-11-24 00:49:07,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:07,770 INFO L471 AbstractCegarLoop]: Abstraction has 3579 states and 4762 transitions. [2024-11-24 00:49:07,771 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 53.4) internal successors, (267), 6 states have internal predecessors, (267), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 00:49:07,771 INFO L276 IsEmpty]: Start isEmpty. Operand 3579 states and 4762 transitions. [2024-11-24 00:49:07,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2024-11-24 00:49:07,777 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:07,777 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:07,795 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-24 00:49:07,977 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:07,978 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:07,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:07,978 INFO L85 PathProgramCache]: Analyzing trace with hash -1714414053, now seen corresponding path program 1 times [2024-11-24 00:49:07,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:07,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396885635] [2024-11-24 00:49:07,979 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:07,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:09,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:14,591 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 51 proven. 40 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:14,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:14,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396885635] [2024-11-24 00:49:14,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396885635] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:14,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [259390282] [2024-11-24 00:49:14,591 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:14,591 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:14,592 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:14,599 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:14,602 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-24 00:49:16,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:16,568 INFO L256 TraceCheckSpWp]: Trace formula consists of 2072 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-11-24 00:49:16,578 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:17,344 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 127 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-24 00:49:17,345 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:49:17,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [259390282] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:49:17,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:49:17,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [18] total 22 [2024-11-24 00:49:17,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121695743] [2024-11-24 00:49:17,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:49:17,346 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:49:17,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:17,347 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:49:17,348 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=394, Unknown=0, NotChecked=0, Total=462 [2024-11-24 00:49:17,348 INFO L87 Difference]: Start difference. First operand 3579 states and 4762 transitions. Second operand has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:49:18,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:18,036 INFO L93 Difference]: Finished difference Result 4977 states and 6656 transitions. [2024-11-24 00:49:18,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:49:18,037 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 352 [2024-11-24 00:49:18,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:18,045 INFO L225 Difference]: With dead ends: 4977 [2024-11-24 00:49:18,046 INFO L226 Difference]: Without dead ends: 3650 [2024-11-24 00:49:18,048 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 369 GetRequests, 349 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 120 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=68, Invalid=394, Unknown=0, NotChecked=0, Total=462 [2024-11-24 00:49:18,049 INFO L435 NwaCegarLoop]: 399 mSDtfsCounter, 436 mSDsluCounter, 1162 mSDsCounter, 0 mSdLazyCounter, 634 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 436 SdHoareTripleChecker+Valid, 1561 SdHoareTripleChecker+Invalid, 636 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 634 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:18,049 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [436 Valid, 1561 Invalid, 636 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 634 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 00:49:18,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3650 states. [2024-11-24 00:49:18,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3650 to 3650. [2024-11-24 00:49:18,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3650 states, 3592 states have (on average 1.322661469933185) internal successors, (4751), 3592 states have internal predecessors, (4751), 56 states have call successors, (56), 1 states have call predecessors, (56), 1 states have return successors, (56), 56 states have call predecessors, (56), 56 states have call successors, (56) [2024-11-24 00:49:18,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3650 states to 3650 states and 4863 transitions. [2024-11-24 00:49:18,149 INFO L78 Accepts]: Start accepts. Automaton has 3650 states and 4863 transitions. Word has length 352 [2024-11-24 00:49:18,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:18,149 INFO L471 AbstractCegarLoop]: Abstraction has 3650 states and 4863 transitions. [2024-11-24 00:49:18,150 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 54.666666666666664) internal successors, (328), 6 states have internal predecessors, (328), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:49:18,150 INFO L276 IsEmpty]: Start isEmpty. Operand 3650 states and 4863 transitions. [2024-11-24 00:49:18,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2024-11-24 00:49:18,157 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:18,157 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:18,178 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-24 00:49:18,357 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:18,358 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:18,359 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:18,359 INFO L85 PathProgramCache]: Analyzing trace with hash 1890107134, now seen corresponding path program 1 times [2024-11-24 00:49:18,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:18,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925535103] [2024-11-24 00:49:18,359 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:18,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:22,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:26,778 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 51 proven. 37 refuted. 0 times theorem prover too weak. 62 trivial. 0 not checked. [2024-11-24 00:49:26,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:26,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925535103] [2024-11-24 00:49:26,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925535103] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:26,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [950275233] [2024-11-24 00:49:26,778 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:26,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:26,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:26,781 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:26,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-24 00:49:28,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:28,933 INFO L256 TraceCheckSpWp]: Trace formula consists of 2072 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 00:49:28,939 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:29,043 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2024-11-24 00:49:29,044 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:49:29,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [950275233] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:49:29,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:49:29,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [17] total 21 [2024-11-24 00:49:29,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804844777] [2024-11-24 00:49:29,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:49:29,045 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:49:29,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:29,046 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:49:29,046 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=358, Unknown=0, NotChecked=0, Total=420 [2024-11-24 00:49:29,047 INFO L87 Difference]: Start difference. First operand 3650 states and 4863 transitions. Second operand has 6 states, 5 states have (on average 55.4) internal successors, (277), 6 states have internal predecessors, (277), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:29,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:29,164 INFO L93 Difference]: Finished difference Result 6387 states and 8494 transitions. [2024-11-24 00:49:29,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:49:29,164 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 55.4) internal successors, (277), 6 states have internal predecessors, (277), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 352 [2024-11-24 00:49:29,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:29,175 INFO L225 Difference]: With dead ends: 6387 [2024-11-24 00:49:29,175 INFO L226 Difference]: Without dead ends: 3650 [2024-11-24 00:49:29,178 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 369 GetRequests, 350 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=62, Invalid=358, Unknown=0, NotChecked=0, Total=420 [2024-11-24 00:49:29,179 INFO L435 NwaCegarLoop]: 545 mSDtfsCounter, 0 mSDsluCounter, 2161 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2706 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:29,180 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2706 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:49:29,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3650 states. [2024-11-24 00:49:29,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3650 to 3650. [2024-11-24 00:49:29,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3650 states, 3592 states have (on average 1.318207126948775) internal successors, (4735), 3592 states have internal predecessors, (4735), 56 states have call successors, (56), 1 states have call predecessors, (56), 1 states have return successors, (56), 56 states have call predecessors, (56), 56 states have call successors, (56) [2024-11-24 00:49:29,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3650 states to 3650 states and 4847 transitions. [2024-11-24 00:49:29,278 INFO L78 Accepts]: Start accepts. Automaton has 3650 states and 4847 transitions. Word has length 352 [2024-11-24 00:49:29,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:29,278 INFO L471 AbstractCegarLoop]: Abstraction has 3650 states and 4847 transitions. [2024-11-24 00:49:29,279 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 55.4) internal successors, (277), 6 states have internal predecessors, (277), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:29,279 INFO L276 IsEmpty]: Start isEmpty. Operand 3650 states and 4847 transitions. [2024-11-24 00:49:29,286 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2024-11-24 00:49:29,286 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:29,286 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:29,310 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-24 00:49:29,487 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable45 [2024-11-24 00:49:29,487 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:29,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:29,488 INFO L85 PathProgramCache]: Analyzing trace with hash -1316213394, now seen corresponding path program 1 times [2024-11-24 00:49:29,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:29,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492991889] [2024-11-24 00:49:29,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:29,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:30,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:32,365 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:32,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:32,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [492991889] [2024-11-24 00:49:32,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [492991889] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:49:32,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:49:32,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 00:49:32,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816828900] [2024-11-24 00:49:32,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:49:32,366 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 00:49:32,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:32,366 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 00:49:32,366 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:49:32,367 INFO L87 Difference]: Start difference. First operand 3650 states and 4847 transitions. Second operand has 9 states, 9 states have (on average 36.333333333333336) internal successors, (327), 9 states have internal predecessors, (327), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:33,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:33,662 INFO L93 Difference]: Finished difference Result 7715 states and 10219 transitions. [2024-11-24 00:49:33,663 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 00:49:33,663 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 36.333333333333336) internal successors, (327), 9 states have internal predecessors, (327), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 354 [2024-11-24 00:49:33,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:33,675 INFO L225 Difference]: With dead ends: 7715 [2024-11-24 00:49:33,676 INFO L226 Difference]: Without dead ends: 6174 [2024-11-24 00:49:33,679 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2024-11-24 00:49:33,680 INFO L435 NwaCegarLoop]: 589 mSDtfsCounter, 1344 mSDsluCounter, 2686 mSDsCounter, 0 mSdLazyCounter, 1488 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1345 SdHoareTripleChecker+Valid, 3275 SdHoareTripleChecker+Invalid, 1494 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 1488 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:33,680 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1345 Valid, 3275 Invalid, 1494 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 1488 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-24 00:49:33,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6174 states. [2024-11-24 00:49:33,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6174 to 5640. [2024-11-24 00:49:33,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5640 states, 5566 states have (on average 1.3045274883219546) internal successors, (7261), 5566 states have internal predecessors, (7261), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 00:49:33,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5640 states to 5640 states and 7405 transitions. [2024-11-24 00:49:33,809 INFO L78 Accepts]: Start accepts. Automaton has 5640 states and 7405 transitions. Word has length 354 [2024-11-24 00:49:33,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:33,809 INFO L471 AbstractCegarLoop]: Abstraction has 5640 states and 7405 transitions. [2024-11-24 00:49:33,810 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 36.333333333333336) internal successors, (327), 9 states have internal predecessors, (327), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:33,810 INFO L276 IsEmpty]: Start isEmpty. Operand 5640 states and 7405 transitions. [2024-11-24 00:49:33,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2024-11-24 00:49:33,818 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:33,819 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:33,819 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46 [2024-11-24 00:49:33,819 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:33,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:33,820 INFO L85 PathProgramCache]: Analyzing trace with hash 1995361007, now seen corresponding path program 1 times [2024-11-24 00:49:33,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:33,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573104977] [2024-11-24 00:49:33,820 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:33,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:36,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:37,679 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 4 proven. 85 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:37,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:37,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573104977] [2024-11-24 00:49:37,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573104977] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:37,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938941364] [2024-11-24 00:49:37,679 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:37,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:37,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:37,681 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:37,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-24 00:49:39,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:39,778 INFO L256 TraceCheckSpWp]: Trace formula consists of 2078 conjuncts, 80 conjuncts are in the unsatisfiable core [2024-11-24 00:49:39,790 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:41,460 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 121 proven. 4 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-11-24 00:49:41,460 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:49:43,684 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 83 proven. 6 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:43,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1938941364] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:49:43,685 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:49:43,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12, 11] total 30 [2024-11-24 00:49:43,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320754938] [2024-11-24 00:49:43,685 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:49:43,686 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2024-11-24 00:49:43,686 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:43,686 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2024-11-24 00:49:43,687 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=757, Unknown=0, NotChecked=0, Total=870 [2024-11-24 00:49:43,687 INFO L87 Difference]: Start difference. First operand 5640 states and 7405 transitions. Second operand has 30 states, 30 states have (on average 29.5) internal successors, (885), 30 states have internal predecessors, (885), 6 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 6 states have call predecessors, (18), 6 states have call successors, (18) [2024-11-24 00:49:46,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:46,435 INFO L93 Difference]: Finished difference Result 11135 states and 14586 transitions. [2024-11-24 00:49:46,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2024-11-24 00:49:46,436 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 30 states have (on average 29.5) internal successors, (885), 30 states have internal predecessors, (885), 6 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 6 states have call predecessors, (18), 6 states have call successors, (18) Word has length 354 [2024-11-24 00:49:46,436 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:46,444 INFO L225 Difference]: With dead ends: 11135 [2024-11-24 00:49:46,444 INFO L226 Difference]: Without dead ends: 5698 [2024-11-24 00:49:46,451 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 733 GetRequests, 689 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=311, Invalid=1759, Unknown=0, NotChecked=0, Total=2070 [2024-11-24 00:49:46,452 INFO L435 NwaCegarLoop]: 489 mSDtfsCounter, 2366 mSDsluCounter, 7810 mSDsCounter, 0 mSdLazyCounter, 3942 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2366 SdHoareTripleChecker+Valid, 8299 SdHoareTripleChecker+Invalid, 3962 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 3942 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:46,452 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2366 Valid, 8299 Invalid, 3962 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 3942 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2024-11-24 00:49:46,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5698 states. [2024-11-24 00:49:46,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5698 to 5660. [2024-11-24 00:49:46,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5660 states, 5586 states have (on average 1.304153240243466) internal successors, (7285), 5586 states have internal predecessors, (7285), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 00:49:46,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5660 states to 5660 states and 7429 transitions. [2024-11-24 00:49:46,583 INFO L78 Accepts]: Start accepts. Automaton has 5660 states and 7429 transitions. Word has length 354 [2024-11-24 00:49:46,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:46,584 INFO L471 AbstractCegarLoop]: Abstraction has 5660 states and 7429 transitions. [2024-11-24 00:49:46,584 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 30 states have (on average 29.5) internal successors, (885), 30 states have internal predecessors, (885), 6 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 6 states have call predecessors, (18), 6 states have call successors, (18) [2024-11-24 00:49:46,584 INFO L276 IsEmpty]: Start isEmpty. Operand 5660 states and 7429 transitions. [2024-11-24 00:49:46,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2024-11-24 00:49:46,592 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:46,593 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:46,613 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-24 00:49:46,793 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable47 [2024-11-24 00:49:46,794 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:46,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:46,794 INFO L85 PathProgramCache]: Analyzing trace with hash 381686227, now seen corresponding path program 1 times [2024-11-24 00:49:46,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:46,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824984013] [2024-11-24 00:49:46,795 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:46,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:48,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:50,286 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 2 proven. 84 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:49:50,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:50,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824984013] [2024-11-24 00:49:50,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824984013] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:50,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [214176982] [2024-11-24 00:49:50,287 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:50,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:50,287 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:50,289 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:50,290 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-24 00:49:52,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:52,731 INFO L256 TraceCheckSpWp]: Trace formula consists of 2076 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 00:49:52,737 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:52,822 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 121 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2024-11-24 00:49:52,823 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:49:52,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [214176982] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:49:52,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:49:52,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [13] total 17 [2024-11-24 00:49:52,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710606667] [2024-11-24 00:49:52,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:49:52,824 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:49:52,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:49:52,825 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:49:52,825 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2024-11-24 00:49:52,826 INFO L87 Difference]: Start difference. First operand 5660 states and 7429 transitions. Second operand has 6 states, 5 states have (on average 65.8) internal successors, (329), 6 states have internal predecessors, (329), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:53,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:49:53,008 INFO L93 Difference]: Finished difference Result 11085 states and 14530 transitions. [2024-11-24 00:49:53,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:49:53,009 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 65.8) internal successors, (329), 6 states have internal predecessors, (329), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 354 [2024-11-24 00:49:53,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:49:53,020 INFO L225 Difference]: With dead ends: 11085 [2024-11-24 00:49:53,020 INFO L226 Difference]: Without dead ends: 5660 [2024-11-24 00:49:53,025 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 369 GetRequests, 352 SyntacticMatches, 2 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2024-11-24 00:49:53,026 INFO L435 NwaCegarLoop]: 544 mSDtfsCounter, 0 mSDsluCounter, 2157 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2701 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:49:53,026 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2701 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:49:53,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5660 states. [2024-11-24 00:49:53,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5660 to 5660. [2024-11-24 00:49:53,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5660 states, 5586 states have (on average 1.3027210884353742) internal successors, (7277), 5586 states have internal predecessors, (7277), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 00:49:53,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5660 states to 5660 states and 7421 transitions. [2024-11-24 00:49:53,155 INFO L78 Accepts]: Start accepts. Automaton has 5660 states and 7421 transitions. Word has length 354 [2024-11-24 00:49:53,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:49:53,155 INFO L471 AbstractCegarLoop]: Abstraction has 5660 states and 7421 transitions. [2024-11-24 00:49:53,156 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 65.8) internal successors, (329), 6 states have internal predecessors, (329), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:49:53,156 INFO L276 IsEmpty]: Start isEmpty. Operand 5660 states and 7421 transitions. [2024-11-24 00:49:53,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 356 [2024-11-24 00:49:53,166 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:49:53,167 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:49:53,189 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-24 00:49:53,367 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable48 [2024-11-24 00:49:53,368 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:49:53,368 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:49:53,369 INFO L85 PathProgramCache]: Analyzing trace with hash 591247886, now seen corresponding path program 1 times [2024-11-24 00:49:53,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:49:53,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652098405] [2024-11-24 00:49:53,369 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:53,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:49:54,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:55,629 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 80 proven. 4 refuted. 0 times theorem prover too weak. 63 trivial. 0 not checked. [2024-11-24 00:49:55,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:49:55,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652098405] [2024-11-24 00:49:55,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652098405] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:49:55,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [154008721] [2024-11-24 00:49:55,629 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:49:55,630 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:49:55,630 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:49:55,632 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:49:55,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-24 00:49:58,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:49:58,339 INFO L256 TraceCheckSpWp]: Trace formula consists of 2079 conjuncts, 41 conjuncts are in the unsatisfiable core [2024-11-24 00:49:58,348 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:49:59,207 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 116 proven. 4 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2024-11-24 00:49:59,207 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:50:00,728 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 83 proven. 4 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:50:00,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [154008721] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:50:00,728 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:50:00,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 11, 13] total 25 [2024-11-24 00:50:00,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147723076] [2024-11-24 00:50:00,728 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:50:00,729 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2024-11-24 00:50:00,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:50:00,730 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-24 00:50:00,730 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=478, Unknown=0, NotChecked=0, Total=600 [2024-11-24 00:50:00,731 INFO L87 Difference]: Start difference. First operand 5660 states and 7421 transitions. Second operand has 25 states, 25 states have (on average 23.36) internal successors, (584), 25 states have internal predecessors, (584), 3 states have call successors, (12), 2 states have call predecessors, (12), 2 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) [2024-11-24 00:50:01,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:50:01,919 INFO L93 Difference]: Finished difference Result 11089 states and 14522 transitions. [2024-11-24 00:50:01,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 00:50:01,920 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 23.36) internal successors, (584), 25 states have internal predecessors, (584), 3 states have call successors, (12), 2 states have call predecessors, (12), 2 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) Word has length 355 [2024-11-24 00:50:01,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:50:01,925 INFO L225 Difference]: With dead ends: 11089 [2024-11-24 00:50:01,925 INFO L226 Difference]: Without dead ends: 5668 [2024-11-24 00:50:01,929 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 720 GetRequests, 693 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 213 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=182, Invalid=630, Unknown=0, NotChecked=0, Total=812 [2024-11-24 00:50:01,930 INFO L435 NwaCegarLoop]: 384 mSDtfsCounter, 917 mSDsluCounter, 3434 mSDsCounter, 0 mSdLazyCounter, 1634 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 917 SdHoareTripleChecker+Valid, 3818 SdHoareTripleChecker+Invalid, 1635 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1634 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:50:01,930 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [917 Valid, 3818 Invalid, 1635 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1634 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-24 00:50:01,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5668 states. [2024-11-24 00:50:02,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5668 to 5636. [2024-11-24 00:50:02,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5636 states, 5562 states have (on average 1.302588996763754) internal successors, (7245), 5562 states have internal predecessors, (7245), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 00:50:02,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5636 states to 5636 states and 7389 transitions. [2024-11-24 00:50:02,052 INFO L78 Accepts]: Start accepts. Automaton has 5636 states and 7389 transitions. Word has length 355 [2024-11-24 00:50:02,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:50:02,053 INFO L471 AbstractCegarLoop]: Abstraction has 5636 states and 7389 transitions. [2024-11-24 00:50:02,053 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 23.36) internal successors, (584), 25 states have internal predecessors, (584), 3 states have call successors, (12), 2 states have call predecessors, (12), 2 states have return successors, (12), 3 states have call predecessors, (12), 3 states have call successors, (12) [2024-11-24 00:50:02,053 INFO L276 IsEmpty]: Start isEmpty. Operand 5636 states and 7389 transitions. [2024-11-24 00:50:02,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 356 [2024-11-24 00:50:02,061 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:50:02,062 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:50:02,085 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2024-11-24 00:50:02,262 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2024-11-24 00:50:02,262 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:50:02,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:50:02,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1535399658, now seen corresponding path program 1 times [2024-11-24 00:50:02,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:50:02,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391829665] [2024-11-24 00:50:02,263 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:50:02,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:50:04,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:50:08,603 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 50 proven. 38 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:50:08,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:50:08,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391829665] [2024-11-24 00:50:08,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391829665] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:50:08,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [918499663] [2024-11-24 00:50:08,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:50:08,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:50:08,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:50:08,606 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:50:08,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-24 00:50:11,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:50:11,218 INFO L256 TraceCheckSpWp]: Trace formula consists of 2079 conjuncts, 154 conjuncts are in the unsatisfiable core [2024-11-24 00:50:11,233 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:50:15,636 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 50 proven. 38 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:50:15,636 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:50:26,276 INFO L134 CoverageAnalysis]: Checked inductivity of 148 backedges. 4 proven. 84 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:50:26,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [918499663] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:50:26,276 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:50:26,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 26, 28] total 68 [2024-11-24 00:50:26,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633030648] [2024-11-24 00:50:26,277 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:50:26,277 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 68 states [2024-11-24 00:50:26,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:50:26,279 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2024-11-24 00:50:26,280 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=564, Invalid=3992, Unknown=0, NotChecked=0, Total=4556 [2024-11-24 00:50:26,280 INFO L87 Difference]: Start difference. First operand 5636 states and 7389 transitions. Second operand has 68 states, 68 states have (on average 13.441176470588236) internal successors, (914), 68 states have internal predecessors, (914), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 00:51:11,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:51:11,158 INFO L93 Difference]: Finished difference Result 42287 states and 55689 transitions. [2024-11-24 00:51:11,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 305 states. [2024-11-24 00:51:11,159 INFO L78 Accepts]: Start accepts. Automaton has has 68 states, 68 states have (on average 13.441176470588236) internal successors, (914), 68 states have internal predecessors, (914), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) Word has length 355 [2024-11-24 00:51:11,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:51:11,188 INFO L225 Difference]: With dead ends: 42287 [2024-11-24 00:51:11,188 INFO L226 Difference]: Without dead ends: 38842 [2024-11-24 00:51:11,211 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1020 GetRequests, 660 SyntacticMatches, 0 SemanticMatches, 360 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49105 ImplicationChecksByTransitivity, 23.1s TimeCoverageRelationStatistics Valid=13287, Invalid=117395, Unknown=0, NotChecked=0, Total=130682 [2024-11-24 00:51:11,211 INFO L435 NwaCegarLoop]: 933 mSDtfsCounter, 23483 mSDsluCounter, 41304 mSDsCounter, 0 mSdLazyCounter, 27667 mSolverCounterSat, 167 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 18.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23488 SdHoareTripleChecker+Valid, 42237 SdHoareTripleChecker+Invalid, 27834 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.2s SdHoareTripleChecker+Time, 167 IncrementalHoareTripleChecker+Valid, 27667 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 21.2s IncrementalHoareTripleChecker+Time [2024-11-24 00:51:11,212 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [23488 Valid, 42237 Invalid, 27834 Unknown, 0 Unchecked, 0.2s Time], IncrementalHoareTripleChecker [167 Valid, 27667 Invalid, 0 Unknown, 0 Unchecked, 21.2s Time] [2024-11-24 00:51:11,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38842 states. [2024-11-24 00:51:11,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38842 to 18786. [2024-11-24 00:51:11,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18786 states, 18518 states have (on average 1.3000864024192678) internal successors, (24075), 18518 states have internal predecessors, (24075), 266 states have call successors, (266), 1 states have call predecessors, (266), 1 states have return successors, (266), 266 states have call predecessors, (266), 266 states have call successors, (266) [2024-11-24 00:51:11,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18786 states to 18786 states and 24607 transitions. [2024-11-24 00:51:11,818 INFO L78 Accepts]: Start accepts. Automaton has 18786 states and 24607 transitions. Word has length 355 [2024-11-24 00:51:11,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:51:11,819 INFO L471 AbstractCegarLoop]: Abstraction has 18786 states and 24607 transitions. [2024-11-24 00:51:11,819 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 68 states, 68 states have (on average 13.441176470588236) internal successors, (914), 68 states have internal predecessors, (914), 11 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 11 states have call predecessors, (18), 11 states have call successors, (18) [2024-11-24 00:51:11,819 INFO L276 IsEmpty]: Start isEmpty. Operand 18786 states and 24607 transitions. [2024-11-24 00:51:11,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 357 [2024-11-24 00:51:11,838 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:51:11,838 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:51:11,853 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-24 00:51:12,042 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:51:12,042 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:51:12,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:51:12,043 INFO L85 PathProgramCache]: Analyzing trace with hash 2041114541, now seen corresponding path program 1 times [2024-11-24 00:51:12,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:51:12,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445821282] [2024-11-24 00:51:12,043 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:12,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:51:14,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:16,889 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:51:16,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:51:16,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445821282] [2024-11-24 00:51:16,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445821282] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:51:16,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1808529959] [2024-11-24 00:51:16,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:16,890 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:51:16,890 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:51:16,892 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:51:16,894 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-24 00:51:20,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:20,475 INFO L256 TraceCheckSpWp]: Trace formula consists of 2082 conjuncts, 126 conjuncts are in the unsatisfiable core [2024-11-24 00:51:20,486 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:51:22,584 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 14 proven. 91 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 00:51:22,584 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:51:27,840 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 14 proven. 91 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 00:51:27,840 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1808529959] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:51:27,840 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:51:27,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 26, 23] total 51 [2024-11-24 00:51:27,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1214117482] [2024-11-24 00:51:27,840 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:51:27,841 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 51 states [2024-11-24 00:51:27,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:51:27,843 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2024-11-24 00:51:27,843 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=2306, Unknown=0, NotChecked=0, Total=2550 [2024-11-24 00:51:27,844 INFO L87 Difference]: Start difference. First operand 18786 states and 24607 transitions. Second operand has 51 states, 48 states have (on average 17.479166666666668) internal successors, (839), 51 states have internal predecessors, (839), 9 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 6 states have call predecessors, (16), 9 states have call successors, (16) [2024-11-24 00:51:34,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:51:34,779 INFO L93 Difference]: Finished difference Result 47779 states and 63048 transitions. [2024-11-24 00:51:34,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2024-11-24 00:51:34,779 INFO L78 Accepts]: Start accepts. Automaton has has 51 states, 48 states have (on average 17.479166666666668) internal successors, (839), 51 states have internal predecessors, (839), 9 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 6 states have call predecessors, (16), 9 states have call successors, (16) Word has length 356 [2024-11-24 00:51:34,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:51:34,817 INFO L225 Difference]: With dead ends: 47779 [2024-11-24 00:51:34,817 INFO L226 Difference]: Without dead ends: 35145 [2024-11-24 00:51:34,833 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 772 GetRequests, 675 SyntacticMatches, 2 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2288 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=950, Invalid=8362, Unknown=0, NotChecked=0, Total=9312 [2024-11-24 00:51:34,833 INFO L435 NwaCegarLoop]: 562 mSDtfsCounter, 3247 mSDsluCounter, 14460 mSDsCounter, 0 mSdLazyCounter, 7604 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3250 SdHoareTripleChecker+Valid, 15022 SdHoareTripleChecker+Invalid, 7615 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 7604 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.9s IncrementalHoareTripleChecker+Time [2024-11-24 00:51:34,834 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3250 Valid, 15022 Invalid, 7615 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [11 Valid, 7604 Invalid, 0 Unknown, 0 Unchecked, 4.9s Time] [2024-11-24 00:51:34,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35145 states. [2024-11-24 00:51:35,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35145 to 19178. [2024-11-24 00:51:35,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19178 states, 18910 states have (on average 1.29555790586991) internal successors, (24499), 18910 states have internal predecessors, (24499), 266 states have call successors, (266), 1 states have call predecessors, (266), 1 states have return successors, (266), 266 states have call predecessors, (266), 266 states have call successors, (266) [2024-11-24 00:51:35,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19178 states to 19178 states and 25031 transitions. [2024-11-24 00:51:35,289 INFO L78 Accepts]: Start accepts. Automaton has 19178 states and 25031 transitions. Word has length 356 [2024-11-24 00:51:35,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:51:35,290 INFO L471 AbstractCegarLoop]: Abstraction has 19178 states and 25031 transitions. [2024-11-24 00:51:35,290 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 51 states, 48 states have (on average 17.479166666666668) internal successors, (839), 51 states have internal predecessors, (839), 9 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 6 states have call predecessors, (16), 9 states have call successors, (16) [2024-11-24 00:51:35,290 INFO L276 IsEmpty]: Start isEmpty. Operand 19178 states and 25031 transitions. [2024-11-24 00:51:35,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 357 [2024-11-24 00:51:35,314 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:51:35,314 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:51:35,339 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-24 00:51:35,515 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51,15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:51:35,515 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:51:35,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:51:35,516 INFO L85 PathProgramCache]: Analyzing trace with hash -152670903, now seen corresponding path program 1 times [2024-11-24 00:51:35,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:51:35,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1573046884] [2024-11-24 00:51:35,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:35,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:51:35,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:36,210 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 53 proven. 0 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-11-24 00:51:36,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:51:36,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1573046884] [2024-11-24 00:51:36,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1573046884] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:51:36,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:51:36,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:51:36,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [665268233] [2024-11-24 00:51:36,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:51:36,211 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:51:36,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:51:36,212 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:51:36,212 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:51:36,212 INFO L87 Difference]: Start difference. First operand 19178 states and 25031 transitions. Second operand has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:51:36,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:51:36,620 INFO L93 Difference]: Finished difference Result 34749 states and 45360 transitions. [2024-11-24 00:51:36,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:51:36,621 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 356 [2024-11-24 00:51:36,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:51:36,641 INFO L225 Difference]: With dead ends: 34749 [2024-11-24 00:51:36,641 INFO L226 Difference]: Without dead ends: 19112 [2024-11-24 00:51:36,651 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:51:36,652 INFO L435 NwaCegarLoop]: 543 mSDtfsCounter, 0 mSDsluCounter, 1076 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1619 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:51:36,652 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1619 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:51:36,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19112 states. [2024-11-24 00:51:37,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19112 to 19112. [2024-11-24 00:51:37,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19112 states, 18844 states have (on average 1.2912863510931862) internal successors, (24333), 18844 states have internal predecessors, (24333), 266 states have call successors, (266), 1 states have call predecessors, (266), 1 states have return successors, (266), 266 states have call predecessors, (266), 266 states have call successors, (266) [2024-11-24 00:51:37,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19112 states to 19112 states and 24865 transitions. [2024-11-24 00:51:37,048 INFO L78 Accepts]: Start accepts. Automaton has 19112 states and 24865 transitions. Word has length 356 [2024-11-24 00:51:37,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:51:37,049 INFO L471 AbstractCegarLoop]: Abstraction has 19112 states and 24865 transitions. [2024-11-24 00:51:37,049 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 60.0) internal successors, (300), 5 states have internal predecessors, (300), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:51:37,049 INFO L276 IsEmpty]: Start isEmpty. Operand 19112 states and 24865 transitions. [2024-11-24 00:51:37,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 358 [2024-11-24 00:51:37,071 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:51:37,071 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:51:37,071 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-11-24 00:51:37,071 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:51:37,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:51:37,072 INFO L85 PathProgramCache]: Analyzing trace with hash 1171553710, now seen corresponding path program 1 times [2024-11-24 00:51:37,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:51:37,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353284502] [2024-11-24 00:51:37,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:37,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:51:37,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:38,229 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 89 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:51:38,229 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:51:38,229 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353284502] [2024-11-24 00:51:38,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353284502] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:51:38,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:51:38,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:51:38,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070538046] [2024-11-24 00:51:38,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:51:38,229 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:51:38,230 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:51:38,230 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:51:38,230 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:51:38,230 INFO L87 Difference]: Start difference. First operand 19112 states and 24865 transitions. Second operand has 6 states, 6 states have (on average 55.0) internal successors, (330), 6 states have internal predecessors, (330), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:51:38,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:51:38,611 INFO L93 Difference]: Finished difference Result 35103 states and 45685 transitions. [2024-11-24 00:51:38,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:51:38,612 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 55.0) internal successors, (330), 6 states have internal predecessors, (330), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 357 [2024-11-24 00:51:38,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:51:38,643 INFO L225 Difference]: With dead ends: 35103 [2024-11-24 00:51:38,644 INFO L226 Difference]: Without dead ends: 26157 [2024-11-24 00:51:38,655 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 00:51:38,655 INFO L435 NwaCegarLoop]: 928 mSDtfsCounter, 372 mSDsluCounter, 3313 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 372 SdHoareTripleChecker+Valid, 4241 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:51:38,655 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [372 Valid, 4241 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:51:38,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26157 states. [2024-11-24 00:51:39,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26157 to 21172. [2024-11-24 00:51:39,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21172 states, 20796 states have (on average 1.2896230044239276) internal successors, (26819), 20796 states have internal predecessors, (26819), 374 states have call successors, (374), 1 states have call predecessors, (374), 1 states have return successors, (374), 374 states have call predecessors, (374), 374 states have call successors, (374) [2024-11-24 00:51:39,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21172 states to 21172 states and 27567 transitions. [2024-11-24 00:51:39,079 INFO L78 Accepts]: Start accepts. Automaton has 21172 states and 27567 transitions. Word has length 357 [2024-11-24 00:51:39,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:51:39,080 INFO L471 AbstractCegarLoop]: Abstraction has 21172 states and 27567 transitions. [2024-11-24 00:51:39,080 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 55.0) internal successors, (330), 6 states have internal predecessors, (330), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 00:51:39,080 INFO L276 IsEmpty]: Start isEmpty. Operand 21172 states and 27567 transitions. [2024-11-24 00:51:39,106 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 358 [2024-11-24 00:51:39,106 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:51:39,106 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:51:39,106 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-11-24 00:51:39,107 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:51:39,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:51:39,107 INFO L85 PathProgramCache]: Analyzing trace with hash -1148173526, now seen corresponding path program 1 times [2024-11-24 00:51:39,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:51:39,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74953463] [2024-11-24 00:51:39,108 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:39,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:51:41,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:43,325 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:51:43,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:51:43,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [74953463] [2024-11-24 00:51:43,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [74953463] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:51:43,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2032207838] [2024-11-24 00:51:43,326 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:43,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:51:43,326 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:51:43,328 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:51:43,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-24 00:51:46,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:51:46,201 INFO L256 TraceCheckSpWp]: Trace formula consists of 2083 conjuncts, 62 conjuncts are in the unsatisfiable core [2024-11-24 00:51:46,210 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:51:48,127 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:51:48,127 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:51:51,844 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 2 proven. 88 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:51:51,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2032207838] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:51:51,844 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:51:51,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 15, 16] total 34 [2024-11-24 00:51:51,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975012149] [2024-11-24 00:51:51,845 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:51:51,845 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 34 states [2024-11-24 00:51:51,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:51:51,847 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2024-11-24 00:51:51,847 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=128, Invalid=994, Unknown=0, NotChecked=0, Total=1122 [2024-11-24 00:51:51,847 INFO L87 Difference]: Start difference. First operand 21172 states and 27567 transitions. Second operand has 34 states, 34 states have (on average 21.235294117647058) internal successors, (722), 34 states have internal predecessors, (722), 5 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 5 states have call predecessors, (12), 5 states have call successors, (12) [2024-11-24 00:51:55,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:51:55,474 INFO L93 Difference]: Finished difference Result 35015 states and 45566 transitions. [2024-11-24 00:51:55,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2024-11-24 00:51:55,474 INFO L78 Accepts]: Start accepts. Automaton has has 34 states, 34 states have (on average 21.235294117647058) internal successors, (722), 34 states have internal predecessors, (722), 5 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 5 states have call predecessors, (12), 5 states have call successors, (12) Word has length 357 [2024-11-24 00:51:55,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:51:55,495 INFO L225 Difference]: With dead ends: 35015 [2024-11-24 00:51:55,495 INFO L226 Difference]: Without dead ends: 22308 [2024-11-24 00:51:55,506 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 743 GetRequests, 692 SyntacticMatches, 1 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 544 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=351, Invalid=2301, Unknown=0, NotChecked=0, Total=2652 [2024-11-24 00:51:55,507 INFO L435 NwaCegarLoop]: 489 mSDtfsCounter, 873 mSDsluCounter, 9038 mSDsCounter, 0 mSdLazyCounter, 4345 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 873 SdHoareTripleChecker+Valid, 9527 SdHoareTripleChecker+Invalid, 4351 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 4345 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.8s IncrementalHoareTripleChecker+Time [2024-11-24 00:51:55,507 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [873 Valid, 9527 Invalid, 4351 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 4345 Invalid, 0 Unknown, 0 Unchecked, 2.8s Time] [2024-11-24 00:51:55,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22308 states. [2024-11-24 00:51:56,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22308 to 21124. [2024-11-24 00:51:56,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21124 states, 20748 states have (on average 1.2879795642953538) internal successors, (26723), 20748 states have internal predecessors, (26723), 374 states have call successors, (374), 1 states have call predecessors, (374), 1 states have return successors, (374), 374 states have call predecessors, (374), 374 states have call successors, (374) [2024-11-24 00:51:56,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21124 states to 21124 states and 27471 transitions. [2024-11-24 00:51:56,107 INFO L78 Accepts]: Start accepts. Automaton has 21124 states and 27471 transitions. Word has length 357 [2024-11-24 00:51:56,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:51:56,107 INFO L471 AbstractCegarLoop]: Abstraction has 21124 states and 27471 transitions. [2024-11-24 00:51:56,108 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 34 states, 34 states have (on average 21.235294117647058) internal successors, (722), 34 states have internal predecessors, (722), 5 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 5 states have call predecessors, (12), 5 states have call successors, (12) [2024-11-24 00:51:56,108 INFO L276 IsEmpty]: Start isEmpty. Operand 21124 states and 27471 transitions. [2024-11-24 00:51:56,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 358 [2024-11-24 00:51:56,125 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:51:56,126 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:51:56,142 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-11-24 00:51:56,326 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:51:56,326 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:51:56,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:51:56,327 INFO L85 PathProgramCache]: Analyzing trace with hash 414587049, now seen corresponding path program 1 times [2024-11-24 00:51:56,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:51:56,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056912954] [2024-11-24 00:51:56,327 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:51:56,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:51:59,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 00:51:59,755 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-24 00:52:03,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 00:52:04,189 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-24 00:52:04,193 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-24 00:52:04,194 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-24 00:52:04,202 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-11-24 00:52:04,211 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:52:04,632 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-24 00:52:04,639 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.11 12:52:04 BoogieIcfgContainer [2024-11-24 00:52:04,641 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-24 00:52:04,643 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-24 00:52:04,647 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-24 00:52:04,647 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-24 00:52:04,648 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:47:26" (3/4) ... [2024-11-24 00:52:04,652 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-11-24 00:52:04,657 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-24 00:52:04,658 INFO L158 Benchmark]: Toolchain (without parser) took 281832.38ms. Allocated memory was 142.6MB in the beginning and 2.3GB in the end (delta: 2.2GB). Free memory was 118.3MB in the beginning and 1.8GB in the end (delta: -1.6GB). Peak memory consumption was 535.3MB. Max. memory is 16.1GB. [2024-11-24 00:52:04,662 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 79.8MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 00:52:04,662 INFO L158 Benchmark]: CACSL2BoogieTranslator took 693.21ms. Allocated memory is still 142.6MB. Free memory was 118.3MB in the beginning and 88.4MB in the end (delta: 29.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-24 00:52:04,662 INFO L158 Benchmark]: Boogie Procedure Inliner took 273.58ms. Allocated memory is still 142.6MB. Free memory was 88.1MB in the beginning and 97.0MB in the end (delta: -8.9MB). Peak memory consumption was 51.3MB. Max. memory is 16.1GB. [2024-11-24 00:52:04,663 INFO L158 Benchmark]: Boogie Preprocessor took 373.44ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 97.0MB in the beginning and 377.5MB in the end (delta: -280.5MB). Peak memory consumption was 24.4MB. Max. memory is 16.1GB. [2024-11-24 00:52:04,663 INFO L158 Benchmark]: RCFGBuilder took 2728.94ms. Allocated memory is still 427.8MB. Free memory was 377.3MB in the beginning and 320.6MB in the end (delta: 56.6MB). Peak memory consumption was 139.7MB. Max. memory is 16.1GB. [2024-11-24 00:52:04,663 INFO L158 Benchmark]: TraceAbstraction took 277739.03ms. Allocated memory was 427.8MB in the beginning and 2.3GB in the end (delta: 1.9GB). Free memory was 320.6MB in the beginning and 1.8GB in the end (delta: -1.4GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. [2024-11-24 00:52:04,663 INFO L158 Benchmark]: Witness Printer took 13.73ms. Allocated memory is still 2.3GB. Free memory was 1.8GB in the beginning and 1.8GB in the end (delta: 164.7kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 00:52:04,664 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 79.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 693.21ms. Allocated memory is still 142.6MB. Free memory was 118.3MB in the beginning and 88.4MB in the end (delta: 29.9MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 273.58ms. Allocated memory is still 142.6MB. Free memory was 88.1MB in the beginning and 97.0MB in the end (delta: -8.9MB). Peak memory consumption was 51.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 373.44ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 97.0MB in the beginning and 377.5MB in the end (delta: -280.5MB). Peak memory consumption was 24.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2728.94ms. Allocated memory is still 427.8MB. Free memory was 377.3MB in the beginning and 320.6MB in the end (delta: 56.6MB). Peak memory consumption was 139.7MB. Max. memory is 16.1GB. * TraceAbstraction took 277739.03ms. Allocated memory was 427.8MB in the beginning and 2.3GB in the end (delta: 1.9GB). Free memory was 320.6MB in the beginning and 1.8GB in the end (delta: -1.4GB). Peak memory consumption was 1.1GB. Max. memory is 16.1GB. * Witness Printer took 13.73ms. Allocated memory is still 2.3GB. Free memory was 1.8GB in the beginning and 1.8GB in the end (delta: 164.7kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 145, overapproximation of bitwiseOr at line 126, overapproximation of bitwiseOr at line 290, overapproximation of bitwiseAnd at line 515, overapproximation of bitwiseAnd at line 234, overapproximation of bitwiseAnd at line 202, overapproximation of bitwiseAnd at line 146, overapproximation of bitwiseAnd at line 365, overapproximation of bitwiseAnd at line 110, overapproximation of bitwiseAnd at line 403, overapproximation of bitwiseAnd at line 299, overapproximation of bitwiseAnd at line 106, overapproximation of bitwiseAnd at line 210, overapproximation of bitwiseAnd at line 222, overapproximation of bitwiseAnd at line 228, overapproximation of bitwiseAnd at line 441, overapproximation of bitwiseAnd at line 384. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 5); [L33] const SORT_11 msb_SORT_11 = (SORT_11)1 << (5 - 1); [L35] const SORT_13 mask_SORT_13 = (SORT_13)-1 >> (sizeof(SORT_13) * 8 - 4); [L36] const SORT_13 msb_SORT_13 = (SORT_13)1 << (4 - 1); [L38] const SORT_19 mask_SORT_19 = (SORT_19)-1 >> (sizeof(SORT_19) * 8 - 3); [L39] const SORT_19 msb_SORT_19 = (SORT_19)1 << (3 - 1); [L41] const SORT_40 mask_SORT_40 = (SORT_40)-1 >> (sizeof(SORT_40) * 8 - 2); [L42] const SORT_40 msb_SORT_40 = (SORT_40)1 << (2 - 1); [L44] const SORT_13 var_15 = 8; [L45] const SORT_19 var_20 = 7; [L46] const SORT_19 var_25 = 6; [L47] const SORT_19 var_30 = 5; [L48] const SORT_19 var_35 = 4; [L49] const SORT_40 var_41 = 3; [L50] const SORT_40 var_46 = 2; [L51] const SORT_1 var_51 = 1; [L52] const SORT_13 var_64 = 9; [L53] const SORT_11 var_81 = 0; [L54] const SORT_1 var_111 = 0; [L55] const SORT_3 var_268 = 0; [L57] SORT_1 input_2; [L58] SORT_3 input_4; [L59] SORT_1 input_5; [L60] SORT_1 input_6; [L61] SORT_1 input_7; [L62] SORT_1 input_8; [L63] SORT_3 input_9; [L64] SORT_1 input_109; [L66] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L66] SORT_3 state_10 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L67] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L67] SORT_11 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L68] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L68] SORT_3 state_18 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L69] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L69] SORT_3 state_24 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L70] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L70] SORT_3 state_29 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L71] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L71] SORT_3 state_34 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L72] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L72] SORT_3 state_39 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L73] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L73] SORT_3 state_45 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L74] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L74] SORT_3 state_50 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L75] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L75] SORT_3 state_55 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L76] SORT_11 state_60 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L77] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L77] SORT_1 state_68 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L78] SORT_1 state_69 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L79] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L79] SORT_11 state_72 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L80] EXPR __VERIFIER_nondet_ushort() & mask_SORT_3 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L80] SORT_3 state_87 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L81] SORT_1 state_91 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L82] SORT_11 state_136 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L84] SORT_1 init_92_arg_1 = var_51; [L85] state_91 = init_92_arg_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L88] input_2 = __VERIFIER_nondet_uchar() [L89] input_4 = __VERIFIER_nondet_ushort() [L90] input_5 = __VERIFIER_nondet_uchar() [L91] input_6 = __VERIFIER_nondet_uchar() [L92] input_7 = __VERIFIER_nondet_uchar() [L93] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L93] input_7 = input_7 & mask_SORT_1 [L94] input_8 = __VERIFIER_nondet_uchar() [L95] input_9 = __VERIFIER_nondet_ushort() [L96] input_109 = __VERIFIER_nondet_uchar() [L98] SORT_1 var_93_arg_0 = input_7; [L99] SORT_1 var_93_arg_1 = state_91; [L100] SORT_1 var_93 = var_93_arg_0 == var_93_arg_1; [L101] SORT_1 var_94_arg_0 = var_51; [L102] SORT_1 var_94 = ~var_94_arg_0; [L103] SORT_1 var_95_arg_0 = var_93; [L104] SORT_1 var_95_arg_1 = var_94; VAL [input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_95_arg_0=0, var_95_arg_1=-2] [L105] EXPR var_95_arg_0 | var_95_arg_1 VAL [input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L105] SORT_1 var_95 = var_95_arg_0 | var_95_arg_1; [L106] EXPR var_95 & mask_SORT_1 VAL [input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L106] var_95 = var_95 & mask_SORT_1 [L107] SORT_1 constr_96_arg_0 = var_95; VAL [constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L108] CALL assume_abort_if_not(constr_96_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L108] RET assume_abort_if_not(constr_96_arg_0) VAL [constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L109] SORT_13 var_65_arg_0 = var_64; VAL [constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_65_arg_0=9, var_81=0] [L110] EXPR var_65_arg_0 & mask_SORT_13 VAL [constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L110] var_65_arg_0 = var_65_arg_0 & mask_SORT_13 [L111] SORT_11 var_65 = var_65_arg_0; [L112] SORT_11 var_66_arg_0 = state_60; [L113] SORT_11 var_66_arg_1 = var_65; [L114] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L115] SORT_1 var_97_arg_0 = var_66; [L116] SORT_1 var_97 = ~var_97_arg_0; [L117] SORT_1 var_98_arg_0 = input_6; [L118] SORT_1 var_98 = ~var_98_arg_0; [L119] SORT_1 var_99_arg_0 = var_97; [L120] SORT_1 var_99_arg_1 = var_98; VAL [constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_99_arg_0=-1, var_99_arg_1=-1] [L121] EXPR var_99_arg_0 | var_99_arg_1 VAL [constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L121] SORT_1 var_99 = var_99_arg_0 | var_99_arg_1; [L122] SORT_1 var_100_arg_0 = var_51; [L123] SORT_1 var_100 = ~var_100_arg_0; [L124] SORT_1 var_101_arg_0 = var_99; [L125] SORT_1 var_101_arg_1 = var_100; VAL [constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_101_arg_0=255, var_101_arg_1=-2, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L126] EXPR var_101_arg_0 | var_101_arg_1 VAL [constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L126] SORT_1 var_101 = var_101_arg_0 | var_101_arg_1; [L127] EXPR var_101 & mask_SORT_1 VAL [constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L127] var_101 = var_101 & mask_SORT_1 [L128] SORT_1 constr_102_arg_0 = var_101; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L129] CALL assume_abort_if_not(constr_102_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L129] RET assume_abort_if_not(constr_102_arg_0) VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L130] SORT_11 var_61_arg_0 = state_60; [L131] SORT_1 var_61 = var_61_arg_0 != 0; [L132] SORT_1 var_62_arg_0 = var_61; [L133] SORT_1 var_62 = ~var_62_arg_0; [L134] SORT_1 var_103_arg_0 = var_62; [L135] SORT_1 var_103 = ~var_103_arg_0; [L136] SORT_1 var_104_arg_0 = input_5; [L137] SORT_1 var_104 = ~var_104_arg_0; [L138] SORT_1 var_105_arg_0 = var_103; [L139] SORT_1 var_105_arg_1 = var_104; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_105_arg_0=-256, var_105_arg_1=-1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L140] EXPR var_105_arg_0 | var_105_arg_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L140] SORT_1 var_105 = var_105_arg_0 | var_105_arg_1; [L141] SORT_1 var_106_arg_0 = var_51; [L142] SORT_1 var_106 = ~var_106_arg_0; [L143] SORT_1 var_107_arg_0 = var_105; [L144] SORT_1 var_107_arg_1 = var_106; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_107_arg_0=255, var_107_arg_1=-2, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L145] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L145] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L146] EXPR var_107 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L146] var_107 = var_107 & mask_SORT_1 [L147] SORT_1 constr_108_arg_0 = var_107; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L148] CALL assume_abort_if_not(constr_108_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L148] RET assume_abort_if_not(constr_108_arg_0) VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L150] SORT_1 var_112_arg_0 = state_91; [L151] SORT_1 var_112_arg_1 = var_111; [L152] SORT_1 var_112_arg_2 = var_51; [L153] SORT_1 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L154] SORT_1 var_70_arg_0 = state_69; [L155] SORT_1 var_70 = ~var_70_arg_0; [L156] SORT_1 var_71_arg_0 = state_68; [L157] SORT_1 var_71_arg_1 = var_70; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_71_arg_0=0, var_71_arg_1=-1, var_81=0] [L158] EXPR var_71_arg_0 & var_71_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L158] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L159] SORT_11 var_73_arg_0 = state_72; [L160] SORT_1 var_73 = var_73_arg_0 != 0; [L161] SORT_1 var_74_arg_0 = var_71; [L162] SORT_1 var_74_arg_1 = var_73; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74_arg_0=0, var_74_arg_1=0, var_81=0] [L163] EXPR var_74_arg_0 & var_74_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L163] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L164] SORT_1 var_75_arg_0 = state_68; [L165] SORT_1 var_75 = ~var_75_arg_0; [L166] SORT_1 var_76_arg_0 = input_6; [L167] SORT_1 var_76_arg_1 = var_75; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_76_arg_0=0, var_76_arg_1=-1, var_81=0] [L168] EXPR var_76_arg_0 & var_76_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L168] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_76; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_77_arg_0=0, var_81=0] [L170] EXPR var_77_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L170] var_77_arg_0 = var_77_arg_0 & mask_SORT_1 [L171] SORT_11 var_77 = var_77_arg_0; [L172] SORT_11 var_78_arg_0 = state_72; [L173] SORT_11 var_78_arg_1 = var_77; [L174] SORT_11 var_78 = var_78_arg_0 + var_78_arg_1; [L175] SORT_1 var_79_arg_0 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_78=0, var_79_arg_0=0, var_81=0] [L176] EXPR var_79_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_78=0, var_81=0] [L176] var_79_arg_0 = var_79_arg_0 & mask_SORT_1 [L177] SORT_11 var_79 = var_79_arg_0; [L178] SORT_11 var_80_arg_0 = var_78; [L179] SORT_11 var_80_arg_1 = var_79; [L180] SORT_11 var_80 = var_80_arg_0 - var_80_arg_1; [L181] SORT_1 var_82_arg_0 = input_7; [L182] SORT_11 var_82_arg_1 = var_81; [L183] SORT_11 var_82_arg_2 = var_80; [L184] SORT_11 var_82 = var_82_arg_0 ? var_82_arg_1 : var_82_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0, var_82=0] [L185] EXPR var_82 & mask_SORT_11 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L185] var_82 = var_82 & mask_SORT_11 [L186] SORT_11 var_83_arg_0 = var_82; [L187] SORT_1 var_83 = var_83_arg_0 != 0; [L188] SORT_1 var_84_arg_0 = var_83; [L189] SORT_1 var_84 = ~var_84_arg_0; [L190] SORT_1 var_85_arg_0 = var_74; [L191] SORT_1 var_85_arg_1 = var_84; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85_arg_0=0, var_85_arg_1=-1] [L192] EXPR var_85_arg_0 & var_85_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L192] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L193] SORT_1 var_86_arg_0 = var_85; [L194] SORT_1 var_86 = ~var_86_arg_0; [L195] SORT_11 var_14_arg_0 = state_12; [L196] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L197] EXPR var_14 & mask_SORT_13 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L197] var_14 = var_14 & mask_SORT_13 [L198] SORT_13 var_56_arg_0 = var_14; [L199] SORT_1 var_56 = var_56_arg_0 != 0; [L200] SORT_1 var_57_arg_0 = var_56; [L201] SORT_1 var_57 = ~var_57_arg_0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_57=-1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L202] EXPR var_57 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L202] var_57 = var_57 & mask_SORT_1 [L203] SORT_1 var_52_arg_0 = var_51; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_52_arg_0=1, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L204] EXPR var_52_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L204] var_52_arg_0 = var_52_arg_0 & mask_SORT_1 [L205] SORT_13 var_52 = var_52_arg_0; [L206] SORT_13 var_53_arg_0 = var_14; [L207] SORT_13 var_53_arg_1 = var_52; [L208] SORT_1 var_53 = var_53_arg_0 == var_53_arg_1; [L209] SORT_40 var_47_arg_0 = var_46; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_47_arg_0=2, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L210] EXPR var_47_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L210] var_47_arg_0 = var_47_arg_0 & mask_SORT_40 [L211] SORT_13 var_47 = var_47_arg_0; [L212] SORT_13 var_48_arg_0 = var_14; [L213] SORT_13 var_48_arg_1 = var_47; [L214] SORT_1 var_48 = var_48_arg_0 == var_48_arg_1; [L215] SORT_40 var_42_arg_0 = var_41; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_42_arg_0=3, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L216] EXPR var_42_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L216] var_42_arg_0 = var_42_arg_0 & mask_SORT_40 [L217] SORT_13 var_42 = var_42_arg_0; [L218] SORT_13 var_43_arg_0 = var_14; [L219] SORT_13 var_43_arg_1 = var_42; [L220] SORT_1 var_43 = var_43_arg_0 == var_43_arg_1; [L221] SORT_19 var_36_arg_0 = var_35; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_36_arg_0=4, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L222] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L222] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L223] SORT_13 var_36 = var_36_arg_0; [L224] SORT_13 var_37_arg_0 = var_14; [L225] SORT_13 var_37_arg_1 = var_36; [L226] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L227] SORT_19 var_31_arg_0 = var_30; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_31_arg_0=5, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L228] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L228] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L229] SORT_13 var_31 = var_31_arg_0; [L230] SORT_13 var_32_arg_0 = var_14; [L231] SORT_13 var_32_arg_1 = var_31; [L232] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L233] SORT_19 var_26_arg_0 = var_25; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_26_arg_0=6, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L234] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L234] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L235] SORT_13 var_26 = var_26_arg_0; [L236] SORT_13 var_27_arg_0 = var_14; [L237] SORT_13 var_27_arg_1 = var_26; [L238] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L239] SORT_19 var_21_arg_0 = var_20; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_21_arg_0=7, var_25=6, var_268=0, var_27=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L240] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_27=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L240] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L241] SORT_13 var_21 = var_21_arg_0; [L242] SORT_13 var_22_arg_0 = var_14; [L243] SORT_13 var_22_arg_1 = var_21; [L244] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L245] SORT_13 var_16_arg_0 = var_14; [L246] SORT_13 var_16_arg_1 = var_15; [L247] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L248] SORT_1 var_17_arg_0 = var_16; [L249] SORT_3 var_17_arg_1 = state_10; [L250] SORT_3 var_17_arg_2 = input_9; [L251] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L252] SORT_1 var_23_arg_0 = var_22; [L253] SORT_3 var_23_arg_1 = state_18; [L254] SORT_3 var_23_arg_2 = var_17; [L255] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L256] SORT_1 var_28_arg_0 = var_27; [L257] SORT_3 var_28_arg_1 = state_24; [L258] SORT_3 var_28_arg_2 = var_23; [L259] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L260] SORT_1 var_33_arg_0 = var_32; [L261] SORT_3 var_33_arg_1 = state_29; [L262] SORT_3 var_33_arg_2 = var_28; [L263] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L264] SORT_1 var_38_arg_0 = var_37; [L265] SORT_3 var_38_arg_1 = state_34; [L266] SORT_3 var_38_arg_2 = var_33; [L267] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L268] SORT_1 var_44_arg_0 = var_43; [L269] SORT_3 var_44_arg_1 = state_39; [L270] SORT_3 var_44_arg_2 = var_38; [L271] SORT_3 var_44 = var_44_arg_0 ? var_44_arg_1 : var_44_arg_2; [L272] SORT_1 var_49_arg_0 = var_48; [L273] SORT_3 var_49_arg_1 = state_45; [L274] SORT_3 var_49_arg_2 = var_44; [L275] SORT_3 var_49 = var_49_arg_0 ? var_49_arg_1 : var_49_arg_2; [L276] SORT_1 var_54_arg_0 = var_53; [L277] SORT_3 var_54_arg_1 = state_50; [L278] SORT_3 var_54_arg_2 = var_49; [L279] SORT_3 var_54 = var_54_arg_0 ? var_54_arg_1 : var_54_arg_2; [L280] SORT_1 var_58_arg_0 = var_57; [L281] SORT_3 var_58_arg_1 = state_55; [L282] SORT_3 var_58_arg_2 = var_54; [L283] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_58=65535, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L284] EXPR var_58 & mask_SORT_3 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L284] var_58 = var_58 & mask_SORT_3 [L285] SORT_3 var_88_arg_0 = state_87; [L286] SORT_3 var_88_arg_1 = var_58; [L287] SORT_1 var_88 = var_88_arg_0 == var_88_arg_1; [L288] SORT_1 var_89_arg_0 = var_86; [L289] SORT_1 var_89_arg_1 = var_88; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_89_arg_0=-1, var_89_arg_1=0] [L290] EXPR var_89_arg_0 | var_89_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=1, var_111=0, var_112=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L290] SORT_1 var_89 = var_89_arg_0 | var_89_arg_1; [L291] SORT_1 var_110_arg_0 = state_91; [L292] SORT_1 var_110_arg_1 = input_109; [L293] SORT_1 var_110_arg_2 = var_89; [L294] SORT_1 var_110 = var_110_arg_0 ? var_110_arg_1 : var_110_arg_2; [L295] SORT_1 var_113_arg_0 = var_110; [L296] SORT_1 var_113 = ~var_113_arg_0; [L297] SORT_1 var_114_arg_0 = var_112; [L298] SORT_1 var_114_arg_1 = var_113; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_114_arg_0=0, var_114_arg_1=-256, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L299] EXPR var_114_arg_0 & var_114_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L299] SORT_1 var_114 = var_114_arg_0 & var_114_arg_1; [L300] EXPR var_114 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L300] var_114 = var_114 & mask_SORT_1 [L301] SORT_1 bad_115_arg_0 = var_114; [L302] CALL __VERIFIER_assert(!(bad_115_arg_0)) [L21] COND FALSE !(!(cond)) [L302] RET __VERIFIER_assert(!(bad_115_arg_0)) [L304] SORT_11 var_137_arg_0 = state_136; [L305] SORT_13 var_137 = var_137_arg_0 >> 0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L306] EXPR var_137 & mask_SORT_13 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L306] var_137 = var_137 & mask_SORT_13 [L307] SORT_13 var_194_arg_0 = var_137; [L308] SORT_13 var_194_arg_1 = var_15; [L309] SORT_1 var_194 = var_194_arg_0 == var_194_arg_1; [L310] SORT_1 var_195_arg_0 = input_6; [L311] SORT_1 var_195_arg_1 = var_194; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_195_arg_0=0, var_195_arg_1=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L312] EXPR var_195_arg_0 & var_195_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L312] SORT_1 var_195 = var_195_arg_0 & var_195_arg_1; [L313] EXPR var_195 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L313] var_195 = var_195 & mask_SORT_1 [L314] SORT_1 var_267_arg_0 = var_195; [L315] SORT_3 var_267_arg_1 = input_4; [L316] SORT_3 var_267_arg_2 = state_10; [L317] SORT_3 var_267 = var_267_arg_0 ? var_267_arg_1 : var_267_arg_2; [L318] SORT_1 var_269_arg_0 = input_7; [L319] SORT_3 var_269_arg_1 = var_268; [L320] SORT_3 var_269_arg_2 = var_267; [L321] SORT_3 var_269 = var_269_arg_0 ? var_269_arg_1 : var_269_arg_2; [L322] SORT_3 next_270_arg_1 = var_269; [L323] SORT_1 var_119_arg_0 = input_6; [L324] SORT_1 var_119_arg_1 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_119_arg_0=0, var_119_arg_1=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L325] EXPR var_119_arg_0 | var_119_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L325] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L326] SORT_1 var_120_arg_0 = var_119; [L327] SORT_1 var_120_arg_1 = input_7; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120_arg_0=0, var_120_arg_1=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L328] EXPR var_120_arg_0 | var_120_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L328] SORT_1 var_120 = var_120_arg_0 | var_120_arg_1; [L329] EXPR var_120 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L329] var_120 = var_120 & mask_SORT_1 [L330] SORT_1 var_198_arg_0 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_198_arg_0=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L331] EXPR var_198_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L331] var_198_arg_0 = var_198_arg_0 & mask_SORT_1 [L332] SORT_11 var_198 = var_198_arg_0; [L333] SORT_11 var_199_arg_0 = state_12; [L334] SORT_11 var_199_arg_1 = var_198; [L335] SORT_11 var_199 = var_199_arg_0 + var_199_arg_1; [L336] SORT_1 var_271_arg_0 = var_120; [L337] SORT_11 var_271_arg_1 = var_199; [L338] SORT_11 var_271_arg_2 = state_12; [L339] SORT_11 var_271 = var_271_arg_0 ? var_271_arg_1 : var_271_arg_2; [L340] SORT_1 var_272_arg_0 = input_7; [L341] SORT_11 var_272_arg_1 = var_81; [L342] SORT_11 var_272_arg_2 = var_271; [L343] SORT_11 var_272 = var_272_arg_0 ? var_272_arg_1 : var_272_arg_2; [L344] SORT_11 next_273_arg_1 = var_272; [L345] SORT_19 var_187_arg_0 = var_20; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_187_arg_0=7, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L346] EXPR var_187_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L346] var_187_arg_0 = var_187_arg_0 & mask_SORT_19 [L347] SORT_13 var_187 = var_187_arg_0; [L348] SORT_13 var_188_arg_0 = var_137; [L349] SORT_13 var_188_arg_1 = var_187; [L350] SORT_1 var_188 = var_188_arg_0 == var_188_arg_1; [L351] SORT_1 var_189_arg_0 = input_6; [L352] SORT_1 var_189_arg_1 = var_188; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_189_arg_0=0, var_189_arg_1=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L353] EXPR var_189_arg_0 & var_189_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L353] SORT_1 var_189 = var_189_arg_0 & var_189_arg_1; [L354] EXPR var_189 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L354] var_189 = var_189 & mask_SORT_1 [L355] SORT_1 var_274_arg_0 = var_189; [L356] SORT_3 var_274_arg_1 = input_4; [L357] SORT_3 var_274_arg_2 = state_18; [L358] SORT_3 var_274 = var_274_arg_0 ? var_274_arg_1 : var_274_arg_2; [L359] SORT_1 var_275_arg_0 = input_7; [L360] SORT_3 var_275_arg_1 = var_268; [L361] SORT_3 var_275_arg_2 = var_274; [L362] SORT_3 var_275 = var_275_arg_0 ? var_275_arg_1 : var_275_arg_2; [L363] SORT_3 next_276_arg_1 = var_275; [L364] SORT_19 var_180_arg_0 = var_25; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, state_136=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_180_arg_0=6, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L365] EXPR var_180_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, state_136=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L365] var_180_arg_0 = var_180_arg_0 & mask_SORT_19 [L366] SORT_13 var_180 = var_180_arg_0; [L367] SORT_13 var_181_arg_0 = var_137; [L368] SORT_13 var_181_arg_1 = var_180; [L369] SORT_1 var_181 = var_181_arg_0 == var_181_arg_1; [L370] SORT_1 var_182_arg_0 = input_6; [L371] SORT_1 var_182_arg_1 = var_181; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, state_136=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_182_arg_0=0, var_182_arg_1=1, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L372] EXPR var_182_arg_0 & var_182_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, state_136=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L372] SORT_1 var_182 = var_182_arg_0 & var_182_arg_1; [L373] EXPR var_182 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, state_136=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L373] var_182 = var_182 & mask_SORT_1 [L374] SORT_1 var_277_arg_0 = var_182; [L375] SORT_3 var_277_arg_1 = input_4; [L376] SORT_3 var_277_arg_2 = state_24; [L377] SORT_3 var_277 = var_277_arg_0 ? var_277_arg_1 : var_277_arg_2; [L378] SORT_1 var_278_arg_0 = input_7; [L379] SORT_3 var_278_arg_1 = var_268; [L380] SORT_3 var_278_arg_2 = var_277; [L381] SORT_3 var_278 = var_278_arg_0 ? var_278_arg_1 : var_278_arg_2; [L382] SORT_3 next_279_arg_1 = var_278; [L383] SORT_19 var_173_arg_0 = var_30; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, state_136=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_173_arg_0=5, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L384] EXPR var_173_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, state_136=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L384] var_173_arg_0 = var_173_arg_0 & mask_SORT_19 [L385] SORT_13 var_173 = var_173_arg_0; [L386] SORT_13 var_174_arg_0 = var_137; [L387] SORT_13 var_174_arg_1 = var_173; [L388] SORT_1 var_174 = var_174_arg_0 == var_174_arg_1; [L389] SORT_1 var_175_arg_0 = input_6; [L390] SORT_1 var_175_arg_1 = var_174; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, state_136=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_175_arg_0=0, var_175_arg_1=1, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L391] EXPR var_175_arg_0 & var_175_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, state_136=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L391] SORT_1 var_175 = var_175_arg_0 & var_175_arg_1; [L392] EXPR var_175 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, state_136=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L392] var_175 = var_175 & mask_SORT_1 [L393] SORT_1 var_280_arg_0 = var_175; [L394] SORT_3 var_280_arg_1 = input_4; [L395] SORT_3 var_280_arg_2 = state_29; [L396] SORT_3 var_280 = var_280_arg_0 ? var_280_arg_1 : var_280_arg_2; [L397] SORT_1 var_281_arg_0 = input_7; [L398] SORT_3 var_281_arg_1 = var_268; [L399] SORT_3 var_281_arg_2 = var_280; [L400] SORT_3 var_281 = var_281_arg_0 ? var_281_arg_1 : var_281_arg_2; [L401] SORT_3 next_282_arg_1 = var_281; [L402] SORT_19 var_166_arg_0 = var_35; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, state_136=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_166_arg_0=4, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L403] EXPR var_166_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, state_136=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L403] var_166_arg_0 = var_166_arg_0 & mask_SORT_19 [L404] SORT_13 var_166 = var_166_arg_0; [L405] SORT_13 var_167_arg_0 = var_137; [L406] SORT_13 var_167_arg_1 = var_166; [L407] SORT_1 var_167 = var_167_arg_0 == var_167_arg_1; [L408] SORT_1 var_168_arg_0 = input_6; [L409] SORT_1 var_168_arg_1 = var_167; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, state_136=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_168_arg_0=0, var_168_arg_1=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L410] EXPR var_168_arg_0 & var_168_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, state_136=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L410] SORT_1 var_168 = var_168_arg_0 & var_168_arg_1; [L411] EXPR var_168 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, state_136=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L411] var_168 = var_168 & mask_SORT_1 [L412] SORT_1 var_283_arg_0 = var_168; [L413] SORT_3 var_283_arg_1 = input_4; [L414] SORT_3 var_283_arg_2 = state_34; [L415] SORT_3 var_283 = var_283_arg_0 ? var_283_arg_1 : var_283_arg_2; [L416] SORT_1 var_284_arg_0 = input_7; [L417] SORT_3 var_284_arg_1 = var_268; [L418] SORT_3 var_284_arg_2 = var_283; [L419] SORT_3 var_284 = var_284_arg_0 ? var_284_arg_1 : var_284_arg_2; [L420] SORT_3 next_285_arg_1 = var_284; [L421] SORT_40 var_159_arg_0 = var_41; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, state_136=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_159_arg_0=3, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L422] EXPR var_159_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, state_136=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L422] var_159_arg_0 = var_159_arg_0 & mask_SORT_40 [L423] SORT_13 var_159 = var_159_arg_0; [L424] SORT_13 var_160_arg_0 = var_137; [L425] SORT_13 var_160_arg_1 = var_159; [L426] SORT_1 var_160 = var_160_arg_0 == var_160_arg_1; [L427] SORT_1 var_161_arg_0 = input_6; [L428] SORT_1 var_161_arg_1 = var_160; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, state_136=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_161_arg_0=0, var_161_arg_1=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L429] EXPR var_161_arg_0 & var_161_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, state_136=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L429] SORT_1 var_161 = var_161_arg_0 & var_161_arg_1; [L430] EXPR var_161 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, state_136=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L430] var_161 = var_161 & mask_SORT_1 [L431] SORT_1 var_286_arg_0 = var_161; [L432] SORT_3 var_286_arg_1 = input_4; [L433] SORT_3 var_286_arg_2 = state_39; [L434] SORT_3 var_286 = var_286_arg_0 ? var_286_arg_1 : var_286_arg_2; [L435] SORT_1 var_287_arg_0 = input_7; [L436] SORT_3 var_287_arg_1 = var_268; [L437] SORT_3 var_287_arg_2 = var_286; [L438] SORT_3 var_287 = var_287_arg_0 ? var_287_arg_1 : var_287_arg_2; [L439] SORT_3 next_288_arg_1 = var_287; [L440] SORT_40 var_152_arg_0 = var_46; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, state_136=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_152_arg_0=2, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L441] EXPR var_152_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, state_136=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L441] var_152_arg_0 = var_152_arg_0 & mask_SORT_40 [L442] SORT_13 var_152 = var_152_arg_0; [L443] SORT_13 var_153_arg_0 = var_137; [L444] SORT_13 var_153_arg_1 = var_152; [L445] SORT_1 var_153 = var_153_arg_0 == var_153_arg_1; [L446] SORT_1 var_154_arg_0 = input_6; [L447] SORT_1 var_154_arg_1 = var_153; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, state_136=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_154_arg_0=0, var_154_arg_1=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L448] EXPR var_154_arg_0 & var_154_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, state_136=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L448] SORT_1 var_154 = var_154_arg_0 & var_154_arg_1; [L449] EXPR var_154 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, state_136=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L449] var_154 = var_154 & mask_SORT_1 [L450] SORT_1 var_289_arg_0 = var_154; [L451] SORT_3 var_289_arg_1 = input_4; [L452] SORT_3 var_289_arg_2 = state_45; [L453] SORT_3 var_289 = var_289_arg_0 ? var_289_arg_1 : var_289_arg_2; [L454] SORT_1 var_290_arg_0 = input_7; [L455] SORT_3 var_290_arg_1 = var_268; [L456] SORT_3 var_290_arg_2 = var_289; [L457] SORT_3 var_290 = var_290_arg_0 ? var_290_arg_1 : var_290_arg_2; [L458] SORT_3 next_291_arg_1 = var_290; [L459] SORT_1 var_145_arg_0 = var_51; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, state_136=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_145_arg_0=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L460] EXPR var_145_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, state_136=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L460] var_145_arg_0 = var_145_arg_0 & mask_SORT_1 [L461] SORT_13 var_145 = var_145_arg_0; [L462] SORT_13 var_146_arg_0 = var_137; [L463] SORT_13 var_146_arg_1 = var_145; [L464] SORT_1 var_146 = var_146_arg_0 == var_146_arg_1; [L465] SORT_1 var_147_arg_0 = input_6; [L466] SORT_1 var_147_arg_1 = var_146; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, state_136=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_147_arg_0=0, var_147_arg_1=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L467] EXPR var_147_arg_0 & var_147_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, state_136=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L467] SORT_1 var_147 = var_147_arg_0 & var_147_arg_1; [L468] EXPR var_147 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, state_136=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_137=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L468] var_147 = var_147 & mask_SORT_1 [L469] SORT_1 var_292_arg_0 = var_147; [L470] SORT_3 var_292_arg_1 = input_4; [L471] SORT_3 var_292_arg_2 = state_50; [L472] SORT_3 var_292 = var_292_arg_0 ? var_292_arg_1 : var_292_arg_2; [L473] SORT_1 var_293_arg_0 = input_7; [L474] SORT_3 var_293_arg_1 = var_268; [L475] SORT_3 var_293_arg_2 = var_292; [L476] SORT_3 var_293 = var_293_arg_0 ? var_293_arg_1 : var_293_arg_2; [L477] SORT_3 next_294_arg_1 = var_293; [L478] SORT_13 var_138_arg_0 = var_137; [L479] SORT_1 var_138 = var_138_arg_0 != 0; [L480] SORT_1 var_139_arg_0 = var_138; [L481] SORT_1 var_139 = ~var_139_arg_0; [L482] SORT_1 var_140_arg_0 = input_6; [L483] SORT_1 var_140_arg_1 = var_139; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, state_136=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_140_arg_0=0, var_140_arg_1=-1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L484] EXPR var_140_arg_0 & var_140_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, state_136=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L484] SORT_1 var_140 = var_140_arg_0 & var_140_arg_1; [L485] EXPR var_140 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, state_136=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L485] var_140 = var_140 & mask_SORT_1 [L486] SORT_1 var_295_arg_0 = var_140; [L487] SORT_3 var_295_arg_1 = input_4; [L488] SORT_3 var_295_arg_2 = state_55; [L489] SORT_3 var_295 = var_295_arg_0 ? var_295_arg_1 : var_295_arg_2; [L490] SORT_1 var_296_arg_0 = input_7; [L491] SORT_3 var_296_arg_1 = var_268; [L492] SORT_3 var_296_arg_2 = var_295; [L493] SORT_3 var_296 = var_296_arg_0 ? var_296_arg_1 : var_296_arg_2; [L494] SORT_3 next_297_arg_1 = var_296; [L495] SORT_1 var_298_arg_0 = input_6; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_298_arg_0=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L496] EXPR var_298_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L496] var_298_arg_0 = var_298_arg_0 & mask_SORT_1 [L497] SORT_11 var_298 = var_298_arg_0; [L498] SORT_11 var_299_arg_0 = state_60; [L499] SORT_11 var_299_arg_1 = var_298; [L500] SORT_11 var_299 = var_299_arg_0 + var_299_arg_1; [L501] SORT_1 var_300_arg_0 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_299=0, var_300_arg_0=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L502] EXPR var_300_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_299=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L502] var_300_arg_0 = var_300_arg_0 & mask_SORT_1 [L503] SORT_11 var_300 = var_300_arg_0; [L504] SORT_11 var_301_arg_0 = var_299; [L505] SORT_11 var_301_arg_1 = var_300; [L506] SORT_11 var_301 = var_301_arg_0 - var_301_arg_1; [L507] SORT_1 var_302_arg_0 = input_7; [L508] SORT_11 var_302_arg_1 = var_81; [L509] SORT_11 var_302_arg_2 = var_301; [L510] SORT_11 var_302 = var_302_arg_0 ? var_302_arg_1 : var_302_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_302=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L511] EXPR var_302 & mask_SORT_11 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L511] var_302 = var_302 & mask_SORT_11 [L512] SORT_11 next_303_arg_1 = var_302; [L513] SORT_1 var_228_arg_0 = state_68; [L514] SORT_1 var_228 = ~var_228_arg_0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_228=-1, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L515] EXPR var_228 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L515] var_228 = var_228 & mask_SORT_1 [L516] SORT_1 var_224_arg_0 = input_8; [L517] SORT_1 var_224_arg_1 = input_6; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224_arg_0=0, var_224_arg_1=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L518] EXPR var_224_arg_0 & var_224_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L518] SORT_1 var_224 = var_224_arg_0 & var_224_arg_1; [L519] SORT_1 var_225_arg_0 = state_68; [L520] SORT_1 var_225_arg_1 = var_224; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_225_arg_0=0, var_225_arg_1=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L521] EXPR var_225_arg_0 | var_225_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L521] SORT_1 var_225 = var_225_arg_0 | var_225_arg_1; [L522] SORT_1 var_304_arg_0 = var_228; [L523] SORT_1 var_304_arg_1 = var_225; [L524] SORT_1 var_304_arg_2 = state_68; [L525] SORT_1 var_304 = var_304_arg_0 ? var_304_arg_1 : var_304_arg_2; [L526] SORT_1 var_305_arg_0 = input_7; [L527] SORT_1 var_305_arg_1 = var_111; [L528] SORT_1 var_305_arg_2 = var_304; [L529] SORT_1 var_305 = var_305_arg_0 ? var_305_arg_1 : var_305_arg_2; [L530] SORT_1 next_306_arg_1 = var_305; [L531] SORT_1 var_236_arg_0 = var_85; [L532] SORT_1 var_236_arg_1 = state_69; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_236_arg_0=0, var_236_arg_1=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L533] EXPR var_236_arg_0 | var_236_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, state_136=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L533] SORT_1 var_236 = var_236_arg_0 | var_236_arg_1; [L534] SORT_1 var_307_arg_0 = var_51; [L535] SORT_1 var_307_arg_1 = var_236; [L536] SORT_1 var_307_arg_2 = state_69; [L537] SORT_1 var_307 = var_307_arg_0 ? var_307_arg_1 : var_307_arg_2; [L538] SORT_1 var_308_arg_0 = input_7; [L539] SORT_1 var_308_arg_1 = var_111; [L540] SORT_1 var_308_arg_2 = var_307; [L541] SORT_1 var_308 = var_308_arg_0 ? var_308_arg_1 : var_308_arg_2; [L542] SORT_1 next_309_arg_1 = var_308; [L543] SORT_1 var_248_arg_0 = input_6; [L544] SORT_1 var_248_arg_1 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_68=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_248_arg_0=0, var_248_arg_1=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L545] EXPR var_248_arg_0 | var_248_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_68=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L545] SORT_1 var_248 = var_248_arg_0 | var_248_arg_1; [L546] SORT_1 var_249_arg_0 = var_248; [L547] SORT_1 var_249_arg_1 = input_7; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_68=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_249_arg_0=0, var_249_arg_1=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L548] EXPR var_249_arg_0 | var_249_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_68=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L548] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L549] SORT_1 var_250_arg_0 = var_249; [L550] SORT_1 var_250_arg_1 = state_68; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_250_arg_0=0, var_250_arg_1=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L551] EXPR var_250_arg_0 | var_250_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L551] SORT_1 var_250 = var_250_arg_0 | var_250_arg_1; [L552] EXPR var_250 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_72=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L552] var_250 = var_250 & mask_SORT_1 [L553] SORT_1 var_310_arg_0 = var_250; [L554] SORT_11 var_310_arg_1 = var_82; [L555] SORT_11 var_310_arg_2 = state_72; [L556] SORT_11 var_310 = var_310_arg_0 ? var_310_arg_1 : var_310_arg_2; [L557] SORT_1 var_311_arg_0 = input_7; [L558] SORT_11 var_311_arg_1 = var_81; [L559] SORT_11 var_311_arg_2 = var_310; [L560] SORT_11 var_311 = var_311_arg_0 ? var_311_arg_1 : var_311_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_311=0, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L561] EXPR var_311 & mask_SORT_11 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, state_136=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_224=0, var_228=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L561] var_311 = var_311 & mask_SORT_11 [L562] SORT_11 next_312_arg_1 = var_311; [L563] SORT_1 var_233_arg_0 = var_224; [L564] SORT_1 var_233_arg_1 = var_228; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, state_136=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_233_arg_0=0, var_233_arg_1=0, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L565] EXPR var_233_arg_0 & var_233_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, state_136=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L565] SORT_1 var_233 = var_233_arg_0 & var_233_arg_1; [L566] EXPR var_233 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, state_136=0, state_87=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L566] var_233 = var_233 & mask_SORT_1 [L567] SORT_1 var_313_arg_0 = var_233; [L568] SORT_3 var_313_arg_1 = input_4; [L569] SORT_3 var_313_arg_2 = state_87; [L570] SORT_3 var_313 = var_313_arg_0 ? var_313_arg_1 : var_313_arg_2; [L571] SORT_1 var_314_arg_0 = input_7; [L572] SORT_3 var_314_arg_1 = var_268; [L573] SORT_3 var_314_arg_2 = var_313; [L574] SORT_3 var_314 = var_314_arg_0 ? var_314_arg_1 : var_314_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, state_136=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_314=0, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L575] EXPR var_314 & mask_SORT_3 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, state_136=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L575] var_314 = var_314 & mask_SORT_3 [L576] SORT_3 next_315_arg_1 = var_314; [L577] SORT_1 next_316_arg_1 = var_111; [L578] SORT_1 var_204_arg_0 = input_6; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, next_315_arg_1=0, next_316_arg_1=0, state_136=0, var_111=0, var_120=0, var_15=8, var_204_arg_0=0, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L579] EXPR var_204_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_7=0, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, next_270_arg_1=0, next_273_arg_1=0, next_276_arg_1=0, next_279_arg_1=0, next_282_arg_1=0, next_285_arg_1=0, next_288_arg_1=0, next_291_arg_1=0, next_294_arg_1=0, next_297_arg_1=0, next_303_arg_1=0, next_306_arg_1=0, next_309_arg_1=0, next_312_arg_1=0, next_315_arg_1=0, next_316_arg_1=0, state_136=0, var_111=0, var_120=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L579] var_204_arg_0 = var_204_arg_0 & mask_SORT_1 [L580] SORT_11 var_204 = var_204_arg_0; [L581] SORT_11 var_205_arg_0 = state_136; [L582] SORT_11 var_205_arg_1 = var_204; [L583] SORT_11 var_205 = var_205_arg_0 + var_205_arg_1; [L584] SORT_1 var_317_arg_0 = var_120; [L585] SORT_11 var_317_arg_1 = var_205; [L586] SORT_11 var_317_arg_2 = state_136; [L587] SORT_11 var_317 = var_317_arg_0 ? var_317_arg_1 : var_317_arg_2; [L588] SORT_1 var_318_arg_0 = input_7; [L589] SORT_11 var_318_arg_1 = var_81; [L590] SORT_11 var_318_arg_2 = var_317; [L591] SORT_11 var_318 = var_318_arg_0 ? var_318_arg_1 : var_318_arg_2; [L592] SORT_11 next_319_arg_1 = var_318; [L594] state_10 = next_270_arg_1 [L595] state_12 = next_273_arg_1 [L596] state_18 = next_276_arg_1 [L597] state_24 = next_279_arg_1 [L598] state_29 = next_282_arg_1 [L599] state_34 = next_285_arg_1 [L600] state_39 = next_288_arg_1 [L601] state_45 = next_291_arg_1 [L602] state_50 = next_294_arg_1 [L603] state_55 = next_297_arg_1 [L604] state_60 = next_303_arg_1 [L605] state_68 = next_306_arg_1 [L606] state_69 = next_309_arg_1 [L607] state_72 = next_312_arg_1 [L608] state_87 = next_315_arg_1 [L609] state_91 = next_316_arg_1 [L610] state_136 = next_319_arg_1 [L88] input_2 = __VERIFIER_nondet_uchar() [L89] input_4 = __VERIFIER_nondet_ushort() [L90] input_5 = __VERIFIER_nondet_uchar() [L91] input_6 = __VERIFIER_nondet_uchar() [L92] input_7 = __VERIFIER_nondet_uchar() [L93] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L93] input_7 = input_7 & mask_SORT_1 [L94] input_8 = __VERIFIER_nondet_uchar() [L95] input_9 = __VERIFIER_nondet_ushort() [L96] input_109 = __VERIFIER_nondet_uchar() [L98] SORT_1 var_93_arg_0 = input_7; [L99] SORT_1 var_93_arg_1 = state_91; [L100] SORT_1 var_93 = var_93_arg_0 == var_93_arg_1; [L101] SORT_1 var_94_arg_0 = var_51; [L102] SORT_1 var_94 = ~var_94_arg_0; [L103] SORT_1 var_95_arg_0 = var_93; [L104] SORT_1 var_95_arg_1 = var_94; VAL [input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_95_arg_0=0, var_95_arg_1=-2] [L105] EXPR var_95_arg_0 | var_95_arg_1 VAL [input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L105] SORT_1 var_95 = var_95_arg_0 | var_95_arg_1; [L106] EXPR var_95 & mask_SORT_1 VAL [input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L106] var_95 = var_95 & mask_SORT_1 [L107] SORT_1 constr_96_arg_0 = var_95; VAL [constr_96_arg_0=1, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L108] CALL assume_abort_if_not(constr_96_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L108] RET assume_abort_if_not(constr_96_arg_0) VAL [constr_96_arg_0=1, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L109] SORT_13 var_65_arg_0 = var_64; VAL [constr_96_arg_0=1, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_65_arg_0=9, var_81=0] [L110] EXPR var_65_arg_0 & mask_SORT_13 VAL [constr_96_arg_0=1, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L110] var_65_arg_0 = var_65_arg_0 & mask_SORT_13 [L111] SORT_11 var_65 = var_65_arg_0; [L112] SORT_11 var_66_arg_0 = state_60; [L113] SORT_11 var_66_arg_1 = var_65; [L114] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L115] SORT_1 var_97_arg_0 = var_66; [L116] SORT_1 var_97 = ~var_97_arg_0; [L117] SORT_1 var_98_arg_0 = input_6; [L118] SORT_1 var_98 = ~var_98_arg_0; [L119] SORT_1 var_99_arg_0 = var_97; [L120] SORT_1 var_99_arg_1 = var_98; VAL [constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_99_arg_0=-1, var_99_arg_1=-1] [L121] EXPR var_99_arg_0 | var_99_arg_1 VAL [constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L121] SORT_1 var_99 = var_99_arg_0 | var_99_arg_1; [L122] SORT_1 var_100_arg_0 = var_51; [L123] SORT_1 var_100 = ~var_100_arg_0; [L124] SORT_1 var_101_arg_0 = var_99; [L125] SORT_1 var_101_arg_1 = var_100; VAL [constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_101_arg_0=255, var_101_arg_1=-2, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L126] EXPR var_101_arg_0 | var_101_arg_1 VAL [constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L126] SORT_1 var_101 = var_101_arg_0 | var_101_arg_1; [L127] EXPR var_101 & mask_SORT_1 VAL [constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L127] var_101 = var_101 & mask_SORT_1 [L128] SORT_1 constr_102_arg_0 = var_101; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L129] CALL assume_abort_if_not(constr_102_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L129] RET assume_abort_if_not(constr_102_arg_0) VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L130] SORT_11 var_61_arg_0 = state_60; [L131] SORT_1 var_61 = var_61_arg_0 != 0; [L132] SORT_1 var_62_arg_0 = var_61; [L133] SORT_1 var_62 = ~var_62_arg_0; [L134] SORT_1 var_103_arg_0 = var_62; [L135] SORT_1 var_103 = ~var_103_arg_0; [L136] SORT_1 var_104_arg_0 = input_5; [L137] SORT_1 var_104 = ~var_104_arg_0; [L138] SORT_1 var_105_arg_0 = var_103; [L139] SORT_1 var_105_arg_1 = var_104; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_105_arg_0=-256, var_105_arg_1=-2, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L140] EXPR var_105_arg_0 | var_105_arg_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L140] SORT_1 var_105 = var_105_arg_0 | var_105_arg_1; [L141] SORT_1 var_106_arg_0 = var_51; [L142] SORT_1 var_106 = ~var_106_arg_0; [L143] SORT_1 var_107_arg_0 = var_105; [L144] SORT_1 var_107_arg_1 = var_106; VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_107_arg_0=254, var_107_arg_1=-2, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L145] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L145] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L146] EXPR var_107 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L146] var_107 = var_107 & mask_SORT_1 [L147] SORT_1 constr_108_arg_0 = var_107; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L148] CALL assume_abort_if_not(constr_108_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L148] RET assume_abort_if_not(constr_108_arg_0) VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L150] SORT_1 var_112_arg_0 = state_91; [L151] SORT_1 var_112_arg_1 = var_111; [L152] SORT_1 var_112_arg_2 = var_51; [L153] SORT_1 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L154] SORT_1 var_70_arg_0 = state_69; [L155] SORT_1 var_70 = ~var_70_arg_0; [L156] SORT_1 var_71_arg_0 = state_68; [L157] SORT_1 var_71_arg_1 = var_70; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_71_arg_0=0, var_71_arg_1=-1, var_81=0] [L158] EXPR var_71_arg_0 & var_71_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L158] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L159] SORT_11 var_73_arg_0 = state_72; [L160] SORT_1 var_73 = var_73_arg_0 != 0; [L161] SORT_1 var_74_arg_0 = var_71; [L162] SORT_1 var_74_arg_1 = var_73; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74_arg_0=0, var_74_arg_1=0, var_81=0] [L163] EXPR var_74_arg_0 & var_74_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0] [L163] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L164] SORT_1 var_75_arg_0 = state_68; [L165] SORT_1 var_75 = ~var_75_arg_0; [L166] SORT_1 var_76_arg_0 = input_6; [L167] SORT_1 var_76_arg_1 = var_75; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_76_arg_0=0, var_76_arg_1=-1, var_81=0] [L168] EXPR var_76_arg_0 & var_76_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L168] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_76; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_77_arg_0=0, var_81=0] [L170] EXPR var_77_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L170] var_77_arg_0 = var_77_arg_0 & mask_SORT_1 [L171] SORT_11 var_77 = var_77_arg_0; [L172] SORT_11 var_78_arg_0 = state_72; [L173] SORT_11 var_78_arg_1 = var_77; [L174] SORT_11 var_78 = var_78_arg_0 + var_78_arg_1; [L175] SORT_1 var_79_arg_0 = input_5; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_78=0, var_79_arg_0=1, var_81=0] [L176] EXPR var_79_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_78=0, var_81=0] [L176] var_79_arg_0 = var_79_arg_0 & mask_SORT_1 [L177] SORT_11 var_79 = var_79_arg_0; [L178] SORT_11 var_80_arg_0 = var_78; [L179] SORT_11 var_80_arg_1 = var_79; [L180] SORT_11 var_80 = var_80_arg_0 - var_80_arg_1; [L181] SORT_1 var_82_arg_0 = input_7; [L182] SORT_11 var_82_arg_1 = var_81; [L183] SORT_11 var_82_arg_2 = var_80; [L184] SORT_11 var_82 = var_82_arg_0 ? var_82_arg_1 : var_82_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0, var_82=0] [L185] EXPR var_82 & mask_SORT_11 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_74=0, var_81=0] [L185] var_82 = var_82 & mask_SORT_11 [L186] SORT_11 var_83_arg_0 = var_82; [L187] SORT_1 var_83 = var_83_arg_0 != 0; [L188] SORT_1 var_84_arg_0 = var_83; [L189] SORT_1 var_84 = ~var_84_arg_0; [L190] SORT_1 var_85_arg_0 = var_74; [L191] SORT_1 var_85_arg_1 = var_84; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85_arg_0=0, var_85_arg_1=-1] [L192] EXPR var_85_arg_0 & var_85_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0] [L192] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L193] SORT_1 var_86_arg_0 = var_85; [L194] SORT_1 var_86 = ~var_86_arg_0; [L195] SORT_11 var_14_arg_0 = state_12; [L196] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L197] EXPR var_14 & mask_SORT_13 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L197] var_14 = var_14 & mask_SORT_13 [L198] SORT_13 var_56_arg_0 = var_14; [L199] SORT_1 var_56 = var_56_arg_0 != 0; [L200] SORT_1 var_57_arg_0 = var_56; [L201] SORT_1 var_57 = ~var_57_arg_0; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_57=-1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L202] EXPR var_57 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L202] var_57 = var_57 & mask_SORT_1 [L203] SORT_1 var_52_arg_0 = var_51; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_52_arg_0=1, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L204] EXPR var_52_arg_0 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L204] var_52_arg_0 = var_52_arg_0 & mask_SORT_1 [L205] SORT_13 var_52 = var_52_arg_0; [L206] SORT_13 var_53_arg_0 = var_14; [L207] SORT_13 var_53_arg_1 = var_52; [L208] SORT_1 var_53 = var_53_arg_0 == var_53_arg_1; [L209] SORT_40 var_47_arg_0 = var_46; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_47_arg_0=2, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L210] EXPR var_47_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L210] var_47_arg_0 = var_47_arg_0 & mask_SORT_40 [L211] SORT_13 var_47 = var_47_arg_0; [L212] SORT_13 var_48_arg_0 = var_14; [L213] SORT_13 var_48_arg_1 = var_47; [L214] SORT_1 var_48 = var_48_arg_0 == var_48_arg_1; [L215] SORT_40 var_42_arg_0 = var_41; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_42_arg_0=3, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L216] EXPR var_42_arg_0 & mask_SORT_40 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L216] var_42_arg_0 = var_42_arg_0 & mask_SORT_40 [L217] SORT_13 var_42 = var_42_arg_0; [L218] SORT_13 var_43_arg_0 = var_14; [L219] SORT_13 var_43_arg_1 = var_42; [L220] SORT_1 var_43 = var_43_arg_0 == var_43_arg_1; [L221] SORT_19 var_36_arg_0 = var_35; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_36_arg_0=4, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L222] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L222] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L223] SORT_13 var_36 = var_36_arg_0; [L224] SORT_13 var_37_arg_0 = var_14; [L225] SORT_13 var_37_arg_1 = var_36; [L226] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L227] SORT_19 var_31_arg_0 = var_30; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_31_arg_0=5, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L228] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L228] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L229] SORT_13 var_31 = var_31_arg_0; [L230] SORT_13 var_32_arg_0 = var_14; [L231] SORT_13 var_32_arg_1 = var_31; [L232] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L233] SORT_19 var_26_arg_0 = var_25; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_26_arg_0=6, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L234] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L234] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L235] SORT_13 var_26 = var_26_arg_0; [L236] SORT_13 var_27_arg_0 = var_14; [L237] SORT_13 var_27_arg_1 = var_26; [L238] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L239] SORT_19 var_21_arg_0 = var_20; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_21_arg_0=7, var_25=6, var_268=0, var_27=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L240] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_14=0, var_15=8, var_20=7, var_25=6, var_268=0, var_27=0, var_30=5, var_32=0, var_35=4, var_37=0, var_41=3, var_43=0, var_46=2, var_48=0, var_51=1, var_53=0, var_57=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L240] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L241] SORT_13 var_21 = var_21_arg_0; [L242] SORT_13 var_22_arg_0 = var_14; [L243] SORT_13 var_22_arg_1 = var_21; [L244] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L245] SORT_13 var_16_arg_0 = var_14; [L246] SORT_13 var_16_arg_1 = var_15; [L247] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L248] SORT_1 var_17_arg_0 = var_16; [L249] SORT_3 var_17_arg_1 = state_10; [L250] SORT_3 var_17_arg_2 = input_9; [L251] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L252] SORT_1 var_23_arg_0 = var_22; [L253] SORT_3 var_23_arg_1 = state_18; [L254] SORT_3 var_23_arg_2 = var_17; [L255] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L256] SORT_1 var_28_arg_0 = var_27; [L257] SORT_3 var_28_arg_1 = state_24; [L258] SORT_3 var_28_arg_2 = var_23; [L259] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L260] SORT_1 var_33_arg_0 = var_32; [L261] SORT_3 var_33_arg_1 = state_29; [L262] SORT_3 var_33_arg_2 = var_28; [L263] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L264] SORT_1 var_38_arg_0 = var_37; [L265] SORT_3 var_38_arg_1 = state_34; [L266] SORT_3 var_38_arg_2 = var_33; [L267] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L268] SORT_1 var_44_arg_0 = var_43; [L269] SORT_3 var_44_arg_1 = state_39; [L270] SORT_3 var_44_arg_2 = var_38; [L271] SORT_3 var_44 = var_44_arg_0 ? var_44_arg_1 : var_44_arg_2; [L272] SORT_1 var_49_arg_0 = var_48; [L273] SORT_3 var_49_arg_1 = state_45; [L274] SORT_3 var_49_arg_2 = var_44; [L275] SORT_3 var_49 = var_49_arg_0 ? var_49_arg_1 : var_49_arg_2; [L276] SORT_1 var_54_arg_0 = var_53; [L277] SORT_3 var_54_arg_1 = state_50; [L278] SORT_3 var_54_arg_2 = var_49; [L279] SORT_3 var_54 = var_54_arg_0 ? var_54_arg_1 : var_54_arg_2; [L280] SORT_1 var_58_arg_0 = var_57; [L281] SORT_3 var_58_arg_1 = state_55; [L282] SORT_3 var_58_arg_2 = var_54; [L283] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_58=0, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L284] EXPR var_58 & mask_SORT_3 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_86=-1] [L284] var_58 = var_58 & mask_SORT_3 [L285] SORT_3 var_88_arg_0 = state_87; [L286] SORT_3 var_88_arg_1 = var_58; [L287] SORT_1 var_88 = var_88_arg_0 == var_88_arg_1; [L288] SORT_1 var_89_arg_0 = var_86; [L289] SORT_1 var_89_arg_1 = var_88; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0, var_89_arg_0=-1, var_89_arg_1=1] [L290] EXPR var_89_arg_0 | var_89_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, state_91=0, var_111=0, var_112=1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L290] SORT_1 var_89 = var_89_arg_0 | var_89_arg_1; [L291] SORT_1 var_110_arg_0 = state_91; [L292] SORT_1 var_110_arg_1 = input_109; [L293] SORT_1 var_110_arg_2 = var_89; [L294] SORT_1 var_110 = var_110_arg_0 ? var_110_arg_1 : var_110_arg_2; [L295] SORT_1 var_113_arg_0 = var_110; [L296] SORT_1 var_113 = ~var_113_arg_0; [L297] SORT_1 var_114_arg_0 = var_112; [L298] SORT_1 var_114_arg_1 = var_113; VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_114_arg_0=1, var_114_arg_1=-1, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L299] EXPR var_114_arg_0 & var_114_arg_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L299] SORT_1 var_114 = var_114_arg_0 & var_114_arg_1; [L300] EXPR var_114 & mask_SORT_1 VAL [constr_102_arg_0=1, constr_108_arg_0=1, constr_96_arg_0=1, input_5=1, input_6=0, input_7=1, mask_SORT_11=31, mask_SORT_13=15, mask_SORT_19=7, mask_SORT_1=1, mask_SORT_3=65535, mask_SORT_40=3, state_10=0, state_12=0, state_136=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_45=0, state_50=0, state_55=0, state_60=0, state_68=0, state_69=0, state_72=0, state_87=0, var_111=0, var_15=8, var_20=7, var_25=6, var_268=0, var_30=5, var_35=4, var_41=3, var_46=2, var_51=1, var_64=9, var_81=0, var_82=0, var_85=0] [L300] var_114 = var_114 & mask_SORT_1 [L301] SORT_1 bad_115_arg_0 = var_114; [L302] CALL __VERIFIER_assert(!(bad_115_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 392 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 277.2s, OverallIterations: 56, TraceHistogramMax: 6, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.4s, AutomataDifference: 79.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 57530 SdHoareTripleChecker+Valid, 47.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 57457 mSDsluCounter, 173626 SdHoareTripleChecker+Invalid, 40.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 143204 mSDsCounter, 287 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 59921 IncrementalHoareTripleChecker+Invalid, 60208 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 287 mSolverCounterUnsat, 30422 mSDtfsCounter, 59921 mSolverCounterSat, 0.8s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 7995 GetRequests, 7079 SyntacticMatches, 5 SemanticMatches, 911 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 53204 ImplicationChecksByTransitivity, 33.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=21172occurred in iteration=54, InterpolantAutomatonStates: 677, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 4.6s AutomataMinimizationTime, 55 MinimizatonAttempts, 46104 StatesRemovedByMinimization, 21 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 3.5s SsaConstructionTime, 55.8s SatisfiabilityAnalysisTime, 103.1s InterpolantComputationTime, 20288 NumberOfCodeBlocks, 20288 NumberOfCodeBlocksAsserted, 71 NumberOfCheckSat, 21982 ConstructedInterpolants, 0 QuantifiedInterpolants, 134050 SizeOfPredicates, 75 NumberOfNonLiveVariables, 29675 ConjunctsInSsa, 728 ConjunctsInUnsatCore, 76 InterpolantComputations, 50 PerfectInterpolantSequences, 7140/8622 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-24 00:52:04,713 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 4d887e46d9e1781030c0b6aae8069b6bddec306ee6a48cba2aa303ff66f408ca --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 00:52:08,034 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 00:52:08,165 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-24 00:52:08,177 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 00:52:08,178 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 00:52:08,248 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 00:52:08,250 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 00:52:08,250 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 00:52:08,251 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 00:52:08,251 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 00:52:08,252 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 00:52:08,253 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 00:52:08,253 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 00:52:08,254 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 00:52:08,254 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 00:52:08,254 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 00:52:08,255 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 00:52:08,255 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 00:52:08,255 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-24 00:52:08,256 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 00:52:08,257 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:52:08,257 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:52:08,258 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:52:08,258 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 00:52:08,258 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-24 00:52:08,259 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-24 00:52:08,259 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 00:52:08,268 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 00:52:08,269 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 00:52:08,269 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 00:52:08,269 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d887e46d9e1781030c0b6aae8069b6bddec306ee6a48cba2aa303ff66f408ca [2024-11-24 00:52:08,658 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 00:52:08,669 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 00:52:08,671 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 00:52:08,673 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 00:52:08,674 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 00:52:08,675 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:52:12,055 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/caf834794/2eb35db602bb4571bebdd015a6089ed5/FLAGf2a3e6fd2 [2024-11-24 00:52:12,538 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 00:52:12,542 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:52:12,566 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/caf834794/2eb35db602bb4571bebdd015a6089ed5/FLAGf2a3e6fd2 [2024-11-24 00:52:12,594 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/data/caf834794/2eb35db602bb4571bebdd015a6089ed5 [2024-11-24 00:52:12,600 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 00:52:12,602 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 00:52:12,605 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 00:52:12,607 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 00:52:12,613 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 00:52:12,615 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:52:12" (1/1) ... [2024-11-24 00:52:12,619 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4e387b06 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:12, skipping insertion in model container [2024-11-24 00:52:12,619 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:52:12" (1/1) ... [2024-11-24 00:52:12,679 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 00:52:12,903 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c[1279,1292] [2024-11-24 00:52:13,097 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:52:13,110 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 00:52:13,123 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c[1279,1292] [2024-11-24 00:52:13,284 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:52:13,304 INFO L204 MainTranslator]: Completed translation [2024-11-24 00:52:13,304 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13 WrapperNode [2024-11-24 00:52:13,305 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 00:52:13,306 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 00:52:13,306 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 00:52:13,306 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 00:52:13,316 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,345 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,416 INFO L138 Inliner]: procedures = 17, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 638 [2024-11-24 00:52:13,417 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 00:52:13,418 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 00:52:13,418 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 00:52:13,418 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 00:52:13,430 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,430 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,439 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,466 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-24 00:52:13,466 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,466 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,486 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,488 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,492 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,495 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,499 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,506 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 00:52:13,507 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 00:52:13,507 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 00:52:13,507 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 00:52:13,508 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (1/1) ... [2024-11-24 00:52:13,523 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:52:13,547 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:52:13,564 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 00:52:13,568 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 00:52:13,597 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 00:52:13,597 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-24 00:52:13,597 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 00:52:13,597 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 00:52:13,598 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 00:52:13,598 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 00:52:13,826 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 00:52:13,828 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 00:52:14,786 INFO L? ?]: Removed 198 outVars from TransFormulas that were not future-live. [2024-11-24 00:52:14,786 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 00:52:14,800 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 00:52:14,800 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-24 00:52:14,802 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:52:14 BoogieIcfgContainer [2024-11-24 00:52:14,802 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 00:52:14,806 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 00:52:14,807 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 00:52:14,816 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 00:52:14,816 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 12:52:12" (1/3) ... [2024-11-24 00:52:14,816 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2ee1cbc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:52:14, skipping insertion in model container [2024-11-24 00:52:14,817 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:52:13" (2/3) ... [2024-11-24 00:52:14,817 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2ee1cbc3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:52:14, skipping insertion in model container [2024-11-24 00:52:14,817 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:52:14" (3/3) ... [2024-11-24 00:52:14,819 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c [2024-11-24 00:52:14,836 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 00:52:14,838 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w16_d8_e0.c that has 2 procedures, 20 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-24 00:52:14,901 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 00:52:14,914 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@7b8a96d1, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 00:52:14,914 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 00:52:14,919 INFO L276 IsEmpty]: Start isEmpty. Operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-24 00:52:14,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2024-11-24 00:52:14,927 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:52:14,928 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:52:14,928 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:52:14,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:52:14,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1676994902, now seen corresponding path program 1 times [2024-11-24 00:52:14,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 00:52:14,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1598030534] [2024-11-24 00:52:14,948 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:52:14,949 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:52:14,949 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:52:14,953 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:52:14,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 00:52:15,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:52:15,453 INFO L256 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 19 conjuncts are in the unsatisfiable core [2024-11-24 00:52:15,478 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:52:15,971 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-11-24 00:52:15,971 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:52:16,257 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 00:52:16,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1598030534] [2024-11-24 00:52:16,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1598030534] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:52:16,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1185104354] [2024-11-24 00:52:16,261 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:52:16,261 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 00:52:16,261 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 00:52:16,263 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 00:52:16,265 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (3)] Waiting until timeout for monitored process [2024-11-24 00:52:16,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:52:16,883 INFO L256 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-24 00:52:16,890 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:52:17,039 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-11-24 00:52:17,039 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 00:52:17,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1185104354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:52:17,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 00:52:17,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-11-24 00:52:17,044 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415966592] [2024-11-24 00:52:17,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:52:17,050 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:52:17,050 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 00:52:17,075 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:52:17,075 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:52:17,078 INFO L87 Difference]: Start difference. First operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:52:17,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:52:17,218 INFO L93 Difference]: Finished difference Result 43 states and 63 transitions. [2024-11-24 00:52:17,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:52:17,221 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 23 [2024-11-24 00:52:17,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:52:17,227 INFO L225 Difference]: With dead ends: 43 [2024-11-24 00:52:17,227 INFO L226 Difference]: Without dead ends: 25 [2024-11-24 00:52:17,230 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 00:52:17,235 INFO L435 NwaCegarLoop]: 14 mSDtfsCounter, 0 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:52:17,236 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 38 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:52:17,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2024-11-24 00:52:17,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-11-24 00:52:17,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-24 00:52:17,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 30 transitions. [2024-11-24 00:52:17,285 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 30 transitions. Word has length 23 [2024-11-24 00:52:17,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:52:17,288 INFO L471 AbstractCegarLoop]: Abstraction has 25 states and 30 transitions. [2024-11-24 00:52:17,288 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-11-24 00:52:17,288 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 30 transitions. [2024-11-24 00:52:17,290 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2024-11-24 00:52:17,291 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:52:17,292 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-11-24 00:52:17,298 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (3)] Ended with exit code 0 [2024-11-24 00:52:17,499 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-24 00:52:17,693 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:52:17,693 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:52:17,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:52:17,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1294995197, now seen corresponding path program 1 times [2024-11-24 00:52:17,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 00:52:17,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1006180399] [2024-11-24 00:52:17,695 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:52:17,696 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:52:17,696 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:52:17,700 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:52:17,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 00:52:18,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:52:18,160 INFO L256 TraceCheckSpWp]: Trace formula consists of 486 conjuncts, 43 conjuncts are in the unsatisfiable core [2024-11-24 00:52:18,173 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:52:18,953 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 00:52:18,954 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:52:19,211 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 00:52:19,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1006180399] [2024-11-24 00:52:19,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1006180399] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:52:19,211 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1733017120] [2024-11-24 00:52:19,212 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:52:19,212 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 00:52:19,212 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 00:52:19,216 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 00:52:19,218 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (5)] Waiting until timeout for monitored process [2024-11-24 00:52:20,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:52:20,118 INFO L256 TraceCheckSpWp]: Trace formula consists of 486 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-11-24 00:52:20,130 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:52:20,539 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-11-24 00:52:20,539 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:52:20,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1733017120] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:52:20,737 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 00:52:20,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-11-24 00:52:20,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673748923] [2024-11-24 00:52:20,738 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 00:52:20,738 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-24 00:52:20,738 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 00:52:20,741 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-24 00:52:20,741 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2024-11-24 00:52:20,741 INFO L87 Difference]: Start difference. First operand 25 states and 30 transitions. Second operand has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:52:21,185 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:52:21,185 INFO L93 Difference]: Finished difference Result 36 states and 44 transitions. [2024-11-24 00:52:21,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-11-24 00:52:21,188 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 44 [2024-11-24 00:52:21,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:52:21,190 INFO L225 Difference]: With dead ends: 36 [2024-11-24 00:52:21,191 INFO L226 Difference]: Without dead ends: 34 [2024-11-24 00:52:21,192 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=47, Invalid=193, Unknown=0, NotChecked=0, Total=240 [2024-11-24 00:52:21,194 INFO L435 NwaCegarLoop]: 12 mSDtfsCounter, 7 mSDsluCounter, 64 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 139 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 00:52:21,195 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 76 Invalid, 139 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 00:52:21,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2024-11-24 00:52:21,202 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2024-11-24 00:52:21,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-11-24 00:52:21,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 42 transitions. [2024-11-24 00:52:21,204 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 42 transitions. Word has length 44 [2024-11-24 00:52:21,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:52:21,205 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 42 transitions. [2024-11-24 00:52:21,205 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-11-24 00:52:21,205 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 42 transitions. [2024-11-24 00:52:21,207 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2024-11-24 00:52:21,207 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:52:21,207 INFO L218 NwaCegarLoop]: trace histogram [9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-11-24 00:52:21,219 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-24 00:52:21,418 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (5)] Ended with exit code 0 [2024-11-24 00:52:21,611 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt [2024-11-24 00:52:21,612 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:52:21,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:52:21,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1531864950, now seen corresponding path program 2 times [2024-11-24 00:52:21,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 00:52:21,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1476488761] [2024-11-24 00:52:21,615 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 00:52:21,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:52:21,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:52:21,622 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:52:21,624 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 00:52:22,280 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 00:52:22,281 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 00:52:22,293 INFO L256 TraceCheckSpWp]: Trace formula consists of 710 conjuncts, 126 conjuncts are in the unsatisfiable core [2024-11-24 00:52:22,329 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:52:30,443 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 24 proven. 55 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2024-11-24 00:52:30,443 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:52:36,478 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 00:52:36,478 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1476488761] [2024-11-24 00:52:36,478 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1476488761] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:52:36,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [887197553] [2024-11-24 00:52:36,479 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 00:52:36,479 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 00:52:36,479 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 00:52:36,481 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 00:52:36,482 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (7)] Waiting until timeout for monitored process [2024-11-24 00:52:37,694 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 00:52:37,694 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 00:52:37,727 INFO L256 TraceCheckSpWp]: Trace formula consists of 710 conjuncts, 87 conjuncts are in the unsatisfiable core [2024-11-24 00:52:37,740 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:53:12,143 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 12 proven. 55 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-11-24 00:53:12,144 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:53:20,567 WARN L851 $PredicateComparison]: unable to prove that (let ((.cse6 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|))) (let ((.cse9 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_68~0#1|)) (.cse2 (forall ((|v_ULTIMATE.start_main_~var_110_arg_1~0#1_21| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse6 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_111~0#1|))) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_110_arg_1~0#1_21|))))))))))))))) (let ((.cse5 (and (forall ((|v_ULTIMATE.start_main_~var_74_arg_1~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_2~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_71_arg_1~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_85_arg_1~0#1_21| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse6 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_74_arg_1~0#1_21|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_71_arg_1~0#1_21|) .cse9)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_85_arg_1~0#1_21|))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_2~0#1_21|)))))))) (_ bv0 8))) .cse2)) (.cse3 ((_ zero_extend 16) |c_ULTIMATE.start_main_~state_87~0#1|)) (.cse4 ((_ zero_extend 16) |c_ULTIMATE.start_main_~mask_SORT_3~0#1|))) (let ((.cse7 (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_13~0#1|) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_12~0#1|)))))))) (.cse1 (let ((.cse8 (= .cse3 ((_ zero_extend 16) ((_ extract 15 0) (bvand .cse4 ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |c_ULTIMATE.start_main_~state_55~0#1|))))))))) (and (or .cse8 .cse5) (or (not .cse8) (and .cse2 (forall ((|v_ULTIMATE.start_main_~var_74_arg_1~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_2~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_71_arg_1~0#1_21| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_85_arg_1~0#1_21| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse6 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv1 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_74_arg_1~0#1_21|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_71_arg_1~0#1_21|) .cse9)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_85_arg_1~0#1_21|))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_2~0#1_21|)))))))))))))))) (and (or (let ((.cse0 (= ((_ extract 7 0) (bvand .cse6 (_ bv254 32))) (_ bv0 8)))) (and (or .cse0 .cse1) (or (and (or .cse2 (forall ((|v_ULTIMATE.start_main_~var_58_arg_2~0#1_19| (_ BitVec 16))) (not (= .cse3 ((_ zero_extend 16) ((_ extract 15 0) (bvand .cse4 ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |v_ULTIMATE.start_main_~var_58_arg_2~0#1_19|)))))))))) (or (forall ((|v_ULTIMATE.start_main_~var_58_arg_2~0#1_19| (_ BitVec 16))) (= .cse3 ((_ zero_extend 16) ((_ extract 15 0) (bvand .cse4 ((_ zero_extend 16) ((_ extract 15 0) ((_ zero_extend 16) |v_ULTIMATE.start_main_~var_58_arg_2~0#1_19|)))))))) .cse5)) (not .cse0)))) .cse7) (or (= (_ bv0 8) ((_ extract 7 0) (bvand .cse6 (_ bv255 32)))) (not .cse7) .cse1)))))) is different from false [2024-11-24 00:53:22,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [887197553] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:53:22,101 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 00:53:22,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 12] total 18 [2024-11-24 00:53:22,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206717667] [2024-11-24 00:53:22,101 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 00:53:22,102 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 00:53:22,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 00:53:22,103 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 00:53:22,103 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=54, Invalid=325, Unknown=5, NotChecked=36, Total=420 [2024-11-24 00:53:22,103 INFO L87 Difference]: Start difference. First operand 34 states and 42 transitions. Second operand has 18 states, 14 states have (on average 2.642857142857143) internal successors, (37), 18 states have internal predecessors, (37), 9 states have call successors, (15), 1 states have call predecessors, (15), 2 states have return successors, (15), 7 states have call predecessors, (15), 9 states have call successors, (15) [2024-11-24 00:53:39,565 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.31s for a HTC check with result VALID. Formula has sorts [Bool, BitVec], hasArrays=false, hasNonlinArith=false, quantifiers [0] [2024-11-24 00:55:25,264 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 4.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, BitVec], hasArrays=false, hasNonlinArith=false, quantifiers [0] [2024-11-24 00:55:52,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:55:52,051 INFO L93 Difference]: Finished difference Result 46 states and 57 transitions. [2024-11-24 00:55:52,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2024-11-24 00:55:52,052 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 14 states have (on average 2.642857142857143) internal successors, (37), 18 states have internal predecessors, (37), 9 states have call successors, (15), 1 states have call predecessors, (15), 2 states have return successors, (15), 7 states have call predecessors, (15), 9 states have call successors, (15) Word has length 65 [2024-11-24 00:55:52,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:55:52,053 INFO L225 Difference]: With dead ends: 46 [2024-11-24 00:55:52,053 INFO L226 Difference]: Without dead ends: 44 [2024-11-24 00:55:52,054 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 151 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 162.3s TimeCoverageRelationStatistics Valid=170, Invalid=996, Unknown=28, NotChecked=66, Total=1260 [2024-11-24 00:55:52,055 INFO L435 NwaCegarLoop]: 15 mSDtfsCounter, 16 mSDsluCounter, 121 mSDsCounter, 0 mSdLazyCounter, 317 mSolverCounterSat, 13 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 14.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 136 SdHoareTripleChecker+Invalid, 331 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 317 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 14.9s IncrementalHoareTripleChecker+Time [2024-11-24 00:55:52,055 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 136 Invalid, 331 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 317 Invalid, 1 Unknown, 0 Unchecked, 14.9s Time] [2024-11-24 00:55:52,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2024-11-24 00:55:52,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 43. [2024-11-24 00:55:52,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-24 00:55:52,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 54 transitions. [2024-11-24 00:55:52,076 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 54 transitions. Word has length 65 [2024-11-24 00:55:52,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:55:52,077 INFO L471 AbstractCegarLoop]: Abstraction has 43 states and 54 transitions. [2024-11-24 00:55:52,077 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 14 states have (on average 2.642857142857143) internal successors, (37), 18 states have internal predecessors, (37), 9 states have call successors, (15), 1 states have call predecessors, (15), 2 states have return successors, (15), 7 states have call predecessors, (15), 9 states have call successors, (15) [2024-11-24 00:55:52,077 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 54 transitions. [2024-11-24 00:55:52,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2024-11-24 00:55:52,080 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:55:52,080 INFO L218 NwaCegarLoop]: trace histogram [12, 12, 12, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1] [2024-11-24 00:55:52,088 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (7)] Ended with exit code 0 [2024-11-24 00:55:52,294 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-24 00:55:52,481 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:55:52,481 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:55:52,481 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:55:52,481 INFO L85 PathProgramCache]: Analyzing trace with hash -1616345373, now seen corresponding path program 3 times [2024-11-24 00:55:52,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 00:55:52,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1390499481] [2024-11-24 00:55:52,482 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-24 00:55:52,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:55:52,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:55:52,486 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:55:52,488 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-24 00:55:53,245 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-11-24 00:55:53,246 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 00:55:53,255 INFO L256 TraceCheckSpWp]: Trace formula consists of 885 conjuncts, 229 conjuncts are in the unsatisfiable core [2024-11-24 00:55:53,280 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:58:07,261 WARN L286 SmtUtils]: Spent 6.69s on a formula simplification that was a NOOP. DAG size: 367 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2024-11-24 00:58:22,768 WARN L286 SmtUtils]: Spent 7.02s on a formula simplification that was a NOOP. DAG size: 377 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2024-11-24 00:58:38,067 WARN L286 SmtUtils]: Spent 6.87s on a formula simplification that was a NOOP. DAG size: 370 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2024-11-24 00:59:18,896 INFO L134 CoverageAnalysis]: Checked inductivity of 315 backedges. 45 proven. 111 refuted. 0 times theorem prover too weak. 159 trivial. 0 not checked. [2024-11-24 00:59:18,897 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 01:00:25,350 WARN L286 SmtUtils]: Spent 32.57s on a formula simplification. DAG size of input: 272 DAG size of output: 269 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2024-11-24 01:00:44,651 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 01:00:44,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1390499481] [2024-11-24 01:00:44,651 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1390499481] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 01:00:44,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [950676220] [2024-11-24 01:00:44,652 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-24 01:00:44,652 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 01:00:44,652 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 01:00:44,654 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 01:00:44,655 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f5b227af-eb33-4e1f-91bf-27c43b105da0/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (9)] Waiting until timeout for monitored process [2024-11-24 01:00:46,258 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2024-11-24 01:00:46,258 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 01:00:46,310 INFO L256 TraceCheckSpWp]: Trace formula consists of 885 conjuncts, 230 conjuncts are in the unsatisfiable core [2024-11-24 01:00:46,339 INFO L279 TraceCheckSpWp]: Computing forward predicates...