./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6497de01 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 02:10:54,635 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 02:10:54,723 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-24 02:10:54,729 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 02:10:54,730 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 02:10:54,758 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 02:10:54,759 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 02:10:54,759 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 02:10:54,759 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 02:10:54,760 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 02:10:54,760 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 02:10:54,760 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 02:10:54,760 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 02:10:54,761 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 02:10:54,761 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 02:10:54,762 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:10:54,762 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:10:54,763 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:10:54,763 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 02:10:54,763 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 02:10:54,764 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-11-24 02:10:55,138 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 02:10:55,150 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 02:10:55,156 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 02:10:55,158 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 02:10:55,159 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 02:10:55,162 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:10:58,295 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/04704b6ca/e8c1e6ba0cd94522885a029f732bda1f/FLAG7915c0955 [2024-11-24 02:10:58,794 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 02:10:58,795 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:10:58,819 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/04704b6ca/e8c1e6ba0cd94522885a029f732bda1f/FLAG7915c0955 [2024-11-24 02:10:58,845 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/04704b6ca/e8c1e6ba0cd94522885a029f732bda1f [2024-11-24 02:10:58,848 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 02:10:58,852 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 02:10:58,855 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 02:10:58,855 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 02:10:58,861 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 02:10:58,862 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:10:58" (1/1) ... [2024-11-24 02:10:58,863 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1a79086f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:58, skipping insertion in model container [2024-11-24 02:10:58,866 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:10:58" (1/1) ... [2024-11-24 02:10:58,928 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 02:10:59,181 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-24 02:10:59,601 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:10:59,616 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 02:10:59,636 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-24 02:10:59,862 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:10:59,887 INFO L204 MainTranslator]: Completed translation [2024-11-24 02:10:59,889 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59 WrapperNode [2024-11-24 02:10:59,889 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 02:10:59,890 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 02:10:59,891 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 02:10:59,892 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 02:10:59,906 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:10:59,952 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,361 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2370 [2024-11-24 02:11:00,362 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 02:11:00,363 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 02:11:00,365 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 02:11:00,366 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 02:11:00,379 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,379 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,493 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,650 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-11-24 02:11:00,650 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,651 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,774 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,809 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,874 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,893 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,912 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:00,992 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 02:11:00,995 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 02:11:00,996 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 02:11:00,996 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 02:11:00,997 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (1/1) ... [2024-11-24 02:11:01,004 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:11:01,020 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:01,051 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 02:11:01,062 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 02:11:01,127 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 02:11:01,127 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 02:11:01,127 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 02:11:01,127 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-24 02:11:01,132 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-11-24 02:11:01,132 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 02:11:01,133 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-11-24 02:11:01,133 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-24 02:11:01,631 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 02:11:01,633 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 02:11:05,898 INFO L? ?]: Removed 1283 outVars from TransFormulas that were not future-live. [2024-11-24 02:11:05,899 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 02:11:05,946 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 02:11:05,946 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-24 02:11:05,947 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:11:05 BoogieIcfgContainer [2024-11-24 02:11:05,947 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 02:11:05,949 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 02:11:05,953 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 02:11:05,961 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 02:11:05,961 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 02:10:58" (1/3) ... [2024-11-24 02:11:05,962 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@b3fd599 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:11:05, skipping insertion in model container [2024-11-24 02:11:05,962 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:10:59" (2/3) ... [2024-11-24 02:11:05,963 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@b3fd599 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:11:05, skipping insertion in model container [2024-11-24 02:11:05,963 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:11:05" (3/3) ... [2024-11-24 02:11:05,964 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:11:05,984 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 02:11:05,987 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 752 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-11-24 02:11:06,092 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 02:11:06,110 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@755d024, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 02:11:06,110 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 02:11:06,121 INFO L276 IsEmpty]: Start isEmpty. Operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:11:06,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-11-24 02:11:06,146 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:06,147 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:06,147 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:06,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:06,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1021292254, now seen corresponding path program 1 times [2024-11-24 02:11:06,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:06,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884391152] [2024-11-24 02:11:06,165 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:06,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:06,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:06,998 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-24 02:11:06,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:07,001 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884391152] [2024-11-24 02:11:07,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884391152] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:07,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [586758575] [2024-11-24 02:11:07,003 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:07,003 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:07,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:07,007 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:07,010 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 02:11:07,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:07,839 INFO L256 TraceCheckSpWp]: Trace formula consists of 1101 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-24 02:11:07,859 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:07,913 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-24 02:11:07,916 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:11:07,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [586758575] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:07,917 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:11:07,917 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-24 02:11:07,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141648912] [2024-11-24 02:11:07,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:07,927 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-24 02:11:07,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:07,957 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-24 02:11:07,958 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 02:11:07,962 INFO L87 Difference]: Start difference. First operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:08,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:08,084 INFO L93 Difference]: Finished difference Result 1493 states and 2239 transitions. [2024-11-24 02:11:08,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-24 02:11:08,088 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 241 [2024-11-24 02:11:08,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:08,117 INFO L225 Difference]: With dead ends: 1493 [2024-11-24 02:11:08,118 INFO L226 Difference]: Without dead ends: 749 [2024-11-24 02:11:08,126 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 242 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 02:11:08,132 INFO L435 NwaCegarLoop]: 1113 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1113 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:08,137 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1113 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:08,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states. [2024-11-24 02:11:08,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 749. [2024-11-24 02:11:08,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 749 states, 742 states have (on average 1.486522911051213) internal successors, (1103), 742 states have internal predecessors, (1103), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:11:08,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 749 states to 749 states and 1113 transitions. [2024-11-24 02:11:08,231 INFO L78 Accepts]: Start accepts. Automaton has 749 states and 1113 transitions. Word has length 241 [2024-11-24 02:11:08,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:08,234 INFO L471 AbstractCegarLoop]: Abstraction has 749 states and 1113 transitions. [2024-11-24 02:11:08,235 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:08,235 INFO L276 IsEmpty]: Start isEmpty. Operand 749 states and 1113 transitions. [2024-11-24 02:11:08,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-11-24 02:11:08,249 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:08,250 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:08,268 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-24 02:11:08,450 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-11-24 02:11:08,451 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:08,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:08,452 INFO L85 PathProgramCache]: Analyzing trace with hash 526745560, now seen corresponding path program 1 times [2024-11-24 02:11:08,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:08,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024533147] [2024-11-24 02:11:08,452 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:08,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:08,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:09,980 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:11:09,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:09,981 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024533147] [2024-11-24 02:11:09,981 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024533147] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:09,981 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:09,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:11:09,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451214169] [2024-11-24 02:11:09,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:09,983 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:11:09,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:09,985 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:11:09,985 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:11:09,986 INFO L87 Difference]: Start difference. First operand 749 states and 1113 transitions. Second operand has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:10,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:10,062 INFO L93 Difference]: Finished difference Result 1496 states and 2224 transitions. [2024-11-24 02:11:10,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:11:10,063 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 241 [2024-11-24 02:11:10,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:10,070 INFO L225 Difference]: With dead ends: 1496 [2024-11-24 02:11:10,070 INFO L226 Difference]: Without dead ends: 755 [2024-11-24 02:11:10,072 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:11:10,074 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1108 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2219 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:10,074 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2219 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:10,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2024-11-24 02:11:10,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 750. [2024-11-24 02:11:10,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 750 states, 743 states have (on average 1.4858681022880216) internal successors, (1104), 743 states have internal predecessors, (1104), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:11:10,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 1114 transitions. [2024-11-24 02:11:10,128 INFO L78 Accepts]: Start accepts. Automaton has 750 states and 1114 transitions. Word has length 241 [2024-11-24 02:11:10,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:10,129 INFO L471 AbstractCegarLoop]: Abstraction has 750 states and 1114 transitions. [2024-11-24 02:11:10,129 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:10,130 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1114 transitions. [2024-11-24 02:11:10,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2024-11-24 02:11:10,136 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:10,136 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:10,136 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-24 02:11:10,137 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:10,137 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:10,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1295801430, now seen corresponding path program 1 times [2024-11-24 02:11:10,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:10,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193600067] [2024-11-24 02:11:10,139 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:10,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:10,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:11,038 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:11:11,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:11,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [193600067] [2024-11-24 02:11:11,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [193600067] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:11,041 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1655131164] [2024-11-24 02:11:11,041 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:11,041 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:11,041 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:11,044 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:11,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-24 02:11:11,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:11,740 INFO L256 TraceCheckSpWp]: Trace formula consists of 1112 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-24 02:11:11,752 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:11,807 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:11:11,810 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:11:11,922 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:11:11,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1655131164] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:11,922 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:11:11,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2024-11-24 02:11:11,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1056707053] [2024-11-24 02:11:11,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:11,923 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:11:11,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:11,927 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:11:11,927 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:11,927 INFO L87 Difference]: Start difference. First operand 750 states and 1114 transitions. Second operand has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:11,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:11,990 INFO L93 Difference]: Finished difference Result 1469 states and 2184 transitions. [2024-11-24 02:11:11,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:11:11,992 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 245 [2024-11-24 02:11:11,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:11,996 INFO L225 Difference]: With dead ends: 1469 [2024-11-24 02:11:11,996 INFO L226 Difference]: Without dead ends: 751 [2024-11-24 02:11:11,998 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 492 GetRequests, 488 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:12,000 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1101 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2212 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:12,001 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2212 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:12,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 751 states. [2024-11-24 02:11:12,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 751 to 751. [2024-11-24 02:11:12,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 751 states, 744 states have (on average 1.4852150537634408) internal successors, (1105), 744 states have internal predecessors, (1105), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:11:12,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 751 states and 1115 transitions. [2024-11-24 02:11:12,031 INFO L78 Accepts]: Start accepts. Automaton has 751 states and 1115 transitions. Word has length 245 [2024-11-24 02:11:12,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:12,032 INFO L471 AbstractCegarLoop]: Abstraction has 751 states and 1115 transitions. [2024-11-24 02:11:12,032 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:12,032 INFO L276 IsEmpty]: Start isEmpty. Operand 751 states and 1115 transitions. [2024-11-24 02:11:12,036 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 250 [2024-11-24 02:11:12,037 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:12,037 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:12,052 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-24 02:11:12,237 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:12,238 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:12,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:12,239 INFO L85 PathProgramCache]: Analyzing trace with hash -1377415492, now seen corresponding path program 1 times [2024-11-24 02:11:12,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:12,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1151438199] [2024-11-24 02:11:12,239 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:12,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:12,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:13,088 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:11:13,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:13,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1151438199] [2024-11-24 02:11:13,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1151438199] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:13,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [898167544] [2024-11-24 02:11:13,091 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:13,091 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:13,091 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:13,096 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:13,098 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 02:11:13,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:13,896 INFO L256 TraceCheckSpWp]: Trace formula consists of 1123 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-11-24 02:11:13,906 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:13,969 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:11:13,970 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:11:15,591 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:11:15,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [898167544] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:11:15,592 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:11:15,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 8] total 12 [2024-11-24 02:11:15,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737525771] [2024-11-24 02:11:15,593 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:11:15,594 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-24 02:11:15,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:15,596 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-24 02:11:15,596 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2024-11-24 02:11:15,597 INFO L87 Difference]: Start difference. First operand 751 states and 1115 transitions. Second operand has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:11:18,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:18,813 INFO L93 Difference]: Finished difference Result 2117 states and 3148 transitions. [2024-11-24 02:11:18,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 02:11:18,814 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 249 [2024-11-24 02:11:18,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:18,821 INFO L225 Difference]: With dead ends: 2117 [2024-11-24 02:11:18,821 INFO L226 Difference]: Without dead ends: 1375 [2024-11-24 02:11:18,823 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 501 GetRequests, 490 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:11:18,825 INFO L435 NwaCegarLoop]: 1385 mSDtfsCounter, 2019 mSDsluCounter, 6303 mSDsCounter, 0 mSdLazyCounter, 2637 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2024 SdHoareTripleChecker+Valid, 7688 SdHoareTripleChecker+Invalid, 2638 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2637 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:18,826 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2024 Valid, 7688 Invalid, 2638 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1 Valid, 2637 Invalid, 0 Unknown, 0 Unchecked, 2.9s Time] [2024-11-24 02:11:18,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1375 states. [2024-11-24 02:11:18,870 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1375 to 986. [2024-11-24 02:11:18,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 986 states, 974 states have (on average 1.482546201232033) internal successors, (1444), 974 states have internal predecessors, (1444), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:18,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 986 states to 986 states and 1464 transitions. [2024-11-24 02:11:18,886 INFO L78 Accepts]: Start accepts. Automaton has 986 states and 1464 transitions. Word has length 249 [2024-11-24 02:11:18,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:18,886 INFO L471 AbstractCegarLoop]: Abstraction has 986 states and 1464 transitions. [2024-11-24 02:11:18,887 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:11:18,887 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 1464 transitions. [2024-11-24 02:11:18,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2024-11-24 02:11:18,892 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:18,892 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:18,908 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-24 02:11:19,096 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:19,097 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:19,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:19,098 INFO L85 PathProgramCache]: Analyzing trace with hash 1657948098, now seen corresponding path program 1 times [2024-11-24 02:11:19,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:19,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1249436156] [2024-11-24 02:11:19,098 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:19,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:19,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:19,876 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:11:19,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:19,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1249436156] [2024-11-24 02:11:19,878 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1249436156] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:19,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1373449237] [2024-11-24 02:11:19,879 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:19,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:19,879 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:19,883 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:19,888 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-24 02:11:20,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:20,502 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-24 02:11:20,510 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:20,566 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:11:20,567 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:11:20,653 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-11-24 02:11:20,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1373449237] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:11:20,654 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:11:20,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 6, 4] total 9 [2024-11-24 02:11:20,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067714303] [2024-11-24 02:11:20,654 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:11:20,655 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:11:20,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:20,657 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:11:20,657 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:11:20,657 INFO L87 Difference]: Start difference. First operand 986 states and 1464 transitions. Second operand has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:20,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:20,813 INFO L93 Difference]: Finished difference Result 2004 states and 2978 transitions. [2024-11-24 02:11:20,814 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 02:11:20,814 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 254 [2024-11-24 02:11:20,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:20,819 INFO L225 Difference]: With dead ends: 2004 [2024-11-24 02:11:20,819 INFO L226 Difference]: Without dead ends: 1033 [2024-11-24 02:11:20,821 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 504 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:11:20,823 INFO L435 NwaCegarLoop]: 1121 mSDtfsCounter, 52 mSDsluCounter, 5563 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 52 SdHoareTripleChecker+Valid, 6684 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:20,823 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [52 Valid, 6684 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:11:20,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1033 states. [2024-11-24 02:11:20,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1033 to 1028. [2024-11-24 02:11:20,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1028 states, 1016 states have (on average 1.4763779527559056) internal successors, (1500), 1016 states have internal predecessors, (1500), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:20,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1520 transitions. [2024-11-24 02:11:20,872 INFO L78 Accepts]: Start accepts. Automaton has 1028 states and 1520 transitions. Word has length 254 [2024-11-24 02:11:20,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:20,872 INFO L471 AbstractCegarLoop]: Abstraction has 1028 states and 1520 transitions. [2024-11-24 02:11:20,872 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:20,872 INFO L276 IsEmpty]: Start isEmpty. Operand 1028 states and 1520 transitions. [2024-11-24 02:11:20,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2024-11-24 02:11:20,879 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:20,879 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:20,896 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-24 02:11:21,083 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:21,084 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:21,085 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:21,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1935099494, now seen corresponding path program 2 times [2024-11-24 02:11:21,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:21,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663452110] [2024-11-24 02:11:21,086 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:11:21,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:21,229 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:11:21,230 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:11:22,193 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-11-24 02:11:22,194 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:22,194 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663452110] [2024-11-24 02:11:22,194 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663452110] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:22,194 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:22,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:11:22,195 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838655843] [2024-11-24 02:11:22,195 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:22,196 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:11:22,196 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:22,197 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:11:22,197 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:22,197 INFO L87 Difference]: Start difference. First operand 1028 states and 1520 transitions. Second operand has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:22,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:22,252 INFO L93 Difference]: Finished difference Result 1032 states and 1524 transitions. [2024-11-24 02:11:22,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:22,253 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 270 [2024-11-24 02:11:22,256 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:22,261 INFO L225 Difference]: With dead ends: 1032 [2024-11-24 02:11:22,262 INFO L226 Difference]: Without dead ends: 1030 [2024-11-24 02:11:22,262 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:22,264 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2216 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3327 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:22,264 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3327 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:22,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1030 states. [2024-11-24 02:11:22,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1030 to 1030. [2024-11-24 02:11:22,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1030 states, 1018 states have (on average 1.475442043222004) internal successors, (1502), 1018 states have internal predecessors, (1502), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:22,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1030 states to 1030 states and 1522 transitions. [2024-11-24 02:11:22,310 INFO L78 Accepts]: Start accepts. Automaton has 1030 states and 1522 transitions. Word has length 270 [2024-11-24 02:11:22,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:22,314 INFO L471 AbstractCegarLoop]: Abstraction has 1030 states and 1522 transitions. [2024-11-24 02:11:22,314 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:22,314 INFO L276 IsEmpty]: Start isEmpty. Operand 1030 states and 1522 transitions. [2024-11-24 02:11:22,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 272 [2024-11-24 02:11:22,337 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:22,337 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:22,338 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-24 02:11:22,338 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:22,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:22,339 INFO L85 PathProgramCache]: Analyzing trace with hash -139761292, now seen corresponding path program 1 times [2024-11-24 02:11:22,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:22,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184715956] [2024-11-24 02:11:22,339 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:22,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:22,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:23,060 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-11-24 02:11:23,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:23,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184715956] [2024-11-24 02:11:23,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184715956] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:23,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1221251627] [2024-11-24 02:11:23,061 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:23,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:23,062 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:23,064 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:23,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 02:11:23,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:23,843 INFO L256 TraceCheckSpWp]: Trace formula consists of 1184 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-24 02:11:23,856 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:23,916 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-11-24 02:11:23,917 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:11:24,239 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 13 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:11:24,239 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1221251627] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:11:24,239 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:11:24,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 10] total 15 [2024-11-24 02:11:24,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637321000] [2024-11-24 02:11:24,240 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:11:24,241 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-24 02:11:24,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:24,243 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-24 02:11:24,243 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2024-11-24 02:11:24,244 INFO L87 Difference]: Start difference. First operand 1030 states and 1522 transitions. Second operand has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:24,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:24,575 INFO L93 Difference]: Finished difference Result 2069 states and 3061 transitions. [2024-11-24 02:11:24,575 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 02:11:24,576 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 271 [2024-11-24 02:11:24,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:24,582 INFO L225 Difference]: With dead ends: 2069 [2024-11-24 02:11:24,582 INFO L226 Difference]: Without dead ends: 1060 [2024-11-24 02:11:24,584 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 533 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=84, Invalid=222, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:11:24,585 INFO L435 NwaCegarLoop]: 1129 mSDtfsCounter, 86 mSDsluCounter, 11200 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 86 SdHoareTripleChecker+Valid, 12329 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:24,586 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [86 Valid, 12329 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:11:24,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1060 states. [2024-11-24 02:11:24,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1060 to 1060. [2024-11-24 02:11:24,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1060 states, 1048 states have (on average 1.4713740458015268) internal successors, (1542), 1048 states have internal predecessors, (1542), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:24,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 1060 states and 1562 transitions. [2024-11-24 02:11:24,629 INFO L78 Accepts]: Start accepts. Automaton has 1060 states and 1562 transitions. Word has length 271 [2024-11-24 02:11:24,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:24,630 INFO L471 AbstractCegarLoop]: Abstraction has 1060 states and 1562 transitions. [2024-11-24 02:11:24,631 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:24,631 INFO L276 IsEmpty]: Start isEmpty. Operand 1060 states and 1562 transitions. [2024-11-24 02:11:24,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 292 [2024-11-24 02:11:24,637 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:24,637 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:24,653 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-24 02:11:24,838 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:24,838 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:24,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:24,839 INFO L85 PathProgramCache]: Analyzing trace with hash 439580942, now seen corresponding path program 2 times [2024-11-24 02:11:24,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:24,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094661468] [2024-11-24 02:11:24,840 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:11:24,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:24,964 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:11:24,964 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:11:25,383 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 188 trivial. 0 not checked. [2024-11-24 02:11:25,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:25,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094661468] [2024-11-24 02:11:25,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094661468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:25,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:25,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:11:25,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794780728] [2024-11-24 02:11:25,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:25,385 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:11:25,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:25,386 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:11:25,386 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:25,387 INFO L87 Difference]: Start difference. First operand 1060 states and 1562 transitions. Second operand has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:25,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:25,461 INFO L93 Difference]: Finished difference Result 1717 states and 2538 transitions. [2024-11-24 02:11:25,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:25,462 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 291 [2024-11-24 02:11:25,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:25,469 INFO L225 Difference]: With dead ends: 1717 [2024-11-24 02:11:25,469 INFO L226 Difference]: Without dead ends: 1062 [2024-11-24 02:11:25,471 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:25,471 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2212 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3323 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:25,472 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3323 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:25,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1062 states. [2024-11-24 02:11:25,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1062 to 1062. [2024-11-24 02:11:25,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1062 states, 1050 states have (on average 1.4704761904761905) internal successors, (1544), 1050 states have internal predecessors, (1544), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:25,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1062 states to 1062 states and 1564 transitions. [2024-11-24 02:11:25,513 INFO L78 Accepts]: Start accepts. Automaton has 1062 states and 1564 transitions. Word has length 291 [2024-11-24 02:11:25,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:25,514 INFO L471 AbstractCegarLoop]: Abstraction has 1062 states and 1564 transitions. [2024-11-24 02:11:25,514 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:25,514 INFO L276 IsEmpty]: Start isEmpty. Operand 1062 states and 1564 transitions. [2024-11-24 02:11:25,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2024-11-24 02:11:25,521 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:25,522 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:25,522 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-24 02:11:25,522 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:25,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:25,523 INFO L85 PathProgramCache]: Analyzing trace with hash -355857243, now seen corresponding path program 1 times [2024-11-24 02:11:25,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:25,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136951273] [2024-11-24 02:11:25,523 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:25,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:25,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:26,401 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-24 02:11:26,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:26,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136951273] [2024-11-24 02:11:26,402 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136951273] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:26,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1480569649] [2024-11-24 02:11:26,402 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:26,402 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:26,402 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:26,405 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:26,408 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-24 02:11:27,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:27,152 INFO L256 TraceCheckSpWp]: Trace formula consists of 1242 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-24 02:11:27,160 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:11:27,319 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 124 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2024-11-24 02:11:27,319 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:11:27,543 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-24 02:11:27,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1480569649] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:11:27,544 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:11:27,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-24 02:11:27,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542496033] [2024-11-24 02:11:27,544 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:11:27,545 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 02:11:27,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:27,547 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 02:11:27,547 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:11:27,548 INFO L87 Difference]: Start difference. First operand 1062 states and 1564 transitions. Second operand has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:27,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:27,918 INFO L93 Difference]: Finished difference Result 2053 states and 3038 transitions. [2024-11-24 02:11:27,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-24 02:11:27,919 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 292 [2024-11-24 02:11:27,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:27,925 INFO L225 Difference]: With dead ends: 2053 [2024-11-24 02:11:27,925 INFO L226 Difference]: Without dead ends: 1110 [2024-11-24 02:11:27,927 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 573 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:11:27,927 INFO L435 NwaCegarLoop]: 1157 mSDtfsCounter, 135 mSDsluCounter, 11475 mSDsCounter, 0 mSdLazyCounter, 232 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 135 SdHoareTripleChecker+Valid, 12632 SdHoareTripleChecker+Invalid, 233 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 232 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:27,928 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [135 Valid, 12632 Invalid, 233 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 232 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:27,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-24 02:11:27,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-24 02:11:27,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.46448087431694) internal successors, (1608), 1098 states have internal predecessors, (1608), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:27,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1628 transitions. [2024-11-24 02:11:27,969 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1628 transitions. Word has length 292 [2024-11-24 02:11:27,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:27,969 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1628 transitions. [2024-11-24 02:11:27,970 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:11:27,970 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1628 transitions. [2024-11-24 02:11:27,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2024-11-24 02:11:27,977 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:27,977 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:27,992 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-24 02:11:28,182 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:28,182 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:28,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:28,184 INFO L85 PathProgramCache]: Analyzing trace with hash 1595157741, now seen corresponding path program 2 times [2024-11-24 02:11:28,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:28,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036071626] [2024-11-24 02:11:28,184 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:11:28,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:28,345 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:11:28,346 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:11:28,879 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:28,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:28,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036071626] [2024-11-24 02:11:28,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036071626] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:28,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:28,880 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:11:28,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751900612] [2024-11-24 02:11:28,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:28,883 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:11:28,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:28,884 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:11:28,884 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:28,885 INFO L87 Difference]: Start difference. First operand 1110 states and 1628 transitions. Second operand has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:29,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:29,243 INFO L93 Difference]: Finished difference Result 1767 states and 2603 transitions. [2024-11-24 02:11:29,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:29,245 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 308 [2024-11-24 02:11:29,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:29,251 INFO L225 Difference]: With dead ends: 1767 [2024-11-24 02:11:29,251 INFO L226 Difference]: Without dead ends: 1110 [2024-11-24 02:11:29,254 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:11:29,255 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 955 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 955 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 204 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:29,255 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [955 Valid, 2026 Invalid, 204 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:11:29,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-24 02:11:29,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-24 02:11:29,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4635701275045538) internal successors, (1607), 1098 states have internal predecessors, (1607), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:29,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1627 transitions. [2024-11-24 02:11:29,305 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1627 transitions. Word has length 308 [2024-11-24 02:11:29,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:29,305 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1627 transitions. [2024-11-24 02:11:29,306 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:29,306 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1627 transitions. [2024-11-24 02:11:29,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2024-11-24 02:11:29,312 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:29,312 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:29,312 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-24 02:11:29,313 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:29,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:29,313 INFO L85 PathProgramCache]: Analyzing trace with hash -663449310, now seen corresponding path program 1 times [2024-11-24 02:11:29,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:29,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014695957] [2024-11-24 02:11:29,314 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:29,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:29,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:30,215 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:30,215 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:30,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014695957] [2024-11-24 02:11:30,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014695957] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:30,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:30,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:11:30,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [27932119] [2024-11-24 02:11:30,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:30,217 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:11:30,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:30,218 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:11:30,218 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:11:30,218 INFO L87 Difference]: Start difference. First operand 1110 states and 1627 transitions. Second operand has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:30,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:30,468 INFO L93 Difference]: Finished difference Result 1805 states and 2656 transitions. [2024-11-24 02:11:30,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:11:30,469 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 309 [2024-11-24 02:11:30,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:30,475 INFO L225 Difference]: With dead ends: 1805 [2024-11-24 02:11:30,475 INFO L226 Difference]: Without dead ends: 1110 [2024-11-24 02:11:30,477 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:11:30,478 INFO L435 NwaCegarLoop]: 1100 mSDtfsCounter, 1046 mSDsluCounter, 2118 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1046 SdHoareTripleChecker+Valid, 3218 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:30,479 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1046 Valid, 3218 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:30,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-24 02:11:30,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-24 02:11:30,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4617486338797814) internal successors, (1605), 1098 states have internal predecessors, (1605), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:30,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1625 transitions. [2024-11-24 02:11:30,524 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1625 transitions. Word has length 309 [2024-11-24 02:11:30,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:30,526 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1625 transitions. [2024-11-24 02:11:30,526 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:30,526 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1625 transitions. [2024-11-24 02:11:30,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2024-11-24 02:11:30,533 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:30,533 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:30,533 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-24 02:11:30,534 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:30,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:30,534 INFO L85 PathProgramCache]: Analyzing trace with hash -280266578, now seen corresponding path program 1 times [2024-11-24 02:11:30,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:30,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483649186] [2024-11-24 02:11:30,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:30,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:30,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:31,630 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:31,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:31,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483649186] [2024-11-24 02:11:31,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483649186] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:31,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:31,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:11:31,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487039033] [2024-11-24 02:11:31,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:31,634 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:11:31,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:31,635 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:11:31,635 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:11:31,636 INFO L87 Difference]: Start difference. First operand 1110 states and 1625 transitions. Second operand has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:32,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:32,064 INFO L93 Difference]: Finished difference Result 1773 states and 2606 transitions. [2024-11-24 02:11:32,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:32,065 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 310 [2024-11-24 02:11:32,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:32,072 INFO L225 Difference]: With dead ends: 1773 [2024-11-24 02:11:32,073 INFO L226 Difference]: Without dead ends: 1110 [2024-11-24 02:11:32,074 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:32,076 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 1090 mSDsluCounter, 1023 mSDsCounter, 0 mSdLazyCounter, 200 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1095 SdHoareTripleChecker+Valid, 2035 SdHoareTripleChecker+Invalid, 200 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 200 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:32,076 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1095 Valid, 2035 Invalid, 200 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 200 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:11:32,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-24 02:11:32,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-24 02:11:32,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4599271402550091) internal successors, (1603), 1098 states have internal predecessors, (1603), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:32,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1623 transitions. [2024-11-24 02:11:32,126 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1623 transitions. Word has length 310 [2024-11-24 02:11:32,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:32,127 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1623 transitions. [2024-11-24 02:11:32,128 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:32,128 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1623 transitions. [2024-11-24 02:11:32,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2024-11-24 02:11:32,135 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:32,135 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:32,135 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-11-24 02:11:32,136 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:32,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:32,138 INFO L85 PathProgramCache]: Analyzing trace with hash 260057573, now seen corresponding path program 1 times [2024-11-24 02:11:32,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:32,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86029289] [2024-11-24 02:11:32,138 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:32,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:32,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:33,319 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:33,320 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:33,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86029289] [2024-11-24 02:11:33,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86029289] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:33,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:33,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:11:33,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077219718] [2024-11-24 02:11:33,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:33,321 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:11:33,321 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:33,322 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:11:33,322 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:33,322 INFO L87 Difference]: Start difference. First operand 1110 states and 1623 transitions. Second operand has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:33,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:33,655 INFO L93 Difference]: Finished difference Result 1767 states and 2595 transitions. [2024-11-24 02:11:33,655 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:33,656 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 311 [2024-11-24 02:11:33,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:33,662 INFO L225 Difference]: With dead ends: 1767 [2024-11-24 02:11:33,662 INFO L226 Difference]: Without dead ends: 1110 [2024-11-24 02:11:33,663 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:11:33,665 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 949 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 949 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 198 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:33,666 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [949 Valid, 2026 Invalid, 198 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:11:33,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-24 02:11:33,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-24 02:11:33,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.459016393442623) internal successors, (1602), 1098 states have internal predecessors, (1602), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:33,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1622 transitions. [2024-11-24 02:11:33,712 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1622 transitions. Word has length 311 [2024-11-24 02:11:33,712 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:33,713 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1622 transitions. [2024-11-24 02:11:33,713 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:33,714 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1622 transitions. [2024-11-24 02:11:33,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 313 [2024-11-24 02:11:33,720 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:33,720 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:33,721 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-24 02:11:33,721 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:33,721 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:33,722 INFO L85 PathProgramCache]: Analyzing trace with hash -815635257, now seen corresponding path program 1 times [2024-11-24 02:11:33,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:33,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876547945] [2024-11-24 02:11:33,722 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:33,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:34,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:36,614 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:36,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:36,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876547945] [2024-11-24 02:11:36,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876547945] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:36,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:36,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:11:36,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [452921220] [2024-11-24 02:11:36,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:36,616 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:11:36,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:36,617 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:11:36,617 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:11:36,618 INFO L87 Difference]: Start difference. First operand 1110 states and 1622 transitions. Second operand has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:36,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:36,882 INFO L93 Difference]: Finished difference Result 1879 states and 2758 transitions. [2024-11-24 02:11:36,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:11:36,883 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 312 [2024-11-24 02:11:36,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:36,889 INFO L225 Difference]: With dead ends: 1879 [2024-11-24 02:11:36,889 INFO L226 Difference]: Without dead ends: 1134 [2024-11-24 02:11:36,891 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:11:36,892 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1034 mSDsluCounter, 5381 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1037 SdHoareTripleChecker+Valid, 6469 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:36,893 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1037 Valid, 6469 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:36,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1134 states. [2024-11-24 02:11:36,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1134 to 1128. [2024-11-24 02:11:36,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1128 states, 1116 states have (on average 1.4587813620071686) internal successors, (1628), 1116 states have internal predecessors, (1628), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:36,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 1128 states and 1648 transitions. [2024-11-24 02:11:36,940 INFO L78 Accepts]: Start accepts. Automaton has 1128 states and 1648 transitions. Word has length 312 [2024-11-24 02:11:36,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:36,941 INFO L471 AbstractCegarLoop]: Abstraction has 1128 states and 1648 transitions. [2024-11-24 02:11:36,942 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:36,942 INFO L276 IsEmpty]: Start isEmpty. Operand 1128 states and 1648 transitions. [2024-11-24 02:11:36,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-11-24 02:11:36,945 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:36,946 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:36,946 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-24 02:11:36,946 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:36,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:36,947 INFO L85 PathProgramCache]: Analyzing trace with hash -395838274, now seen corresponding path program 1 times [2024-11-24 02:11:36,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:36,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392961158] [2024-11-24 02:11:36,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:36,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:37,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:37,825 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:37,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:37,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392961158] [2024-11-24 02:11:37,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392961158] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:37,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:37,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:11:37,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [415104676] [2024-11-24 02:11:37,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:37,827 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:11:37,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:37,828 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:11:37,828 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:37,828 INFO L87 Difference]: Start difference. First operand 1128 states and 1648 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:39,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:39,075 INFO L93 Difference]: Finished difference Result 1886 states and 2767 transitions. [2024-11-24 02:11:39,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:11:39,076 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-11-24 02:11:39,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:39,081 INFO L225 Difference]: With dead ends: 1886 [2024-11-24 02:11:39,082 INFO L226 Difference]: Without dead ends: 1136 [2024-11-24 02:11:39,083 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:39,084 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1024 mSDsluCounter, 2423 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1027 SdHoareTripleChecker+Valid, 3239 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:39,084 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1027 Valid, 3239 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-11-24 02:11:39,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-11-24 02:11:39,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1132. [2024-11-24 02:11:39,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1132 states, 1120 states have (on average 1.457142857142857) internal successors, (1632), 1120 states have internal predecessors, (1632), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:39,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1652 transitions. [2024-11-24 02:11:39,131 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1652 transitions. Word has length 313 [2024-11-24 02:11:39,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:39,133 INFO L471 AbstractCegarLoop]: Abstraction has 1132 states and 1652 transitions. [2024-11-24 02:11:39,133 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:39,133 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1652 transitions. [2024-11-24 02:11:39,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-11-24 02:11:39,137 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:39,138 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:39,138 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-24 02:11:39,138 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:39,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:39,139 INFO L85 PathProgramCache]: Analyzing trace with hash -257926317, now seen corresponding path program 1 times [2024-11-24 02:11:39,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:39,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355121739] [2024-11-24 02:11:39,139 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:39,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:39,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:39,971 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:39,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:39,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355121739] [2024-11-24 02:11:39,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355121739] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:39,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:39,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:11:39,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694446310] [2024-11-24 02:11:39,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:39,973 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:11:39,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:39,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:11:39,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:39,976 INFO L87 Difference]: Start difference. First operand 1132 states and 1652 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:41,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:41,157 INFO L93 Difference]: Finished difference Result 1908 states and 2796 transitions. [2024-11-24 02:11:41,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:11:41,158 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-11-24 02:11:41,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:41,165 INFO L225 Difference]: With dead ends: 1908 [2024-11-24 02:11:41,166 INFO L226 Difference]: Without dead ends: 1136 [2024-11-24 02:11:41,167 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:11:41,169 INFO L435 NwaCegarLoop]: 818 mSDtfsCounter, 1030 mSDsluCounter, 2426 mSDsCounter, 0 mSdLazyCounter, 1180 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1033 SdHoareTripleChecker+Valid, 3244 SdHoareTripleChecker+Invalid, 1182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:41,169 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1033 Valid, 3244 Invalid, 1182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1180 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-24 02:11:41,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-11-24 02:11:41,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1136. [2024-11-24 02:11:41,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1124 states have (on average 1.4555160142348755) internal successors, (1636), 1124 states have internal predecessors, (1636), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:41,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1656 transitions. [2024-11-24 02:11:41,216 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1656 transitions. Word has length 313 [2024-11-24 02:11:41,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:41,217 INFO L471 AbstractCegarLoop]: Abstraction has 1136 states and 1656 transitions. [2024-11-24 02:11:41,217 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:41,218 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1656 transitions. [2024-11-24 02:11:41,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2024-11-24 02:11:41,221 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:41,222 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:41,222 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-11-24 02:11:41,222 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:41,223 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:41,223 INFO L85 PathProgramCache]: Analyzing trace with hash 1921876768, now seen corresponding path program 1 times [2024-11-24 02:11:41,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:41,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1490375424] [2024-11-24 02:11:41,223 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:41,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:41,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:42,885 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:42,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:42,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1490375424] [2024-11-24 02:11:42,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1490375424] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:42,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:42,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:11:42,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [793665118] [2024-11-24 02:11:42,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:42,887 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:11:42,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:42,889 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:11:42,889 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:42,890 INFO L87 Difference]: Start difference. First operand 1136 states and 1656 transitions. Second operand has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:44,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:44,437 INFO L93 Difference]: Finished difference Result 2363 states and 3467 transitions. [2024-11-24 02:11:44,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:11:44,438 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 314 [2024-11-24 02:11:44,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:44,446 INFO L225 Difference]: With dead ends: 2363 [2024-11-24 02:11:44,446 INFO L226 Difference]: Without dead ends: 1693 [2024-11-24 02:11:44,448 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:11:44,448 INFO L435 NwaCegarLoop]: 809 mSDtfsCounter, 2525 mSDsluCounter, 2343 mSDsCounter, 0 mSdLazyCounter, 1165 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2530 SdHoareTripleChecker+Valid, 3152 SdHoareTripleChecker+Invalid, 1168 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1165 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:44,449 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2530 Valid, 3152 Invalid, 1168 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1165 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-24 02:11:44,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2024-11-24 02:11:44,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 1022. [2024-11-24 02:11:44,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1022 states, 1010 states have (on average 1.4584158415841584) internal successors, (1473), 1010 states have internal predecessors, (1473), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:44,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 1493 transitions. [2024-11-24 02:11:44,510 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 1493 transitions. Word has length 314 [2024-11-24 02:11:44,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:44,514 INFO L471 AbstractCegarLoop]: Abstraction has 1022 states and 1493 transitions. [2024-11-24 02:11:44,515 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:44,515 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 1493 transitions. [2024-11-24 02:11:44,517 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 316 [2024-11-24 02:11:44,517 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:44,518 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:44,518 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-11-24 02:11:44,518 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:44,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:44,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1323386401, now seen corresponding path program 1 times [2024-11-24 02:11:44,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:44,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73521250] [2024-11-24 02:11:44,523 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:44,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:44,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:46,673 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:46,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:46,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73521250] [2024-11-24 02:11:46,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73521250] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:46,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:46,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:11:46,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1634852010] [2024-11-24 02:11:46,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:46,675 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:11:46,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:46,676 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:11:46,677 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:11:46,677 INFO L87 Difference]: Start difference. First operand 1022 states and 1493 transitions. Second operand has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:46,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:46,934 INFO L93 Difference]: Finished difference Result 1767 states and 2590 transitions. [2024-11-24 02:11:46,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:11:46,935 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 315 [2024-11-24 02:11:46,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:46,940 INFO L225 Difference]: With dead ends: 1767 [2024-11-24 02:11:46,940 INFO L226 Difference]: Without dead ends: 1046 [2024-11-24 02:11:46,942 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:11:46,943 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1010 mSDsluCounter, 5390 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1012 SdHoareTripleChecker+Valid, 6478 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:46,943 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1012 Valid, 6478 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:46,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1046 states. [2024-11-24 02:11:46,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1046 to 1040. [2024-11-24 02:11:46,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1040 states, 1028 states have (on average 1.4581712062256809) internal successors, (1499), 1028 states have internal predecessors, (1499), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:46,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1519 transitions. [2024-11-24 02:11:46,999 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1519 transitions. Word has length 315 [2024-11-24 02:11:47,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:47,000 INFO L471 AbstractCegarLoop]: Abstraction has 1040 states and 1519 transitions. [2024-11-24 02:11:47,001 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:47,002 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1519 transitions. [2024-11-24 02:11:47,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-24 02:11:47,004 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:47,005 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:47,005 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-11-24 02:11:47,005 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:47,006 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:47,007 INFO L85 PathProgramCache]: Analyzing trace with hash 1658628649, now seen corresponding path program 1 times [2024-11-24 02:11:47,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:47,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899221424] [2024-11-24 02:11:47,007 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:47,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:47,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:47,730 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:47,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:47,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899221424] [2024-11-24 02:11:47,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899221424] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:47,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:47,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:11:47,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749525660] [2024-11-24 02:11:47,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:47,732 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:11:47,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:47,733 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:11:47,733 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:47,734 INFO L87 Difference]: Start difference. First operand 1040 states and 1519 transitions. Second operand has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 02:11:48,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:48,910 INFO L93 Difference]: Finished difference Result 1774 states and 2599 transitions. [2024-11-24 02:11:48,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:11:48,910 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 316 [2024-11-24 02:11:48,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:48,915 INFO L225 Difference]: With dead ends: 1774 [2024-11-24 02:11:48,916 INFO L226 Difference]: Without dead ends: 1048 [2024-11-24 02:11:48,918 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:48,919 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1071 mSDsluCounter, 2414 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 3230 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:48,919 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 3230 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-24 02:11:48,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1048 states. [2024-11-24 02:11:48,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1048 to 1044. [2024-11-24 02:11:48,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1044 states, 1032 states have (on average 1.4563953488372092) internal successors, (1503), 1032 states have internal predecessors, (1503), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:48,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1044 states to 1044 states and 1523 transitions. [2024-11-24 02:11:48,961 INFO L78 Accepts]: Start accepts. Automaton has 1044 states and 1523 transitions. Word has length 316 [2024-11-24 02:11:48,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:48,962 INFO L471 AbstractCegarLoop]: Abstraction has 1044 states and 1523 transitions. [2024-11-24 02:11:48,962 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-24 02:11:48,962 INFO L276 IsEmpty]: Start isEmpty. Operand 1044 states and 1523 transitions. [2024-11-24 02:11:48,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-24 02:11:48,965 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:48,965 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:48,965 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-11-24 02:11:48,966 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:48,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:48,966 INFO L85 PathProgramCache]: Analyzing trace with hash 874653310, now seen corresponding path program 1 times [2024-11-24 02:11:48,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:48,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971469428] [2024-11-24 02:11:48,967 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:48,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:49,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:50,838 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:50,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:50,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971469428] [2024-11-24 02:11:50,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971469428] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:50,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:50,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:11:50,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724646435] [2024-11-24 02:11:50,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:50,840 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:11:50,840 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:50,841 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:11:50,841 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:11:50,842 INFO L87 Difference]: Start difference. First operand 1044 states and 1523 transitions. Second operand has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:51,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:51,062 INFO L93 Difference]: Finished difference Result 1859 states and 2719 transitions. [2024-11-24 02:11:51,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:11:51,062 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-11-24 02:11:51,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:51,067 INFO L225 Difference]: With dead ends: 1859 [2024-11-24 02:11:51,067 INFO L226 Difference]: Without dead ends: 1070 [2024-11-24 02:11:51,069 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:11:51,069 INFO L435 NwaCegarLoop]: 1089 mSDtfsCounter, 1022 mSDsluCounter, 4311 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1025 SdHoareTripleChecker+Valid, 5400 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:51,069 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1025 Valid, 5400 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:51,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1070 states. [2024-11-24 02:11:51,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1070 to 1050. [2024-11-24 02:11:51,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1050 states, 1038 states have (on average 1.4556840077071291) internal successors, (1511), 1038 states have internal predecessors, (1511), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:51,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1050 states to 1050 states and 1531 transitions. [2024-11-24 02:11:51,112 INFO L78 Accepts]: Start accepts. Automaton has 1050 states and 1531 transitions. Word has length 316 [2024-11-24 02:11:51,113 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:51,113 INFO L471 AbstractCegarLoop]: Abstraction has 1050 states and 1531 transitions. [2024-11-24 02:11:51,114 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:51,114 INFO L276 IsEmpty]: Start isEmpty. Operand 1050 states and 1531 transitions. [2024-11-24 02:11:51,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-24 02:11:51,117 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:51,117 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:51,117 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-11-24 02:11:51,117 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:51,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:51,119 INFO L85 PathProgramCache]: Analyzing trace with hash 2027061502, now seen corresponding path program 1 times [2024-11-24 02:11:51,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:51,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535245332] [2024-11-24 02:11:51,119 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:51,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:51,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:52,190 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:52,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:52,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535245332] [2024-11-24 02:11:52,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535245332] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:52,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:52,191 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:11:52,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1940884422] [2024-11-24 02:11:52,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:52,192 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:11:52,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:52,193 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:11:52,194 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:11:52,194 INFO L87 Difference]: Start difference. First operand 1050 states and 1531 transitions. Second operand has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:52,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:52,282 INFO L93 Difference]: Finished difference Result 1830 states and 2678 transitions. [2024-11-24 02:11:52,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:11:52,283 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-11-24 02:11:52,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:52,288 INFO L225 Difference]: With dead ends: 1830 [2024-11-24 02:11:52,288 INFO L226 Difference]: Without dead ends: 1046 [2024-11-24 02:11:52,289 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:11:52,290 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1010 mSDsluCounter, 1100 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1013 SdHoareTripleChecker+Valid, 2193 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:52,291 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1013 Valid, 2193 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:52,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1046 states. [2024-11-24 02:11:52,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1046 to 1046. [2024-11-24 02:11:52,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1046 states, 1034 states have (on average 1.4555125725338491) internal successors, (1505), 1034 states have internal predecessors, (1505), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:52,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1046 states to 1046 states and 1525 transitions. [2024-11-24 02:11:52,326 INFO L78 Accepts]: Start accepts. Automaton has 1046 states and 1525 transitions. Word has length 316 [2024-11-24 02:11:52,326 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:52,326 INFO L471 AbstractCegarLoop]: Abstraction has 1046 states and 1525 transitions. [2024-11-24 02:11:52,327 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:52,327 INFO L276 IsEmpty]: Start isEmpty. Operand 1046 states and 1525 transitions. [2024-11-24 02:11:52,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-24 02:11:52,329 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:52,330 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:52,330 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-11-24 02:11:52,330 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:52,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:52,331 INFO L85 PathProgramCache]: Analyzing trace with hash -657479526, now seen corresponding path program 1 times [2024-11-24 02:11:52,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:52,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281461046] [2024-11-24 02:11:52,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:52,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:52,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:53,933 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:53,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:53,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281461046] [2024-11-24 02:11:53,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281461046] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:53,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:53,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:11:53,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752099357] [2024-11-24 02:11:53,934 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:53,935 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:11:53,935 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:53,936 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:11:53,936 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:11:53,936 INFO L87 Difference]: Start difference. First operand 1046 states and 1525 transitions. Second operand has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:54,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:54,152 INFO L93 Difference]: Finished difference Result 1813 states and 2650 transitions. [2024-11-24 02:11:54,152 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:11:54,153 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-11-24 02:11:54,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:54,157 INFO L225 Difference]: With dead ends: 1813 [2024-11-24 02:11:54,158 INFO L226 Difference]: Without dead ends: 1072 [2024-11-24 02:11:54,159 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:11:54,162 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1001 mSDsluCounter, 4316 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1003 SdHoareTripleChecker+Valid, 5404 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:54,162 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1003 Valid, 5404 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:11:54,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1072 states. [2024-11-24 02:11:54,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1072 to 1052. [2024-11-24 02:11:54,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1052 states, 1040 states have (on average 1.4548076923076922) internal successors, (1513), 1040 states have internal predecessors, (1513), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:54,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1052 states to 1052 states and 1533 transitions. [2024-11-24 02:11:54,199 INFO L78 Accepts]: Start accepts. Automaton has 1052 states and 1533 transitions. Word has length 316 [2024-11-24 02:11:54,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:54,200 INFO L471 AbstractCegarLoop]: Abstraction has 1052 states and 1533 transitions. [2024-11-24 02:11:54,200 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:11:54,200 INFO L276 IsEmpty]: Start isEmpty. Operand 1052 states and 1533 transitions. [2024-11-24 02:11:54,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 318 [2024-11-24 02:11:54,203 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:54,204 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:54,204 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-11-24 02:11:54,204 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:54,205 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:54,205 INFO L85 PathProgramCache]: Analyzing trace with hash 1689075490, now seen corresponding path program 1 times [2024-11-24 02:11:54,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:54,205 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103731351] [2024-11-24 02:11:54,205 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:54,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:54,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:55,985 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-24 02:11:55,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:55,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [103731351] [2024-11-24 02:11:55,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [103731351] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:55,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:55,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:11:55,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909778061] [2024-11-24 02:11:55,986 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:55,987 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:11:55,987 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:55,988 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:11:55,988 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:11:55,988 INFO L87 Difference]: Start difference. First operand 1052 states and 1533 transitions. Second operand has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:56,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:56,215 INFO L93 Difference]: Finished difference Result 1908 states and 2795 transitions. [2024-11-24 02:11:56,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:11:56,216 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 317 [2024-11-24 02:11:56,217 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:56,224 INFO L225 Difference]: With dead ends: 1908 [2024-11-24 02:11:56,224 INFO L226 Difference]: Without dead ends: 1223 [2024-11-24 02:11:56,225 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:11:56,226 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 1815 mSDsluCounter, 3267 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1820 SdHoareTripleChecker+Valid, 4358 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:56,230 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1820 Valid, 4358 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:11:56,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-11-24 02:11:56,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-11-24 02:11:56,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.458298926507019) internal successors, (1766), 1211 states have internal predecessors, (1766), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:56,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1786 transitions. [2024-11-24 02:11:56,274 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1786 transitions. Word has length 317 [2024-11-24 02:11:56,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:56,275 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1786 transitions. [2024-11-24 02:11:56,275 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.833333333333336) internal successors, (239), 6 states have internal predecessors, (239), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:11:56,275 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1786 transitions. [2024-11-24 02:11:56,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2024-11-24 02:11:56,283 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:56,284 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:56,284 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-11-24 02:11:56,284 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:56,285 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:56,286 INFO L85 PathProgramCache]: Analyzing trace with hash -1448692047, now seen corresponding path program 1 times [2024-11-24 02:11:56,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:56,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1784045499] [2024-11-24 02:11:56,286 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:56,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:56,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:57,697 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:11:57,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:57,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1784045499] [2024-11-24 02:11:57,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1784045499] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:11:57,698 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:11:57,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:11:57,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143409053] [2024-11-24 02:11:57,699 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:11:57,699 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:11:57,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:11:57,701 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:11:57,701 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:11:57,702 INFO L87 Difference]: Start difference. First operand 1223 states and 1786 transitions. Second operand has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:11:57,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:11:57,745 INFO L93 Difference]: Finished difference Result 1910 states and 2797 transitions. [2024-11-24 02:11:57,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:11:57,747 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 678 [2024-11-24 02:11:57,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:11:57,755 INFO L225 Difference]: With dead ends: 1910 [2024-11-24 02:11:57,756 INFO L226 Difference]: Without dead ends: 1225 [2024-11-24 02:11:57,760 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:11:57,761 INFO L435 NwaCegarLoop]: 1106 mSDtfsCounter, 1 mSDsluCounter, 1102 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2208 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:11:57,762 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2208 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:11:57,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1225 states. [2024-11-24 02:11:57,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1225 to 1224. [2024-11-24 02:11:57,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1224 states, 1212 states have (on average 1.4579207920792079) internal successors, (1767), 1212 states have internal predecessors, (1767), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:11:57,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1224 states to 1224 states and 1787 transitions. [2024-11-24 02:11:57,804 INFO L78 Accepts]: Start accepts. Automaton has 1224 states and 1787 transitions. Word has length 678 [2024-11-24 02:11:57,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:11:57,805 INFO L471 AbstractCegarLoop]: Abstraction has 1224 states and 1787 transitions. [2024-11-24 02:11:57,805 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 191.66666666666666) internal successors, (575), 3 states have internal predecessors, (575), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:11:57,806 INFO L276 IsEmpty]: Start isEmpty. Operand 1224 states and 1787 transitions. [2024-11-24 02:11:57,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 681 [2024-11-24 02:11:57,813 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:11:57,814 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:11:57,815 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2024-11-24 02:11:57,815 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:11:57,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:11:57,816 INFO L85 PathProgramCache]: Analyzing trace with hash 1803025741, now seen corresponding path program 1 times [2024-11-24 02:11:57,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:11:57,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285978850] [2024-11-24 02:11:57,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:57,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:11:58,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:11:59,540 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:11:59,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:11:59,540 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [285978850] [2024-11-24 02:11:59,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [285978850] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:11:59,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [85192740] [2024-11-24 02:11:59,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:11:59,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:11:59,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:11:59,544 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:11:59,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-24 02:12:01,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:01,104 INFO L256 TraceCheckSpWp]: Trace formula consists of 3370 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-24 02:12:01,118 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:02,528 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-24 02:12:02,528 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:12:02,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [85192740] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:12:02,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:12:02,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-24 02:12:02,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [487706978] [2024-11-24 02:12:02,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:02,530 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:12:02,530 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:02,531 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:12:02,531 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:12:02,532 INFO L87 Difference]: Start difference. First operand 1224 states and 1787 transitions. Second operand has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:03,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:03,306 INFO L93 Difference]: Finished difference Result 1909 states and 2795 transitions. [2024-11-24 02:12:03,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:03,307 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 680 [2024-11-24 02:12:03,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:03,316 INFO L225 Difference]: With dead ends: 1909 [2024-11-24 02:12:03,316 INFO L226 Difference]: Without dead ends: 1223 [2024-11-24 02:12:03,319 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 684 GetRequests, 679 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:03,319 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 830 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 601 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 830 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 602 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 601 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:03,320 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [830 Valid, 1616 Invalid, 602 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 601 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 02:12:03,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-11-24 02:12:03,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-11-24 02:12:03,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.4566473988439306) internal successors, (1764), 1211 states have internal predecessors, (1764), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:03,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1784 transitions. [2024-11-24 02:12:03,362 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1784 transitions. Word has length 680 [2024-11-24 02:12:03,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:03,363 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1784 transitions. [2024-11-24 02:12:03,364 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:03,364 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1784 transitions. [2024-11-24 02:12:03,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 682 [2024-11-24 02:12:03,371 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:03,371 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:03,393 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-24 02:12:03,572 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2024-11-24 02:12:03,573 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:03,573 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:03,573 INFO L85 PathProgramCache]: Analyzing trace with hash 1248578247, now seen corresponding path program 1 times [2024-11-24 02:12:03,573 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:03,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381383340] [2024-11-24 02:12:03,574 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:03,574 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:04,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:05,032 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:05,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:05,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381383340] [2024-11-24 02:12:05,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381383340] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:05,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1276539683] [2024-11-24 02:12:05,033 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:05,033 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:05,033 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:05,035 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:05,038 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-24 02:12:06,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:06,659 INFO L256 TraceCheckSpWp]: Trace formula consists of 3373 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-24 02:12:06,671 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:07,986 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-24 02:12:07,987 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:12:07,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1276539683] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:12:07,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:12:07,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-24 02:12:07,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288706427] [2024-11-24 02:12:07,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:07,989 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:12:07,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:07,990 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:12:07,990 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:12:07,990 INFO L87 Difference]: Start difference. First operand 1223 states and 1784 transitions. Second operand has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:08,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:08,609 INFO L93 Difference]: Finished difference Result 1907 states and 2789 transitions. [2024-11-24 02:12:08,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:08,610 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 681 [2024-11-24 02:12:08,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:08,613 INFO L225 Difference]: With dead ends: 1907 [2024-11-24 02:12:08,613 INFO L226 Difference]: Without dead ends: 1222 [2024-11-24 02:12:08,614 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 685 GetRequests, 680 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:08,615 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 822 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 595 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 822 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 596 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 595 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:08,615 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [822 Valid, 1616 Invalid, 596 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 595 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 02:12:08,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states. [2024-11-24 02:12:08,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-24 02:12:08,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4553719008264463) internal successors, (1761), 1210 states have internal predecessors, (1761), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:08,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1781 transitions. [2024-11-24 02:12:08,656 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1781 transitions. Word has length 681 [2024-11-24 02:12:08,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:08,656 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1781 transitions. [2024-11-24 02:12:08,657 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.25) internal successors, (581), 4 states have internal predecessors, (581), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:08,657 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1781 transitions. [2024-11-24 02:12:08,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2024-11-24 02:12:08,664 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:08,665 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:08,686 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-24 02:12:08,865 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:08,868 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:08,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:08,869 INFO L85 PathProgramCache]: Analyzing trace with hash -454481253, now seen corresponding path program 1 times [2024-11-24 02:12:08,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:08,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10119017] [2024-11-24 02:12:08,869 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:08,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:09,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:10,305 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:10,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:10,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10119017] [2024-11-24 02:12:10,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10119017] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:10,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1852535243] [2024-11-24 02:12:10,305 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:10,306 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:10,306 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:10,308 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:10,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-24 02:12:11,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:11,890 INFO L256 TraceCheckSpWp]: Trace formula consists of 3376 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-24 02:12:11,902 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:13,225 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-24 02:12:13,226 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:12:13,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1852535243] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:12:13,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:12:13,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-24 02:12:13,226 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2031301958] [2024-11-24 02:12:13,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:13,227 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:12:13,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:13,228 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:12:13,228 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:12:13,229 INFO L87 Difference]: Start difference. First operand 1222 states and 1781 transitions. Second operand has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:13,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:13,842 INFO L93 Difference]: Finished difference Result 1905 states and 2783 transitions. [2024-11-24 02:12:13,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:13,843 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 682 [2024-11-24 02:12:13,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:13,847 INFO L225 Difference]: With dead ends: 1905 [2024-11-24 02:12:13,847 INFO L226 Difference]: Without dead ends: 1221 [2024-11-24 02:12:13,848 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 686 GetRequests, 681 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:13,849 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 808 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 589 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 808 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 590 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 589 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:13,850 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [808 Valid, 1616 Invalid, 590 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 589 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-24 02:12:13,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-24 02:12:13,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-24 02:12:13,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4540942928039702) internal successors, (1758), 1209 states have internal predecessors, (1758), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:13,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1778 transitions. [2024-11-24 02:12:13,888 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1778 transitions. Word has length 682 [2024-11-24 02:12:13,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:13,889 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1778 transitions. [2024-11-24 02:12:13,889 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.5) internal successors, (582), 4 states have internal predecessors, (582), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:13,890 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1778 transitions. [2024-11-24 02:12:13,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 684 [2024-11-24 02:12:13,897 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:13,897 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:13,918 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-24 02:12:14,098 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2024-11-24 02:12:14,098 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:14,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:14,099 INFO L85 PathProgramCache]: Analyzing trace with hash -725772091, now seen corresponding path program 1 times [2024-11-24 02:12:14,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:14,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521079756] [2024-11-24 02:12:14,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:14,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:14,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:15,543 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:15,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:15,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521079756] [2024-11-24 02:12:15,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521079756] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:15,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1400777373] [2024-11-24 02:12:15,544 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:15,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:15,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:15,546 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:15,551 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-24 02:12:17,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:17,248 INFO L256 TraceCheckSpWp]: Trace formula consists of 3379 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-24 02:12:17,264 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:18,554 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-24 02:12:18,554 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:19,640 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:19,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1400777373] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:19,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:19,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-24 02:12:19,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026540364] [2024-11-24 02:12:19,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:19,643 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:12:19,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:19,644 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:12:19,645 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-24 02:12:19,645 INFO L87 Difference]: Start difference. First operand 1221 states and 1778 transitions. Second operand has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:20,034 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:20,035 INFO L93 Difference]: Finished difference Result 1904 states and 2778 transitions. [2024-11-24 02:12:20,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:20,036 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 683 [2024-11-24 02:12:20,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:20,040 INFO L225 Difference]: With dead ends: 1904 [2024-11-24 02:12:20,041 INFO L226 Difference]: Without dead ends: 1221 [2024-11-24 02:12:20,042 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1369 GetRequests, 1351 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:12:20,043 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 915 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 196 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 920 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 197 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 196 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:20,043 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [920 Valid, 2015 Invalid, 197 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 196 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:12:20,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-24 02:12:20,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-24 02:12:20,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4532671629445824) internal successors, (1757), 1209 states have internal predecessors, (1757), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:20,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1777 transitions. [2024-11-24 02:12:20,110 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1777 transitions. Word has length 683 [2024-11-24 02:12:20,111 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:20,111 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1777 transitions. [2024-11-24 02:12:20,112 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:20,112 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1777 transitions. [2024-11-24 02:12:20,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2024-11-24 02:12:20,125 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:20,125 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:20,147 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-24 02:12:20,326 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2024-11-24 02:12:20,327 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:20,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:20,328 INFO L85 PathProgramCache]: Analyzing trace with hash -187341309, now seen corresponding path program 1 times [2024-11-24 02:12:20,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:20,328 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515375646] [2024-11-24 02:12:20,328 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:20,328 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:21,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:21,812 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:21,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:21,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1515375646] [2024-11-24 02:12:21,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1515375646] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:21,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [237530062] [2024-11-24 02:12:21,813 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:21,813 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:21,813 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:21,816 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:21,819 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-24 02:12:23,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:23,562 INFO L256 TraceCheckSpWp]: Trace formula consists of 3382 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-24 02:12:23,572 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:24,948 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-24 02:12:24,949 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:26,090 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:26,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [237530062] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:26,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:26,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-24 02:12:26,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615419002] [2024-11-24 02:12:26,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:26,092 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:12:26,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:26,093 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:12:26,093 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-24 02:12:26,093 INFO L87 Difference]: Start difference. First operand 1221 states and 1777 transitions. Second operand has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:26,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:26,350 INFO L93 Difference]: Finished difference Result 1904 states and 2776 transitions. [2024-11-24 02:12:26,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:26,353 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 684 [2024-11-24 02:12:26,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:26,356 INFO L225 Difference]: With dead ends: 1904 [2024-11-24 02:12:26,357 INFO L226 Difference]: Without dead ends: 1221 [2024-11-24 02:12:26,358 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1371 GetRequests, 1353 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:12:26,359 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1803 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 194 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1808 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 201 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:26,362 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1808 Valid, 2006 Invalid, 201 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 194 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:12:26,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-24 02:12:26,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-24 02:12:26,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4524400330851943) internal successors, (1756), 1209 states have internal predecessors, (1756), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:26,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1776 transitions. [2024-11-24 02:12:26,408 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1776 transitions. Word has length 684 [2024-11-24 02:12:26,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:26,409 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1776 transitions. [2024-11-24 02:12:26,409 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:26,409 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1776 transitions. [2024-11-24 02:12:26,416 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 686 [2024-11-24 02:12:26,416 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:26,417 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:26,438 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-24 02:12:26,617 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2024-11-24 02:12:26,618 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:26,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:26,620 INFO L85 PathProgramCache]: Analyzing trace with hash -1903378360, now seen corresponding path program 1 times [2024-11-24 02:12:26,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:26,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065827883] [2024-11-24 02:12:26,620 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:26,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:27,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:27,836 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:27,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:27,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065827883] [2024-11-24 02:12:27,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065827883] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:27,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [608924049] [2024-11-24 02:12:27,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:27,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:27,837 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:27,839 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:27,842 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-24 02:12:29,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:29,658 INFO L256 TraceCheckSpWp]: Trace formula consists of 3385 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-24 02:12:29,671 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:31,009 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-24 02:12:31,009 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:32,247 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:32,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [608924049] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:32,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:32,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-24 02:12:32,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308274444] [2024-11-24 02:12:32,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:32,249 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:12:32,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:32,249 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:12:32,249 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-24 02:12:32,250 INFO L87 Difference]: Start difference. First operand 1221 states and 1776 transitions. Second operand has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:32,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:32,497 INFO L93 Difference]: Finished difference Result 1904 states and 2774 transitions. [2024-11-24 02:12:32,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:32,498 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 685 [2024-11-24 02:12:32,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:32,501 INFO L225 Difference]: With dead ends: 1904 [2024-11-24 02:12:32,501 INFO L226 Difference]: Without dead ends: 1221 [2024-11-24 02:12:32,503 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1373 GetRequests, 1355 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:12:32,504 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 897 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 192 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 902 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 193 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 192 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:32,504 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [902 Valid, 2015 Invalid, 193 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 192 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:12:32,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-24 02:12:32,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-24 02:12:32,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4516129032258065) internal successors, (1755), 1209 states have internal predecessors, (1755), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:32,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1775 transitions. [2024-11-24 02:12:32,538 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1775 transitions. Word has length 685 [2024-11-24 02:12:32,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:32,538 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1775 transitions. [2024-11-24 02:12:32,539 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.4) internal successors, (582), 5 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:32,539 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1775 transitions. [2024-11-24 02:12:32,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 687 [2024-11-24 02:12:32,545 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:32,546 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:32,567 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-24 02:12:32,746 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:32,747 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:32,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:32,747 INFO L85 PathProgramCache]: Analyzing trace with hash 2069984561, now seen corresponding path program 1 times [2024-11-24 02:12:32,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:32,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281519255] [2024-11-24 02:12:32,748 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:32,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:33,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:33,912 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:33,913 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:33,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281519255] [2024-11-24 02:12:33,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281519255] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:33,913 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1906529919] [2024-11-24 02:12:33,913 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:33,913 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:33,913 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:33,917 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:33,919 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-24 02:12:35,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:35,878 INFO L256 TraceCheckSpWp]: Trace formula consists of 3388 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-24 02:12:35,891 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:37,272 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-24 02:12:37,272 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:38,454 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:38,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1906529919] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:38,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:38,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-24 02:12:38,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56181356] [2024-11-24 02:12:38,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:38,456 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:12:38,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:38,457 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:12:38,457 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-24 02:12:38,457 INFO L87 Difference]: Start difference. First operand 1221 states and 1775 transitions. Second operand has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:38,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:38,741 INFO L93 Difference]: Finished difference Result 1904 states and 2772 transitions. [2024-11-24 02:12:38,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:12:38,741 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 686 [2024-11-24 02:12:38,742 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:38,745 INFO L225 Difference]: With dead ends: 1904 [2024-11-24 02:12:38,746 INFO L226 Difference]: Without dead ends: 1221 [2024-11-24 02:12:38,747 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1375 GetRequests, 1357 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:12:38,748 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 885 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 190 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 890 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 191 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 190 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:38,748 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [890 Valid, 2015 Invalid, 191 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 190 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:12:38,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-24 02:12:38,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-24 02:12:38,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4507857733664185) internal successors, (1754), 1209 states have internal predecessors, (1754), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:38,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1774 transitions. [2024-11-24 02:12:38,788 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1774 transitions. Word has length 686 [2024-11-24 02:12:38,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:38,789 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1774 transitions. [2024-11-24 02:12:38,789 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.6) internal successors, (583), 5 states have internal predecessors, (583), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:38,789 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1774 transitions. [2024-11-24 02:12:38,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 688 [2024-11-24 02:12:38,798 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:38,798 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:38,821 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2024-11-24 02:12:38,999 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable30 [2024-11-24 02:12:39,000 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:39,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:39,000 INFO L85 PathProgramCache]: Analyzing trace with hash 918314603, now seen corresponding path program 1 times [2024-11-24 02:12:39,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:39,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100263168] [2024-11-24 02:12:39,001 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:39,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:39,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:40,208 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-24 02:12:40,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:40,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100263168] [2024-11-24 02:12:40,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100263168] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:40,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [715282727] [2024-11-24 02:12:40,208 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:40,208 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:40,208 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:40,210 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:40,213 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-24 02:12:42,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:42,140 INFO L256 TraceCheckSpWp]: Trace formula consists of 3391 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-24 02:12:42,146 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:42,171 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2024-11-24 02:12:42,171 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:42,234 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:42,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [715282727] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:42,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:42,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-24 02:12:42,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381382380] [2024-11-24 02:12:42,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:42,236 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:12:42,236 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:42,237 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:12:42,237 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:42,237 INFO L87 Difference]: Start difference. First operand 1221 states and 1774 transitions. Second operand has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:42,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:42,267 INFO L93 Difference]: Finished difference Result 1905 states and 2772 transitions. [2024-11-24 02:12:42,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:12:42,267 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 687 [2024-11-24 02:12:42,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:42,270 INFO L225 Difference]: With dead ends: 1905 [2024-11-24 02:12:42,270 INFO L226 Difference]: Without dead ends: 1222 [2024-11-24 02:12:42,271 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1376 GetRequests, 1371 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:42,271 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:42,272 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:12:42,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states. [2024-11-24 02:12:42,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-24 02:12:42,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4504132231404958) internal successors, (1755), 1210 states have internal predecessors, (1755), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:42,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1775 transitions. [2024-11-24 02:12:42,298 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1775 transitions. Word has length 687 [2024-11-24 02:12:42,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:42,299 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1775 transitions. [2024-11-24 02:12:42,299 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:42,300 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1775 transitions. [2024-11-24 02:12:42,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 690 [2024-11-24 02:12:42,306 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:42,306 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:42,330 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-24 02:12:42,507 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable31 [2024-11-24 02:12:42,508 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:42,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:42,508 INFO L85 PathProgramCache]: Analyzing trace with hash 434424231, now seen corresponding path program 1 times [2024-11-24 02:12:42,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:42,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [587517630] [2024-11-24 02:12:42,509 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:42,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:43,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:43,703 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-24 02:12:43,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:43,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [587517630] [2024-11-24 02:12:43,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [587517630] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:43,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [432569037] [2024-11-24 02:12:43,704 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:43,704 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:43,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:43,706 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:43,707 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-24 02:12:45,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:45,789 INFO L256 TraceCheckSpWp]: Trace formula consists of 3400 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-24 02:12:45,797 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:45,831 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 314 trivial. 0 not checked. [2024-11-24 02:12:45,831 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:45,891 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-11-24 02:12:45,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [432569037] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:45,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:45,892 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-24 02:12:45,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1970676971] [2024-11-24 02:12:45,892 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:45,893 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:12:45,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:45,893 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:12:45,894 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:45,894 INFO L87 Difference]: Start difference. First operand 1222 states and 1775 transitions. Second operand has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:45,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:45,922 INFO L93 Difference]: Finished difference Result 1907 states and 2774 transitions. [2024-11-24 02:12:45,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:12:45,923 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 689 [2024-11-24 02:12:45,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:45,927 INFO L225 Difference]: With dead ends: 1907 [2024-11-24 02:12:45,927 INFO L226 Difference]: Without dead ends: 1223 [2024-11-24 02:12:45,928 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1380 GetRequests, 1375 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:45,929 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:45,929 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:12:45,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-11-24 02:12:45,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1223. [2024-11-24 02:12:45,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1223 states, 1211 states have (on average 1.4500412881915772) internal successors, (1756), 1211 states have internal predecessors, (1756), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:45,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1223 states to 1223 states and 1776 transitions. [2024-11-24 02:12:45,965 INFO L78 Accepts]: Start accepts. Automaton has 1223 states and 1776 transitions. Word has length 689 [2024-11-24 02:12:45,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:45,966 INFO L471 AbstractCegarLoop]: Abstraction has 1223 states and 1776 transitions. [2024-11-24 02:12:45,966 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:45,966 INFO L276 IsEmpty]: Start isEmpty. Operand 1223 states and 1776 transitions. [2024-11-24 02:12:45,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2024-11-24 02:12:45,972 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:45,973 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:45,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-11-24 02:12:46,173 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable32 [2024-11-24 02:12:46,174 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:46,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:46,175 INFO L85 PathProgramCache]: Analyzing trace with hash -186461469, now seen corresponding path program 1 times [2024-11-24 02:12:46,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:46,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683293460] [2024-11-24 02:12:46,175 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:46,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:46,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:47,197 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-11-24 02:12:47,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:47,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683293460] [2024-11-24 02:12:47,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683293460] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:47,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1544291455] [2024-11-24 02:12:47,197 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:47,198 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:47,198 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:47,199 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:47,201 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-24 02:12:49,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:49,329 INFO L256 TraceCheckSpWp]: Trace formula consists of 3409 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-24 02:12:49,336 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:49,371 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 282 proven. 8 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-11-24 02:12:49,371 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:49,445 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-24 02:12:49,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1544291455] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:49,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:12:49,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-24 02:12:49,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82111311] [2024-11-24 02:12:49,446 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:49,446 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:12:49,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:49,447 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:12:49,447 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:49,448 INFO L87 Difference]: Start difference. First operand 1223 states and 1776 transitions. Second operand has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:49,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:49,491 INFO L93 Difference]: Finished difference Result 1909 states and 2776 transitions. [2024-11-24 02:12:49,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:12:49,492 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 691 [2024-11-24 02:12:49,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:49,496 INFO L225 Difference]: With dead ends: 1909 [2024-11-24 02:12:49,497 INFO L226 Difference]: Without dead ends: 1224 [2024-11-24 02:12:49,498 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1384 GetRequests, 1379 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:12:49,498 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:49,499 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:12:49,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1224 states. [2024-11-24 02:12:49,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1224 to 1224. [2024-11-24 02:12:49,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1224 states, 1212 states have (on average 1.4496699669966997) internal successors, (1757), 1212 states have internal predecessors, (1757), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:49,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1224 states to 1224 states and 1777 transitions. [2024-11-24 02:12:49,533 INFO L78 Accepts]: Start accepts. Automaton has 1224 states and 1777 transitions. Word has length 691 [2024-11-24 02:12:49,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:49,534 INFO L471 AbstractCegarLoop]: Abstraction has 1224 states and 1777 transitions. [2024-11-24 02:12:49,534 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 196.0) internal successors, (588), 3 states have internal predecessors, (588), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:12:49,534 INFO L276 IsEmpty]: Start isEmpty. Operand 1224 states and 1777 transitions. [2024-11-24 02:12:49,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 694 [2024-11-24 02:12:49,541 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:49,541 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:49,568 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-11-24 02:12:49,742 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable33 [2024-11-24 02:12:49,742 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:49,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:49,743 INFO L85 PathProgramCache]: Analyzing trace with hash 1053219807, now seen corresponding path program 1 times [2024-11-24 02:12:49,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:49,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711779869] [2024-11-24 02:12:49,744 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:49,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:50,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:50,864 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-24 02:12:50,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:50,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711779869] [2024-11-24 02:12:50,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1711779869] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:50,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [267490703] [2024-11-24 02:12:50,865 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:50,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:50,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:50,869 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:50,872 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-24 02:12:53,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:53,039 INFO L256 TraceCheckSpWp]: Trace formula consists of 3418 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-24 02:12:53,046 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:53,092 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 282 proven. 37 refuted. 0 times theorem prover too weak. 287 trivial. 0 not checked. [2024-11-24 02:12:53,092 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:53,189 INFO L134 CoverageAnalysis]: Checked inductivity of 606 backedges. 182 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-24 02:12:53,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [267490703] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:12:53,190 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:12:53,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-24 02:12:53,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142562261] [2024-11-24 02:12:53,191 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:12:53,195 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:12:53,195 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:53,196 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:12:53,196 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:12:53,196 INFO L87 Difference]: Start difference. First operand 1224 states and 1777 transitions. Second operand has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:12:53,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:53,329 INFO L93 Difference]: Finished difference Result 1916 states and 2785 transitions. [2024-11-24 02:12:53,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:12:53,331 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 693 [2024-11-24 02:12:53,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:53,334 INFO L225 Difference]: With dead ends: 1916 [2024-11-24 02:12:53,335 INFO L226 Difference]: Without dead ends: 1230 [2024-11-24 02:12:53,336 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1389 GetRequests, 1381 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:12:53,336 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 15 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:53,337 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6552 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:12:53,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1230 states. [2024-11-24 02:12:53,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1230 to 1230. [2024-11-24 02:12:53,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1230 states, 1218 states have (on average 1.4474548440065682) internal successors, (1763), 1218 states have internal predecessors, (1763), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:53,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1230 states to 1230 states and 1783 transitions. [2024-11-24 02:12:53,376 INFO L78 Accepts]: Start accepts. Automaton has 1230 states and 1783 transitions. Word has length 693 [2024-11-24 02:12:53,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:53,377 INFO L471 AbstractCegarLoop]: Abstraction has 1230 states and 1783 transitions. [2024-11-24 02:12:53,377 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.22222222222223) internal successors, (605), 9 states have internal predecessors, (605), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:12:53,377 INFO L276 IsEmpty]: Start isEmpty. Operand 1230 states and 1783 transitions. [2024-11-24 02:12:53,383 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 700 [2024-11-24 02:12:53,384 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:53,384 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:53,409 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-11-24 02:12:53,585 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable34 [2024-11-24 02:12:53,585 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:53,585 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:53,586 INFO L85 PathProgramCache]: Analyzing trace with hash -1992758645, now seen corresponding path program 2 times [2024-11-24 02:12:53,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:53,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755568696] [2024-11-24 02:12:53,586 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:12:53,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:53,825 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:12:53,826 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:12:54,573 INFO L134 CoverageAnalysis]: Checked inductivity of 621 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 539 trivial. 0 not checked. [2024-11-24 02:12:54,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:54,574 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755568696] [2024-11-24 02:12:54,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755568696] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:12:54,574 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:12:54,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:12:54,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350039625] [2024-11-24 02:12:54,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:12:54,575 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:12:54,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:54,577 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:12:54,577 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:12:54,577 INFO L87 Difference]: Start difference. First operand 1230 states and 1783 transitions. Second operand has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:12:54,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:54,666 INFO L93 Difference]: Finished difference Result 2220 states and 3230 transitions. [2024-11-24 02:12:54,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:12:54,667 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 699 [2024-11-24 02:12:54,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:54,670 INFO L225 Difference]: With dead ends: 2220 [2024-11-24 02:12:54,671 INFO L226 Difference]: Without dead ends: 1526 [2024-11-24 02:12:54,672 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:12:54,673 INFO L435 NwaCegarLoop]: 1089 mSDtfsCounter, 142 mSDsluCounter, 3258 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 4347 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:54,673 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 4347 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:12:54,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1526 states. [2024-11-24 02:12:54,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1526 to 1522. [2024-11-24 02:12:54,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1522 states, 1510 states have (on average 1.4536423841059603) internal successors, (2195), 1510 states have internal predecessors, (2195), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:54,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1522 states to 1522 states and 2215 transitions. [2024-11-24 02:12:54,738 INFO L78 Accepts]: Start accepts. Automaton has 1522 states and 2215 transitions. Word has length 699 [2024-11-24 02:12:54,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:54,739 INFO L471 AbstractCegarLoop]: Abstraction has 1522 states and 2215 transitions. [2024-11-24 02:12:54,739 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 99.4) internal successors, (497), 5 states have internal predecessors, (497), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:12:54,739 INFO L276 IsEmpty]: Start isEmpty. Operand 1522 states and 2215 transitions. [2024-11-24 02:12:54,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 702 [2024-11-24 02:12:54,752 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:54,753 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:54,753 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2024-11-24 02:12:54,753 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:54,754 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:54,754 INFO L85 PathProgramCache]: Analyzing trace with hash 706771481, now seen corresponding path program 1 times [2024-11-24 02:12:54,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:54,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648953713] [2024-11-24 02:12:54,755 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:54,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:55,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:56,059 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-24 02:12:56,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:12:56,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648953713] [2024-11-24 02:12:56,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648953713] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:12:56,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1277024685] [2024-11-24 02:12:56,059 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:12:56,059 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:12:56,060 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:12:56,061 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:12:56,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-24 02:12:58,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:12:58,460 INFO L256 TraceCheckSpWp]: Trace formula consists of 3451 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-24 02:12:58,467 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:12:58,597 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 283 proven. 112 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2024-11-24 02:12:58,598 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:12:58,801 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-24 02:12:58,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1277024685] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:12:58,801 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:12:58,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-24 02:12:58,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [307617022] [2024-11-24 02:12:58,802 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:12:58,804 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 02:12:58,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:12:58,805 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 02:12:58,806 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:12:58,806 INFO L87 Difference]: Start difference. First operand 1522 states and 2215 transitions. Second operand has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:12:59,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:12:59,139 INFO L93 Difference]: Finished difference Result 2368 states and 3448 transitions. [2024-11-24 02:12:59,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-24 02:12:59,140 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 701 [2024-11-24 02:12:59,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:12:59,144 INFO L225 Difference]: With dead ends: 2368 [2024-11-24 02:12:59,144 INFO L226 Difference]: Without dead ends: 1530 [2024-11-24 02:12:59,146 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1409 GetRequests, 1391 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:12:59,146 INFO L435 NwaCegarLoop]: 1115 mSDtfsCounter, 28 mSDsluCounter, 12196 mSDsCounter, 0 mSdLazyCounter, 251 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 13311 SdHoareTripleChecker+Invalid, 252 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 251 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:12:59,147 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 13311 Invalid, 252 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 251 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:12:59,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1530 states. [2024-11-24 02:12:59,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1530 to 1530. [2024-11-24 02:12:59,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1530 states, 1518 states have (on average 1.4512516469038208) internal successors, (2203), 1518 states have internal predecessors, (2203), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:12:59,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1530 states to 1530 states and 2223 transitions. [2024-11-24 02:12:59,190 INFO L78 Accepts]: Start accepts. Automaton has 1530 states and 2223 transitions. Word has length 701 [2024-11-24 02:12:59,190 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:12:59,191 INFO L471 AbstractCegarLoop]: Abstraction has 1530 states and 2223 transitions. [2024-11-24 02:12:59,191 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:12:59,191 INFO L276 IsEmpty]: Start isEmpty. Operand 1530 states and 2223 transitions. [2024-11-24 02:12:59,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 710 [2024-11-24 02:12:59,198 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:12:59,198 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:12:59,224 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-11-24 02:12:59,399 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable36 [2024-11-24 02:12:59,399 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:12:59,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:12:59,400 INFO L85 PathProgramCache]: Analyzing trace with hash -310514551, now seen corresponding path program 2 times [2024-11-24 02:12:59,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:12:59,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826802966] [2024-11-24 02:12:59,401 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:12:59,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:12:59,687 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:12:59,687 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:00,082 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 2 proven. 176 refuted. 0 times theorem prover too weak. 492 trivial. 0 not checked. [2024-11-24 02:13:00,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:00,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826802966] [2024-11-24 02:13:00,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826802966] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:00,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1011035739] [2024-11-24 02:13:00,083 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:00,083 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:00,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:00,086 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:00,089 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-24 02:13:02,058 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:02,058 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:02,065 INFO L256 TraceCheckSpWp]: Trace formula consists of 798 conjuncts, 60 conjuncts are in the unsatisfiable core [2024-11-24 02:13:02,082 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:04,104 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 277 proven. 3 refuted. 0 times theorem prover too weak. 390 trivial. 0 not checked. [2024-11-24 02:13:04,104 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:05,564 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 180 proven. 0 refuted. 0 times theorem prover too weak. 490 trivial. 0 not checked. [2024-11-24 02:13:05,565 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1011035739] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:05,565 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:13:05,565 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [7, 8] total 21 [2024-11-24 02:13:05,566 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292745217] [2024-11-24 02:13:05,566 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:13:05,567 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-11-24 02:13:05,567 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:05,568 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-11-24 02:13:05,568 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=336, Unknown=0, NotChecked=0, Total=420 [2024-11-24 02:13:05,568 INFO L87 Difference]: Start difference. First operand 1530 states and 2223 transitions. Second operand has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:13:08,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:08,137 INFO L93 Difference]: Finished difference Result 3422 states and 4980 transitions. [2024-11-24 02:13:08,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-24 02:13:08,138 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 709 [2024-11-24 02:13:08,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:08,142 INFO L225 Difference]: With dead ends: 3422 [2024-11-24 02:13:08,142 INFO L226 Difference]: Without dead ends: 1842 [2024-11-24 02:13:08,144 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1405 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 87 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=96, Invalid=366, Unknown=0, NotChecked=0, Total=462 [2024-11-24 02:13:08,145 INFO L435 NwaCegarLoop]: 1251 mSDtfsCounter, 958 mSDsluCounter, 6143 mSDsCounter, 0 mSdLazyCounter, 2482 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 958 SdHoareTripleChecker+Valid, 7394 SdHoareTripleChecker+Invalid, 2500 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 2482 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:08,145 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [958 Valid, 7394 Invalid, 2500 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 2482 Invalid, 0 Unknown, 0 Unchecked, 2.4s Time] [2024-11-24 02:13:08,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1842 states. [2024-11-24 02:13:08,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1842 to 1842. [2024-11-24 02:13:08,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1842 states, 1820 states have (on average 1.45) internal successors, (2639), 1820 states have internal predecessors, (2639), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:13:08,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1842 states to 1842 states and 2679 transitions. [2024-11-24 02:13:08,206 INFO L78 Accepts]: Start accepts. Automaton has 1842 states and 2679 transitions. Word has length 709 [2024-11-24 02:13:08,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:08,206 INFO L471 AbstractCegarLoop]: Abstraction has 1842 states and 2679 transitions. [2024-11-24 02:13:08,207 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 53.63636363636363) internal successors, (590), 11 states have internal predecessors, (590), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:13:08,207 INFO L276 IsEmpty]: Start isEmpty. Operand 1842 states and 2679 transitions. [2024-11-24 02:13:08,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 712 [2024-11-24 02:13:08,214 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:08,214 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:08,233 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-11-24 02:13:08,415 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2024-11-24 02:13:08,415 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:08,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:08,416 INFO L85 PathProgramCache]: Analyzing trace with hash 260568597, now seen corresponding path program 1 times [2024-11-24 02:13:08,417 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:08,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1433427405] [2024-11-24 02:13:08,417 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:08,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:08,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:09,731 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 91 proven. 0 refuted. 0 times theorem prover too weak. 580 trivial. 0 not checked. [2024-11-24 02:13:09,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:09,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1433427405] [2024-11-24 02:13:09,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1433427405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:13:09,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:13:09,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:13:09,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506591583] [2024-11-24 02:13:09,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:13:09,733 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:13:09,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:09,734 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:13:09,734 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:13:09,734 INFO L87 Difference]: Start difference. First operand 1842 states and 2679 transitions. Second operand has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:13:10,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:10,210 INFO L93 Difference]: Finished difference Result 3570 states and 5197 transitions. [2024-11-24 02:13:10,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:13:10,210 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 711 [2024-11-24 02:13:10,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:10,214 INFO L225 Difference]: With dead ends: 3570 [2024-11-24 02:13:10,214 INFO L226 Difference]: Without dead ends: 1850 [2024-11-24 02:13:10,217 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:13:10,219 INFO L435 NwaCegarLoop]: 1393 mSDtfsCounter, 323 mSDsluCounter, 4974 mSDsCounter, 0 mSdLazyCounter, 369 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 323 SdHoareTripleChecker+Valid, 6367 SdHoareTripleChecker+Invalid, 378 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 369 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:10,219 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [323 Valid, 6367 Invalid, 378 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 369 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-24 02:13:10,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states. [2024-11-24 02:13:10,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 1846. [2024-11-24 02:13:10,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1846 states, 1824 states have (on average 1.449013157894737) internal successors, (2643), 1824 states have internal predecessors, (2643), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:13:10,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1846 states to 1846 states and 2683 transitions. [2024-11-24 02:13:10,275 INFO L78 Accepts]: Start accepts. Automaton has 1846 states and 2683 transitions. Word has length 711 [2024-11-24 02:13:10,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:10,276 INFO L471 AbstractCegarLoop]: Abstraction has 1846 states and 2683 transitions. [2024-11-24 02:13:10,276 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 84.0) internal successors, (504), 6 states have internal predecessors, (504), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:13:10,276 INFO L276 IsEmpty]: Start isEmpty. Operand 1846 states and 2683 transitions. [2024-11-24 02:13:10,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 712 [2024-11-24 02:13:10,283 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:10,283 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:10,284 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2024-11-24 02:13:10,284 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:10,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:10,284 INFO L85 PathProgramCache]: Analyzing trace with hash 2103450263, now seen corresponding path program 1 times [2024-11-24 02:13:10,285 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:10,285 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18847139] [2024-11-24 02:13:10,285 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:10,285 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:10,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:11,636 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-24 02:13:11,636 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:11,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18847139] [2024-11-24 02:13:11,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18847139] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:11,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1088990310] [2024-11-24 02:13:11,637 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:11,637 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:11,637 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:11,640 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:11,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-11-24 02:13:14,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:14,174 INFO L256 TraceCheckSpWp]: Trace formula consists of 3493 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-24 02:13:14,185 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:14,323 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 284 proven. 37 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2024-11-24 02:13:14,324 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:14,435 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-24 02:13:14,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1088990310] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:13:14,436 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:13:14,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-24 02:13:14,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111158413] [2024-11-24 02:13:14,437 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:13:14,438 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:13:14,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:14,439 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:13:14,439 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:13:14,439 INFO L87 Difference]: Start difference. First operand 1846 states and 2683 transitions. Second operand has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:14,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:14,563 INFO L93 Difference]: Finished difference Result 2856 states and 4151 transitions. [2024-11-24 02:13:14,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:13:14,563 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 711 [2024-11-24 02:13:14,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:14,567 INFO L225 Difference]: With dead ends: 2856 [2024-11-24 02:13:14,567 INFO L226 Difference]: Without dead ends: 1852 [2024-11-24 02:13:14,569 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1417 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:13:14,569 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 15 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:14,569 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6552 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:13:14,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1852 states. [2024-11-24 02:13:14,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1852 to 1852. [2024-11-24 02:13:14,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1852 states, 1830 states have (on average 1.4475409836065574) internal successors, (2649), 1830 states have internal predecessors, (2649), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:13:14,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1852 states to 1852 states and 2689 transitions. [2024-11-24 02:13:14,631 INFO L78 Accepts]: Start accepts. Automaton has 1852 states and 2689 transitions. Word has length 711 [2024-11-24 02:13:14,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:14,631 INFO L471 AbstractCegarLoop]: Abstraction has 1852 states and 2689 transitions. [2024-11-24 02:13:14,632 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:14,632 INFO L276 IsEmpty]: Start isEmpty. Operand 1852 states and 2689 transitions. [2024-11-24 02:13:14,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-11-24 02:13:14,639 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:14,640 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:14,666 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2024-11-24 02:13:14,840 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2024-11-24 02:13:14,840 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:14,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:14,841 INFO L85 PathProgramCache]: Analyzing trace with hash -1769476725, now seen corresponding path program 2 times [2024-11-24 02:13:14,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:14,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113861637] [2024-11-24 02:13:14,841 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:14,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:15,093 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:15,093 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:15,518 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 175 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-11-24 02:13:15,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:15,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113861637] [2024-11-24 02:13:15,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113861637] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:15,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1751854586] [2024-11-24 02:13:15,520 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:15,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:15,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:15,522 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:15,525 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-11-24 02:13:17,779 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:17,779 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:17,786 INFO L256 TraceCheckSpWp]: Trace formula consists of 801 conjuncts, 30 conjuncts are in the unsatisfiable core [2024-11-24 02:13:17,798 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:19,611 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 275 proven. 4 refuted. 0 times theorem prover too weak. 407 trivial. 0 not checked. [2024-11-24 02:13:19,612 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:21,602 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 175 proven. 4 refuted. 0 times theorem prover too weak. 507 trivial. 0 not checked. [2024-11-24 02:13:21,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1751854586] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:13:21,602 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:13:21,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-11-24 02:13:21,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536343615] [2024-11-24 02:13:21,603 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:13:21,605 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-11-24 02:13:21,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:21,606 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-24 02:13:21,606 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:13:21,607 INFO L87 Difference]: Start difference. First operand 1852 states and 2689 transitions. Second operand has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-11-24 02:13:23,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:23,007 INFO L93 Difference]: Finished difference Result 3210 states and 4666 transitions. [2024-11-24 02:13:23,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:13:23,007 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) Word has length 717 [2024-11-24 02:13:23,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:23,011 INFO L225 Difference]: With dead ends: 3210 [2024-11-24 02:13:23,011 INFO L226 Difference]: Without dead ends: 1556 [2024-11-24 02:13:23,013 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1443 GetRequests, 1428 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2024-11-24 02:13:23,014 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 680 mSDsluCounter, 3969 mSDsCounter, 0 mSdLazyCounter, 1808 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 680 SdHoareTripleChecker+Valid, 4766 SdHoareTripleChecker+Invalid, 1811 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1808 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:23,014 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [680 Valid, 4766 Invalid, 1811 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1808 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-24 02:13:23,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1556 states. [2024-11-24 02:13:23,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1556 to 1546. [2024-11-24 02:13:23,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1546 states, 1534 states have (on average 1.4452411994784875) internal successors, (2217), 1534 states have internal predecessors, (2217), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:23,064 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1546 states to 1546 states and 2237 transitions. [2024-11-24 02:13:23,064 INFO L78 Accepts]: Start accepts. Automaton has 1546 states and 2237 transitions. Word has length 717 [2024-11-24 02:13:23,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:23,065 INFO L471 AbstractCegarLoop]: Abstraction has 1546 states and 2237 transitions. [2024-11-24 02:13:23,065 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 77.76923076923077) internal successors, (1011), 13 states have internal predecessors, (1011), 3 states have call successors, (20), 2 states have call predecessors, (20), 2 states have return successors, (20), 3 states have call predecessors, (20), 3 states have call successors, (20) [2024-11-24 02:13:23,065 INFO L276 IsEmpty]: Start isEmpty. Operand 1546 states and 2237 transitions. [2024-11-24 02:13:23,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 720 [2024-11-24 02:13:23,072 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:23,073 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:23,092 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-11-24 02:13:23,273 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable40 [2024-11-24 02:13:23,274 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:23,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:23,275 INFO L85 PathProgramCache]: Analyzing trace with hash 104734005, now seen corresponding path program 1 times [2024-11-24 02:13:23,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:23,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1153164789] [2024-11-24 02:13:23,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:23,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:23,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:24,721 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-24 02:13:24,722 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:24,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1153164789] [2024-11-24 02:13:24,722 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1153164789] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:24,722 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2047319268] [2024-11-24 02:13:24,722 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:24,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:24,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:24,725 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:24,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-24 02:13:27,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:27,448 INFO L256 TraceCheckSpWp]: Trace formula consists of 3522 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-24 02:13:27,460 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:27,594 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 285 proven. 112 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-11-24 02:13:27,595 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:27,786 INFO L134 CoverageAnalysis]: Checked inductivity of 687 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-24 02:13:27,786 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2047319268] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:13:27,786 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:13:27,787 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-24 02:13:27,787 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359688713] [2024-11-24 02:13:27,787 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:13:27,788 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 02:13:27,788 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:27,788 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 02:13:27,788 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:13:27,789 INFO L87 Difference]: Start difference. First operand 1546 states and 2237 transitions. Second operand has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:28,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:28,053 INFO L93 Difference]: Finished difference Result 2411 states and 3488 transitions. [2024-11-24 02:13:28,053 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-24 02:13:28,053 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 719 [2024-11-24 02:13:28,054 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:28,056 INFO L225 Difference]: With dead ends: 2411 [2024-11-24 02:13:28,056 INFO L226 Difference]: Without dead ends: 1554 [2024-11-24 02:13:28,057 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1445 GetRequests, 1427 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:13:28,058 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 28 mSDsluCounter, 13295 mSDsCounter, 0 mSdLazyCounter, 263 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 14409 SdHoareTripleChecker+Invalid, 264 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 263 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:28,058 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 14409 Invalid, 264 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 263 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:13:28,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1554 states. [2024-11-24 02:13:28,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1554 to 1554. [2024-11-24 02:13:28,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1554 states, 1542 states have (on average 1.4429312581063554) internal successors, (2225), 1542 states have internal predecessors, (2225), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:28,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1554 states to 1554 states and 2245 transitions. [2024-11-24 02:13:28,090 INFO L78 Accepts]: Start accepts. Automaton has 1554 states and 2245 transitions. Word has length 719 [2024-11-24 02:13:28,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:28,091 INFO L471 AbstractCegarLoop]: Abstraction has 1554 states and 2245 transitions. [2024-11-24 02:13:28,091 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:28,091 INFO L276 IsEmpty]: Start isEmpty. Operand 1554 states and 2245 transitions. [2024-11-24 02:13:28,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 728 [2024-11-24 02:13:28,095 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:28,096 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:28,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2024-11-24 02:13:28,296 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable41 [2024-11-24 02:13:28,296 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:28,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:28,297 INFO L85 PathProgramCache]: Analyzing trace with hash 317190469, now seen corresponding path program 2 times [2024-11-24 02:13:28,297 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:28,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422765899] [2024-11-24 02:13:28,297 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:28,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:28,509 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:28,509 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:28,901 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 652 trivial. 0 not checked. [2024-11-24 02:13:28,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:28,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422765899] [2024-11-24 02:13:28,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422765899] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:13:28,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:13:28,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:13:28,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988569452] [2024-11-24 02:13:28,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:13:28,902 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:13:28,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:28,903 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:13:28,903 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:13:28,904 INFO L87 Difference]: Start difference. First operand 1554 states and 2245 transitions. Second operand has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:29,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:29,025 INFO L93 Difference]: Finished difference Result 2427 states and 3503 transitions. [2024-11-24 02:13:29,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:13:29,025 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 727 [2024-11-24 02:13:29,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:29,028 INFO L225 Difference]: With dead ends: 2427 [2024-11-24 02:13:29,028 INFO L226 Difference]: Without dead ends: 1562 [2024-11-24 02:13:29,029 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:13:29,030 INFO L435 NwaCegarLoop]: 1087 mSDtfsCounter, 141 mSDsluCounter, 6499 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 7586 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:29,030 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 7586 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:13:29,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1562 states. [2024-11-24 02:13:29,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1562 to 1555. [2024-11-24 02:13:29,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1555 states, 1543 states have (on average 1.443292287751134) internal successors, (2227), 1543 states have internal predecessors, (2227), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:29,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1555 states to 1555 states and 2247 transitions. [2024-11-24 02:13:29,071 INFO L78 Accepts]: Start accepts. Automaton has 1555 states and 2247 transitions. Word has length 727 [2024-11-24 02:13:29,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:29,072 INFO L471 AbstractCegarLoop]: Abstraction has 1555 states and 2247 transitions. [2024-11-24 02:13:29,072 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 62.625) internal successors, (501), 8 states have internal predecessors, (501), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:29,072 INFO L276 IsEmpty]: Start isEmpty. Operand 1555 states and 2247 transitions. [2024-11-24 02:13:29,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 728 [2024-11-24 02:13:29,077 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:29,078 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:29,078 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-11-24 02:13:29,078 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:29,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:29,079 INFO L85 PathProgramCache]: Analyzing trace with hash -2072821086, now seen corresponding path program 1 times [2024-11-24 02:13:29,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:29,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86161881] [2024-11-24 02:13:29,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:29,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:29,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:30,186 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:13:30,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:30,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86161881] [2024-11-24 02:13:30,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86161881] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:30,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [324305615] [2024-11-24 02:13:30,186 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:30,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:30,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:30,191 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:30,193 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-11-24 02:13:33,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:33,029 INFO L256 TraceCheckSpWp]: Trace formula consists of 3558 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-24 02:13:33,036 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:33,220 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 108 proven. 24 refuted. 0 times theorem prover too weak. 602 trivial. 0 not checked. [2024-11-24 02:13:33,220 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:33,361 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 626 trivial. 0 not checked. [2024-11-24 02:13:33,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [324305615] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:33,361 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:13:33,361 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 8] total 13 [2024-11-24 02:13:33,361 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369124044] [2024-11-24 02:13:33,361 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:13:33,362 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:13:33,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:33,363 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:13:33,363 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:13:33,363 INFO L87 Difference]: Start difference. First operand 1555 states and 2247 transitions. Second operand has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:33,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:33,422 INFO L93 Difference]: Finished difference Result 2669 states and 3857 transitions. [2024-11-24 02:13:33,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:13:33,423 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 727 [2024-11-24 02:13:33,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:33,426 INFO L225 Difference]: With dead ends: 2669 [2024-11-24 02:13:33,426 INFO L226 Difference]: Without dead ends: 1651 [2024-11-24 02:13:33,427 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1456 GetRequests, 1445 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:13:33,428 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 40 mSDsluCounter, 3261 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 4352 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:33,428 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 4352 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:13:33,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1651 states. [2024-11-24 02:13:33,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1651 to 1651. [2024-11-24 02:13:33,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1651 states, 1639 states have (on average 1.4405125076266017) internal successors, (2361), 1639 states have internal predecessors, (2361), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:33,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1651 states to 1651 states and 2381 transitions. [2024-11-24 02:13:33,459 INFO L78 Accepts]: Start accepts. Automaton has 1651 states and 2381 transitions. Word has length 727 [2024-11-24 02:13:33,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:33,459 INFO L471 AbstractCegarLoop]: Abstraction has 1651 states and 2381 transitions. [2024-11-24 02:13:33,459 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:33,459 INFO L276 IsEmpty]: Start isEmpty. Operand 1651 states and 2381 transitions. [2024-11-24 02:13:33,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 729 [2024-11-24 02:13:33,464 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:33,464 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:33,482 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-11-24 02:13:33,664 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable43 [2024-11-24 02:13:33,664 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:33,665 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:33,665 INFO L85 PathProgramCache]: Analyzing trace with hash 1203079047, now seen corresponding path program 1 times [2024-11-24 02:13:33,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:33,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775980196] [2024-11-24 02:13:33,665 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:33,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:34,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:34,817 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:13:34,817 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:34,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775980196] [2024-11-24 02:13:34,817 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775980196] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:34,817 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [212443021] [2024-11-24 02:13:34,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:34,818 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:34,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:34,819 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:34,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-11-24 02:13:37,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:37,844 INFO L256 TraceCheckSpWp]: Trace formula consists of 3561 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-24 02:13:37,859 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:38,006 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 110 proven. 24 refuted. 0 times theorem prover too weak. 600 trivial. 0 not checked. [2024-11-24 02:13:38,006 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:38,101 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 624 trivial. 0 not checked. [2024-11-24 02:13:38,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [212443021] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:38,102 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:13:38,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4, 7] total 11 [2024-11-24 02:13:38,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [664070627] [2024-11-24 02:13:38,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:13:38,104 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:13:38,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:38,105 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:13:38,105 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2024-11-24 02:13:38,105 INFO L87 Difference]: Start difference. First operand 1651 states and 2381 transitions. Second operand has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:38,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:38,183 INFO L93 Difference]: Finished difference Result 2917 states and 4215 transitions. [2024-11-24 02:13:38,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:13:38,183 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 728 [2024-11-24 02:13:38,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:38,187 INFO L225 Difference]: With dead ends: 2917 [2024-11-24 02:13:38,187 INFO L226 Difference]: Without dead ends: 1655 [2024-11-24 02:13:38,189 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1458 GetRequests, 1449 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2024-11-24 02:13:38,189 INFO L435 NwaCegarLoop]: 1092 mSDtfsCounter, 0 mSDsluCounter, 2174 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3266 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:38,190 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3266 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:13:38,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1655 states. [2024-11-24 02:13:38,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1655 to 1655. [2024-11-24 02:13:38,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1655 states, 1643 states have (on average 1.439440048691418) internal successors, (2365), 1643 states have internal predecessors, (2365), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:38,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1655 states to 1655 states and 2385 transitions. [2024-11-24 02:13:38,240 INFO L78 Accepts]: Start accepts. Automaton has 1655 states and 2385 transitions. Word has length 728 [2024-11-24 02:13:38,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:38,241 INFO L471 AbstractCegarLoop]: Abstraction has 1655 states and 2385 transitions. [2024-11-24 02:13:38,241 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 132.25) internal successors, (529), 4 states have internal predecessors, (529), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:13:38,241 INFO L276 IsEmpty]: Start isEmpty. Operand 1655 states and 2385 transitions. [2024-11-24 02:13:38,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 729 [2024-11-24 02:13:38,248 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:38,249 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:38,273 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-11-24 02:13:38,449 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable44 [2024-11-24 02:13:38,450 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:38,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:38,450 INFO L85 PathProgramCache]: Analyzing trace with hash 1562317618, now seen corresponding path program 1 times [2024-11-24 02:13:38,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:38,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1737898993] [2024-11-24 02:13:38,451 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:38,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:38,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:39,531 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:13:39,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:39,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1737898993] [2024-11-24 02:13:39,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1737898993] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:39,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [546724914] [2024-11-24 02:13:39,532 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:13:39,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:39,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:39,534 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:39,535 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-24 02:13:42,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:13:42,591 INFO L256 TraceCheckSpWp]: Trace formula consists of 3559 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-24 02:13:42,598 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:42,638 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 285 proven. 37 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-11-24 02:13:42,638 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:13:42,712 INFO L134 CoverageAnalysis]: Checked inductivity of 735 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:13:42,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [546724914] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:13:42,712 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:13:42,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-24 02:13:42,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927258230] [2024-11-24 02:13:42,713 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:13:42,714 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:13:42,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:13:42,714 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:13:42,715 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:13:42,715 INFO L87 Difference]: Start difference. First operand 1655 states and 2385 transitions. Second operand has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:42,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:13:42,822 INFO L93 Difference]: Finished difference Result 2579 states and 3715 transitions. [2024-11-24 02:13:42,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:13:42,823 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 728 [2024-11-24 02:13:42,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:13:42,825 INFO L225 Difference]: With dead ends: 2579 [2024-11-24 02:13:42,825 INFO L226 Difference]: Without dead ends: 1661 [2024-11-24 02:13:42,826 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1459 GetRequests, 1451 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:13:42,827 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 15 mSDsluCounter, 5450 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6546 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:13:42,827 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6546 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:13:42,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1661 states. [2024-11-24 02:13:42,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1661 to 1661. [2024-11-24 02:13:42,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1661 states, 1649 states have (on average 1.4378411158277744) internal successors, (2371), 1649 states have internal predecessors, (2371), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:13:42,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1661 states to 1661 states and 2391 transitions. [2024-11-24 02:13:42,859 INFO L78 Accepts]: Start accepts. Automaton has 1661 states and 2391 transitions. Word has length 728 [2024-11-24 02:13:42,860 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:13:42,860 INFO L471 AbstractCegarLoop]: Abstraction has 1661 states and 2391 transitions. [2024-11-24 02:13:42,860 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:13:42,860 INFO L276 IsEmpty]: Start isEmpty. Operand 1661 states and 2391 transitions. [2024-11-24 02:13:42,864 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 735 [2024-11-24 02:13:42,864 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:13:42,865 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:13:42,883 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2024-11-24 02:13:43,065 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:43,065 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:13:43,066 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:13:43,066 INFO L85 PathProgramCache]: Analyzing trace with hash -915378394, now seen corresponding path program 2 times [2024-11-24 02:13:43,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:13:43,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962971752] [2024-11-24 02:13:43,066 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:43,066 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:13:43,354 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:43,354 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:44,490 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 103 proven. 79 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-11-24 02:13:44,491 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:13:44,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962971752] [2024-11-24 02:13:44,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962971752] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:13:44,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [479156705] [2024-11-24 02:13:44,491 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:13:44,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:13:44,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:13:44,494 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:13:44,498 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-24 02:13:47,207 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:13:47,207 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:13:47,215 INFO L256 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 85 conjuncts are in the unsatisfiable core [2024-11-24 02:13:47,229 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:13:50,577 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 4 proven. 178 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-11-24 02:13:50,577 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:14:00,225 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 98 proven. 84 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-11-24 02:14:00,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [479156705] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:14:00,225 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:14:00,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 22, 17] total 43 [2024-11-24 02:14:00,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482081731] [2024-11-24 02:14:00,225 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:14:00,226 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 43 states [2024-11-24 02:14:00,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:00,228 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2024-11-24 02:14:00,228 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=270, Invalid=1536, Unknown=0, NotChecked=0, Total=1806 [2024-11-24 02:14:00,229 INFO L87 Difference]: Start difference. First operand 1661 states and 2391 transitions. Second operand has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-11-24 02:14:07,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:07,729 INFO L93 Difference]: Finished difference Result 4829 states and 6992 transitions. [2024-11-24 02:14:07,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2024-11-24 02:14:07,729 INFO L78 Accepts]: Start accepts. Automaton has has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) Word has length 734 [2024-11-24 02:14:07,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:07,732 INFO L225 Difference]: With dead ends: 4829 [2024-11-24 02:14:07,732 INFO L226 Difference]: Without dead ends: 3541 [2024-11-24 02:14:07,734 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1506 GetRequests, 1433 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1170 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=748, Invalid=4802, Unknown=0, NotChecked=0, Total=5550 [2024-11-24 02:14:07,735 INFO L435 NwaCegarLoop]: 880 mSDtfsCounter, 7655 mSDsluCounter, 17222 mSDsCounter, 0 mSdLazyCounter, 8197 mSolverCounterSat, 22 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7655 SdHoareTripleChecker+Valid, 18102 SdHoareTripleChecker+Invalid, 8219 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 22 IncrementalHoareTripleChecker+Valid, 8197 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:07,735 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7655 Valid, 18102 Invalid, 8219 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [22 Valid, 8197 Invalid, 0 Unknown, 0 Unchecked, 5.9s Time] [2024-11-24 02:14:07,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3541 states. [2024-11-24 02:14:07,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3541 to 2064. [2024-11-24 02:14:07,775 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2064 states, 2042 states have (on average 1.4333986287952987) internal successors, (2927), 2042 states have internal predecessors, (2927), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:14:07,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2064 states to 2064 states and 2967 transitions. [2024-11-24 02:14:07,778 INFO L78 Accepts]: Start accepts. Automaton has 2064 states and 2967 transitions. Word has length 734 [2024-11-24 02:14:07,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:07,778 INFO L471 AbstractCegarLoop]: Abstraction has 2064 states and 2967 transitions. [2024-11-24 02:14:07,779 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 43 states, 43 states have (on average 41.18604651162791) internal successors, (1771), 43 states have internal predecessors, (1771), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-11-24 02:14:07,779 INFO L276 IsEmpty]: Start isEmpty. Operand 2064 states and 2967 transitions. [2024-11-24 02:14:07,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 736 [2024-11-24 02:14:07,783 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:07,784 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:07,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2024-11-24 02:14:07,984 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable46 [2024-11-24 02:14:07,984 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:07,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:07,985 INFO L85 PathProgramCache]: Analyzing trace with hash 1631054289, now seen corresponding path program 1 times [2024-11-24 02:14:07,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:07,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [442412935] [2024-11-24 02:14:07,985 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:07,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:08,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:09,308 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:14:09,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:09,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [442412935] [2024-11-24 02:14:09,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [442412935] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:14:09,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [749808176] [2024-11-24 02:14:09,309 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:09,309 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:14:09,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:14:09,311 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:14:09,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-24 02:14:12,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:12,499 INFO L256 TraceCheckSpWp]: Trace formula consists of 3587 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-24 02:14:12,506 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:14:12,610 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 285 proven. 112 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2024-11-24 02:14:12,610 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:14:12,768 INFO L134 CoverageAnalysis]: Checked inductivity of 750 backedges. 185 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-24 02:14:12,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [749808176] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:14:12,768 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:14:12,768 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-24 02:14:12,768 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066771351] [2024-11-24 02:14:12,769 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:14:12,770 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 02:14:12,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:12,771 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 02:14:12,771 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:14:12,772 INFO L87 Difference]: Start difference. First operand 2064 states and 2967 transitions. Second operand has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:13,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:13,153 INFO L93 Difference]: Finished difference Result 3201 states and 4599 transitions. [2024-11-24 02:14:13,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-24 02:14:13,154 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 735 [2024-11-24 02:14:13,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:13,157 INFO L225 Difference]: With dead ends: 3201 [2024-11-24 02:14:13,157 INFO L226 Difference]: Without dead ends: 2072 [2024-11-24 02:14:13,159 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1477 GetRequests, 1459 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:14:13,159 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 27 mSDsluCounter, 13295 mSDsCounter, 0 mSdLazyCounter, 273 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 14409 SdHoareTripleChecker+Invalid, 274 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 273 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:13,160 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 14409 Invalid, 274 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 273 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:14:13,162 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2072 states. [2024-11-24 02:14:13,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2072 to 2072. [2024-11-24 02:14:13,201 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2072 states, 2050 states have (on average 1.4317073170731707) internal successors, (2935), 2050 states have internal predecessors, (2935), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:14:13,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2072 states to 2072 states and 2975 transitions. [2024-11-24 02:14:13,204 INFO L78 Accepts]: Start accepts. Automaton has 2072 states and 2975 transitions. Word has length 735 [2024-11-24 02:14:13,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:13,205 INFO L471 AbstractCegarLoop]: Abstraction has 2072 states and 2975 transitions. [2024-11-24 02:14:13,205 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.388888888888886) internal successors, (637), 18 states have internal predecessors, (637), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:13,205 INFO L276 IsEmpty]: Start isEmpty. Operand 2072 states and 2975 transitions. [2024-11-24 02:14:13,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 744 [2024-11-24 02:14:13,210 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:13,210 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:13,232 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-11-24 02:14:13,411 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable47 [2024-11-24 02:14:13,411 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:13,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:13,412 INFO L85 PathProgramCache]: Analyzing trace with hash 1617889761, now seen corresponding path program 2 times [2024-11-24 02:14:13,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:13,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846381228] [2024-11-24 02:14:13,412 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:14:13,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:13,762 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:14:13,762 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:14:15,237 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 4 proven. 108 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-11-24 02:14:15,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:15,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846381228] [2024-11-24 02:14:15,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846381228] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:14:15,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [268615602] [2024-11-24 02:14:15,238 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:14:15,238 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:14:15,238 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:14:15,240 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:14:15,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-24 02:14:18,101 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:14:18,101 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:14:18,108 INFO L256 TraceCheckSpWp]: Trace formula consists of 804 conjuncts, 26 conjuncts are in the unsatisfiable core [2024-11-24 02:14:18,116 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:14:22,120 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 2 proven. 110 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-11-24 02:14:22,120 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:14:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 2 proven. 110 refuted. 0 times theorem prover too weak. 686 trivial. 0 not checked. [2024-11-24 02:14:37,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [268615602] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:14:37,218 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:14:37,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 9] total 23 [2024-11-24 02:14:37,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1298503622] [2024-11-24 02:14:37,218 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:14:37,219 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2024-11-24 02:14:37,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:37,221 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-11-24 02:14:37,221 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=444, Unknown=0, NotChecked=0, Total=506 [2024-11-24 02:14:37,221 INFO L87 Difference]: Start difference. First operand 2072 states and 2975 transitions. Second operand has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) [2024-11-24 02:14:40,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:40,626 INFO L93 Difference]: Finished difference Result 3213 states and 4609 transitions. [2024-11-24 02:14:40,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-11-24 02:14:40,627 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) Word has length 743 [2024-11-24 02:14:40,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:40,630 INFO L225 Difference]: With dead ends: 3213 [2024-11-24 02:14:40,630 INFO L226 Difference]: Without dead ends: 2076 [2024-11-24 02:14:40,631 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1509 GetRequests, 1474 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=190, Invalid=1142, Unknown=0, NotChecked=0, Total=1332 [2024-11-24 02:14:40,632 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 1629 mSDsluCounter, 8346 mSDsCounter, 0 mSdLazyCounter, 3726 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1629 SdHoareTripleChecker+Valid, 9131 SdHoareTripleChecker+Invalid, 3732 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 3726 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:40,632 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1629 Valid, 9131 Invalid, 3732 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 3726 Invalid, 0 Unknown, 0 Unchecked, 2.9s Time] [2024-11-24 02:14:40,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2024-11-24 02:14:40,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 2070. [2024-11-24 02:14:40,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2070 states, 2048 states have (on average 1.4306640625) internal successors, (2930), 2048 states have internal predecessors, (2930), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:14:40,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2070 states to 2070 states and 2970 transitions. [2024-11-24 02:14:40,675 INFO L78 Accepts]: Start accepts. Automaton has 2070 states and 2970 transitions. Word has length 743 [2024-11-24 02:14:40,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:40,676 INFO L471 AbstractCegarLoop]: Abstraction has 2070 states and 2970 transitions. [2024-11-24 02:14:40,676 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 68.56521739130434) internal successors, (1577), 23 states have internal predecessors, (1577), 3 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 3 states have call predecessors, (15), 3 states have call successors, (15) [2024-11-24 02:14:40,676 INFO L276 IsEmpty]: Start isEmpty. Operand 2070 states and 2970 transitions. [2024-11-24 02:14:40,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 744 [2024-11-24 02:14:40,682 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:40,682 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:40,697 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2024-11-24 02:14:40,883 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable48 [2024-11-24 02:14:40,883 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:40,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:40,884 INFO L85 PathProgramCache]: Analyzing trace with hash -1114316960, now seen corresponding path program 1 times [2024-11-24 02:14:40,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:40,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957643047] [2024-11-24 02:14:40,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:40,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:41,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:42,028 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-24 02:14:42,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:42,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957643047] [2024-11-24 02:14:42,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957643047] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:14:42,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1497250637] [2024-11-24 02:14:42,029 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:42,029 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:14:42,029 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:14:42,031 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:14:42,033 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-24 02:14:45,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:45,447 INFO L256 TraceCheckSpWp]: Trace formula consists of 3623 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-24 02:14:45,453 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:14:45,496 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 285 proven. 37 refuted. 0 times theorem prover too weak. 476 trivial. 0 not checked. [2024-11-24 02:14:45,496 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:14:45,572 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-24 02:14:45,572 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1497250637] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:14:45,572 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:14:45,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-24 02:14:45,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147457032] [2024-11-24 02:14:45,573 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:14:45,574 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:14:45,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:45,576 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:14:45,576 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:14:45,576 INFO L87 Difference]: Start difference. First operand 2070 states and 2970 transitions. Second operand has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:45,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:45,739 INFO L93 Difference]: Finished difference Result 3211 states and 4602 transitions. [2024-11-24 02:14:45,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:14:45,740 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 743 [2024-11-24 02:14:45,741 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:45,744 INFO L225 Difference]: With dead ends: 3211 [2024-11-24 02:14:45,744 INFO L226 Difference]: Without dead ends: 2076 [2024-11-24 02:14:45,746 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1489 GetRequests, 1481 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:14:45,746 INFO L435 NwaCegarLoop]: 1094 mSDtfsCounter, 15 mSDsluCounter, 5440 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6534 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:45,747 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6534 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:14:45,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2076 states. [2024-11-24 02:14:45,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2076 to 2076. [2024-11-24 02:14:45,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2076 states, 2054 states have (on average 1.4294060370009738) internal successors, (2936), 2054 states have internal predecessors, (2936), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:14:45,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2076 states to 2076 states and 2976 transitions. [2024-11-24 02:14:45,813 INFO L78 Accepts]: Start accepts. Automaton has 2076 states and 2976 transitions. Word has length 743 [2024-11-24 02:14:45,814 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:45,814 INFO L471 AbstractCegarLoop]: Abstraction has 2076 states and 2976 transitions. [2024-11-24 02:14:45,814 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.11111111111111) internal successors, (613), 9 states have internal predecessors, (613), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:45,814 INFO L276 IsEmpty]: Start isEmpty. Operand 2076 states and 2976 transitions. [2024-11-24 02:14:45,822 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 750 [2024-11-24 02:14:45,822 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:45,823 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:45,854 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-11-24 02:14:46,023 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2024-11-24 02:14:46,024 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:46,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:46,024 INFO L85 PathProgramCache]: Analyzing trace with hash 970100908, now seen corresponding path program 2 times [2024-11-24 02:14:46,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:46,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1805253609] [2024-11-24 02:14:46,025 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:14:46,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:46,533 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:14:46,533 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:14:47,764 INFO L134 CoverageAnalysis]: Checked inductivity of 813 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 628 trivial. 0 not checked. [2024-11-24 02:14:47,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:47,764 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1805253609] [2024-11-24 02:14:47,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1805253609] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:14:47,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:14:47,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:14:47,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012115191] [2024-11-24 02:14:47,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:14:47,765 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:14:47,766 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:47,766 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:14:47,766 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:14:47,767 INFO L87 Difference]: Start difference. First operand 2076 states and 2976 transitions. Second operand has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:14:48,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:48,656 INFO L93 Difference]: Finished difference Result 4760 states and 6817 transitions. [2024-11-24 02:14:48,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:14:48,656 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 749 [2024-11-24 02:14:48,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:48,661 INFO L225 Difference]: With dead ends: 4760 [2024-11-24 02:14:48,661 INFO L226 Difference]: Without dead ends: 3210 [2024-11-24 02:14:48,663 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:14:48,663 INFO L435 NwaCegarLoop]: 1853 mSDtfsCounter, 1321 mSDsluCounter, 8020 mSDsCounter, 0 mSdLazyCounter, 605 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1321 SdHoareTripleChecker+Valid, 9873 SdHoareTripleChecker+Invalid, 613 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 605 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:48,664 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1321 Valid, 9873 Invalid, 613 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 605 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 02:14:48,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3210 states. [2024-11-24 02:14:48,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3210 to 2608. [2024-11-24 02:14:48,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2608 states, 2576 states have (on average 1.423524844720497) internal successors, (3667), 2576 states have internal predecessors, (3667), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:14:48,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2608 states to 2608 states and 3727 transitions. [2024-11-24 02:14:48,754 INFO L78 Accepts]: Start accepts. Automaton has 2608 states and 3727 transitions. Word has length 749 [2024-11-24 02:14:48,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:48,755 INFO L471 AbstractCegarLoop]: Abstraction has 2608 states and 3727 transitions. [2024-11-24 02:14:48,755 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.42857142857143) internal successors, (598), 7 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:14:48,755 INFO L276 IsEmpty]: Start isEmpty. Operand 2608 states and 3727 transitions. [2024-11-24 02:14:48,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 751 [2024-11-24 02:14:48,764 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:48,765 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:48,765 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-11-24 02:14:48,765 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:48,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:48,766 INFO L85 PathProgramCache]: Analyzing trace with hash 905986860, now seen corresponding path program 1 times [2024-11-24 02:14:48,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:48,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799187332] [2024-11-24 02:14:48,766 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:48,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:49,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:50,077 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 186 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-24 02:14:50,078 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:50,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799187332] [2024-11-24 02:14:50,078 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799187332] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:14:50,078 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1186293413] [2024-11-24 02:14:50,078 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:50,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:14:50,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:14:50,080 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:14:50,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-11-24 02:14:53,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:14:53,411 INFO L256 TraceCheckSpWp]: Trace formula consists of 3653 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-24 02:14:53,419 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:14:53,529 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 286 proven. 112 refuted. 0 times theorem prover too weak. 416 trivial. 0 not checked. [2024-11-24 02:14:53,529 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:14:53,775 INFO L134 CoverageAnalysis]: Checked inductivity of 814 backedges. 186 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-24 02:14:53,775 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1186293413] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:14:53,775 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:14:53,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-24 02:14:53,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479712003] [2024-11-24 02:14:53,775 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:14:53,776 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-24 02:14:53,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:53,777 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-24 02:14:53,777 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:14:53,777 INFO L87 Difference]: Start difference. First operand 2608 states and 3727 transitions. Second operand has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:54,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:54,048 INFO L93 Difference]: Finished difference Result 4297 states and 6131 transitions. [2024-11-24 02:14:54,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-24 02:14:54,049 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 750 [2024-11-24 02:14:54,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:54,052 INFO L225 Difference]: With dead ends: 4297 [2024-11-24 02:14:54,052 INFO L226 Difference]: Without dead ends: 2624 [2024-11-24 02:14:54,054 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1507 GetRequests, 1489 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:14:54,054 INFO L435 NwaCegarLoop]: 1112 mSDtfsCounter, 27 mSDsluCounter, 13271 mSDsCounter, 0 mSdLazyCounter, 264 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 14383 SdHoareTripleChecker+Invalid, 265 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 264 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:54,054 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 14383 Invalid, 265 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 264 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:14:54,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2624 states. [2024-11-24 02:14:54,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2624 to 2624. [2024-11-24 02:14:54,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2624 states, 2592 states have (on average 1.4209104938271604) internal successors, (3683), 2592 states have internal predecessors, (3683), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:14:54,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2624 states to 2624 states and 3743 transitions. [2024-11-24 02:14:54,138 INFO L78 Accepts]: Start accepts. Automaton has 2624 states and 3743 transitions. Word has length 750 [2024-11-24 02:14:54,139 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:54,139 INFO L471 AbstractCegarLoop]: Abstraction has 2624 states and 3743 transitions. [2024-11-24 02:14:54,139 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.44444444444444) internal successors, (638), 18 states have internal predecessors, (638), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:14:54,139 INFO L276 IsEmpty]: Start isEmpty. Operand 2624 states and 3743 transitions. [2024-11-24 02:14:54,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 759 [2024-11-24 02:14:54,147 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:54,148 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:54,176 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-11-24 02:14:54,348 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable51 [2024-11-24 02:14:54,349 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:54,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:54,349 INFO L85 PathProgramCache]: Analyzing trace with hash 794369052, now seen corresponding path program 2 times [2024-11-24 02:14:54,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:54,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303046984] [2024-11-24 02:14:54,350 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:14:54,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:55,049 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:14:55,049 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:14:56,388 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:14:56,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:14:56,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303046984] [2024-11-24 02:14:56,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303046984] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:14:56,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:14:56,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:14:56,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083215402] [2024-11-24 02:14:56,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:14:56,389 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:14:56,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:14:56,390 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:14:56,390 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:14:56,391 INFO L87 Difference]: Start difference. First operand 2624 states and 3743 transitions. Second operand has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:14:58,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:14:58,002 INFO L93 Difference]: Finished difference Result 4915 states and 7007 transitions. [2024-11-24 02:14:58,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:14:58,003 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 758 [2024-11-24 02:14:58,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:14:58,006 INFO L225 Difference]: With dead ends: 4915 [2024-11-24 02:14:58,007 INFO L226 Difference]: Without dead ends: 3226 [2024-11-24 02:14:58,008 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:14:58,009 INFO L435 NwaCegarLoop]: 1413 mSDtfsCounter, 1514 mSDsluCounter, 5010 mSDsCounter, 0 mSdLazyCounter, 2185 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1514 SdHoareTripleChecker+Valid, 6423 SdHoareTripleChecker+Invalid, 2185 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2185 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-24 02:14:58,009 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1514 Valid, 6423 Invalid, 2185 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2185 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-24 02:14:58,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3226 states. [2024-11-24 02:14:58,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3226 to 2626. [2024-11-24 02:14:58,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.420585967617579) internal successors, (3685), 2594 states have internal predecessors, (3685), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:14:58,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3745 transitions. [2024-11-24 02:14:58,081 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3745 transitions. Word has length 758 [2024-11-24 02:14:58,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:14:58,082 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3745 transitions. [2024-11-24 02:14:58,083 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.57142857142857) internal successors, (599), 7 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:14:58,083 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3745 transitions. [2024-11-24 02:14:58,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 759 [2024-11-24 02:14:58,091 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:14:58,091 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:14:58,091 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-11-24 02:14:58,092 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:14:58,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:14:58,093 INFO L85 PathProgramCache]: Analyzing trace with hash -1684021553, now seen corresponding path program 1 times [2024-11-24 02:14:58,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:14:58,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736507040] [2024-11-24 02:14:58,093 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:14:58,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:14:59,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:01,105 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:01,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:01,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736507040] [2024-11-24 02:15:01,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736507040] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:01,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:01,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:15:01,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680506284] [2024-11-24 02:15:01,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:01,107 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:15:01,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:01,108 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:15:01,108 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:15:01,108 INFO L87 Difference]: Start difference. First operand 2626 states and 3745 transitions. Second operand has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:01,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:01,341 INFO L93 Difference]: Finished difference Result 4317 states and 6143 transitions. [2024-11-24 02:15:01,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:15:01,341 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 758 [2024-11-24 02:15:01,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:01,344 INFO L225 Difference]: With dead ends: 4317 [2024-11-24 02:15:01,344 INFO L226 Difference]: Without dead ends: 2626 [2024-11-24 02:15:01,346 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:15:01,346 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 774 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 774 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 188 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:01,346 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [774 Valid, 2000 Invalid, 188 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:15:01,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-11-24 02:15:01,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-11-24 02:15:01,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4202004626060138) internal successors, (3684), 2594 states have internal predecessors, (3684), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:01,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3744 transitions. [2024-11-24 02:15:01,399 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3744 transitions. Word has length 758 [2024-11-24 02:15:01,400 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:01,400 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3744 transitions. [2024-11-24 02:15:01,400 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:01,400 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3744 transitions. [2024-11-24 02:15:01,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 760 [2024-11-24 02:15:01,405 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:01,405 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:01,405 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-11-24 02:15:01,405 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:01,406 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:01,406 INFO L85 PathProgramCache]: Analyzing trace with hash 2126536928, now seen corresponding path program 1 times [2024-11-24 02:15:01,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:01,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022026328] [2024-11-24 02:15:01,406 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:01,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:02,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:03,875 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:03,875 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:03,875 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022026328] [2024-11-24 02:15:03,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022026328] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:03,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:03,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:15:03,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2042473944] [2024-11-24 02:15:03,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:03,876 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:15:03,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:03,877 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:15:03,877 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:15:03,877 INFO L87 Difference]: Start difference. First operand 2626 states and 3744 transitions. Second operand has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:04,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:04,163 INFO L93 Difference]: Finished difference Result 4317 states and 6141 transitions. [2024-11-24 02:15:04,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:15:04,164 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 759 [2024-11-24 02:15:04,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:04,168 INFO L225 Difference]: With dead ends: 4317 [2024-11-24 02:15:04,169 INFO L226 Difference]: Without dead ends: 2626 [2024-11-24 02:15:04,171 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:04,172 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 1070 mSDsluCounter, 1010 mSDsCounter, 0 mSdLazyCounter, 186 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 2009 SdHoareTripleChecker+Invalid, 186 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 186 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:04,172 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 2009 Invalid, 186 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 186 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:15:04,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-11-24 02:15:04,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-11-24 02:15:04,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4198149575944488) internal successors, (3683), 2594 states have internal predecessors, (3683), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:04,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3743 transitions. [2024-11-24 02:15:04,254 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3743 transitions. Word has length 759 [2024-11-24 02:15:04,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:04,254 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3743 transitions. [2024-11-24 02:15:04,255 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:04,255 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3743 transitions. [2024-11-24 02:15:04,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 761 [2024-11-24 02:15:04,261 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:04,262 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:04,262 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-11-24 02:15:04,262 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:04,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:04,263 INFO L85 PathProgramCache]: Analyzing trace with hash -193696654, now seen corresponding path program 1 times [2024-11-24 02:15:04,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:04,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319661448] [2024-11-24 02:15:04,263 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:04,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:05,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:06,577 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:06,577 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:06,577 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319661448] [2024-11-24 02:15:06,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319661448] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:06,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:06,578 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:15:06,578 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529983207] [2024-11-24 02:15:06,578 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:06,579 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:15:06,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:06,580 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:15:06,580 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:15:06,580 INFO L87 Difference]: Start difference. First operand 2626 states and 3743 transitions. Second operand has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:06,915 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:06,915 INFO L93 Difference]: Finished difference Result 4317 states and 6139 transitions. [2024-11-24 02:15:06,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:15:06,916 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 760 [2024-11-24 02:15:06,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:06,919 INFO L225 Difference]: With dead ends: 4317 [2024-11-24 02:15:06,919 INFO L226 Difference]: Without dead ends: 2626 [2024-11-24 02:15:06,921 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:06,921 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 1822 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 184 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1827 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 184 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 184 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:06,921 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1827 Valid, 2000 Invalid, 184 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 184 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:15:06,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-11-24 02:15:06,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-11-24 02:15:06,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4194294525828837) internal successors, (3682), 2594 states have internal predecessors, (3682), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:06,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3742 transitions. [2024-11-24 02:15:06,996 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3742 transitions. Word has length 760 [2024-11-24 02:15:06,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:06,997 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3742 transitions. [2024-11-24 02:15:06,997 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 120.2) internal successors, (601), 5 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:06,997 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3742 transitions. [2024-11-24 02:15:07,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 762 [2024-11-24 02:15:07,003 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:07,003 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:07,004 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-11-24 02:15:07,004 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:07,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:07,004 INFO L85 PathProgramCache]: Analyzing trace with hash -1004198968, now seen corresponding path program 1 times [2024-11-24 02:15:07,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:07,005 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335347014] [2024-11-24 02:15:07,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:07,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:07,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:09,153 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:09,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:09,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335347014] [2024-11-24 02:15:09,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335347014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:09,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:09,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:15:09,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238766246] [2024-11-24 02:15:09,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:09,154 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:15:09,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:09,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:15:09,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:15:09,156 INFO L87 Difference]: Start difference. First operand 2626 states and 3742 transitions. Second operand has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:09,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:09,466 INFO L93 Difference]: Finished difference Result 4317 states and 6137 transitions. [2024-11-24 02:15:09,467 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:15:09,467 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 761 [2024-11-24 02:15:09,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:09,471 INFO L225 Difference]: With dead ends: 4317 [2024-11-24 02:15:09,472 INFO L226 Difference]: Without dead ends: 2626 [2024-11-24 02:15:09,474 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:15:09,475 INFO L435 NwaCegarLoop]: 999 mSDtfsCounter, 741 mSDsluCounter, 1001 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 741 SdHoareTripleChecker+Valid, 2000 SdHoareTripleChecker+Invalid, 182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:09,475 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [741 Valid, 2000 Invalid, 182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:15:09,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states. [2024-11-24 02:15:09,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2024-11-24 02:15:09,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2594 states have (on average 1.4190439475713184) internal successors, (3681), 2594 states have internal predecessors, (3681), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:09,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 3741 transitions. [2024-11-24 02:15:09,537 INFO L78 Accepts]: Start accepts. Automaton has 2626 states and 3741 transitions. Word has length 761 [2024-11-24 02:15:09,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:09,537 INFO L471 AbstractCegarLoop]: Abstraction has 2626 states and 3741 transitions. [2024-11-24 02:15:09,538 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 150.5) internal successors, (602), 4 states have internal predecessors, (602), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:09,538 INFO L276 IsEmpty]: Start isEmpty. Operand 2626 states and 3741 transitions. [2024-11-24 02:15:09,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 763 [2024-11-24 02:15:09,542 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:09,542 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:09,542 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-11-24 02:15:09,542 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:09,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:09,543 INFO L85 PathProgramCache]: Analyzing trace with hash -135984971, now seen corresponding path program 1 times [2024-11-24 02:15:09,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:09,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155575394] [2024-11-24 02:15:09,543 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:09,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:11,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:13,361 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:13,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:13,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155575394] [2024-11-24 02:15:13,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155575394] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:13,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:13,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:15:13,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519636654] [2024-11-24 02:15:13,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:13,363 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:13,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:13,363 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:13,364 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:13,364 INFO L87 Difference]: Start difference. First operand 2626 states and 3741 transitions. Second operand has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:13,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:13,464 INFO L93 Difference]: Finished difference Result 5304 states and 7550 transitions. [2024-11-24 02:15:13,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:13,465 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 762 [2024-11-24 02:15:13,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:13,469 INFO L225 Difference]: With dead ends: 5304 [2024-11-24 02:15:13,469 INFO L226 Difference]: Without dead ends: 3613 [2024-11-24 02:15:13,471 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:13,472 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 307 mSDsluCounter, 4299 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 307 SdHoareTripleChecker+Valid, 5378 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:13,472 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [307 Valid, 5378 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:15:13,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3613 states. [2024-11-24 02:15:13,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3613 to 3609. [2024-11-24 02:15:13,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3609 states, 3577 states have (on average 1.423259714844842) internal successors, (5091), 3577 states have internal predecessors, (5091), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:13,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3609 states to 3609 states and 5151 transitions. [2024-11-24 02:15:13,529 INFO L78 Accepts]: Start accepts. Automaton has 3609 states and 5151 transitions. Word has length 762 [2024-11-24 02:15:13,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:13,530 INFO L471 AbstractCegarLoop]: Abstraction has 3609 states and 5151 transitions. [2024-11-24 02:15:13,530 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.5) internal successors, (603), 6 states have internal predecessors, (603), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:13,530 INFO L276 IsEmpty]: Start isEmpty. Operand 3609 states and 5151 transitions. [2024-11-24 02:15:13,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-11-24 02:15:13,536 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:13,537 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:13,537 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-11-24 02:15:13,537 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:13,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:13,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1471099119, now seen corresponding path program 1 times [2024-11-24 02:15:13,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:13,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555067734] [2024-11-24 02:15:13,538 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:13,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:16,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:17,861 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:17,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:17,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555067734] [2024-11-24 02:15:17,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555067734] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:17,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:17,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:15:17,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960666725] [2024-11-24 02:15:17,862 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:17,862 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:17,862 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:17,863 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:17,863 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:17,863 INFO L87 Difference]: Start difference. First operand 3609 states and 5151 transitions. Second operand has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:17,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:17,961 INFO L93 Difference]: Finished difference Result 7453 states and 10654 transitions. [2024-11-24 02:15:17,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:17,962 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 763 [2024-11-24 02:15:17,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:17,966 INFO L225 Difference]: With dead ends: 7453 [2024-11-24 02:15:17,966 INFO L226 Difference]: Without dead ends: 5163 [2024-11-24 02:15:17,969 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:17,969 INFO L435 NwaCegarLoop]: 1083 mSDtfsCounter, 292 mSDsluCounter, 4317 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 292 SdHoareTripleChecker+Valid, 5400 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:17,969 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [292 Valid, 5400 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:15:17,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5163 states. [2024-11-24 02:15:18,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5163 to 5159. [2024-11-24 02:15:18,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5159 states, 5127 states have (on average 1.4322215720694362) internal successors, (7343), 5127 states have internal predecessors, (7343), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:18,036 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5159 states to 5159 states and 7403 transitions. [2024-11-24 02:15:18,037 INFO L78 Accepts]: Start accepts. Automaton has 5159 states and 7403 transitions. Word has length 763 [2024-11-24 02:15:18,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:18,037 INFO L471 AbstractCegarLoop]: Abstraction has 5159 states and 7403 transitions. [2024-11-24 02:15:18,037 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.66666666666667) internal successors, (604), 6 states have internal predecessors, (604), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:18,037 INFO L276 IsEmpty]: Start isEmpty. Operand 5159 states and 7403 transitions. [2024-11-24 02:15:18,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 765 [2024-11-24 02:15:18,043 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:18,044 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:18,044 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-11-24 02:15:18,044 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:18,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:18,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1993213138, now seen corresponding path program 1 times [2024-11-24 02:15:18,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:18,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [207075941] [2024-11-24 02:15:18,045 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:18,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:20,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:21,335 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:21,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:21,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [207075941] [2024-11-24 02:15:21,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [207075941] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:21,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:21,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:15:21,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2104530905] [2024-11-24 02:15:21,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:21,336 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:21,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:21,337 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:21,337 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:21,337 INFO L87 Difference]: Start difference. First operand 5159 states and 7403 transitions. Second operand has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:22,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:22,291 INFO L93 Difference]: Finished difference Result 8817 states and 12591 transitions. [2024-11-24 02:15:22,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:22,291 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 764 [2024-11-24 02:15:22,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:22,296 INFO L225 Difference]: With dead ends: 8817 [2024-11-24 02:15:22,296 INFO L226 Difference]: Without dead ends: 5549 [2024-11-24 02:15:22,300 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:22,300 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 1039 mSDsluCounter, 2391 mSDsCounter, 0 mSdLazyCounter, 1156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1044 SdHoareTripleChecker+Valid, 3195 SdHoareTripleChecker+Invalid, 1157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:22,300 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1044 Valid, 3195 Invalid, 1157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1156 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-24 02:15:22,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5549 states. [2024-11-24 02:15:22,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5549 to 5545. [2024-11-24 02:15:22,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5545 states, 5513 states have (on average 1.4280790857972065) internal successors, (7873), 5513 states have internal predecessors, (7873), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:22,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5545 states to 5545 states and 7933 transitions. [2024-11-24 02:15:22,382 INFO L78 Accepts]: Start accepts. Automaton has 5545 states and 7933 transitions. Word has length 764 [2024-11-24 02:15:22,383 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:22,383 INFO L471 AbstractCegarLoop]: Abstraction has 5545 states and 7933 transitions. [2024-11-24 02:15:22,383 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 100.83333333333333) internal successors, (605), 6 states have internal predecessors, (605), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:22,383 INFO L276 IsEmpty]: Start isEmpty. Operand 5545 states and 7933 transitions. [2024-11-24 02:15:22,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-11-24 02:15:22,389 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:22,389 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:22,389 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-11-24 02:15:22,389 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:22,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:22,390 INFO L85 PathProgramCache]: Analyzing trace with hash -212438930, now seen corresponding path program 1 times [2024-11-24 02:15:22,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:22,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982539019] [2024-11-24 02:15:22,390 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:22,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:25,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:26,179 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:26,179 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:26,179 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982539019] [2024-11-24 02:15:26,179 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982539019] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:26,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:26,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:15:26,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1802718258] [2024-11-24 02:15:26,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:26,180 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:26,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:26,181 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:26,181 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:26,181 INFO L87 Difference]: Start difference. First operand 5545 states and 7933 transitions. Second operand has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:27,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:27,066 INFO L93 Difference]: Finished difference Result 9203 states and 13119 transitions. [2024-11-24 02:15:27,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:27,067 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-11-24 02:15:27,067 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:27,071 INFO L225 Difference]: With dead ends: 9203 [2024-11-24 02:15:27,071 INFO L226 Difference]: Without dead ends: 5549 [2024-11-24 02:15:27,073 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:27,073 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 897 mSDsluCounter, 2391 mSDsCounter, 0 mSdLazyCounter, 1156 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 897 SdHoareTripleChecker+Valid, 3195 SdHoareTripleChecker+Invalid, 1156 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:27,074 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [897 Valid, 3195 Invalid, 1156 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1156 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-11-24 02:15:27,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5549 states. [2024-11-24 02:15:27,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5549 to 5547. [2024-11-24 02:15:27,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5547 states, 5515 states have (on average 1.42792384406165) internal successors, (7875), 5515 states have internal predecessors, (7875), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:27,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5547 states to 5547 states and 7935 transitions. [2024-11-24 02:15:27,160 INFO L78 Accepts]: Start accepts. Automaton has 5547 states and 7935 transitions. Word has length 765 [2024-11-24 02:15:27,160 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:27,160 INFO L471 AbstractCegarLoop]: Abstraction has 5547 states and 7935 transitions. [2024-11-24 02:15:27,161 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:27,161 INFO L276 IsEmpty]: Start isEmpty. Operand 5547 states and 7935 transitions. [2024-11-24 02:15:27,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-11-24 02:15:27,169 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:27,169 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:27,169 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-11-24 02:15:27,170 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:27,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:27,170 INFO L85 PathProgramCache]: Analyzing trace with hash 1488522947, now seen corresponding path program 1 times [2024-11-24 02:15:27,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:27,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257322164] [2024-11-24 02:15:27,171 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:27,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:29,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:31,025 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:31,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:31,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257322164] [2024-11-24 02:15:31,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257322164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:31,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:31,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:15:31,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942727202] [2024-11-24 02:15:31,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:31,027 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:31,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:31,027 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:31,027 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:31,028 INFO L87 Difference]: Start difference. First operand 5547 states and 7935 transitions. Second operand has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:31,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:31,776 INFO L93 Difference]: Finished difference Result 9203 states and 13117 transitions. [2024-11-24 02:15:31,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:31,776 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-11-24 02:15:31,777 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:31,783 INFO L225 Difference]: With dead ends: 9203 [2024-11-24 02:15:31,783 INFO L226 Difference]: Without dead ends: 5547 [2024-11-24 02:15:31,787 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:15:31,788 INFO L435 NwaCegarLoop]: 804 mSDtfsCounter, 689 mSDsluCounter, 2249 mSDsCounter, 0 mSdLazyCounter, 1094 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 689 SdHoareTripleChecker+Valid, 3053 SdHoareTripleChecker+Invalid, 1097 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1094 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:31,788 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [689 Valid, 3053 Invalid, 1097 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1094 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-24 02:15:31,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5547 states. [2024-11-24 02:15:31,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5547 to 5159. [2024-11-24 02:15:31,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5159 states, 5127 states have (on average 1.4314413887263506) internal successors, (7339), 5127 states have internal predecessors, (7339), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:15:31,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5159 states to 5159 states and 7399 transitions. [2024-11-24 02:15:31,917 INFO L78 Accepts]: Start accepts. Automaton has 5159 states and 7399 transitions. Word has length 765 [2024-11-24 02:15:31,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:31,918 INFO L471 AbstractCegarLoop]: Abstraction has 5159 states and 7399 transitions. [2024-11-24 02:15:31,919 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:31,919 INFO L276 IsEmpty]: Start isEmpty. Operand 5159 states and 7399 transitions. [2024-11-24 02:15:31,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-11-24 02:15:31,929 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:31,930 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:31,930 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-11-24 02:15:31,930 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:31,931 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:31,931 INFO L85 PathProgramCache]: Analyzing trace with hash -896827729, now seen corresponding path program 1 times [2024-11-24 02:15:31,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:31,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683349841] [2024-11-24 02:15:31,932 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:31,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:34,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:36,474 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:36,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:36,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683349841] [2024-11-24 02:15:36,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683349841] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:36,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:36,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:15:36,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967671486] [2024-11-24 02:15:36,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:36,475 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:15:36,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:36,476 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:15:36,476 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:15:36,477 INFO L87 Difference]: Start difference. First operand 5159 states and 7399 transitions. Second operand has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:37,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:37,859 INFO L93 Difference]: Finished difference Result 9198 states and 13104 transitions. [2024-11-24 02:15:37,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:15:37,860 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-11-24 02:15:37,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:37,865 INFO L225 Difference]: With dead ends: 9198 [2024-11-24 02:15:37,865 INFO L226 Difference]: Without dead ends: 5930 [2024-11-24 02:15:37,869 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:15:37,869 INFO L435 NwaCegarLoop]: 1399 mSDtfsCounter, 1429 mSDsluCounter, 4787 mSDsCounter, 0 mSdLazyCounter, 2113 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1429 SdHoareTripleChecker+Valid, 6186 SdHoareTripleChecker+Invalid, 2116 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2113 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:37,869 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1429 Valid, 6186 Invalid, 2116 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2113 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-24 02:15:37,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5930 states. [2024-11-24 02:15:37,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5930 to 4595. [2024-11-24 02:15:37,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4595 states, 4573 states have (on average 1.4358189372403236) internal successors, (6566), 4573 states have internal predecessors, (6566), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:15:37,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4595 states to 4595 states and 6606 transitions. [2024-11-24 02:15:37,955 INFO L78 Accepts]: Start accepts. Automaton has 4595 states and 6606 transitions. Word has length 766 [2024-11-24 02:15:37,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:37,956 INFO L471 AbstractCegarLoop]: Abstraction has 4595 states and 6606 transitions. [2024-11-24 02:15:37,956 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 86.71428571428571) internal successors, (607), 7 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:15:37,956 INFO L276 IsEmpty]: Start isEmpty. Operand 4595 states and 6606 transitions. [2024-11-24 02:15:37,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 768 [2024-11-24 02:15:37,964 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:37,965 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:37,965 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-11-24 02:15:37,965 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:37,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:37,966 INFO L85 PathProgramCache]: Analyzing trace with hash -1085093831, now seen corresponding path program 1 times [2024-11-24 02:15:37,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:37,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085769368] [2024-11-24 02:15:37,966 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:37,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:40,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:44,515 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 183 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:44,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:44,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085769368] [2024-11-24 02:15:44,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085769368] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:15:44,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [120370508] [2024-11-24 02:15:44,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:44,516 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:15:44,516 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:15:44,518 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:15:44,519 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-11-24 02:15:49,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:49,587 INFO L256 TraceCheckSpWp]: Trace formula consists of 3704 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 02:15:49,595 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:15:49,661 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 776 trivial. 0 not checked. [2024-11-24 02:15:49,661 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:15:49,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [120370508] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:49,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:15:49,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [9] total 13 [2024-11-24 02:15:49,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246008314] [2024-11-24 02:15:49,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:49,663 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:15:49,663 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:49,663 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:15:49,664 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:15:49,664 INFO L87 Difference]: Start difference. First operand 4595 states and 6606 transitions. Second operand has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-24 02:15:49,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:49,781 INFO L93 Difference]: Finished difference Result 8959 states and 12887 transitions. [2024-11-24 02:15:49,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:15:49,782 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 767 [2024-11-24 02:15:49,782 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:49,788 INFO L225 Difference]: With dead ends: 8959 [2024-11-24 02:15:49,790 INFO L226 Difference]: Without dead ends: 4595 [2024-11-24 02:15:49,796 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 775 GetRequests, 764 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=130, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:15:49,796 INFO L435 NwaCegarLoop]: 1077 mSDtfsCounter, 0 mSDsluCounter, 4289 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5366 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:49,796 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5366 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:15:49,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4595 states. [2024-11-24 02:15:49,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4595 to 4595. [2024-11-24 02:15:49,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4595 states, 4573 states have (on average 1.4349442379182156) internal successors, (6562), 4573 states have internal predecessors, (6562), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:15:49,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4595 states to 4595 states and 6602 transitions. [2024-11-24 02:15:49,904 INFO L78 Accepts]: Start accepts. Automaton has 4595 states and 6602 transitions. Word has length 767 [2024-11-24 02:15:49,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:49,905 INFO L471 AbstractCegarLoop]: Abstraction has 4595 states and 6602 transitions. [2024-11-24 02:15:49,905 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-24 02:15:49,905 INFO L276 IsEmpty]: Start isEmpty. Operand 4595 states and 6602 transitions. [2024-11-24 02:15:49,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 770 [2024-11-24 02:15:49,916 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:49,916 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:49,952 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2024-11-24 02:15:50,117 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable63 [2024-11-24 02:15:50,117 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:50,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:50,119 INFO L85 PathProgramCache]: Analyzing trace with hash -273292665, now seen corresponding path program 1 times [2024-11-24 02:15:50,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:50,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [952681029] [2024-11-24 02:15:50,119 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:50,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:53,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:15:55,093 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:15:55,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:15:55,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [952681029] [2024-11-24 02:15:55,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [952681029] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:15:55,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:15:55,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:15:55,094 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069320312] [2024-11-24 02:15:55,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:15:55,095 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:15:55,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:15:55,096 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:15:55,096 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:15:55,096 INFO L87 Difference]: Start difference. First operand 4595 states and 6602 transitions. Second operand has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:15:56,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:15:56,040 INFO L93 Difference]: Finished difference Result 12673 states and 18262 transitions. [2024-11-24 02:15:56,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:15:56,041 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 769 [2024-11-24 02:15:56,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:15:56,047 INFO L225 Difference]: With dead ends: 12673 [2024-11-24 02:15:56,047 INFO L226 Difference]: Without dead ends: 6333 [2024-11-24 02:15:56,053 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:15:56,054 INFO L435 NwaCegarLoop]: 1016 mSDtfsCounter, 1633 mSDsluCounter, 4614 mSDsCounter, 0 mSdLazyCounter, 1124 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1637 SdHoareTripleChecker+Valid, 5630 SdHoareTripleChecker+Invalid, 1125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-11-24 02:15:56,055 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1637 Valid, 5630 Invalid, 1125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1124 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-11-24 02:15:56,059 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6333 states. [2024-11-24 02:15:56,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6333 to 5321. [2024-11-24 02:15:56,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5321 states, 5291 states have (on average 1.433944433944434) internal successors, (7587), 5291 states have internal predecessors, (7587), 28 states have call successors, (28), 1 states have call predecessors, (28), 1 states have return successors, (28), 28 states have call predecessors, (28), 28 states have call successors, (28) [2024-11-24 02:15:56,177 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5321 states to 5321 states and 7643 transitions. [2024-11-24 02:15:56,179 INFO L78 Accepts]: Start accepts. Automaton has 5321 states and 7643 transitions. Word has length 769 [2024-11-24 02:15:56,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:15:56,180 INFO L471 AbstractCegarLoop]: Abstraction has 5321 states and 7643 transitions. [2024-11-24 02:15:56,180 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 76.25) internal successors, (610), 8 states have internal predecessors, (610), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:15:56,180 INFO L276 IsEmpty]: Start isEmpty. Operand 5321 states and 7643 transitions. [2024-11-24 02:15:56,189 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 771 [2024-11-24 02:15:56,189 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:15:56,190 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:15:56,190 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64 [2024-11-24 02:15:56,190 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:15:56,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:15:56,191 INFO L85 PathProgramCache]: Analyzing trace with hash -540838156, now seen corresponding path program 1 times [2024-11-24 02:15:56,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:15:56,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295307454] [2024-11-24 02:15:56,191 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:15:56,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:15:59,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:00,917 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 184 proven. 4 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:00,917 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:00,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1295307454] [2024-11-24 02:16:00,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1295307454] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:16:00,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1942378288] [2024-11-24 02:16:00,917 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:00,917 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:16:00,917 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:16:00,919 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:16:00,920 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-11-24 02:16:04,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:04,460 INFO L256 TraceCheckSpWp]: Trace formula consists of 3711 conjuncts, 29 conjuncts are in the unsatisfiable core [2024-11-24 02:16:04,468 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:16:05,040 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 167 proven. 0 refuted. 0 times theorem prover too weak. 697 trivial. 0 not checked. [2024-11-24 02:16:05,041 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:16:05,041 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1942378288] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:05,041 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:16:05,041 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [8] total 15 [2024-11-24 02:16:05,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083250533] [2024-11-24 02:16:05,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:05,041 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:16:05,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:05,042 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:16:05,042 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=167, Unknown=0, NotChecked=0, Total=210 [2024-11-24 02:16:05,042 INFO L87 Difference]: Start difference. First operand 5321 states and 7643 transitions. Second operand has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-24 02:16:06,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:06,232 INFO L93 Difference]: Finished difference Result 9479 states and 13618 transitions. [2024-11-24 02:16:06,233 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 02:16:06,233 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 770 [2024-11-24 02:16:06,233 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:06,237 INFO L225 Difference]: With dead ends: 9479 [2024-11-24 02:16:06,237 INFO L226 Difference]: Without dead ends: 4627 [2024-11-24 02:16:06,241 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 782 GetRequests, 766 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2024-11-24 02:16:06,241 INFO L435 NwaCegarLoop]: 786 mSDtfsCounter, 962 mSDsluCounter, 4685 mSDsCounter, 0 mSdLazyCounter, 2097 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 963 SdHoareTripleChecker+Valid, 5471 SdHoareTripleChecker+Invalid, 2100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2097 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:06,241 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [963 Valid, 5471 Invalid, 2100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2097 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-24 02:16:06,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4627 states. [2024-11-24 02:16:06,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4627 to 4619. [2024-11-24 02:16:06,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4619 states, 4597 states have (on average 1.4309332173156406) internal successors, (6578), 4597 states have internal predecessors, (6578), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:16:06,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4619 states to 4619 states and 6618 transitions. [2024-11-24 02:16:06,329 INFO L78 Accepts]: Start accepts. Automaton has 4619 states and 6618 transitions. Word has length 770 [2024-11-24 02:16:06,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:06,329 INFO L471 AbstractCegarLoop]: Abstraction has 4619 states and 6618 transitions. [2024-11-24 02:16:06,329 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 55.77777777777778) internal successors, (502), 9 states have internal predecessors, (502), 2 states have call successors, (9), 2 states have call predecessors, (9), 2 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-24 02:16:06,329 INFO L276 IsEmpty]: Start isEmpty. Operand 4619 states and 6618 transitions. [2024-11-24 02:16:06,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-11-24 02:16:06,338 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:06,339 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:06,373 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-11-24 02:16:06,539 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65,33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:16:06,540 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:06,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:06,540 INFO L85 PathProgramCache]: Analyzing trace with hash 856036729, now seen corresponding path program 1 times [2024-11-24 02:16:06,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:06,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1562576952] [2024-11-24 02:16:06,540 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:06,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:10,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:12,832 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:12,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:12,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1562576952] [2024-11-24 02:16:12,832 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1562576952] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:12,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:12,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:16:12,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289633271] [2024-11-24 02:16:12,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:12,833 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:16:12,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:12,834 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:16:12,834 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:16:12,834 INFO L87 Difference]: Start difference. First operand 4619 states and 6618 transitions. Second operand has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:13,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:13,095 INFO L93 Difference]: Finished difference Result 7355 states and 10501 transitions. [2024-11-24 02:16:13,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:16:13,096 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 775 [2024-11-24 02:16:13,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:13,102 INFO L225 Difference]: With dead ends: 7355 [2024-11-24 02:16:13,102 INFO L226 Difference]: Without dead ends: 4639 [2024-11-24 02:16:13,105 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:16:13,106 INFO L435 NwaCegarLoop]: 1037 mSDtfsCounter, 805 mSDsluCounter, 4127 mSDsCounter, 0 mSdLazyCounter, 247 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 805 SdHoareTripleChecker+Valid, 5164 SdHoareTripleChecker+Invalid, 248 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 247 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:13,106 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [805 Valid, 5164 Invalid, 248 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 247 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:16:13,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4639 states. [2024-11-24 02:16:13,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4639 to 4639. [2024-11-24 02:16:13,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4639 states, 4617 states have (on average 1.4290664933939787) internal successors, (6598), 4617 states have internal predecessors, (6598), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:16:13,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4639 states to 4639 states and 6638 transitions. [2024-11-24 02:16:13,178 INFO L78 Accepts]: Start accepts. Automaton has 4639 states and 6638 transitions. Word has length 775 [2024-11-24 02:16:13,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:13,178 INFO L471 AbstractCegarLoop]: Abstraction has 4639 states and 6638 transitions. [2024-11-24 02:16:13,178 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:13,178 INFO L276 IsEmpty]: Start isEmpty. Operand 4639 states and 6638 transitions. [2024-11-24 02:16:13,188 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-11-24 02:16:13,188 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:13,188 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:13,189 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-11-24 02:16:13,189 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:13,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:13,189 INFO L85 PathProgramCache]: Analyzing trace with hash -1439769918, now seen corresponding path program 1 times [2024-11-24 02:16:13,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:13,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [317260828] [2024-11-24 02:16:13,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:13,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:17,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:19,330 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:19,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:19,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [317260828] [2024-11-24 02:16:19,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [317260828] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:19,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:19,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:16:19,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515497745] [2024-11-24 02:16:19,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:19,331 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:16:19,331 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:19,332 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:16:19,332 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:16:19,332 INFO L87 Difference]: Start difference. First operand 4639 states and 6638 transitions. Second operand has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:19,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:19,626 INFO L93 Difference]: Finished difference Result 7383 states and 10529 transitions. [2024-11-24 02:16:19,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:16:19,626 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-11-24 02:16:19,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:19,632 INFO L225 Difference]: With dead ends: 7383 [2024-11-24 02:16:19,632 INFO L226 Difference]: Without dead ends: 4647 [2024-11-24 02:16:19,634 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:16:19,635 INFO L435 NwaCegarLoop]: 1037 mSDtfsCounter, 806 mSDsluCounter, 4127 mSDsCounter, 0 mSdLazyCounter, 249 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 806 SdHoareTripleChecker+Valid, 5164 SdHoareTripleChecker+Invalid, 249 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 249 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:19,635 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [806 Valid, 5164 Invalid, 249 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 249 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:16:19,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4647 states. [2024-11-24 02:16:19,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4647 to 4643. [2024-11-24 02:16:19,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4643 states, 4621 states have (on average 1.4286950876433673) internal successors, (6602), 4621 states have internal predecessors, (6602), 20 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 20 states have call predecessors, (20), 20 states have call successors, (20) [2024-11-24 02:16:19,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4643 states to 4643 states and 6642 transitions. [2024-11-24 02:16:19,700 INFO L78 Accepts]: Start accepts. Automaton has 4643 states and 6642 transitions. Word has length 776 [2024-11-24 02:16:19,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:19,701 INFO L471 AbstractCegarLoop]: Abstraction has 4643 states and 6642 transitions. [2024-11-24 02:16:19,701 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:19,701 INFO L276 IsEmpty]: Start isEmpty. Operand 4643 states and 6642 transitions. [2024-11-24 02:16:19,710 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-11-24 02:16:19,710 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:19,710 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:19,710 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable67 [2024-11-24 02:16:19,711 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:19,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:19,711 INFO L85 PathProgramCache]: Analyzing trace with hash -961437342, now seen corresponding path program 1 times [2024-11-24 02:16:19,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:19,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001732797] [2024-11-24 02:16:19,712 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:19,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:20,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:21,079 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:21,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:21,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001732797] [2024-11-24 02:16:21,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001732797] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:21,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:21,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:16:21,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1529237204] [2024-11-24 02:16:21,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:21,081 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:16:21,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:21,081 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:16:21,081 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:16:21,082 INFO L87 Difference]: Start difference. First operand 4643 states and 6642 transitions. Second operand has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:21,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:21,223 INFO L93 Difference]: Finished difference Result 9982 states and 14231 transitions. [2024-11-24 02:16:21,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:16:21,224 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-11-24 02:16:21,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:21,229 INFO L225 Difference]: With dead ends: 9982 [2024-11-24 02:16:21,230 INFO L226 Difference]: Without dead ends: 7242 [2024-11-24 02:16:21,232 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:16:21,233 INFO L435 NwaCegarLoop]: 1325 mSDtfsCounter, 605 mSDsluCounter, 3710 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 605 SdHoareTripleChecker+Valid, 5035 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:21,233 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [605 Valid, 5035 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:16:21,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7242 states. [2024-11-24 02:16:21,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7242 to 6775. [2024-11-24 02:16:21,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6775 states, 6743 states have (on average 1.4303722378763162) internal successors, (9645), 6743 states have internal predecessors, (9645), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-24 02:16:21,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6775 states to 6775 states and 9705 transitions. [2024-11-24 02:16:21,369 INFO L78 Accepts]: Start accepts. Automaton has 6775 states and 9705 transitions. Word has length 776 [2024-11-24 02:16:21,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:21,369 INFO L471 AbstractCegarLoop]: Abstraction has 6775 states and 9705 transitions. [2024-11-24 02:16:21,370 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:21,370 INFO L276 IsEmpty]: Start isEmpty. Operand 6775 states and 9705 transitions. [2024-11-24 02:16:21,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-24 02:16:21,381 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:21,381 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:21,381 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-11-24 02:16:21,381 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:21,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:21,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1414783750, now seen corresponding path program 1 times [2024-11-24 02:16:21,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:21,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016549199] [2024-11-24 02:16:21,383 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:21,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:22,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:23,725 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:23,726 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:23,726 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1016549199] [2024-11-24 02:16:23,726 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1016549199] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:23,726 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:23,726 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:16:23,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1434304160] [2024-11-24 02:16:23,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:23,727 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:16:23,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:23,728 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:16:23,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:23,728 INFO L87 Difference]: Start difference. First operand 6775 states and 9705 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:23,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:23,965 INFO L93 Difference]: Finished difference Result 12150 states and 17344 transitions. [2024-11-24 02:16:23,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:16:23,965 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-11-24 02:16:23,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:23,973 INFO L225 Difference]: With dead ends: 12150 [2024-11-24 02:16:23,973 INFO L226 Difference]: Without dead ends: 9410 [2024-11-24 02:16:23,976 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:16:23,977 INFO L435 NwaCegarLoop]: 1556 mSDtfsCounter, 540 mSDsluCounter, 8113 mSDsCounter, 0 mSdLazyCounter, 152 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 540 SdHoareTripleChecker+Valid, 9669 SdHoareTripleChecker+Invalid, 152 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:23,977 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [540 Valid, 9669 Invalid, 152 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 152 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:16:23,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9410 states. [2024-11-24 02:16:24,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9410 to 9386. [2024-11-24 02:16:24,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9386 states, 9344 states have (on average 1.4281892123287672) internal successors, (13345), 9344 states have internal predecessors, (13345), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-11-24 02:16:24,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9386 states to 9386 states and 13425 transitions. [2024-11-24 02:16:24,120 INFO L78 Accepts]: Start accepts. Automaton has 9386 states and 13425 transitions. Word has length 777 [2024-11-24 02:16:24,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:24,121 INFO L471 AbstractCegarLoop]: Abstraction has 9386 states and 13425 transitions. [2024-11-24 02:16:24,121 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:24,121 INFO L276 IsEmpty]: Start isEmpty. Operand 9386 states and 13425 transitions. [2024-11-24 02:16:24,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-24 02:16:24,129 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:24,130 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:24,130 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-11-24 02:16:24,130 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:24,130 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:24,130 INFO L85 PathProgramCache]: Analyzing trace with hash -722585695, now seen corresponding path program 1 times [2024-11-24 02:16:24,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:24,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238063874] [2024-11-24 02:16:24,131 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:24,131 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:26,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:27,842 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:27,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:27,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238063874] [2024-11-24 02:16:27,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238063874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:27,843 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:27,843 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:16:27,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [967143828] [2024-11-24 02:16:27,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:27,844 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:16:27,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:27,844 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:16:27,844 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:27,845 INFO L87 Difference]: Start difference. First operand 9386 states and 13425 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:28,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:28,074 INFO L93 Difference]: Finished difference Result 13791 states and 19709 transitions. [2024-11-24 02:16:28,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:16:28,075 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-11-24 02:16:28,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:28,085 INFO L225 Difference]: With dead ends: 13791 [2024-11-24 02:16:28,085 INFO L226 Difference]: Without dead ends: 10905 [2024-11-24 02:16:28,089 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:16:28,090 INFO L435 NwaCegarLoop]: 1455 mSDtfsCounter, 739 mSDsluCounter, 6117 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 739 SdHoareTripleChecker+Valid, 7572 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:28,090 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [739 Valid, 7572 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:16:28,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10905 states. [2024-11-24 02:16:28,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10905 to 10747. [2024-11-24 02:16:28,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10747 states, 10705 states have (on average 1.43176085941149) internal successors, (15327), 10705 states have internal predecessors, (15327), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-11-24 02:16:28,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10747 states to 10747 states and 15407 transitions. [2024-11-24 02:16:28,264 INFO L78 Accepts]: Start accepts. Automaton has 10747 states and 15407 transitions. Word has length 777 [2024-11-24 02:16:28,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:28,265 INFO L471 AbstractCegarLoop]: Abstraction has 10747 states and 15407 transitions. [2024-11-24 02:16:28,265 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:28,265 INFO L276 IsEmpty]: Start isEmpty. Operand 10747 states and 15407 transitions. [2024-11-24 02:16:28,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-24 02:16:28,274 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:28,274 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:28,274 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-11-24 02:16:28,274 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:28,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:28,275 INFO L85 PathProgramCache]: Analyzing trace with hash -558029514, now seen corresponding path program 1 times [2024-11-24 02:16:28,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:28,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668981383] [2024-11-24 02:16:28,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:28,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:28,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:29,552 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 779 trivial. 0 not checked. [2024-11-24 02:16:29,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:29,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668981383] [2024-11-24 02:16:29,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668981383] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:29,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:29,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:16:29,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087779341] [2024-11-24 02:16:29,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:29,554 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:16:29,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:29,554 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:16:29,555 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:16:29,555 INFO L87 Difference]: Start difference. First operand 10747 states and 15407 transitions. Second operand has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:29,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:29,687 INFO L93 Difference]: Finished difference Result 16451 states and 23567 transitions. [2024-11-24 02:16:29,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:16:29,688 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-11-24 02:16:29,688 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:29,700 INFO L225 Difference]: With dead ends: 16451 [2024-11-24 02:16:29,700 INFO L226 Difference]: Without dead ends: 10763 [2024-11-24 02:16:29,707 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:16:29,707 INFO L435 NwaCegarLoop]: 1079 mSDtfsCounter, 0 mSDsluCounter, 2144 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3223 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:29,708 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3223 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:16:29,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10763 states. [2024-11-24 02:16:29,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10763 to 10763. [2024-11-24 02:16:29,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10763 states, 10721 states have (on average 1.431116500326462) internal successors, (15343), 10721 states have internal predecessors, (15343), 40 states have call successors, (40), 1 states have call predecessors, (40), 1 states have return successors, (40), 40 states have call predecessors, (40), 40 states have call successors, (40) [2024-11-24 02:16:29,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10763 states to 10763 states and 15423 transitions. [2024-11-24 02:16:29,873 INFO L78 Accepts]: Start accepts. Automaton has 10763 states and 15423 transitions. Word has length 777 [2024-11-24 02:16:29,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:29,873 INFO L471 AbstractCegarLoop]: Abstraction has 10763 states and 15423 transitions. [2024-11-24 02:16:29,873 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 130.0) internal successors, (520), 4 states have internal predecessors, (520), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:29,873 INFO L276 IsEmpty]: Start isEmpty. Operand 10763 states and 15423 transitions. [2024-11-24 02:16:29,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-24 02:16:29,882 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:29,882 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:29,882 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-11-24 02:16:29,882 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:29,883 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:29,883 INFO L85 PathProgramCache]: Analyzing trace with hash -262177162, now seen corresponding path program 1 times [2024-11-24 02:16:29,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:29,883 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246863488] [2024-11-24 02:16:29,883 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:29,883 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:34,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:38,657 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 757 trivial. 0 not checked. [2024-11-24 02:16:38,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:38,657 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246863488] [2024-11-24 02:16:38,657 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246863488] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:38,657 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:38,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:16:38,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386281547] [2024-11-24 02:16:38,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:38,658 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:16:38,658 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:38,659 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:16:38,659 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:38,659 INFO L87 Difference]: Start difference. First operand 10763 states and 15423 transitions. Second operand has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:16:39,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:39,026 INFO L93 Difference]: Finished difference Result 18269 states and 26110 transitions. [2024-11-24 02:16:39,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:16:39,026 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 777 [2024-11-24 02:16:39,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:39,036 INFO L225 Difference]: With dead ends: 18269 [2024-11-24 02:16:39,036 INFO L226 Difference]: Without dead ends: 12867 [2024-11-24 02:16:39,044 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-24 02:16:39,044 INFO L435 NwaCegarLoop]: 1102 mSDtfsCounter, 1306 mSDsluCounter, 5443 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1310 SdHoareTripleChecker+Valid, 6545 SdHoareTripleChecker+Invalid, 190 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:39,045 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1310 Valid, 6545 Invalid, 190 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:16:39,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12867 states. [2024-11-24 02:16:39,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12867 to 12643. [2024-11-24 02:16:39,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12643 states, 12569 states have (on average 1.4243774365502426) internal successors, (17903), 12569 states have internal predecessors, (17903), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 02:16:39,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12643 states to 12643 states and 18047 transitions. [2024-11-24 02:16:39,245 INFO L78 Accepts]: Start accepts. Automaton has 12643 states and 18047 transitions. Word has length 777 [2024-11-24 02:16:39,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:39,246 INFO L471 AbstractCegarLoop]: Abstraction has 12643 states and 18047 transitions. [2024-11-24 02:16:39,246 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 67.625) internal successors, (541), 8 states have internal predecessors, (541), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:16:39,246 INFO L276 IsEmpty]: Start isEmpty. Operand 12643 states and 18047 transitions. [2024-11-24 02:16:39,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-11-24 02:16:39,257 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:39,257 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:39,257 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72 [2024-11-24 02:16:39,258 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:39,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:39,258 INFO L85 PathProgramCache]: Analyzing trace with hash 114641850, now seen corresponding path program 1 times [2024-11-24 02:16:39,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:39,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675331309] [2024-11-24 02:16:39,258 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:39,258 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:41,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:43,729 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:43,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:43,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [675331309] [2024-11-24 02:16:43,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [675331309] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:43,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:43,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 02:16:43,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399781444] [2024-11-24 02:16:43,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:43,731 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:16:43,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:43,732 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:16:43,732 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:16:43,732 INFO L87 Difference]: Start difference. First operand 12643 states and 18047 transitions. Second operand has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:44,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:44,263 INFO L93 Difference]: Finished difference Result 18048 states and 25744 transitions. [2024-11-24 02:16:44,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 02:16:44,263 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 779 [2024-11-24 02:16:44,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:44,275 INFO L225 Difference]: With dead ends: 18048 [2024-11-24 02:16:44,276 INFO L226 Difference]: Without dead ends: 14329 [2024-11-24 02:16:44,281 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2024-11-24 02:16:44,282 INFO L435 NwaCegarLoop]: 1405 mSDtfsCounter, 1197 mSDsluCounter, 7987 mSDsCounter, 0 mSdLazyCounter, 518 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1197 SdHoareTripleChecker+Valid, 9392 SdHoareTripleChecker+Invalid, 518 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 518 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:44,282 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1197 Valid, 9392 Invalid, 518 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 518 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:16:44,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14329 states. [2024-11-24 02:16:44,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14329 to 14007. [2024-11-24 02:16:44,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14007 states, 13933 states have (on average 1.4276178855953492) internal successors, (19891), 13933 states have internal predecessors, (19891), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 02:16:44,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14007 states to 14007 states and 20035 transitions. [2024-11-24 02:16:44,522 INFO L78 Accepts]: Start accepts. Automaton has 14007 states and 20035 transitions. Word has length 779 [2024-11-24 02:16:44,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:44,523 INFO L471 AbstractCegarLoop]: Abstraction has 14007 states and 20035 transitions. [2024-11-24 02:16:44,523 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.88888888888889) internal successors, (620), 9 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:44,523 INFO L276 IsEmpty]: Start isEmpty. Operand 14007 states and 20035 transitions. [2024-11-24 02:16:44,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-11-24 02:16:44,537 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:44,537 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:44,537 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73 [2024-11-24 02:16:44,537 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:44,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:44,538 INFO L85 PathProgramCache]: Analyzing trace with hash 248295512, now seen corresponding path program 1 times [2024-11-24 02:16:44,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:44,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921323085] [2024-11-24 02:16:44,538 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:44,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:47,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:49,679 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 190 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:16:49,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:49,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921323085] [2024-11-24 02:16:49,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921323085] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:49,679 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:49,679 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:16:49,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598337993] [2024-11-24 02:16:49,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:49,680 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:16:49,680 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:49,681 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:16:49,681 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:49,681 INFO L87 Difference]: Start difference. First operand 14007 states and 20035 transitions. Second operand has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:50,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:50,776 INFO L93 Difference]: Finished difference Result 18319 states and 26141 transitions. [2024-11-24 02:16:50,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:16:50,776 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 779 [2024-11-24 02:16:50,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:50,787 INFO L225 Difference]: With dead ends: 18319 [2024-11-24 02:16:50,788 INFO L226 Difference]: Without dead ends: 14047 [2024-11-24 02:16:50,793 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-11-24 02:16:50,793 INFO L435 NwaCegarLoop]: 795 mSDtfsCounter, 797 mSDsluCounter, 3159 mSDsCounter, 0 mSdLazyCounter, 1457 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 797 SdHoareTripleChecker+Valid, 3954 SdHoareTripleChecker+Invalid, 1459 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1457 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:50,793 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [797 Valid, 3954 Invalid, 1459 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1457 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-24 02:16:50,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14047 states. [2024-11-24 02:16:50,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14047 to 14047. [2024-11-24 02:16:50,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14047 states, 13973 states have (on average 1.4263937593931153) internal successors, (19931), 13973 states have internal predecessors, (19931), 72 states have call successors, (72), 1 states have call predecessors, (72), 1 states have return successors, (72), 72 states have call predecessors, (72), 72 states have call successors, (72) [2024-11-24 02:16:51,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14047 states to 14047 states and 20075 transitions. [2024-11-24 02:16:51,003 INFO L78 Accepts]: Start accepts. Automaton has 14047 states and 20075 transitions. Word has length 779 [2024-11-24 02:16:51,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:51,004 INFO L471 AbstractCegarLoop]: Abstraction has 14047 states and 20075 transitions. [2024-11-24 02:16:51,004 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.5) internal successors, (620), 8 states have internal predecessors, (620), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:16:51,004 INFO L276 IsEmpty]: Start isEmpty. Operand 14047 states and 20075 transitions. [2024-11-24 02:16:51,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-11-24 02:16:51,019 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:51,020 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:51,020 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-11-24 02:16:51,020 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:51,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:51,020 INFO L85 PathProgramCache]: Analyzing trace with hash -58242511, now seen corresponding path program 1 times [2024-11-24 02:16:51,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:51,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651886104] [2024-11-24 02:16:51,021 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:51,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:16:55,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:16:59,129 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 757 trivial. 0 not checked. [2024-11-24 02:16:59,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:16:59,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651886104] [2024-11-24 02:16:59,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651886104] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:16:59,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:16:59,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:16:59,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1625072703] [2024-11-24 02:16:59,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:16:59,130 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:16:59,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:16:59,130 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:16:59,130 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:59,131 INFO L87 Difference]: Start difference. First operand 14047 states and 20075 transitions. Second operand has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:16:59,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:16:59,457 INFO L93 Difference]: Finished difference Result 23049 states and 32839 transitions. [2024-11-24 02:16:59,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:16:59,457 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 780 [2024-11-24 02:16:59,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:16:59,471 INFO L225 Difference]: With dead ends: 23049 [2024-11-24 02:16:59,471 INFO L226 Difference]: Without dead ends: 16811 [2024-11-24 02:16:59,477 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:16:59,478 INFO L435 NwaCegarLoop]: 1064 mSDtfsCounter, 140 mSDsluCounter, 6358 mSDsCounter, 0 mSdLazyCounter, 141 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 140 SdHoareTripleChecker+Valid, 7422 SdHoareTripleChecker+Invalid, 141 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 141 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:16:59,478 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [140 Valid, 7422 Invalid, 141 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 141 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:16:59,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16811 states. [2024-11-24 02:16:59,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16811 to 16795. [2024-11-24 02:16:59,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4191789032064728) internal successors, (23679), 16685 states have internal predecessors, (23679), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:16:59,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23895 transitions. [2024-11-24 02:16:59,726 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23895 transitions. Word has length 780 [2024-11-24 02:16:59,727 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:16:59,727 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23895 transitions. [2024-11-24 02:16:59,727 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 68.0) internal successors, (544), 8 states have internal predecessors, (544), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:16:59,727 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23895 transitions. [2024-11-24 02:16:59,811 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-11-24 02:16:59,811 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:16:59,811 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:16:59,811 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75 [2024-11-24 02:16:59,812 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:16:59,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:16:59,812 INFO L85 PathProgramCache]: Analyzing trace with hash -167713359, now seen corresponding path program 1 times [2024-11-24 02:16:59,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:16:59,813 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987750201] [2024-11-24 02:16:59,813 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:16:59,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:17:04,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:07,882 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 190 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:17:07,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:17:07,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987750201] [2024-11-24 02:17:07,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987750201] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:17:07,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:17:07,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 02:17:07,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065134795] [2024-11-24 02:17:07,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:17:07,883 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:17:07,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:17:07,883 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:17:07,883 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:17:07,884 INFO L87 Difference]: Start difference. First operand 16795 states and 23895 transitions. Second operand has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:17:09,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:17:09,712 INFO L93 Difference]: Finished difference Result 21764 states and 30912 transitions. [2024-11-24 02:17:09,713 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 02:17:09,713 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 780 [2024-11-24 02:17:09,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:17:09,726 INFO L225 Difference]: With dead ends: 21764 [2024-11-24 02:17:09,726 INFO L226 Difference]: Without dead ends: 16861 [2024-11-24 02:17:09,732 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:17:09,732 INFO L435 NwaCegarLoop]: 1546 mSDtfsCounter, 603 mSDsluCounter, 6660 mSDsCounter, 0 mSdLazyCounter, 2618 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 603 SdHoareTripleChecker+Valid, 8206 SdHoareTripleChecker+Invalid, 2619 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2618 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2024-11-24 02:17:09,732 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [603 Valid, 8206 Invalid, 2619 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2618 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2024-11-24 02:17:09,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16861 states. [2024-11-24 02:17:10,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16861 to 16827. [2024-11-24 02:17:10,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16827 states, 16717 states have (on average 1.419094335107974) internal successors, (23723), 16717 states have internal predecessors, (23723), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:17:10,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16827 states to 16827 states and 23939 transitions. [2024-11-24 02:17:10,076 INFO L78 Accepts]: Start accepts. Automaton has 16827 states and 23939 transitions. Word has length 780 [2024-11-24 02:17:10,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:17:10,077 INFO L471 AbstractCegarLoop]: Abstraction has 16827 states and 23939 transitions. [2024-11-24 02:17:10,077 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 69.0) internal successors, (621), 9 states have internal predecessors, (621), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:17:10,077 INFO L276 IsEmpty]: Start isEmpty. Operand 16827 states and 23939 transitions. [2024-11-24 02:17:10,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 781 [2024-11-24 02:17:10,091 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:17:10,091 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:17:10,091 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76 [2024-11-24 02:17:10,091 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:17:10,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:17:10,092 INFO L85 PathProgramCache]: Analyzing trace with hash -320502005, now seen corresponding path program 1 times [2024-11-24 02:17:10,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:17:10,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312681338] [2024-11-24 02:17:10,092 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:10,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:17:15,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:19,526 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:17:19,527 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:17:19,527 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312681338] [2024-11-24 02:17:19,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312681338] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:17:19,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:17:19,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2024-11-24 02:17:19,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266047631] [2024-11-24 02:17:19,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:17:19,528 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-24 02:17:19,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:17:19,528 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-24 02:17:19,528 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-11-24 02:17:19,529 INFO L87 Difference]: Start difference. First operand 16827 states and 23939 transitions. Second operand has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:17:21,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:17:21,310 INFO L93 Difference]: Finished difference Result 21978 states and 31192 transitions. [2024-11-24 02:17:21,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-11-24 02:17:21,311 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 780 [2024-11-24 02:17:21,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:17:21,323 INFO L225 Difference]: With dead ends: 21978 [2024-11-24 02:17:21,323 INFO L226 Difference]: Without dead ends: 16875 [2024-11-24 02:17:21,328 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=163, Unknown=0, NotChecked=0, Total=210 [2024-11-24 02:17:21,328 INFO L435 NwaCegarLoop]: 791 mSDtfsCounter, 1675 mSDsluCounter, 6252 mSDsCounter, 0 mSdLazyCounter, 2664 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1676 SdHoareTripleChecker+Valid, 7043 SdHoareTripleChecker+Invalid, 2667 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 2664 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2024-11-24 02:17:21,329 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1676 Valid, 7043 Invalid, 2667 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 2664 Invalid, 0 Unknown, 0 Unchecked, 1.5s Time] [2024-11-24 02:17:21,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-11-24 02:17:21,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-11-24 02:17:21,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.4178944229048613) internal successors, (23771), 16765 states have internal predecessors, (23771), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:17:21,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23987 transitions. [2024-11-24 02:17:21,677 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23987 transitions. Word has length 780 [2024-11-24 02:17:21,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:17:21,677 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23987 transitions. [2024-11-24 02:17:21,677 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 51.75) internal successors, (621), 12 states have internal predecessors, (621), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:17:21,678 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23987 transitions. [2024-11-24 02:17:21,695 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-11-24 02:17:21,695 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:17:21,696 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:17:21,696 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77 [2024-11-24 02:17:21,696 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:17:21,696 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:17:21,697 INFO L85 PathProgramCache]: Analyzing trace with hash -575460998, now seen corresponding path program 1 times [2024-11-24 02:17:21,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:17:21,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895486562] [2024-11-24 02:17:21,697 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:21,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:17:27,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:29,042 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 829 trivial. 0 not checked. [2024-11-24 02:17:29,042 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:17:29,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895486562] [2024-11-24 02:17:29,042 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895486562] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:17:29,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1313985112] [2024-11-24 02:17:29,043 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:29,043 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:17:29,043 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:17:29,044 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:17:29,046 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-11-24 02:17:36,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:36,481 INFO L256 TraceCheckSpWp]: Trace formula consists of 3736 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 02:17:36,488 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:17:36,549 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 232 proven. 0 refuted. 0 times theorem prover too weak. 636 trivial. 0 not checked. [2024-11-24 02:17:36,549 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:17:36,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1313985112] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:17:36,549 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:17:36,549 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-11-24 02:17:36,549 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [923762027] [2024-11-24 02:17:36,549 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:17:36,550 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:17:36,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:17:36,551 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:17:36,551 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:17:36,551 INFO L87 Difference]: Start difference. First operand 16875 states and 23987 transitions. Second operand has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-11-24 02:17:37,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:17:37,013 INFO L93 Difference]: Finished difference Result 32042 states and 45566 transitions. [2024-11-24 02:17:37,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:17:37,013 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) Word has length 781 [2024-11-24 02:17:37,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:17:37,039 INFO L225 Difference]: With dead ends: 32042 [2024-11-24 02:17:37,043 INFO L226 Difference]: Without dead ends: 16875 [2024-11-24 02:17:37,055 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 786 GetRequests, 779 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:17:37,060 INFO L435 NwaCegarLoop]: 1074 mSDtfsCounter, 0 mSDsluCounter, 4277 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5351 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:17:37,060 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5351 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:17:37,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-11-24 02:17:37,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-11-24 02:17:37,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.4164628690724723) internal successors, (23747), 16765 states have internal predecessors, (23747), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:17:37,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23963 transitions. [2024-11-24 02:17:37,556 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23963 transitions. Word has length 781 [2024-11-24 02:17:37,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:17:37,557 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23963 transitions. [2024-11-24 02:17:37,557 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 117.2) internal successors, (586), 6 states have internal predecessors, (586), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-11-24 02:17:37,557 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23963 transitions. [2024-11-24 02:17:37,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 784 [2024-11-24 02:17:37,584 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:17:37,585 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:17:37,620 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2024-11-24 02:17:37,786 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78,34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:17:37,786 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:17:37,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:17:37,787 INFO L85 PathProgramCache]: Analyzing trace with hash 818835622, now seen corresponding path program 1 times [2024-11-24 02:17:37,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:17:37,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096984321] [2024-11-24 02:17:37,787 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:37,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:17:43,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:44,755 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 830 trivial. 0 not checked. [2024-11-24 02:17:44,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:17:44,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2096984321] [2024-11-24 02:17:44,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2096984321] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:17:44,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1259574292] [2024-11-24 02:17:44,755 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:44,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:17:44,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:17:44,757 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:17:44,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-11-24 02:17:50,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:50,271 INFO L256 TraceCheckSpWp]: Trace formula consists of 3742 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 02:17:50,282 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:17:50,304 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 821 trivial. 0 not checked. [2024-11-24 02:17:50,304 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:17:50,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1259574292] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:17:50,304 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:17:50,304 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-11-24 02:17:50,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871646749] [2024-11-24 02:17:50,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:17:50,305 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:17:50,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:17:50,305 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:17:50,306 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:17:50,306 INFO L87 Difference]: Start difference. First operand 16875 states and 23963 transitions. Second operand has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:17:50,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:17:50,522 INFO L93 Difference]: Finished difference Result 32262 states and 45830 transitions. [2024-11-24 02:17:50,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:17:50,523 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) Word has length 783 [2024-11-24 02:17:50,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:17:50,536 INFO L225 Difference]: With dead ends: 32262 [2024-11-24 02:17:50,536 INFO L226 Difference]: Without dead ends: 16875 [2024-11-24 02:17:50,546 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 783 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:17:50,546 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 0 mSDsluCounter, 4277 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5352 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:17:50,546 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5352 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:17:50,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16875 states. [2024-11-24 02:17:50,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16875 to 16875. [2024-11-24 02:17:50,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16875 states, 16765 states have (on average 1.415985684461676) internal successors, (23739), 16765 states have internal predecessors, (23739), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:17:50,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16875 states to 16875 states and 23955 transitions. [2024-11-24 02:17:50,780 INFO L78 Accepts]: Start accepts. Automaton has 16875 states and 23955 transitions. Word has length 783 [2024-11-24 02:17:50,780 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:17:50,780 INFO L471 AbstractCegarLoop]: Abstraction has 16875 states and 23955 transitions. [2024-11-24 02:17:50,781 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 90.8) internal successors, (454), 6 states have internal predecessors, (454), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:17:50,781 INFO L276 IsEmpty]: Start isEmpty. Operand 16875 states and 23955 transitions. [2024-11-24 02:17:50,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-24 02:17:50,793 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:17:50,794 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:17:50,818 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Forceful destruction successful, exit code 0 [2024-11-24 02:17:50,994 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable79 [2024-11-24 02:17:50,994 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:17:50,995 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:17:50,995 INFO L85 PathProgramCache]: Analyzing trace with hash -534796464, now seen corresponding path program 1 times [2024-11-24 02:17:50,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:17:50,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550320174] [2024-11-24 02:17:50,995 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:50,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:17:54,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:17:56,141 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 87 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-11-24 02:17:56,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:17:56,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550320174] [2024-11-24 02:17:56,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550320174] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:17:56,141 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:17:56,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:17:56,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769512405] [2024-11-24 02:17:56,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:17:56,142 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:17:56,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:17:56,143 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:17:56,143 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:17:56,143 INFO L87 Difference]: Start difference. First operand 16875 states and 23955 transitions. Second operand has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:17:56,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:17:56,363 INFO L93 Difference]: Finished difference Result 24378 states and 34590 transitions. [2024-11-24 02:17:56,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:17:56,363 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 785 [2024-11-24 02:17:56,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:17:56,378 INFO L225 Difference]: With dead ends: 24378 [2024-11-24 02:17:56,378 INFO L226 Difference]: Without dead ends: 16843 [2024-11-24 02:17:56,385 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:17:56,385 INFO L435 NwaCegarLoop]: 1070 mSDtfsCounter, 104 mSDsluCounter, 3195 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 104 SdHoareTripleChecker+Valid, 4265 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:17:56,385 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [104 Valid, 4265 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:17:56,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16843 states. [2024-11-24 02:17:56,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16843 to 16843. [2024-11-24 02:17:56,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16843 states, 16733 states have (on average 1.4158250164345902) internal successors, (23691), 16733 states have internal predecessors, (23691), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:17:56,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16843 states to 16843 states and 23907 transitions. [2024-11-24 02:17:56,687 INFO L78 Accepts]: Start accepts. Automaton has 16843 states and 23907 transitions. Word has length 785 [2024-11-24 02:17:56,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:17:56,687 INFO L471 AbstractCegarLoop]: Abstraction has 16843 states and 23907 transitions. [2024-11-24 02:17:56,688 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 105.2) internal successors, (526), 5 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:17:56,688 INFO L276 IsEmpty]: Start isEmpty. Operand 16843 states and 23907 transitions. [2024-11-24 02:17:56,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-24 02:17:56,701 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:17:56,702 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:17:56,702 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-11-24 02:17:56,702 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:17:56,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:17:56,702 INFO L85 PathProgramCache]: Analyzing trace with hash -2123494800, now seen corresponding path program 1 times [2024-11-24 02:17:56,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:17:56,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005413735] [2024-11-24 02:17:56,703 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:17:56,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:02,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:03,510 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 80 proven. 18 refuted. 0 times theorem prover too weak. 772 trivial. 0 not checked. [2024-11-24 02:18:03,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:03,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005413735] [2024-11-24 02:18:03,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005413735] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:18:03,511 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [56808734] [2024-11-24 02:18:03,511 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:03,511 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:18:03,511 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:18:03,512 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:18:03,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-11-24 02:18:10,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:10,461 INFO L256 TraceCheckSpWp]: Trace formula consists of 3748 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-24 02:18:10,468 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:18:10,490 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 176 proven. 0 refuted. 0 times theorem prover too weak. 694 trivial. 0 not checked. [2024-11-24 02:18:10,490 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:18:10,490 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [56808734] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:10,490 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-24 02:18:10,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-11-24 02:18:10,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1036489678] [2024-11-24 02:18:10,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:10,491 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:18:10,491 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:10,492 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:18:10,492 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:18:10,492 INFO L87 Difference]: Start difference. First operand 16843 states and 23907 transitions. Second operand has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-11-24 02:18:10,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:10,733 INFO L93 Difference]: Finished difference Result 31042 states and 44062 transitions. [2024-11-24 02:18:10,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:18:10,734 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) Word has length 785 [2024-11-24 02:18:10,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:10,749 INFO L225 Difference]: With dead ends: 31042 [2024-11-24 02:18:10,749 INFO L226 Difference]: Without dead ends: 16843 [2024-11-24 02:18:10,759 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 790 GetRequests, 785 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:18:10,759 INFO L435 NwaCegarLoop]: 1072 mSDtfsCounter, 0 mSDsluCounter, 4269 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5341 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:10,759 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5341 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:18:10,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16843 states. [2024-11-24 02:18:10,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16843 to 16795. [2024-11-24 02:18:11,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4155828588552593) internal successors, (23619), 16685 states have internal predecessors, (23619), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:18:11,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23835 transitions. [2024-11-24 02:18:11,024 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23835 transitions. Word has length 785 [2024-11-24 02:18:11,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:11,025 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23835 transitions. [2024-11-24 02:18:11,025 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 102.8) internal successors, (514), 6 states have internal predecessors, (514), 3 states have call successors, (9), 2 states have call predecessors, (9), 3 states have return successors, (9), 2 states have call predecessors, (9), 3 states have call successors, (9) [2024-11-24 02:18:11,025 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23835 transitions. [2024-11-24 02:18:11,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-24 02:18:11,039 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:11,040 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:11,071 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Forceful destruction successful, exit code 0 [2024-11-24 02:18:11,240 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:18:11,240 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:11,241 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:11,241 INFO L85 PathProgramCache]: Analyzing trace with hash -1141675208, now seen corresponding path program 1 times [2024-11-24 02:18:11,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:11,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [266439826] [2024-11-24 02:18:11,241 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:11,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:14,299 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 804 trivial. 0 not checked. [2024-11-24 02:18:14,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:14,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [266439826] [2024-11-24 02:18:14,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [266439826] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:14,300 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:18:14,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 02:18:14,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89764868] [2024-11-24 02:18:14,300 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:14,300 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 02:18:14,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:14,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 02:18:14,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 02:18:14,302 INFO L87 Difference]: Start difference. First operand 16795 states and 23835 transitions. Second operand has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-24 02:18:14,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:14,698 INFO L93 Difference]: Finished difference Result 31042 states and 44044 transitions. [2024-11-24 02:18:14,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 02:18:14,699 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 785 [2024-11-24 02:18:14,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:14,717 INFO L225 Difference]: With dead ends: 31042 [2024-11-24 02:18:14,718 INFO L226 Difference]: Without dead ends: 16795 [2024-11-24 02:18:14,726 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:18:14,726 INFO L435 NwaCegarLoop]: 1062 mSDtfsCounter, 951 mSDsluCounter, 1069 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 953 SdHoareTripleChecker+Valid, 2131 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:14,726 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [953 Valid, 2131 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:18:14,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16795 states. [2024-11-24 02:18:14,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16795 to 16795. [2024-11-24 02:18:14,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16795 states, 16685 states have (on average 1.4141444411147737) internal successors, (23595), 16685 states have internal predecessors, (23595), 108 states have call successors, (108), 1 states have call predecessors, (108), 1 states have return successors, (108), 108 states have call predecessors, (108), 108 states have call successors, (108) [2024-11-24 02:18:14,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16795 states to 16795 states and 23811 transitions. [2024-11-24 02:18:14,988 INFO L78 Accepts]: Start accepts. Automaton has 16795 states and 23811 transitions. Word has length 785 [2024-11-24 02:18:14,989 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:14,989 INFO L471 AbstractCegarLoop]: Abstraction has 16795 states and 23811 transitions. [2024-11-24 02:18:14,989 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 126.0) internal successors, (504), 4 states have internal predecessors, (504), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-24 02:18:14,989 INFO L276 IsEmpty]: Start isEmpty. Operand 16795 states and 23811 transitions. [2024-11-24 02:18:15,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-24 02:18:15,003 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:15,004 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:15,004 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-11-24 02:18:15,004 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:15,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:15,004 INFO L85 PathProgramCache]: Analyzing trace with hash -967026906, now seen corresponding path program 1 times [2024-11-24 02:18:15,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:15,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853003659] [2024-11-24 02:18:15,005 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:15,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:20,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:25,378 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 852 trivial. 0 not checked. [2024-11-24 02:18:25,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:25,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853003659] [2024-11-24 02:18:25,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853003659] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:25,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:18:25,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2024-11-24 02:18:25,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447998330] [2024-11-24 02:18:25,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:25,379 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-11-24 02:18:25,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:25,380 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-11-24 02:18:25,380 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-24 02:18:25,381 INFO L87 Difference]: Start difference. First operand 16795 states and 23811 transitions. Second operand has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:27,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:27,606 INFO L93 Difference]: Finished difference Result 52833 states and 75280 transitions. [2024-11-24 02:18:27,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 02:18:27,607 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 787 [2024-11-24 02:18:27,607 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:27,638 INFO L225 Difference]: With dead ends: 52833 [2024-11-24 02:18:27,638 INFO L226 Difference]: Without dead ends: 38955 [2024-11-24 02:18:27,652 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2024-11-24 02:18:27,652 INFO L435 NwaCegarLoop]: 786 mSDtfsCounter, 2792 mSDsluCounter, 5550 mSDsCounter, 0 mSdLazyCounter, 2472 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2806 SdHoareTripleChecker+Valid, 6336 SdHoareTripleChecker+Invalid, 2477 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 2472 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.8s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:27,653 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2806 Valid, 6336 Invalid, 2477 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 2472 Invalid, 0 Unknown, 0 Unchecked, 1.8s Time] [2024-11-24 02:18:27,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38955 states. [2024-11-24 02:18:27,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38955 to 17324. [2024-11-24 02:18:28,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17324 states, 17205 states have (on average 1.4129032258064516) internal successors, (24309), 17205 states have internal predecessors, (24309), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-11-24 02:18:28,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17324 states to 17324 states and 24543 transitions. [2024-11-24 02:18:28,029 INFO L78 Accepts]: Start accepts. Automaton has 17324 states and 24543 transitions. Word has length 787 [2024-11-24 02:18:28,030 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:28,030 INFO L471 AbstractCegarLoop]: Abstraction has 17324 states and 24543 transitions. [2024-11-24 02:18:28,030 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 41.90909090909091) internal successors, (461), 11 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:28,030 INFO L276 IsEmpty]: Start isEmpty. Operand 17324 states and 24543 transitions. [2024-11-24 02:18:28,045 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-24 02:18:28,045 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:28,045 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:28,045 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable83 [2024-11-24 02:18:28,045 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:28,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:28,046 INFO L85 PathProgramCache]: Analyzing trace with hash 848315724, now seen corresponding path program 1 times [2024-11-24 02:18:28,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:28,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409262450] [2024-11-24 02:18:28,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:28,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:31,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:34,412 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 193 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:18:34,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:34,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409262450] [2024-11-24 02:18:34,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409262450] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:34,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:18:34,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:18:34,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642951464] [2024-11-24 02:18:34,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:34,413 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:18:34,413 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:34,414 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:18:34,414 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:18:34,415 INFO L87 Difference]: Start difference. First operand 17324 states and 24543 transitions. Second operand has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:18:34,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:34,730 INFO L93 Difference]: Finished difference Result 21988 states and 31111 transitions. [2024-11-24 02:18:34,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:18:34,731 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 787 [2024-11-24 02:18:34,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:34,745 INFO L225 Difference]: With dead ends: 21988 [2024-11-24 02:18:34,745 INFO L226 Difference]: Without dead ends: 17324 [2024-11-24 02:18:34,751 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:18:34,752 INFO L435 NwaCegarLoop]: 1061 mSDtfsCounter, 415 mSDsluCounter, 5659 mSDsCounter, 0 mSdLazyCounter, 103 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 415 SdHoareTripleChecker+Valid, 6720 SdHoareTripleChecker+Invalid, 105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 103 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:34,752 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [415 Valid, 6720 Invalid, 105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 103 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:18:34,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17324 states. [2024-11-24 02:18:35,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17324 to 14024. [2024-11-24 02:18:35,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14024 states, 13905 states have (on average 1.406616325062927) internal successors, (19559), 13905 states have internal predecessors, (19559), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-11-24 02:18:35,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14024 states to 14024 states and 19793 transitions. [2024-11-24 02:18:35,118 INFO L78 Accepts]: Start accepts. Automaton has 14024 states and 19793 transitions. Word has length 787 [2024-11-24 02:18:35,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:35,118 INFO L471 AbstractCegarLoop]: Abstraction has 14024 states and 19793 transitions. [2024-11-24 02:18:35,118 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 78.5) internal successors, (628), 8 states have internal predecessors, (628), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-24 02:18:35,118 INFO L276 IsEmpty]: Start isEmpty. Operand 14024 states and 19793 transitions. [2024-11-24 02:18:35,133 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-24 02:18:35,133 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:35,133 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:35,133 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84 [2024-11-24 02:18:35,134 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:35,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:35,134 INFO L85 PathProgramCache]: Analyzing trace with hash -304177618, now seen corresponding path program 1 times [2024-11-24 02:18:35,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:35,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485872619] [2024-11-24 02:18:35,135 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:35,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:38,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:40,104 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 854 trivial. 0 not checked. [2024-11-24 02:18:40,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:40,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485872619] [2024-11-24 02:18:40,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485872619] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:40,105 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:18:40,105 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:18:40,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556803659] [2024-11-24 02:18:40,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:40,105 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:18:40,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:40,106 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:18:40,106 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:18:40,106 INFO L87 Difference]: Start difference. First operand 14024 states and 19793 transitions. Second operand has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:40,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:40,304 INFO L93 Difference]: Finished difference Result 24647 states and 34877 transitions. [2024-11-24 02:18:40,305 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:18:40,305 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 787 [2024-11-24 02:18:40,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:40,318 INFO L225 Difference]: With dead ends: 24647 [2024-11-24 02:18:40,318 INFO L226 Difference]: Without dead ends: 14006 [2024-11-24 02:18:40,328 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:18:40,329 INFO L435 NwaCegarLoop]: 1071 mSDtfsCounter, 1 mSDsluCounter, 1068 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2139 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:40,329 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2139 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:18:40,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14006 states. [2024-11-24 02:18:40,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14006 to 13997. [2024-11-24 02:18:40,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13997 states, 13878 states have (on average 1.4058942210693184) internal successors, (19511), 13878 states have internal predecessors, (19511), 117 states have call successors, (117), 1 states have call predecessors, (117), 1 states have return successors, (117), 117 states have call predecessors, (117), 117 states have call successors, (117) [2024-11-24 02:18:40,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13997 states to 13997 states and 19745 transitions. [2024-11-24 02:18:40,623 INFO L78 Accepts]: Start accepts. Automaton has 13997 states and 19745 transitions. Word has length 787 [2024-11-24 02:18:40,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:40,623 INFO L471 AbstractCegarLoop]: Abstraction has 13997 states and 19745 transitions. [2024-11-24 02:18:40,623 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 153.33333333333334) internal successors, (460), 3 states have internal predecessors, (460), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:40,623 INFO L276 IsEmpty]: Start isEmpty. Operand 13997 states and 19745 transitions. [2024-11-24 02:18:40,636 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-11-24 02:18:40,636 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:40,637 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:40,637 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-11-24 02:18:40,637 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:40,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:40,638 INFO L85 PathProgramCache]: Analyzing trace with hash 689269577, now seen corresponding path program 1 times [2024-11-24 02:18:40,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:40,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529227185] [2024-11-24 02:18:40,638 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:40,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:46,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:18:51,252 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 852 trivial. 0 not checked. [2024-11-24 02:18:51,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:18:51,252 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1529227185] [2024-11-24 02:18:51,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1529227185] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:18:51,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:18:51,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-24 02:18:51,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [520151410] [2024-11-24 02:18:51,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:18:51,254 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-24 02:18:51,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:18:51,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-24 02:18:51,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:18:51,254 INFO L87 Difference]: Start difference. First operand 13997 states and 19745 transitions. Second operand has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:51,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:18:51,638 INFO L93 Difference]: Finished difference Result 19522 states and 27591 transitions. [2024-11-24 02:18:51,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-24 02:18:51,639 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 788 [2024-11-24 02:18:51,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:18:51,650 INFO L225 Difference]: With dead ends: 19522 [2024-11-24 02:18:51,650 INFO L226 Difference]: Without dead ends: 12169 [2024-11-24 02:18:51,656 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:18:51,656 INFO L435 NwaCegarLoop]: 1054 mSDtfsCounter, 1016 mSDsluCounter, 5225 mSDsCounter, 0 mSdLazyCounter, 174 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1021 SdHoareTripleChecker+Valid, 6279 SdHoareTripleChecker+Invalid, 174 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 174 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:18:51,656 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1021 Valid, 6279 Invalid, 174 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 174 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:18:51,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12169 states. [2024-11-24 02:18:51,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12169 to 12153. [2024-11-24 02:18:51,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12153 states, 12066 states have (on average 1.4099950273495774) internal successors, (17013), 12066 states have internal predecessors, (17013), 85 states have call successors, (85), 1 states have call predecessors, (85), 1 states have return successors, (85), 85 states have call predecessors, (85), 85 states have call successors, (85) [2024-11-24 02:18:51,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12153 states to 12153 states and 17183 transitions. [2024-11-24 02:18:51,872 INFO L78 Accepts]: Start accepts. Automaton has 12153 states and 17183 transitions. Word has length 788 [2024-11-24 02:18:51,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:18:51,873 INFO L471 AbstractCegarLoop]: Abstraction has 12153 states and 17183 transitions. [2024-11-24 02:18:51,873 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 57.875) internal successors, (463), 8 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-24 02:18:51,873 INFO L276 IsEmpty]: Start isEmpty. Operand 12153 states and 17183 transitions. [2024-11-24 02:18:51,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-11-24 02:18:51,884 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:18:51,884 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:18:51,884 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86 [2024-11-24 02:18:51,884 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:18:51,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:18:51,885 INFO L85 PathProgramCache]: Analyzing trace with hash 1345986953, now seen corresponding path program 1 times [2024-11-24 02:18:51,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:18:51,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358228373] [2024-11-24 02:18:51,886 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:18:51,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:18:57,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:02,103 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 88 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-11-24 02:19:02,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:19:02,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [358228373] [2024-11-24 02:19:02,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [358228373] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:19:02,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:19:02,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-24 02:19:02,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801341478] [2024-11-24 02:19:02,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:19:02,104 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-24 02:19:02,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:19:02,105 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-24 02:19:02,105 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:19:02,105 INFO L87 Difference]: Start difference. First operand 12153 states and 17183 transitions. Second operand has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:02,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:19:02,692 INFO L93 Difference]: Finished difference Result 35062 states and 49577 transitions. [2024-11-24 02:19:02,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-24 02:19:02,693 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-11-24 02:19:02,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:19:02,722 INFO L225 Difference]: With dead ends: 35062 [2024-11-24 02:19:02,723 INFO L226 Difference]: Without dead ends: 30405 [2024-11-24 02:19:02,732 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-11-24 02:19:02,732 INFO L435 NwaCegarLoop]: 1060 mSDtfsCounter, 2838 mSDsluCounter, 7218 mSDsCounter, 0 mSdLazyCounter, 148 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2848 SdHoareTripleChecker+Valid, 8278 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 148 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:19:02,732 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2848 Valid, 8278 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 148 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:19:02,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30405 states. [2024-11-24 02:19:03,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30405 to 12585. [2024-11-24 02:19:03,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12585 states, 12498 states have (on average 1.4121459433509362) internal successors, (17649), 12498 states have internal predecessors, (17649), 85 states have call successors, (85), 1 states have call predecessors, (85), 1 states have return successors, (85), 85 states have call predecessors, (85), 85 states have call successors, (85) [2024-11-24 02:19:03,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12585 states to 12585 states and 17819 transitions. [2024-11-24 02:19:03,042 INFO L78 Accepts]: Start accepts. Automaton has 12585 states and 17819 transitions. Word has length 788 [2024-11-24 02:19:03,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:19:03,042 INFO L471 AbstractCegarLoop]: Abstraction has 12585 states and 17819 transitions. [2024-11-24 02:19:03,043 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 58.666666666666664) internal successors, (528), 9 states have internal predecessors, (528), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:03,043 INFO L276 IsEmpty]: Start isEmpty. Operand 12585 states and 17819 transitions. [2024-11-24 02:19:03,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-11-24 02:19:03,054 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:19:03,055 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:19:03,055 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-11-24 02:19:03,055 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:19:03,055 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:19:03,055 INFO L85 PathProgramCache]: Analyzing trace with hash -1698584879, now seen corresponding path program 1 times [2024-11-24 02:19:03,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:19:03,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550857861] [2024-11-24 02:19:03,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:19:03,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:19:06,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:09,167 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 781 trivial. 0 not checked. [2024-11-24 02:19:09,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:19:09,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550857861] [2024-11-24 02:19:09,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550857861] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:19:09,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:19:09,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:19:09,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [423800498] [2024-11-24 02:19:09,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:19:09,168 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:19:09,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:19:09,169 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:19:09,169 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:19:09,169 INFO L87 Difference]: Start difference. First operand 12585 states and 17819 transitions. Second operand has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:09,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:19:09,554 INFO L93 Difference]: Finished difference Result 19871 states and 28122 transitions. [2024-11-24 02:19:09,554 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:19:09,554 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-11-24 02:19:09,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:19:09,571 INFO L225 Difference]: With dead ends: 19871 [2024-11-24 02:19:09,571 INFO L226 Difference]: Without dead ends: 14012 [2024-11-24 02:19:09,579 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:19:09,580 INFO L435 NwaCegarLoop]: 1255 mSDtfsCounter, 201 mSDsluCounter, 2493 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 201 SdHoareTripleChecker+Valid, 3748 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:19:09,580 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [201 Valid, 3748 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:19:09,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14012 states. [2024-11-24 02:19:09,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14012 to 13980. [2024-11-24 02:19:09,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13980 states, 13854 states have (on average 1.4082575429478852) internal successors, (19510), 13854 states have internal predecessors, (19510), 124 states have call successors, (124), 1 states have call predecessors, (124), 1 states have return successors, (124), 124 states have call predecessors, (124), 124 states have call successors, (124) [2024-11-24 02:19:09,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13980 states to 13980 states and 19758 transitions. [2024-11-24 02:19:09,921 INFO L78 Accepts]: Start accepts. Automaton has 13980 states and 19758 transitions. Word has length 788 [2024-11-24 02:19:09,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:19:09,921 INFO L471 AbstractCegarLoop]: Abstraction has 13980 states and 19758 transitions. [2024-11-24 02:19:09,922 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 88.16666666666667) internal successors, (529), 6 states have internal predecessors, (529), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:09,922 INFO L276 IsEmpty]: Start isEmpty. Operand 13980 states and 19758 transitions. [2024-11-24 02:19:09,935 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-24 02:19:09,935 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:19:09,935 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:19:09,935 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88 [2024-11-24 02:19:09,935 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:19:09,936 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:19:09,936 INFO L85 PathProgramCache]: Analyzing trace with hash -1068037669, now seen corresponding path program 1 times [2024-11-24 02:19:09,936 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:19:09,936 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1840767278] [2024-11-24 02:19:09,936 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:19:09,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:19:16,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:18,259 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 682 trivial. 0 not checked. [2024-11-24 02:19:18,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:19:18,259 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1840767278] [2024-11-24 02:19:18,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1840767278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:19:18,259 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:19:18,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:19:18,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892493213] [2024-11-24 02:19:18,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:19:18,260 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:19:18,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:19:18,261 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:19:18,261 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:19:18,261 INFO L87 Difference]: Start difference. First operand 13980 states and 19758 transitions. Second operand has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:18,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:19:18,632 INFO L93 Difference]: Finished difference Result 28880 states and 40698 transitions. [2024-11-24 02:19:18,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:19:18,632 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 789 [2024-11-24 02:19:18,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:19:18,652 INFO L225 Difference]: With dead ends: 28880 [2024-11-24 02:19:18,652 INFO L226 Difference]: Without dead ends: 24505 [2024-11-24 02:19:18,659 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:19:18,660 INFO L435 NwaCegarLoop]: 1068 mSDtfsCounter, 756 mSDsluCounter, 4257 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 756 SdHoareTripleChecker+Valid, 5325 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:19:18,660 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [756 Valid, 5325 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:19:18,671 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24505 states. [2024-11-24 02:19:19,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24505 to 22848. [2024-11-24 02:19:19,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22848 states, 22626 states have (on average 1.4114735260319986) internal successors, (31936), 22626 states have internal predecessors, (31936), 220 states have call successors, (220), 1 states have call predecessors, (220), 1 states have return successors, (220), 220 states have call predecessors, (220), 220 states have call successors, (220) [2024-11-24 02:19:19,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22848 states to 22848 states and 32376 transitions. [2024-11-24 02:19:19,400 INFO L78 Accepts]: Start accepts. Automaton has 22848 states and 32376 transitions. Word has length 789 [2024-11-24 02:19:19,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:19:19,401 INFO L471 AbstractCegarLoop]: Abstraction has 22848 states and 32376 transitions. [2024-11-24 02:19:19,401 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 104.5) internal successors, (627), 6 states have internal predecessors, (627), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:19,401 INFO L276 IsEmpty]: Start isEmpty. Operand 22848 states and 32376 transitions. [2024-11-24 02:19:19,419 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-24 02:19:19,419 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:19:19,419 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:19:19,419 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable89 [2024-11-24 02:19:19,420 INFO L396 AbstractCegarLoop]: === Iteration 91 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:19:19,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:19:19,420 INFO L85 PathProgramCache]: Analyzing trace with hash 1666567700, now seen corresponding path program 1 times [2024-11-24 02:19:19,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:19:19,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438926578] [2024-11-24 02:19:19,420 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:19:19,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:19:24,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:26,418 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 182 proven. 0 refuted. 0 times theorem prover too weak. 685 trivial. 0 not checked. [2024-11-24 02:19:26,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:19:26,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438926578] [2024-11-24 02:19:26,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438926578] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:19:26,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:19:26,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-24 02:19:26,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184546848] [2024-11-24 02:19:26,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:19:26,420 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:19:26,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:19:26,421 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:19:26,421 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:19:26,421 INFO L87 Difference]: Start difference. First operand 22848 states and 32376 transitions. Second operand has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:27,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:19:27,065 INFO L93 Difference]: Finished difference Result 27827 states and 39341 transitions. [2024-11-24 02:19:27,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-24 02:19:27,066 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 790 [2024-11-24 02:19:27,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:19:27,089 INFO L225 Difference]: With dead ends: 27827 [2024-11-24 02:19:27,089 INFO L226 Difference]: Without dead ends: 23128 [2024-11-24 02:19:27,098 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-24 02:19:27,098 INFO L435 NwaCegarLoop]: 1010 mSDtfsCounter, 834 mSDsluCounter, 4008 mSDsCounter, 0 mSdLazyCounter, 356 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 834 SdHoareTripleChecker+Valid, 5018 SdHoareTripleChecker+Invalid, 358 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 356 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:19:27,098 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [834 Valid, 5018 Invalid, 358 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 356 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:19:27,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23128 states. [2024-11-24 02:19:27,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23128 to 23128. [2024-11-24 02:19:27,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23128 states, 22906 states have (on average 1.408888500829477) internal successors, (32272), 22906 states have internal predecessors, (32272), 220 states have call successors, (220), 1 states have call predecessors, (220), 1 states have return successors, (220), 220 states have call predecessors, (220), 220 states have call successors, (220) [2024-11-24 02:19:27,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23128 states to 23128 states and 32712 transitions. [2024-11-24 02:19:27,556 INFO L78 Accepts]: Start accepts. Automaton has 23128 states and 32712 transitions. Word has length 790 [2024-11-24 02:19:27,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:19:27,557 INFO L471 AbstractCegarLoop]: Abstraction has 23128 states and 32712 transitions. [2024-11-24 02:19:27,557 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 89.42857142857143) internal successors, (626), 7 states have internal predecessors, (626), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:19:27,557 INFO L276 IsEmpty]: Start isEmpty. Operand 23128 states and 32712 transitions. [2024-11-24 02:19:27,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-24 02:19:27,578 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:19:27,578 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:19:27,579 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable90 [2024-11-24 02:19:27,579 INFO L396 AbstractCegarLoop]: === Iteration 92 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:19:27,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:19:27,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1138924976, now seen corresponding path program 1 times [2024-11-24 02:19:27,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:19:27,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1825460310] [2024-11-24 02:19:27,580 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:19:27,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:19:35,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:38,548 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 122 proven. 70 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:19:38,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:19:38,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1825460310] [2024-11-24 02:19:38,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1825460310] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:19:38,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1071149257] [2024-11-24 02:19:38,549 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:19:38,549 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:19:38,549 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:19:38,556 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:19:38,558 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2024-11-24 02:19:50,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:19:50,394 INFO L256 TraceCheckSpWp]: Trace formula consists of 3757 conjuncts, 205 conjuncts are in the unsatisfiable core [2024-11-24 02:19:50,412 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:19:54,642 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 273 proven. 66 refuted. 0 times theorem prover too weak. 529 trivial. 0 not checked. [2024-11-24 02:19:54,642 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:20:01,248 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 109 proven. 83 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:20:01,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1071149257] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:20:01,249 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:20:01,249 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 36, 31] total 71 [2024-11-24 02:20:01,249 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236216598] [2024-11-24 02:20:01,249 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:20:01,251 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 71 states [2024-11-24 02:20:01,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:20:01,253 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2024-11-24 02:20:01,254 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=942, Invalid=4028, Unknown=0, NotChecked=0, Total=4970 [2024-11-24 02:20:01,255 INFO L87 Difference]: Start difference. First operand 23128 states and 32712 transitions. Second operand has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) [2024-11-24 02:20:20,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:20:20,952 INFO L93 Difference]: Finished difference Result 37018 states and 52012 transitions. [2024-11-24 02:20:20,952 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2024-11-24 02:20:20,952 INFO L78 Accepts]: Start accepts. Automaton has has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) Word has length 790 [2024-11-24 02:20:20,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:20:20,983 INFO L225 Difference]: With dead ends: 37018 [2024-11-24 02:20:20,983 INFO L226 Difference]: Without dead ends: 33444 [2024-11-24 02:20:20,993 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1667 GetRequests, 1523 SyntacticMatches, 0 SemanticMatches, 144 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5781 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=3269, Invalid=17901, Unknown=0, NotChecked=0, Total=21170 [2024-11-24 02:20:20,994 INFO L435 NwaCegarLoop]: 1634 mSDtfsCounter, 16618 mSDsluCounter, 37666 mSDsCounter, 0 mSdLazyCounter, 21490 mSolverCounterSat, 86 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 12.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16618 SdHoareTripleChecker+Valid, 39300 SdHoareTripleChecker+Invalid, 21576 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 86 IncrementalHoareTripleChecker+Valid, 21490 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 14.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:20:20,994 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16618 Valid, 39300 Invalid, 21576 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [86 Valid, 21490 Invalid, 0 Unknown, 0 Unchecked, 14.3s Time] [2024-11-24 02:20:21,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33444 states. [2024-11-24 02:20:21,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33444 to 25209. [2024-11-24 02:20:21,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25209 states, 24961 states have (on average 1.403108849805697) internal successors, (35023), 24961 states have internal predecessors, (35023), 246 states have call successors, (246), 1 states have call predecessors, (246), 1 states have return successors, (246), 246 states have call predecessors, (246), 246 states have call successors, (246) [2024-11-24 02:20:21,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25209 states to 25209 states and 35515 transitions. [2024-11-24 02:20:21,635 INFO L78 Accepts]: Start accepts. Automaton has 25209 states and 35515 transitions. Word has length 790 [2024-11-24 02:20:21,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:20:21,636 INFO L471 AbstractCegarLoop]: Abstraction has 25209 states and 35515 transitions. [2024-11-24 02:20:21,636 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 71 states, 71 states have (on average 23.380281690140844) internal successors, (1660), 71 states have internal predecessors, (1660), 9 states have call successors, (30), 2 states have call predecessors, (30), 2 states have return successors, (30), 9 states have call predecessors, (30), 9 states have call successors, (30) [2024-11-24 02:20:21,636 INFO L276 IsEmpty]: Start isEmpty. Operand 25209 states and 35515 transitions. [2024-11-24 02:20:21,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2024-11-24 02:20:21,659 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:20:21,659 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:20:21,697 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Ended with exit code 0 [2024-11-24 02:20:21,860 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable91,37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:20:21,860 INFO L396 AbstractCegarLoop]: === Iteration 93 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:20:21,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:20:21,861 INFO L85 PathProgramCache]: Analyzing trace with hash 1029824092, now seen corresponding path program 1 times [2024-11-24 02:20:21,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:20:21,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011715784] [2024-11-24 02:20:21,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:20:21,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:20:27,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:20:28,945 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 128 proven. 3 refuted. 0 times theorem prover too weak. 738 trivial. 0 not checked. [2024-11-24 02:20:28,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:20:28,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011715784] [2024-11-24 02:20:28,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011715784] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:20:28,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1505160678] [2024-11-24 02:20:28,945 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:20:28,945 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:20:28,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:20:28,947 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:20:28,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2024-11-24 02:20:41,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:20:41,265 INFO L256 TraceCheckSpWp]: Trace formula consists of 3758 conjuncts, 192 conjuncts are in the unsatisfiable core [2024-11-24 02:20:41,281 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:20:46,908 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 273 proven. 52 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2024-11-24 02:20:46,908 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:20:55,853 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 212 proven. 17 refuted. 0 times theorem prover too weak. 640 trivial. 0 not checked. [2024-11-24 02:20:55,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1505160678] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:20:55,854 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 02:20:55,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 36, 33] total 72 [2024-11-24 02:20:55,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886577479] [2024-11-24 02:20:55,854 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 02:20:55,855 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2024-11-24 02:20:55,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:20:55,857 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2024-11-24 02:20:55,857 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1021, Invalid=4091, Unknown=0, NotChecked=0, Total=5112 [2024-11-24 02:20:55,858 INFO L87 Difference]: Start difference. First operand 25209 states and 35515 transitions. Second operand has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) [2024-11-24 02:21:12,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:21:12,515 INFO L93 Difference]: Finished difference Result 57810 states and 81319 transitions. [2024-11-24 02:21:12,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2024-11-24 02:21:12,516 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) Word has length 791 [2024-11-24 02:21:12,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:21:12,552 INFO L225 Difference]: With dead ends: 57810 [2024-11-24 02:21:12,552 INFO L226 Difference]: Without dead ends: 39730 [2024-11-24 02:21:12,570 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1633 GetRequests, 1517 SyntacticMatches, 1 SemanticMatches, 115 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3716 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=2601, Invalid=10971, Unknown=0, NotChecked=0, Total=13572 [2024-11-24 02:21:12,571 INFO L435 NwaCegarLoop]: 1314 mSDtfsCounter, 11764 mSDsluCounter, 37042 mSDsCounter, 0 mSdLazyCounter, 18460 mSolverCounterSat, 42 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 11.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 11773 SdHoareTripleChecker+Valid, 38356 SdHoareTripleChecker+Invalid, 18502 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 42 IncrementalHoareTripleChecker+Valid, 18460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 12.6s IncrementalHoareTripleChecker+Time [2024-11-24 02:21:12,571 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [11773 Valid, 38356 Invalid, 18502 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [42 Valid, 18460 Invalid, 0 Unknown, 0 Unchecked, 12.6s Time] [2024-11-24 02:21:12,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39730 states. [2024-11-24 02:21:13,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39730 to 25133. [2024-11-24 02:21:13,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25133 states, 24881 states have (on average 1.4011896627949036) internal successors, (34863), 24881 states have internal predecessors, (34863), 250 states have call successors, (250), 1 states have call predecessors, (250), 1 states have return successors, (250), 250 states have call predecessors, (250), 250 states have call successors, (250) [2024-11-24 02:21:13,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25133 states to 25133 states and 35363 transitions. [2024-11-24 02:21:13,180 INFO L78 Accepts]: Start accepts. Automaton has 25133 states and 35363 transitions. Word has length 791 [2024-11-24 02:21:13,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:21:13,180 INFO L471 AbstractCegarLoop]: Abstraction has 25133 states and 35363 transitions. [2024-11-24 02:21:13,181 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 21.430555555555557) internal successors, (1543), 72 states have internal predecessors, (1543), 8 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 8 states have call predecessors, (25), 8 states have call successors, (25) [2024-11-24 02:21:13,181 INFO L276 IsEmpty]: Start isEmpty. Operand 25133 states and 35363 transitions. [2024-11-24 02:21:13,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-11-24 02:21:13,204 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:21:13,204 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:21:13,241 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2024-11-24 02:21:13,405 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable92,38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:21:13,405 INFO L396 AbstractCegarLoop]: === Iteration 94 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:21:13,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:21:13,405 INFO L85 PathProgramCache]: Analyzing trace with hash -2126866009, now seen corresponding path program 1 times [2024-11-24 02:21:13,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:21:13,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494568801] [2024-11-24 02:21:13,406 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:21:13,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:21:19,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:21:23,782 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 195 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-24 02:21:23,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:21:23,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494568801] [2024-11-24 02:21:23,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494568801] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:21:23,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:21:23,782 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-24 02:21:23,782 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1600655539] [2024-11-24 02:21:23,782 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:21:23,783 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-24 02:21:23,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:21:23,784 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-24 02:21:23,784 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-11-24 02:21:23,784 INFO L87 Difference]: Start difference. First operand 25133 states and 35363 transitions. Second operand has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:21:24,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:21:24,546 INFO L93 Difference]: Finished difference Result 35453 states and 49672 transitions. [2024-11-24 02:21:24,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-24 02:21:24,547 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 792 [2024-11-24 02:21:24,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:21:24,579 INFO L225 Difference]: With dead ends: 35453 [2024-11-24 02:21:24,579 INFO L226 Difference]: Without dead ends: 30391 [2024-11-24 02:21:24,589 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:21:24,589 INFO L435 NwaCegarLoop]: 1955 mSDtfsCounter, 1199 mSDsluCounter, 12769 mSDsCounter, 0 mSdLazyCounter, 178 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1204 SdHoareTripleChecker+Valid, 14724 SdHoareTripleChecker+Invalid, 179 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 178 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:21:24,590 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1204 Valid, 14724 Invalid, 179 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 178 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:21:24,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30391 states. [2024-11-24 02:21:25,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30391 to 25435. [2024-11-24 02:21:25,182 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25435 states, 25183 states have (on average 1.400031767462177) internal successors, (35257), 25183 states have internal predecessors, (35257), 250 states have call successors, (250), 1 states have call predecessors, (250), 1 states have return successors, (250), 250 states have call predecessors, (250), 250 states have call successors, (250) [2024-11-24 02:21:25,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25435 states to 25435 states and 35757 transitions. [2024-11-24 02:21:25,215 INFO L78 Accepts]: Start accepts. Automaton has 25435 states and 35757 transitions. Word has length 792 [2024-11-24 02:21:25,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:21:25,216 INFO L471 AbstractCegarLoop]: Abstraction has 25435 states and 35757 transitions. [2024-11-24 02:21:25,216 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 63.3) internal successors, (633), 10 states have internal predecessors, (633), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:21:25,216 INFO L276 IsEmpty]: Start isEmpty. Operand 25435 states and 35757 transitions. [2024-11-24 02:21:25,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-11-24 02:21:25,239 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:21:25,239 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:21:25,239 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable93 [2024-11-24 02:21:25,239 INFO L396 AbstractCegarLoop]: === Iteration 95 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:21:25,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:21:25,240 INFO L85 PathProgramCache]: Analyzing trace with hash 2061226320, now seen corresponding path program 1 times [2024-11-24 02:21:25,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:21:25,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [33108247] [2024-11-24 02:21:25,240 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:21:25,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:21:31,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:21:34,378 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-11-24 02:21:34,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 02:21:34,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [33108247] [2024-11-24 02:21:34,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [33108247] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:21:34,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:21:34,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 02:21:34,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258345651] [2024-11-24 02:21:34,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:21:34,379 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 02:21:34,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 02:21:34,380 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 02:21:34,380 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-24 02:21:34,380 INFO L87 Difference]: Start difference. First operand 25435 states and 35757 transitions. Second operand has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-24 02:21:35,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:21:35,065 INFO L93 Difference]: Finished difference Result 42939 states and 60321 transitions. [2024-11-24 02:21:35,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:21:35,065 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 792 [2024-11-24 02:21:35,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:21:35,103 INFO L225 Difference]: With dead ends: 42939 [2024-11-24 02:21:35,103 INFO L226 Difference]: Without dead ends: 33011 [2024-11-24 02:21:35,120 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:21:35,121 INFO L435 NwaCegarLoop]: 1289 mSDtfsCounter, 126 mSDsluCounter, 4912 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 126 SdHoareTripleChecker+Valid, 6201 SdHoareTripleChecker+Invalid, 64 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:21:35,121 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [126 Valid, 6201 Invalid, 64 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:21:35,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33011 states. [2024-11-24 02:21:35,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33011 to 27865. [2024-11-24 02:21:35,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27865 states, 27551 states have (on average 1.3994047402998075) internal successors, (38555), 27551 states have internal predecessors, (38555), 312 states have call successors, (312), 1 states have call predecessors, (312), 1 states have return successors, (312), 312 states have call predecessors, (312), 312 states have call successors, (312) [2024-11-24 02:21:35,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27865 states to 27865 states and 39179 transitions. [2024-11-24 02:21:35,818 INFO L78 Accepts]: Start accepts. Automaton has 27865 states and 39179 transitions. Word has length 792 [2024-11-24 02:21:35,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:21:35,818 INFO L471 AbstractCegarLoop]: Abstraction has 27865 states and 39179 transitions. [2024-11-24 02:21:35,818 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 104.0) internal successors, (624), 6 states have internal predecessors, (624), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-24 02:21:35,819 INFO L276 IsEmpty]: Start isEmpty. Operand 27865 states and 39179 transitions. [2024-11-24 02:21:35,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 794 [2024-11-24 02:21:35,844 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:21:35,844 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:21:35,844 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable94 [2024-11-24 02:21:35,844 INFO L396 AbstractCegarLoop]: === Iteration 96 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:21:35,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:21:35,845 INFO L85 PathProgramCache]: Analyzing trace with hash 1134932309, now seen corresponding path program 1 times [2024-11-24 02:21:35,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 02:21:35,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791080940] [2024-11-24 02:21:35,845 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:21:35,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 02:21:48,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 02:21:48,214 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-24 02:21:59,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 02:21:59,797 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-24 02:21:59,797 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-24 02:21:59,798 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-24 02:21:59,800 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable95 [2024-11-24 02:21:59,803 INFO L422 BasicCegarLoop]: Path program histogram: [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:00,396 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-24 02:22:00,400 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.11 02:22:00 BoogieIcfgContainer [2024-11-24 02:22:00,400 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-24 02:22:00,401 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-24 02:22:00,401 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-24 02:22:00,401 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-24 02:22:00,402 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:11:05" (3/4) ... [2024-11-24 02:22:00,404 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-11-24 02:22:00,405 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-24 02:22:00,406 INFO L158 Benchmark]: Toolchain (without parser) took 661555.14ms. Allocated memory was 142.6MB in the beginning and 4.2GB in the end (delta: 4.0GB). Free memory was 116.4MB in the beginning and 2.8GB in the end (delta: -2.7GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2024-11-24 02:22:00,406 INFO L158 Benchmark]: CDTParser took 0.51ms. Allocated memory is still 117.4MB. Free memory was 73.6MB in the beginning and 73.5MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 02:22:00,406 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1034.55ms. Allocated memory is still 142.6MB. Free memory was 116.1MB in the beginning and 75.5MB in the end (delta: 40.6MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-11-24 02:22:00,407 INFO L158 Benchmark]: Boogie Procedure Inliner took 472.21ms. Allocated memory is still 142.6MB. Free memory was 75.5MB in the beginning and 74.6MB in the end (delta: 863.2kB). Peak memory consumption was 72.0MB. Max. memory is 16.1GB. [2024-11-24 02:22:00,407 INFO L158 Benchmark]: Boogie Preprocessor took 629.62ms. Allocated memory was 142.6MB in the beginning and 394.3MB in the end (delta: 251.7MB). Free memory was 74.6MB in the beginning and 320.4MB in the end (delta: -245.7MB). Peak memory consumption was 30.5MB. Max. memory is 16.1GB. [2024-11-24 02:22:00,408 INFO L158 Benchmark]: RCFGBuilder took 4952.05ms. Allocated memory was 394.3MB in the beginning and 285.2MB in the end (delta: -109.1MB). Free memory was 320.2MB in the beginning and 182.1MB in the end (delta: 138.2MB). Peak memory consumption was 141.9MB. Max. memory is 16.1GB. [2024-11-24 02:22:00,408 INFO L158 Benchmark]: TraceAbstraction took 654450.62ms. Allocated memory was 285.2MB in the beginning and 4.2GB in the end (delta: 3.9GB). Free memory was 182.1MB in the beginning and 2.8GB in the end (delta: -2.6GB). Peak memory consumption was 3.0GB. Max. memory is 16.1GB. [2024-11-24 02:22:00,409 INFO L158 Benchmark]: Witness Printer took 4.83ms. Allocated memory is still 4.2GB. Free memory was 2.8GB in the beginning and 2.8GB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 02:22:00,414 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.51ms. Allocated memory is still 117.4MB. Free memory was 73.6MB in the beginning and 73.5MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1034.55ms. Allocated memory is still 142.6MB. Free memory was 116.1MB in the beginning and 75.5MB in the end (delta: 40.6MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 472.21ms. Allocated memory is still 142.6MB. Free memory was 75.5MB in the beginning and 74.6MB in the end (delta: 863.2kB). Peak memory consumption was 72.0MB. Max. memory is 16.1GB. * Boogie Preprocessor took 629.62ms. Allocated memory was 142.6MB in the beginning and 394.3MB in the end (delta: 251.7MB). Free memory was 74.6MB in the beginning and 320.4MB in the end (delta: -245.7MB). Peak memory consumption was 30.5MB. Max. memory is 16.1GB. * RCFGBuilder took 4952.05ms. Allocated memory was 394.3MB in the beginning and 285.2MB in the end (delta: -109.1MB). Free memory was 320.2MB in the beginning and 182.1MB in the end (delta: 138.2MB). Peak memory consumption was 141.9MB. Max. memory is 16.1GB. * TraceAbstraction took 654450.62ms. Allocated memory was 285.2MB in the beginning and 4.2GB in the end (delta: 3.9GB). Free memory was 182.1MB in the beginning and 2.8GB in the end (delta: -2.6GB). Peak memory consumption was 3.0GB. Max. memory is 16.1GB. * Witness Printer took 4.83ms. Allocated memory is still 4.2GB. Free memory was 2.8GB in the beginning and 2.8GB in the end (delta: 3.8MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 142, overapproximation of bitwiseOr at line 226, overapproximation of bitwiseOr at line 403, overapproximation of bitwiseOr at line 187, overapproximation of bitwiseAnd at line 274, overapproximation of bitwiseAnd at line 578, overapproximation of bitwiseAnd at line 641, overapproximation of bitwiseAnd at line 318, overapproximation of bitwiseAnd at line 502, overapproximation of bitwiseAnd at line 148, overapproximation of bitwiseAnd at line 271, overapproximation of bitwiseAnd at line 408, overapproximation of bitwiseAnd at line 128, overapproximation of bitwiseAnd at line 657, overapproximation of bitwiseAnd at line 238, overapproximation of bitwiseAnd at line 284, overapproximation of bitwiseAnd at line 765, overapproximation of bitwiseAnd at line 622. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 2); [L33] const SORT_5 msb_SORT_5 = (SORT_5)1 << (2 - 1); [L35] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 8); [L36] const SORT_11 msb_SORT_11 = (SORT_11)1 << (8 - 1); [L38] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 3); [L39] const SORT_12 msb_SORT_12 = (SORT_12)1 << (3 - 1); [L42] const SORT_15 mask_SORT_15 = (SORT_15)-1 >> (sizeof(SORT_15) * 8 - 4); [L43] const SORT_15 msb_SORT_15 = (SORT_15)1 << (4 - 1); [L45] const SORT_36 mask_SORT_36 = (SORT_36)-1 >> (sizeof(SORT_36) * 8 - 5); [L46] const SORT_36 msb_SORT_36 = (SORT_36)1 << (5 - 1); [L48] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 6); [L49] const SORT_38 msb_SORT_38 = (SORT_38)1 << (6 - 1); [L51] const SORT_40 mask_SORT_40 = (SORT_40)-1 >> (sizeof(SORT_40) * 8 - 7); [L52] const SORT_40 msb_SORT_40 = (SORT_40)1 << (7 - 1); [L54] const SORT_229 mask_SORT_229 = (SORT_229)-1 >> (sizeof(SORT_229) * 8 - 32); [L55] const SORT_229 msb_SORT_229 = (SORT_229)1 << (32 - 1); [L57] const SORT_15 var_27 = 8; [L58] const SORT_15 var_99 = 0; [L59] const SORT_1 var_109 = 1; [L60] const SORT_1 var_110 = 0; [L61] const SORT_11 var_183 = 0; [L62] const SORT_229 var_230 = 2; [L63] const SORT_11 var_410 = 255; [L65] SORT_1 input_2; [L66] SORT_3 input_4; [L67] SORT_5 input_6; [L68] SORT_3 input_7; [L69] SORT_5 input_8; [L70] SORT_1 input_9; [L71] SORT_1 input_10; [L73] SORT_13 state_14; [L74] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] SORT_15 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L76] SORT_15 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L77] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L77] SORT_11 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L78] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L79] SORT_13 state_44; [L80] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] SORT_15 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L82] SORT_15 state_48 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L83] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L83] SORT_11 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L84] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L84] SORT_1 state_85 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L85] SORT_1 state_86 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L86] SORT_15 state_89 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L87] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L87] SORT_11 state_105 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L88] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L88] SORT_1 state_111 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L89] SORT_1 state_333 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L90] SORT_1 state_334 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L91] SORT_1 state_335 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L92] SORT_1 state_336 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L93] SORT_1 state_337 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L94] SORT_1 state_338 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L95] SORT_1 state_339 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L96] SORT_1 state_340 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 init_112_arg_1 = var_109; [L99] state_111 = init_112_arg_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=0, var_115_arg_1=-256, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND FALSE !(!(cond)) [L411] RET __VERIFIER_assert(!(bad_116_arg_0)) [L413] SORT_1 var_298_arg_0 = var_136; [L414] SORT_1 var_298_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_298_arg_0=0, var_298_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] EXPR var_298_arg_0 | var_298_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] SORT_1 var_298 = var_298_arg_0 | var_298_arg_1; [L416] SORT_1 var_299_arg_0 = var_298; [L417] SORT_1 var_299_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299_arg_0=0, var_299_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] EXPR var_299_arg_0 | var_299_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L419] EXPR var_299 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L419] var_299 = var_299 & mask_SORT_1 [L420] SORT_1 var_310_arg_0 = var_136; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_310_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] EXPR var_310_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] var_310_arg_0 = var_310_arg_0 & mask_SORT_1 [L422] SORT_15 var_310 = var_310_arg_0; [L423] SORT_15 var_311_arg_0 = state_16; [L424] SORT_15 var_311_arg_1 = var_310; [L425] SORT_15 var_311 = var_311_arg_0 + var_311_arg_1; [L426] SORT_1 var_404_arg_0 = var_299; [L427] SORT_15 var_404_arg_1 = var_311; [L428] SORT_15 var_404_arg_2 = state_16; [L429] SORT_15 var_404 = var_404_arg_0 ? var_404_arg_1 : var_404_arg_2; [L430] SORT_1 var_405_arg_0 = input_9; [L431] SORT_15 var_405_arg_1 = var_99; [L432] SORT_15 var_405_arg_2 = var_404; [L433] SORT_15 var_405 = var_405_arg_0 ? var_405_arg_1 : var_405_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_405=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] EXPR var_405 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] var_405 = var_405 & mask_SORT_15 [L435] SORT_15 next_406_arg_1 = var_405; [L436] SORT_1 var_304_arg_0 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_304_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] EXPR var_304_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] var_304_arg_0 = var_304_arg_0 & mask_SORT_1 [L438] SORT_15 var_304 = var_304_arg_0; [L439] SORT_15 var_305_arg_0 = state_19; [L440] SORT_15 var_305_arg_1 = var_304; [L441] SORT_15 var_305 = var_305_arg_0 + var_305_arg_1; [L442] SORT_1 var_407_arg_0 = var_299; [L443] SORT_15 var_407_arg_1 = var_305; [L444] SORT_15 var_407_arg_2 = state_19; [L445] SORT_15 var_407 = var_407_arg_0 ? var_407_arg_1 : var_407_arg_2; [L446] SORT_1 var_408_arg_0 = input_9; [L447] SORT_15 var_408_arg_1 = var_99; [L448] SORT_15 var_408_arg_2 = var_407; [L449] SORT_15 var_408 = var_408_arg_0 ? var_408_arg_1 : var_408_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_408=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] EXPR var_408 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] var_408 = var_408 & mask_SORT_15 [L451] SORT_15 next_409_arg_1 = var_408; [L452] SORT_11 var_417_arg_0 = var_410; [L453] SORT_1 var_417 = var_417_arg_0 != 0; [L454] SORT_3 var_258_arg_0 = input_4; [L455] SORT_11 var_258 = var_258_arg_0 >> 8; [L456] SORT_11* var_18_arg_0 = state_14; [L457] SORT_12 var_18_arg_1 = var_17; [L458] EXPR var_18_arg_0[(unsigned char) var_18_arg_1] [L458] SORT_11 var_18 = var_18_arg_0[(unsigned char) var_18_arg_1]; [L459] SORT_1 var_317_arg_0 = var_136; [L460] SORT_11 var_317_arg_1 = var_258; [L461] SORT_11 var_317_arg_2 = var_18; [L462] SORT_11 var_317 = var_317_arg_0 ? var_317_arg_1 : var_317_arg_2; [L463] SORT_11 var_414_arg_0 = var_317; [L464] SORT_11 var_414_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414_arg_0=0, var_414_arg_1=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] EXPR var_414_arg_0 & var_414_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] SORT_11 var_414 = var_414_arg_0 & var_414_arg_1; [L466] SORT_11* var_411_arg_0 = state_14; [L467] SORT_12 var_411_arg_1 = var_17; [L468] EXPR var_411_arg_0[(unsigned char) var_411_arg_1] [L468] SORT_11 var_411 = var_411_arg_0[(unsigned char) var_411_arg_1]; [L469] SORT_11 var_412_arg_0 = var_410; [L470] SORT_11 var_412 = ~var_412_arg_0; [L471] SORT_11 var_413_arg_0 = var_411; [L472] SORT_11 var_413_arg_1 = var_412; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_413_arg_0=0, var_413_arg_1=-256, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] EXPR var_413_arg_0 & var_413_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] SORT_11 var_413 = var_413_arg_0 & var_413_arg_1; [L474] SORT_11 var_415_arg_0 = var_414; [L475] SORT_11 var_415_arg_1 = var_413; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_415_arg_0=0, var_415_arg_1=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] EXPR var_415_arg_0 | var_415_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] SORT_11 var_415 = var_415_arg_0 | var_415_arg_1; [L477] SORT_11* var_416_arg_0 = state_14; [L478] SORT_12 var_416_arg_1 = var_17; [L479] SORT_11 var_416_arg_2 = var_415; [L480] SORT_13 var_416; [L481] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L482] var_416[(unsigned char) var_416_arg_1] = var_416_arg_2 [L483] SORT_1 var_418_arg_0 = var_417; [L484] SORT_11* var_418_arg_1 = var_416; [L485] SORT_11* var_418_arg_2 = state_14; [L486] SORT_11* var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L487] SORT_11* next_419_arg_1 = var_418; [L488] SORT_1 var_157_arg_0 = var_25; [L489] SORT_1 var_157_arg_1 = var_54; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157_arg_0=0, var_157_arg_1=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] EXPR ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] SORT_5 var_157 = ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1; [L491] EXPR var_157 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L491] var_157 = var_157 & mask_SORT_5 [L492] SORT_1 var_162_arg_0 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162_arg_0=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] EXPR var_162_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] var_162_arg_0 = var_162_arg_0 & mask_SORT_1 [L494] SORT_5 var_162 = var_162_arg_0; [L495] SORT_1 var_163_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_163_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] EXPR var_163_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] var_163_arg_0 = var_163_arg_0 & mask_SORT_1 [L497] SORT_5 var_163 = var_163_arg_0; [L498] SORT_5 var_164_arg_0 = var_162; [L499] SORT_5 var_164_arg_1 = var_163; [L500] SORT_5 var_164 = var_164_arg_0 + var_164_arg_1; [L501] SORT_5 var_165_arg_0 = var_164; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] EXPR var_165_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] var_165_arg_0 = var_165_arg_0 & mask_SORT_5 [L503] SORT_12 var_165 = var_165_arg_0; [L504] SORT_1 var_166_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_166_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] EXPR var_166_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] var_166_arg_0 = var_166_arg_0 & mask_SORT_1 [L506] SORT_12 var_166 = var_166_arg_0; [L507] SORT_12 var_167_arg_0 = var_165; [L508] SORT_12 var_167_arg_1 = var_166; [L509] SORT_12 var_167 = var_167_arg_0 + var_167_arg_1; [L510] SORT_12 var_168_arg_0 = var_167; [L511] SORT_1 var_168 = var_168_arg_0 >> 0; [L512] SORT_1 var_169_arg_0 = var_168; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_169_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] EXPR var_169_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] var_169_arg_0 = var_169_arg_0 & mask_SORT_1 [L514] SORT_5 var_169 = var_169_arg_0; [L515] SORT_5 var_170_arg_0 = var_157; [L516] SORT_5 var_170_arg_1 = var_169; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_170_arg_0=0, var_170_arg_1=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] EXPR var_170_arg_0 >> var_170_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] SORT_5 var_170 = var_170_arg_0 >> var_170_arg_1; [L518] SORT_5 var_171_arg_0 = var_170; [L519] SORT_1 var_171 = var_171_arg_0 >> 0; [L520] SORT_1 var_152_arg_0 = var_110; [L521] SORT_1 var_152_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_152_arg_0=0, var_152_arg_1=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] EXPR ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] SORT_5 var_152 = ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1; [L523] SORT_5 var_153_arg_0 = var_152; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153_arg_0=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] EXPR var_153_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] var_153_arg_0 = var_153_arg_0 & mask_SORT_5 [L525] SORT_12 var_153 = var_153_arg_0; [L526] SORT_1 var_154_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_154_arg_0=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] EXPR var_154_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] var_154_arg_0 = var_154_arg_0 & mask_SORT_1 [L528] SORT_12 var_154 = var_154_arg_0; [L529] SORT_12 var_155_arg_0 = var_153; [L530] SORT_12 var_155_arg_1 = var_154; [L531] SORT_12 var_155 = var_155_arg_0 + var_155_arg_1; [L532] SORT_12 var_156_arg_0 = var_155; [L533] SORT_1 var_156 = var_156_arg_0 >> 0; [L534] SORT_1 var_158_arg_0 = var_156; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_158_arg_0=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] EXPR var_158_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] var_158_arg_0 = var_158_arg_0 & mask_SORT_1 [L536] SORT_5 var_158 = var_158_arg_0; [L537] SORT_5 var_159_arg_0 = var_157; [L538] SORT_5 var_159_arg_1 = var_158; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_159_arg_0=0, var_159_arg_1=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] EXPR var_159_arg_0 >> var_159_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] SORT_5 var_159 = var_159_arg_0 >> var_159_arg_1; [L540] SORT_5 var_160_arg_0 = var_159; [L541] SORT_1 var_160 = var_160_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] EXPR var_160 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] var_160 = var_160 & mask_SORT_1 [L543] SORT_1 var_172_arg_0 = var_160; [L544] SORT_1 var_172 = ~var_172_arg_0; [L545] SORT_1 var_173_arg_0 = var_171; [L546] SORT_1 var_173_arg_1 = var_172; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_173_arg_0=0, var_173_arg_1=-1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] EXPR var_173_arg_0 & var_173_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] SORT_1 var_173 = var_173_arg_0 & var_173_arg_1; [L548] EXPR var_173 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L548] var_173 = var_173 & mask_SORT_1 [L549] SORT_1 var_161_arg_0 = var_160; [L550] SORT_1 var_161_arg_1 = var_156; [L551] SORT_1 var_161_arg_2 = state_31; [L552] SORT_1 var_161 = var_161_arg_0 ? var_161_arg_1 : var_161_arg_2; [L553] SORT_1 var_174_arg_0 = var_173; [L554] SORT_1 var_174_arg_1 = var_168; [L555] SORT_1 var_174_arg_2 = var_161; [L556] SORT_1 var_174 = var_174_arg_0 ? var_174_arg_1 : var_174_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] EXPR var_174 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] var_174 = var_174 & mask_SORT_1 [L558] SORT_1 var_204_arg_0 = var_174; [L559] SORT_1 var_204_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_204_arg_0=0, var_204_arg_1=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] EXPR var_204_arg_0 | var_204_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] SORT_1 var_204 = var_204_arg_0 | var_204_arg_1; [L561] EXPR var_204 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L561] var_204 = var_204 & mask_SORT_1 [L562] SORT_1 var_198_arg_0 = var_25; [L563] SORT_1 var_198 = ~var_198_arg_0; [L564] SORT_1 var_199_arg_0 = state_31; [L565] SORT_1 var_199_arg_1 = var_198; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_199_arg_0=0, var_199_arg_1=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] EXPR var_199_arg_0 & var_199_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] SORT_1 var_199 = var_199_arg_0 & var_199_arg_1; [L567] EXPR var_199 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L567] var_199 = var_199 & mask_SORT_1 [L568] SORT_3 var_191_arg_0 = input_7; [L569] SORT_11 var_191 = var_191_arg_0 >> 8; [L570] SORT_11 var_192_arg_0 = state_26; [L571] SORT_11 var_192_arg_1 = var_191; [L572] SORT_11 var_192 = var_192_arg_0 + var_192_arg_1; [L573] SORT_1 var_193_arg_0 = var_174; [L574] SORT_11 var_193_arg_1 = var_192; [L575] SORT_11 var_193_arg_2 = state_26; [L576] SORT_11 var_193 = var_193_arg_0 ? var_193_arg_1 : var_193_arg_2; [L577] SORT_15 var_195_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_195_arg_0=8, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] EXPR var_195_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] var_195_arg_0 = var_195_arg_0 & mask_SORT_15 [L579] SORT_11 var_195 = var_195_arg_0; [L580] SORT_11 var_196_arg_0 = var_193; [L581] SORT_11 var_196_arg_1 = var_195; [L582] SORT_11 var_196 = var_196_arg_0 - var_196_arg_1; [L583] SORT_1 var_197_arg_0 = var_32; [L584] SORT_11 var_197_arg_1 = var_196; [L585] SORT_11 var_197_arg_2 = var_193; [L586] SORT_11 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L587] SORT_1 var_200_arg_0 = var_199; [L588] SORT_11 var_200_arg_1 = state_26; [L589] SORT_11 var_200_arg_2 = var_197; [L590] SORT_11 var_200 = var_200_arg_0 ? var_200_arg_1 : var_200_arg_2; [L591] SORT_1 var_201_arg_0 = input_9; [L592] SORT_11 var_201_arg_1 = var_183; [L593] SORT_11 var_201_arg_2 = var_200; [L594] SORT_11 var_201 = var_201_arg_0 ? var_201_arg_1 : var_201_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] EXPR var_201 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] var_201 = var_201 & mask_SORT_11 [L596] SORT_1 var_420_arg_0 = var_204; [L597] SORT_11 var_420_arg_1 = var_201; [L598] SORT_11 var_420_arg_2 = state_26; [L599] SORT_11 var_420 = var_420_arg_0 ? var_420_arg_1 : var_420_arg_2; [L600] SORT_1 var_421_arg_0 = input_9; [L601] SORT_11 var_421_arg_1 = var_183; [L602] SORT_11 var_421_arg_2 = var_420; [L603] SORT_11 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_421=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] EXPR var_421 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] var_421 = var_421 & mask_SORT_11 [L605] SORT_11 next_422_arg_1 = var_421; [L606] SORT_1 var_180_arg_0 = var_54; [L607] SORT_1 var_180 = ~var_180_arg_0; [L608] SORT_1 var_181_arg_0 = var_59; [L609] SORT_1 var_181_arg_1 = var_180; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_181_arg_0=0, var_181_arg_1=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] EXPR var_181_arg_0 & var_181_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] SORT_1 var_181 = var_181_arg_0 & var_181_arg_1; [L611] EXPR var_181 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L611] var_181 = var_181 & mask_SORT_1 [L612] SORT_3 var_150_arg_0 = input_7; [L613] SORT_11 var_150 = var_150_arg_0 >> 0; [L614] SORT_11 var_151_arg_0 = state_55; [L615] SORT_11 var_151_arg_1 = var_150; [L616] SORT_11 var_151 = var_151_arg_0 + var_151_arg_1; [L617] SORT_1 var_175_arg_0 = var_174; [L618] SORT_11 var_175_arg_1 = state_55; [L619] SORT_11 var_175_arg_2 = var_151; [L620] SORT_11 var_175 = var_175_arg_0 ? var_175_arg_1 : var_175_arg_2; [L621] SORT_15 var_177_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_177_arg_0=8, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] EXPR var_177_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] var_177_arg_0 = var_177_arg_0 & mask_SORT_15 [L623] SORT_11 var_177 = var_177_arg_0; [L624] SORT_11 var_178_arg_0 = var_175; [L625] SORT_11 var_178_arg_1 = var_177; [L626] SORT_11 var_178 = var_178_arg_0 - var_178_arg_1; [L627] SORT_1 var_179_arg_0 = var_60; [L628] SORT_11 var_179_arg_1 = var_178; [L629] SORT_11 var_179_arg_2 = var_175; [L630] SORT_11 var_179 = var_179_arg_0 ? var_179_arg_1 : var_179_arg_2; [L631] SORT_1 var_182_arg_0 = var_181; [L632] SORT_11 var_182_arg_1 = state_55; [L633] SORT_11 var_182_arg_2 = var_179; [L634] SORT_11 var_182 = var_182_arg_0 ? var_182_arg_1 : var_182_arg_2; [L635] SORT_1 var_184_arg_0 = input_9; [L636] SORT_11 var_184_arg_1 = var_183; [L637] SORT_11 var_184_arg_2 = var_182; [L638] SORT_11 var_184 = var_184_arg_0 ? var_184_arg_1 : var_184_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] EXPR var_184 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] var_184 = var_184 & mask_SORT_11 [L640] SORT_15 var_212_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_212_arg_0=8, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] EXPR var_212_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] var_212_arg_0 = var_212_arg_0 & mask_SORT_15 [L642] SORT_11 var_212 = var_212_arg_0; [L643] SORT_11 var_213_arg_0 = var_184; [L644] SORT_11 var_213_arg_1 = var_212; [L645] SORT_1 var_213 = var_213_arg_0 < var_213_arg_1; [L646] SORT_1 var_214_arg_0 = var_180; [L647] SORT_1 var_214_arg_1 = var_213; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_214_arg_0=-1, var_214_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] EXPR var_214_arg_0 | var_214_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] SORT_1 var_214 = var_214_arg_0 | var_214_arg_1; [L649] SORT_1 var_215_arg_0 = var_59; [L650] SORT_1 var_215_arg_1 = var_214; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_215_arg_0=0, var_215_arg_1=255, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] EXPR var_215_arg_0 & var_215_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] SORT_1 var_215 = var_215_arg_0 & var_215_arg_1; [L652] SORT_1 var_216_arg_0 = var_60; [L653] SORT_1 var_216_arg_1 = var_215; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216_arg_0=0, var_216_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] EXPR var_216_arg_0 & var_216_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] SORT_1 var_216 = var_216_arg_0 & var_216_arg_1; [L655] EXPR var_216 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L655] var_216 = var_216 & mask_SORT_1 [L656] SORT_15 var_207_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_207_arg_0=8, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] EXPR var_207_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] var_207_arg_0 = var_207_arg_0 & mask_SORT_15 [L658] SORT_11 var_207 = var_207_arg_0; [L659] SORT_11 var_208_arg_0 = var_201; [L660] SORT_11 var_208_arg_1 = var_207; [L661] SORT_1 var_208 = var_208_arg_0 < var_208_arg_1; [L662] SORT_1 var_209_arg_0 = var_198; [L663] SORT_1 var_209_arg_1 = var_208; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_209_arg_0=-1, var_209_arg_1=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] EXPR var_209_arg_0 | var_209_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] SORT_1 var_209 = var_209_arg_0 | var_209_arg_1; [L665] SORT_1 var_210_arg_0 = state_31; [L666] SORT_1 var_210_arg_1 = var_209; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_210_arg_0=0, var_210_arg_1=255, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] EXPR var_210_arg_0 & var_210_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L668] SORT_1 var_211_arg_0 = var_32; [L669] SORT_1 var_211_arg_1 = var_210; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_211_arg_0=0, var_211_arg_1=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] EXPR var_211_arg_0 & var_211_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L671] EXPR var_211 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L671] var_211 = var_211 & mask_SORT_1 [L672] SORT_1 var_217_arg_0 = var_216; [L673] SORT_1 var_217_arg_1 = var_211; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_217_arg_0=0, var_217_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] EXPR ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] SORT_5 var_217 = ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1; [L675] EXPR var_217 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L675] var_217 = var_217 & mask_SORT_5 [L676] SORT_5 var_218_arg_0 = var_217; [L677] SORT_1 var_218 = var_218_arg_0 != 0; [L678] SORT_1 var_423_arg_0 = var_218; [L679] SORT_1 var_423_arg_1 = var_174; [L680] SORT_1 var_423_arg_2 = state_31; [L681] SORT_1 var_423 = var_423_arg_0 ? var_423_arg_1 : var_423_arg_2; [L682] SORT_1 var_424_arg_0 = input_9; [L683] SORT_1 var_424_arg_1 = var_110; [L684] SORT_1 var_424_arg_2 = var_423; [L685] SORT_1 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_424=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] EXPR var_424 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] var_424 = var_424 & mask_SORT_1 [L687] SORT_1 next_425_arg_1 = var_424; [L688] SORT_1 var_269_arg_0 = var_92; [L689] SORT_1 var_269_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_269_arg_0=0, var_269_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] EXPR var_269_arg_0 | var_269_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] SORT_1 var_269 = var_269_arg_0 | var_269_arg_1; [L691] SORT_1 var_270_arg_0 = var_269; [L692] SORT_1 var_270_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270_arg_0=0, var_270_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] EXPR var_270_arg_0 | var_270_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L694] EXPR var_270 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L694] var_270 = var_270 & mask_SORT_1 [L695] SORT_1 var_281_arg_0 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_281_arg_0=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] EXPR var_281_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] var_281_arg_0 = var_281_arg_0 & mask_SORT_1 [L697] SORT_15 var_281 = var_281_arg_0; [L698] SORT_15 var_282_arg_0 = state_45; [L699] SORT_15 var_282_arg_1 = var_281; [L700] SORT_15 var_282 = var_282_arg_0 + var_282_arg_1; [L701] SORT_1 var_426_arg_0 = var_270; [L702] SORT_15 var_426_arg_1 = var_282; [L703] SORT_15 var_426_arg_2 = state_45; [L704] SORT_15 var_426 = var_426_arg_0 ? var_426_arg_1 : var_426_arg_2; [L705] SORT_1 var_427_arg_0 = input_9; [L706] SORT_15 var_427_arg_1 = var_99; [L707] SORT_15 var_427_arg_2 = var_426; [L708] SORT_15 var_427 = var_427_arg_0 ? var_427_arg_1 : var_427_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_427=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] EXPR var_427 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] var_427 = var_427 & mask_SORT_15 [L710] SORT_15 next_428_arg_1 = var_427; [L711] SORT_1 var_275_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_275_arg_0=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] EXPR var_275_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] var_275_arg_0 = var_275_arg_0 & mask_SORT_1 [L713] SORT_15 var_275 = var_275_arg_0; [L714] SORT_15 var_276_arg_0 = state_48; [L715] SORT_15 var_276_arg_1 = var_275; [L716] SORT_15 var_276 = var_276_arg_0 + var_276_arg_1; [L717] SORT_1 var_429_arg_0 = var_270; [L718] SORT_15 var_429_arg_1 = var_276; [L719] SORT_15 var_429_arg_2 = state_48; [L720] SORT_15 var_429 = var_429_arg_0 ? var_429_arg_1 : var_429_arg_2; [L721] SORT_1 var_430_arg_0 = input_9; [L722] SORT_15 var_430_arg_1 = var_99; [L723] SORT_15 var_430_arg_2 = var_429; [L724] SORT_15 var_430 = var_430_arg_0 ? var_430_arg_1 : var_430_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_430=0, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] EXPR var_430 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] var_430 = var_430 & mask_SORT_15 [L726] SORT_15 next_431_arg_1 = var_430; [L727] SORT_11 var_438_arg_0 = var_410; [L728] SORT_1 var_438 = var_438_arg_0 != 0; [L729] SORT_3 var_256_arg_0 = input_4; [L730] SORT_11 var_256 = var_256_arg_0 >> 0; [L731] SORT_11* var_47_arg_0 = state_44; [L732] SORT_12 var_47_arg_1 = var_46; [L733] EXPR var_47_arg_0[(unsigned char) var_47_arg_1] [L733] SORT_11 var_47 = var_47_arg_0[(unsigned char) var_47_arg_1]; [L734] SORT_1 var_288_arg_0 = var_92; [L735] SORT_11 var_288_arg_1 = var_256; [L736] SORT_11 var_288_arg_2 = var_47; [L737] SORT_11 var_288 = var_288_arg_0 ? var_288_arg_1 : var_288_arg_2; [L738] SORT_11 var_435_arg_0 = var_288; [L739] SORT_11 var_435_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435_arg_0=0, var_435_arg_1=255, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] EXPR var_435_arg_0 & var_435_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] SORT_11 var_435 = var_435_arg_0 & var_435_arg_1; [L741] SORT_11* var_432_arg_0 = state_44; [L742] SORT_12 var_432_arg_1 = var_46; [L743] EXPR var_432_arg_0[(unsigned char) var_432_arg_1] [L743] SORT_11 var_432 = var_432_arg_0[(unsigned char) var_432_arg_1]; [L744] SORT_11 var_433_arg_0 = var_410; [L745] SORT_11 var_433 = ~var_433_arg_0; [L746] SORT_11 var_434_arg_0 = var_432; [L747] SORT_11 var_434_arg_1 = var_433; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_434_arg_0=0, var_434_arg_1=-256, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] EXPR var_434_arg_0 & var_434_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] SORT_11 var_434 = var_434_arg_0 & var_434_arg_1; [L749] SORT_11 var_436_arg_0 = var_435; [L750] SORT_11 var_436_arg_1 = var_434; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_436_arg_0=0, var_436_arg_1=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] EXPR var_436_arg_0 | var_436_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] SORT_11 var_436 = var_436_arg_0 | var_436_arg_1; [L752] SORT_11* var_437_arg_0 = state_44; [L753] SORT_12 var_437_arg_1 = var_46; [L754] SORT_11 var_437_arg_2 = var_436; [L755] SORT_13 var_437; [L756] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L757] var_437[(unsigned char) var_437_arg_1] = var_437_arg_2 [L758] SORT_1 var_439_arg_0 = var_438; [L759] SORT_11* var_439_arg_1 = var_437; [L760] SORT_11* var_439_arg_2 = state_44; [L761] SORT_11* var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L762] SORT_11* next_440_arg_1 = var_439; [L763] SORT_1 var_187_arg_0 = var_174; [L764] SORT_1 var_187 = ~var_187_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_187=-1, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] EXPR var_187 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] var_187 = var_187 & mask_SORT_1 [L766] SORT_1 var_188_arg_0 = var_187; [L767] SORT_1 var_188_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_188_arg_0=0, var_188_arg_1=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] EXPR var_188_arg_0 | var_188_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] SORT_1 var_188 = var_188_arg_0 | var_188_arg_1; [L769] EXPR var_188 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L769] var_188 = var_188 & mask_SORT_1 [L770] SORT_1 var_441_arg_0 = var_188; [L771] SORT_11 var_441_arg_1 = var_184; [L772] SORT_11 var_441_arg_2 = state_55; [L773] SORT_11 var_441 = var_441_arg_0 ? var_441_arg_1 : var_441_arg_2; [L774] SORT_1 var_442_arg_0 = input_9; [L775] SORT_11 var_442_arg_1 = var_183; [L776] SORT_11 var_442_arg_2 = var_441; [L777] SORT_11 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_442=0, var_92=0, var_93=-1, var_99=0] [L778] EXPR var_442 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L778] var_442 = var_442 & mask_SORT_11 [L779] SORT_11 next_443_arg_1 = var_442; [L780] SORT_1 var_365_arg_0 = input_10; [L781] SORT_1 var_365_arg_1 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365_arg_0=0, var_365_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] EXPR var_365_arg_0 & var_365_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L783] SORT_1 var_366_arg_0 = state_85; [L784] SORT_1 var_366_arg_1 = var_365; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_366_arg_0=0, var_366_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] EXPR var_366_arg_0 | var_366_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] SORT_1 var_366 = var_366_arg_0 | var_366_arg_1; [L786] SORT_1 var_444_arg_0 = state_85; [L787] SORT_1 var_444_arg_1 = var_109; [L788] SORT_1 var_444_arg_2 = var_366; [L789] SORT_1 var_444 = var_444_arg_0 ? var_444_arg_1 : var_444_arg_2; [L790] SORT_1 var_445_arg_0 = input_9; [L791] SORT_1 var_445_arg_1 = var_110; [L792] SORT_1 var_445_arg_2 = var_444; [L793] SORT_1 var_445 = var_445_arg_0 ? var_445_arg_1 : var_445_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_445=0, var_93=-1, var_99=0] [L794] EXPR var_445 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L794] var_445 = var_445 & mask_SORT_1 [L795] SORT_1 next_446_arg_1 = var_445; [L796] SORT_1 var_376_arg_0 = var_103; [L797] SORT_1 var_376_arg_1 = state_86; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_376_arg_0=0, var_376_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] EXPR var_376_arg_0 | var_376_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L799] SORT_1 var_447_arg_0 = input_9; [L800] SORT_1 var_447_arg_1 = var_110; [L801] SORT_1 var_447_arg_2 = var_376; [L802] SORT_1 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L803] SORT_1 next_448_arg_1 = var_447; [L804] SORT_1 var_388_arg_0 = var_270; [L805] SORT_1 var_388_arg_1 = state_85; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_388_arg_0=0, var_388_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] EXPR var_388_arg_0 | var_388_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] SORT_1 var_388 = var_388_arg_0 | var_388_arg_1; [L807] EXPR var_388 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L807] var_388 = var_388 & mask_SORT_1 [L808] SORT_1 var_449_arg_0 = var_388; [L809] SORT_15 var_449_arg_1 = var_100; [L810] SORT_15 var_449_arg_2 = state_89; [L811] SORT_15 var_449 = var_449_arg_0 ? var_449_arg_1 : var_449_arg_2; [L812] SORT_1 var_450_arg_0 = input_9; [L813] SORT_15 var_450_arg_1 = var_99; [L814] SORT_15 var_450_arg_2 = var_449; [L815] SORT_15 var_450 = var_450_arg_0 ? var_450_arg_1 : var_450_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_450=0, var_93=-1, var_99=0] [L816] EXPR var_450 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L816] var_450 = var_450 & mask_SORT_15 [L817] SORT_15 next_451_arg_1 = var_450; [L818] SORT_1 var_373_arg_0 = var_365; [L819] SORT_1 var_373_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_373_arg_0=0, var_373_arg_1=-1, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] EXPR var_373_arg_0 & var_373_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L821] EXPR var_373 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L821] var_373 = var_373 & mask_SORT_1 [L822] SORT_1 var_452_arg_0 = var_373; [L823] SORT_11 var_452_arg_1 = var_256; [L824] SORT_11 var_452_arg_2 = state_105; [L825] SORT_11 var_452 = var_452_arg_0 ? var_452_arg_1 : var_452_arg_2; [L826] SORT_1 var_453_arg_0 = input_9; [L827] SORT_11 var_453_arg_1 = var_183; [L828] SORT_11 var_453_arg_2 = var_452; [L829] SORT_11 var_453 = var_453_arg_0 ? var_453_arg_1 : var_453_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_453=0, var_99=0] [L830] EXPR var_453 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L830] var_453 = var_453 & mask_SORT_11 [L831] SORT_11 next_454_arg_1 = var_453; [L832] SORT_1 next_455_arg_1 = var_110; [L834] state_16 = next_406_arg_1 [L835] state_19 = next_409_arg_1 [L836] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L837] state_26 = next_422_arg_1 [L838] state_31 = next_425_arg_1 [L839] state_45 = next_428_arg_1 [L840] state_48 = next_431_arg_1 [L841] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L842] state_55 = next_443_arg_1 [L843] state_85 = next_446_arg_1 [L844] state_86 = next_448_arg_1 [L845] state_89 = next_451_arg_1 [L846] state_105 = next_454_arg_1 [L847] state_111 = next_455_arg_1 [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=1, var_115_arg_1=-1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 752 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 653.8s, OverallIterations: 96, TraceHistogramMax: 10, PathProgramHistogramMax: 2, EmptinessCheckTime: 1.0s, AutomataDifference: 96.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 101041 SdHoareTripleChecker+Valid, 70.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 100908 mSDsluCounter, 584091 SdHoareTripleChecker+Invalid, 60.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 480476 mSDsCounter, 289 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 94408 IncrementalHoareTripleChecker+Invalid, 94697 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 289 mSolverCounterUnsat, 103615 mSDtfsCounter, 94408 mSolverCounterSat, 1.4s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 42665 GetRequests, 41622 SyntacticMatches, 2 SemanticMatches, 1041 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11643 ImplicationChecksByTransitivity, 23.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=27865occurred in iteration=95, InterpolantAutomatonStates: 798, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 13.1s AutomataMinimizationTime, 95 MinimizatonAttempts, 85294 StatesRemovedByMinimization, 47 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 12.5s SsaConstructionTime, 211.7s SatisfiabilityAnalysisTime, 224.0s InterpolantComputationTime, 85496 NumberOfCodeBlocks, 79685 NumberOfCodeBlocksAsserted, 135 NumberOfCheckSat, 102378 ConstructedInterpolants, 0 QuantifiedInterpolants, 358350 SizeOfPredicates, 94 NumberOfNonLiveVariables, 105539 ConjunctsInSsa, 1064 ConjunctsInUnsatCore, 160 InterpolantComputations, 78 PerfectInterpolantSequences, 97658/100452 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-24 02:22:00,494 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 02:22:03,783 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 02:22:03,905 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-24 02:22:03,913 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 02:22:03,914 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 02:22:03,965 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 02:22:03,966 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 02:22:03,966 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 02:22:03,967 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 02:22:03,968 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 02:22:03,969 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 02:22:03,969 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 02:22:03,969 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 02:22:03,970 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 02:22:03,970 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 02:22:03,971 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 02:22:03,971 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 02:22:03,971 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 02:22:03,971 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 02:22:03,971 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 02:22:03,972 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 02:22:03,972 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-24 02:22:03,972 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-24 02:22:03,972 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-24 02:22:03,972 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 02:22:03,973 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 02:22:03,973 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 02:22:03,973 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 02:22:03,973 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:22:03,973 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:22:03,973 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:22:03,974 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:22:03,975 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:22:03,975 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 02:22:03,975 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 02:22:03,976 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-11-24 02:22:04,369 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 02:22:04,379 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 02:22:04,382 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 02:22:04,383 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 02:22:04,383 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 02:22:04,386 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:22:07,832 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/3e9d2d3a4/8d6c5fedc6304532af7018a1bdc14586/FLAG0a7b99a7c [2024-11-24 02:22:08,240 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 02:22:08,241 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:22:08,267 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/3e9d2d3a4/8d6c5fedc6304532af7018a1bdc14586/FLAG0a7b99a7c [2024-11-24 02:22:08,296 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/data/3e9d2d3a4/8d6c5fedc6304532af7018a1bdc14586 [2024-11-24 02:22:08,300 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 02:22:08,302 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 02:22:08,304 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 02:22:08,305 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 02:22:08,310 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 02:22:08,312 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:22:08" (1/1) ... [2024-11-24 02:22:08,313 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2153cf1c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:08, skipping insertion in model container [2024-11-24 02:22:08,316 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 02:22:08" (1/1) ... [2024-11-24 02:22:08,391 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 02:22:08,617 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-24 02:22:08,916 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:22:08,931 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 02:22:08,946 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-24 02:22:09,161 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 02:22:09,178 INFO L204 MainTranslator]: Completed translation [2024-11-24 02:22:09,179 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09 WrapperNode [2024-11-24 02:22:09,180 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 02:22:09,181 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 02:22:09,181 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 02:22:09,181 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 02:22:09,189 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,229 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,352 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 952 [2024-11-24 02:22:09,355 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 02:22:09,356 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 02:22:09,356 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 02:22:09,356 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 02:22:09,369 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,370 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,382 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,429 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-11-24 02:22:09,432 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,433 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,494 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,501 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,512 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,521 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,531 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,548 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 02:22:09,549 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 02:22:09,549 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 02:22:09,549 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 02:22:09,550 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (1/1) ... [2024-11-24 02:22:09,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 02:22:09,583 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:09,603 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 02:22:09,608 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 02:22:09,642 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 02:22:09,642 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#0 [2024-11-24 02:22:09,643 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#1 [2024-11-24 02:22:09,643 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#2 [2024-11-24 02:22:09,643 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-24 02:22:09,643 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#1 [2024-11-24 02:22:09,644 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#2 [2024-11-24 02:22:09,644 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-24 02:22:09,644 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-24 02:22:09,644 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-24 02:22:09,644 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 02:22:09,644 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 02:22:09,645 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#0 [2024-11-24 02:22:09,645 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#1 [2024-11-24 02:22:09,645 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#2 [2024-11-24 02:22:09,646 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-24 02:22:09,991 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 02:22:09,993 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 02:22:11,273 INFO L? ?]: Removed 681 outVars from TransFormulas that were not future-live. [2024-11-24 02:22:11,273 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 02:22:11,288 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 02:22:11,289 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-24 02:22:11,290 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:22:11 BoogieIcfgContainer [2024-11-24 02:22:11,291 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 02:22:11,294 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 02:22:11,294 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 02:22:11,301 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 02:22:11,301 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 02:22:08" (1/3) ... [2024-11-24 02:22:11,302 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a33a4ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:22:11, skipping insertion in model container [2024-11-24 02:22:11,302 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 02:22:09" (2/3) ... [2024-11-24 02:22:11,304 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a33a4ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 02:22:11, skipping insertion in model container [2024-11-24 02:22:11,304 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 02:22:11" (3/3) ... [2024-11-24 02:22:11,306 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-24 02:22:11,326 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 02:22:11,327 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 42 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-11-24 02:22:11,405 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 02:22:11,431 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@20b16bf0, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 02:22:11,432 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 02:22:11,439 INFO L276 IsEmpty]: Start isEmpty. Operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:22:11,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-11-24 02:22:11,454 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:11,454 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:11,455 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:11,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:11,464 INFO L85 PathProgramCache]: Analyzing trace with hash -172425956, now seen corresponding path program 1 times [2024-11-24 02:22:11,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:11,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1355516184] [2024-11-24 02:22:11,483 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:11,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:11,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:11,486 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:11,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 02:22:12,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:12,130 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-24 02:22:12,139 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:12,172 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-24 02:22:12,172 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:12,175 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:12,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1355516184] [2024-11-24 02:22:12,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1355516184] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:12,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:12,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-24 02:22:12,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320449138] [2024-11-24 02:22:12,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:12,184 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-24 02:22:12,185 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:12,210 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-24 02:22:12,211 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 02:22:12,213 INFO L87 Difference]: Start difference. First operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:22:12,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:12,244 INFO L93 Difference]: Finished difference Result 77 states and 117 transitions. [2024-11-24 02:22:12,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-24 02:22:12,247 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 39 [2024-11-24 02:22:12,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:12,255 INFO L225 Difference]: With dead ends: 77 [2024-11-24 02:22:12,255 INFO L226 Difference]: Without dead ends: 39 [2024-11-24 02:22:12,259 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-24 02:22:12,268 INFO L435 NwaCegarLoop]: 49 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:12,269 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:12,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2024-11-24 02:22:12,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2024-11-24 02:22:12,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 32 states have (on average 1.21875) internal successors, (39), 32 states have internal predecessors, (39), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:22:12,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2024-11-24 02:22:12,327 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 49 transitions. Word has length 39 [2024-11-24 02:22:12,327 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:12,328 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 49 transitions. [2024-11-24 02:22:12,329 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-24 02:22:12,329 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 49 transitions. [2024-11-24 02:22:12,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-11-24 02:22:12,332 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:12,332 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:12,345 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:12,532 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:12,533 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:12,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:12,534 INFO L85 PathProgramCache]: Analyzing trace with hash -1962528174, now seen corresponding path program 1 times [2024-11-24 02:22:12,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:12,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1606441956] [2024-11-24 02:22:12,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:12,535 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:12,535 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:12,538 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:12,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-24 02:22:13,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:13,149 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:13,155 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:13,195 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-24 02:22:13,197 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:13,197 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:13,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1606441956] [2024-11-24 02:22:13,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1606441956] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:13,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:13,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:13,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [585627522] [2024-11-24 02:22:13,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:13,200 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:13,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:13,201 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:13,203 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:13,203 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:13,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:13,239 INFO L93 Difference]: Finished difference Result 76 states and 96 transitions. [2024-11-24 02:22:13,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:13,241 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 39 [2024-11-24 02:22:13,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:13,241 INFO L225 Difference]: With dead ends: 76 [2024-11-24 02:22:13,241 INFO L226 Difference]: Without dead ends: 41 [2024-11-24 02:22:13,242 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:13,243 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 91 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:13,243 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 91 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:13,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2024-11-24 02:22:13,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2024-11-24 02:22:13,256 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 33 states have (on average 1.2121212121212122) internal successors, (40), 33 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:22:13,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2024-11-24 02:22:13,258 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 50 transitions. Word has length 39 [2024-11-24 02:22:13,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:13,258 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 50 transitions. [2024-11-24 02:22:13,258 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:13,258 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 50 transitions. [2024-11-24 02:22:13,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2024-11-24 02:22:13,259 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:13,260 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:13,272 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-24 02:22:13,460 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:13,461 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:13,462 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:13,463 INFO L85 PathProgramCache]: Analyzing trace with hash 482086798, now seen corresponding path program 1 times [2024-11-24 02:22:13,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:13,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1972065392] [2024-11-24 02:22:13,465 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:13,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:13,466 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:13,469 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:13,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-24 02:22:14,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:14,007 INFO L256 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:14,016 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:14,036 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:22:14,039 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:14,039 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:14,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1972065392] [2024-11-24 02:22:14,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1972065392] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:14,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:14,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:14,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071334930] [2024-11-24 02:22:14,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:14,041 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:14,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:14,041 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:14,041 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:14,042 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:14,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:14,088 INFO L93 Difference]: Finished difference Result 74 states and 93 transitions. [2024-11-24 02:22:14,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:14,089 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 41 [2024-11-24 02:22:14,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:14,090 INFO L225 Difference]: With dead ends: 74 [2024-11-24 02:22:14,092 INFO L226 Difference]: Without dead ends: 42 [2024-11-24 02:22:14,093 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:14,094 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:14,094 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:14,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2024-11-24 02:22:14,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2024-11-24 02:22:14,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 34 states have (on average 1.2058823529411764) internal successors, (41), 34 states have internal predecessors, (41), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:22:14,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 51 transitions. [2024-11-24 02:22:14,107 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 51 transitions. Word has length 41 [2024-11-24 02:22:14,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:14,108 INFO L471 AbstractCegarLoop]: Abstraction has 41 states and 51 transitions. [2024-11-24 02:22:14,108 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:14,108 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 51 transitions. [2024-11-24 02:22:14,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2024-11-24 02:22:14,110 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:14,110 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:14,125 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:14,314 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:14,315 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:14,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:14,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1508766582, now seen corresponding path program 1 times [2024-11-24 02:22:14,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:14,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1848566062] [2024-11-24 02:22:14,317 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:14,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:14,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:14,321 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:14,323 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-24 02:22:14,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:14,869 INFO L256 TraceCheckSpWp]: Trace formula consists of 386 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:14,875 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:14,929 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:22:14,930 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:15,064 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-24 02:22:15,065 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:15,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1848566062] [2024-11-24 02:22:15,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1848566062] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:15,066 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:15,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:15,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078063814] [2024-11-24 02:22:15,066 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:15,067 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:15,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:15,068 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:15,069 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:15,069 INFO L87 Difference]: Start difference. First operand 41 states and 51 transitions. Second operand has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:15,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:15,180 INFO L93 Difference]: Finished difference Result 83 states and 105 transitions. [2024-11-24 02:22:15,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:15,181 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 43 [2024-11-24 02:22:15,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:15,182 INFO L225 Difference]: With dead ends: 83 [2024-11-24 02:22:15,182 INFO L226 Difference]: Without dead ends: 47 [2024-11-24 02:22:15,183 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:15,183 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 132 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 179 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:15,184 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 179 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:15,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2024-11-24 02:22:15,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2024-11-24 02:22:15,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.175) internal successors, (47), 40 states have internal predecessors, (47), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-24 02:22:15,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 57 transitions. [2024-11-24 02:22:15,198 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 57 transitions. Word has length 43 [2024-11-24 02:22:15,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:15,199 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 57 transitions. [2024-11-24 02:22:15,199 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:15,199 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 57 transitions. [2024-11-24 02:22:15,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2024-11-24 02:22:15,200 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:15,201 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:15,215 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:15,401 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:15,402 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:15,402 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:15,403 INFO L85 PathProgramCache]: Analyzing trace with hash 1082379582, now seen corresponding path program 2 times [2024-11-24 02:22:15,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:15,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [408525] [2024-11-24 02:22:15,404 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:22:15,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:15,404 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:15,407 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:15,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-24 02:22:15,900 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-24 02:22:15,900 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:15,909 INFO L256 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-11-24 02:22:15,916 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:16,391 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2024-11-24 02:22:16,391 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:16,391 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:16,391 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [408525] [2024-11-24 02:22:16,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [408525] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:16,392 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:16,392 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 02:22:16,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581957646] [2024-11-24 02:22:16,392 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:16,392 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 02:22:16,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:16,393 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 02:22:16,393 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 02:22:16,394 INFO L87 Difference]: Start difference. First operand 47 states and 57 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:16,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:16,718 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2024-11-24 02:22:16,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 02:22:16,719 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 49 [2024-11-24 02:22:16,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:16,722 INFO L225 Difference]: With dead ends: 61 [2024-11-24 02:22:16,722 INFO L226 Difference]: Without dead ends: 59 [2024-11-24 02:22:16,722 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:16,723 INFO L435 NwaCegarLoop]: 37 mSDtfsCounter, 34 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:16,723 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 112 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-24 02:22:16,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2024-11-24 02:22:16,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2024-11-24 02:22:16,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 47 states have (on average 1.148936170212766) internal successors, (54), 47 states have internal predecessors, (54), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:16,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 74 transitions. [2024-11-24 02:22:16,751 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 74 transitions. Word has length 49 [2024-11-24 02:22:16,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:16,753 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 74 transitions. [2024-11-24 02:22:16,753 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-24 02:22:16,753 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 74 transitions. [2024-11-24 02:22:16,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2024-11-24 02:22:16,755 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:16,755 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:16,767 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-24 02:22:16,959 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:16,960 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:16,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:16,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1262899509, now seen corresponding path program 1 times [2024-11-24 02:22:16,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:16,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [411990662] [2024-11-24 02:22:16,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:16,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:16,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:16,966 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:16,970 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-24 02:22:17,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:17,953 INFO L256 TraceCheckSpWp]: Trace formula consists of 1125 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:17,964 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:17,987 INFO L134 CoverageAnalysis]: Checked inductivity of 209 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-11-24 02:22:17,988 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:17,988 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:17,988 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [411990662] [2024-11-24 02:22:17,988 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [411990662] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:17,988 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:17,988 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:17,988 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [229984510] [2024-11-24 02:22:17,988 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:17,989 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:17,989 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:17,989 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:17,989 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:17,990 INFO L87 Difference]: Start difference. First operand 59 states and 74 transitions. Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:18,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:18,098 INFO L93 Difference]: Finished difference Result 92 states and 116 transitions. [2024-11-24 02:22:18,101 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:18,102 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 90 [2024-11-24 02:22:18,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:18,103 INFO L225 Difference]: With dead ends: 92 [2024-11-24 02:22:18,103 INFO L226 Difference]: Without dead ends: 61 [2024-11-24 02:22:18,104 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:18,104 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:18,105 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:18,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2024-11-24 02:22:18,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2024-11-24 02:22:18,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 48 states have (on average 1.1458333333333333) internal successors, (55), 48 states have internal predecessors, (55), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:18,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2024-11-24 02:22:18,120 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 75 transitions. Word has length 90 [2024-11-24 02:22:18,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:18,121 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-11-24 02:22:18,121 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:18,121 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 75 transitions. [2024-11-24 02:22:18,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-11-24 02:22:18,123 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:18,123 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:18,139 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:18,323 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:18,324 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:18,324 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:18,324 INFO L85 PathProgramCache]: Analyzing trace with hash 1332255303, now seen corresponding path program 1 times [2024-11-24 02:22:18,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:18,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [520147700] [2024-11-24 02:22:18,326 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:18,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:18,326 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:18,331 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:18,333 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-24 02:22:19,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:19,270 INFO L256 TraceCheckSpWp]: Trace formula consists of 1131 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:19,276 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:19,304 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2024-11-24 02:22:19,305 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:19,305 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:19,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [520147700] [2024-11-24 02:22:19,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [520147700] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:19,305 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:19,305 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:19,305 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1785478807] [2024-11-24 02:22:19,305 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:19,306 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:19,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:19,306 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:19,306 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:19,307 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:19,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:19,360 INFO L93 Difference]: Finished difference Result 94 states and 118 transitions. [2024-11-24 02:22:19,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:19,364 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 92 [2024-11-24 02:22:19,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:19,365 INFO L225 Difference]: With dead ends: 94 [2024-11-24 02:22:19,365 INFO L226 Difference]: Without dead ends: 62 [2024-11-24 02:22:19,366 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:19,366 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:19,367 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:19,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2024-11-24 02:22:19,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2024-11-24 02:22:19,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 49 states have (on average 1.1428571428571428) internal successors, (56), 49 states have internal predecessors, (56), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:19,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 76 transitions. [2024-11-24 02:22:19,389 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 76 transitions. Word has length 92 [2024-11-24 02:22:19,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:19,390 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 76 transitions. [2024-11-24 02:22:19,390 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:19,390 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 76 transitions. [2024-11-24 02:22:19,392 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2024-11-24 02:22:19,395 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:19,395 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:19,415 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-24 02:22:19,596 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:19,596 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:19,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:19,597 INFO L85 PathProgramCache]: Analyzing trace with hash -523258493, now seen corresponding path program 1 times [2024-11-24 02:22:19,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:19,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1515065369] [2024-11-24 02:22:19,599 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:19,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:19,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:19,601 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:19,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-24 02:22:20,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:20,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:20,597 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:20,614 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-11-24 02:22:20,617 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:20,617 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:20,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1515065369] [2024-11-24 02:22:20,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1515065369] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:20,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:20,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:20,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612583908] [2024-11-24 02:22:20,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:20,619 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:20,622 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:20,623 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:20,623 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:20,623 INFO L87 Difference]: Start difference. First operand 61 states and 76 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:20,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:20,664 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2024-11-24 02:22:20,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:20,665 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 94 [2024-11-24 02:22:20,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:20,667 INFO L225 Difference]: With dead ends: 96 [2024-11-24 02:22:20,667 INFO L226 Difference]: Without dead ends: 63 [2024-11-24 02:22:20,667 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:20,668 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:20,669 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:20,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2024-11-24 02:22:20,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 62. [2024-11-24 02:22:20,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 50 states have (on average 1.14) internal successors, (57), 50 states have internal predecessors, (57), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:20,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 77 transitions. [2024-11-24 02:22:20,684 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 77 transitions. Word has length 94 [2024-11-24 02:22:20,684 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:20,684 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 77 transitions. [2024-11-24 02:22:20,685 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:20,685 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2024-11-24 02:22:20,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2024-11-24 02:22:20,687 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:20,689 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:20,706 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:20,893 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:20,894 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:20,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:20,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1675280511, now seen corresponding path program 1 times [2024-11-24 02:22:20,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:20,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1367885015] [2024-11-24 02:22:20,895 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:20,895 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:20,895 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:20,897 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:20,898 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-24 02:22:21,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:21,942 INFO L256 TraceCheckSpWp]: Trace formula consists of 1143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-24 02:22:21,948 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:21,967 INFO L134 CoverageAnalysis]: Checked inductivity of 212 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2024-11-24 02:22:21,971 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-24 02:22:21,972 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:21,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1367885015] [2024-11-24 02:22:21,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1367885015] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 02:22:21,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 02:22:21,972 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-24 02:22:21,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1286490930] [2024-11-24 02:22:21,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 02:22:21,973 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-24 02:22:21,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:21,974 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-24 02:22:21,974 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:21,974 INFO L87 Difference]: Start difference. First operand 62 states and 77 transitions. Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:22,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:22,014 INFO L93 Difference]: Finished difference Result 98 states and 122 transitions. [2024-11-24 02:22:22,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-24 02:22:22,015 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 96 [2024-11-24 02:22:22,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:22,016 INFO L225 Difference]: With dead ends: 98 [2024-11-24 02:22:22,016 INFO L226 Difference]: Without dead ends: 64 [2024-11-24 02:22:22,016 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-24 02:22:22,017 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:22,017 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 02:22:22,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2024-11-24 02:22:22,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2024-11-24 02:22:22,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 51 states have (on average 1.1372549019607843) internal successors, (58), 51 states have internal predecessors, (58), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:22,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 78 transitions. [2024-11-24 02:22:22,034 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 78 transitions. Word has length 96 [2024-11-24 02:22:22,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:22,034 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 78 transitions. [2024-11-24 02:22:22,035 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-24 02:22:22,035 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 78 transitions. [2024-11-24 02:22:22,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2024-11-24 02:22:22,038 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:22,039 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:22,054 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-24 02:22:22,246 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:22,247 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:22,247 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:22,247 INFO L85 PathProgramCache]: Analyzing trace with hash -571376837, now seen corresponding path program 1 times [2024-11-24 02:22:22,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:22,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1741113818] [2024-11-24 02:22:22,248 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 02:22:22,248 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:22,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:22,251 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:22,252 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-24 02:22:23,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:23,338 INFO L256 TraceCheckSpWp]: Trace formula consists of 1149 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:23,344 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:23,372 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-11-24 02:22:23,372 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:23,498 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-11-24 02:22:23,498 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:23,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1741113818] [2024-11-24 02:22:23,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1741113818] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:23,498 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:23,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:23,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1983062627] [2024-11-24 02:22:23,499 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:23,499 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:23,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:23,500 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:23,500 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:23,501 INFO L87 Difference]: Start difference. First operand 63 states and 78 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:23,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:23,612 INFO L93 Difference]: Finished difference Result 117 states and 148 transitions. [2024-11-24 02:22:23,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:23,613 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 98 [2024-11-24 02:22:23,613 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:23,615 INFO L225 Difference]: With dead ends: 117 [2024-11-24 02:22:23,615 INFO L226 Difference]: Without dead ends: 69 [2024-11-24 02:22:23,616 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:23,617 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:23,618 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:23,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2024-11-24 02:22:23,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2024-11-24 02:22:23,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 57 states have (on average 1.1228070175438596) internal successors, (64), 57 states have internal predecessors, (64), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:23,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 84 transitions. [2024-11-24 02:22:23,639 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 84 transitions. Word has length 98 [2024-11-24 02:22:23,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:23,639 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 84 transitions. [2024-11-24 02:22:23,639 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:23,639 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 84 transitions. [2024-11-24 02:22:23,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2024-11-24 02:22:23,640 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:23,640 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:23,660 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:23,847 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:23,848 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:23,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:23,848 INFO L85 PathProgramCache]: Analyzing trace with hash -327439417, now seen corresponding path program 2 times [2024-11-24 02:22:23,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:23,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [871263852] [2024-11-24 02:22:23,850 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:22:23,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:23,850 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:23,851 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:23,853 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-24 02:22:24,950 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:22:24,950 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:24,968 INFO L256 TraceCheckSpWp]: Trace formula consists of 1164 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:24,974 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:24,999 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2024-11-24 02:22:24,999 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:25,102 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2024-11-24 02:22:25,102 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:25,102 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [871263852] [2024-11-24 02:22:25,102 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [871263852] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:25,102 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:25,103 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:25,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878096046] [2024-11-24 02:22:25,103 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:25,103 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:25,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:25,104 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:25,104 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:25,104 INFO L87 Difference]: Start difference. First operand 69 states and 84 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:25,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:25,247 INFO L93 Difference]: Finished difference Result 110 states and 136 transitions. [2024-11-24 02:22:25,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:25,251 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 104 [2024-11-24 02:22:25,251 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:25,253 INFO L225 Difference]: With dead ends: 110 [2024-11-24 02:22:25,253 INFO L226 Difference]: Without dead ends: 75 [2024-11-24 02:22:25,254 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 207 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:25,255 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:25,257 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:25,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2024-11-24 02:22:25,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2024-11-24 02:22:25,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 63 states have (on average 1.1111111111111112) internal successors, (70), 63 states have internal predecessors, (70), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:25,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 90 transitions. [2024-11-24 02:22:25,276 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 90 transitions. Word has length 104 [2024-11-24 02:22:25,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:25,277 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 90 transitions. [2024-11-24 02:22:25,277 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:25,277 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 90 transitions. [2024-11-24 02:22:25,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2024-11-24 02:22:25,282 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:25,282 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:25,313 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-24 02:22:25,482 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:25,483 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:25,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:25,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1578953669, now seen corresponding path program 3 times [2024-11-24 02:22:25,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:25,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [143121211] [2024-11-24 02:22:25,485 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-24 02:22:25,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:25,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:25,488 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:25,490 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-24 02:22:26,699 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-11-24 02:22:26,699 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:26,710 INFO L256 TraceCheckSpWp]: Trace formula consists of 977 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:26,716 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:26,745 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2024-11-24 02:22:26,745 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:26,897 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 230 trivial. 0 not checked. [2024-11-24 02:22:26,897 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:26,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [143121211] [2024-11-24 02:22:26,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [143121211] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:26,897 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:26,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:26,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320154721] [2024-11-24 02:22:26,897 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:26,898 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:26,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:26,898 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:26,899 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:26,899 INFO L87 Difference]: Start difference. First operand 75 states and 90 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:26,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:26,991 INFO L93 Difference]: Finished difference Result 122 states and 148 transitions. [2024-11-24 02:22:26,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:26,992 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 110 [2024-11-24 02:22:26,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:26,993 INFO L225 Difference]: With dead ends: 122 [2024-11-24 02:22:26,993 INFO L226 Difference]: Without dead ends: 81 [2024-11-24 02:22:26,993 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:26,994 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:26,994 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:26,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2024-11-24 02:22:27,007 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2024-11-24 02:22:27,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 69 states have (on average 1.1014492753623188) internal successors, (76), 69 states have internal predecessors, (76), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:27,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 96 transitions. [2024-11-24 02:22:27,012 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 96 transitions. Word has length 110 [2024-11-24 02:22:27,013 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:27,013 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 96 transitions. [2024-11-24 02:22:27,013 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:27,013 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 96 transitions. [2024-11-24 02:22:27,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2024-11-24 02:22:27,015 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:27,015 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:27,032 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-24 02:22:27,216 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:27,216 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:27,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:27,217 INFO L85 PathProgramCache]: Analyzing trace with hash 710782511, now seen corresponding path program 4 times [2024-11-24 02:22:27,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:27,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1027091151] [2024-11-24 02:22:27,218 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-24 02:22:27,218 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:27,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:27,222 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:27,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-24 02:22:28,341 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-24 02:22:28,342 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:28,356 INFO L256 TraceCheckSpWp]: Trace formula consists of 1154 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:28,362 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:28,383 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-11-24 02:22:28,383 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:28,474 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-11-24 02:22:28,474 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:28,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1027091151] [2024-11-24 02:22:28,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1027091151] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:28,474 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:28,475 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:28,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163266730] [2024-11-24 02:22:28,475 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:28,475 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:28,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:28,476 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:28,476 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:28,476 INFO L87 Difference]: Start difference. First operand 81 states and 96 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:28,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:28,566 INFO L93 Difference]: Finished difference Result 134 states and 160 transitions. [2024-11-24 02:22:28,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:28,567 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 116 [2024-11-24 02:22:28,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:28,568 INFO L225 Difference]: With dead ends: 134 [2024-11-24 02:22:28,568 INFO L226 Difference]: Without dead ends: 87 [2024-11-24 02:22:28,568 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:28,569 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 129 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 176 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:28,571 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 176 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:28,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2024-11-24 02:22:28,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2024-11-24 02:22:28,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 75 states have (on average 1.0933333333333333) internal successors, (82), 75 states have internal predecessors, (82), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:28,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 102 transitions. [2024-11-24 02:22:28,590 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 102 transitions. Word has length 116 [2024-11-24 02:22:28,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:28,590 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 102 transitions. [2024-11-24 02:22:28,590 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:28,591 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 102 transitions. [2024-11-24 02:22:28,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2024-11-24 02:22:28,592 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:28,592 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:28,609 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-11-24 02:22:28,792 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:28,793 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:28,793 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:28,793 INFO L85 PathProgramCache]: Analyzing trace with hash -739418781, now seen corresponding path program 5 times [2024-11-24 02:22:28,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:28,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [704831947] [2024-11-24 02:22:28,794 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-24 02:22:28,794 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:28,794 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:28,796 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:28,797 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-24 02:22:34,108 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-11-24 02:22:34,108 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:34,123 INFO L256 TraceCheckSpWp]: Trace formula consists of 963 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-24 02:22:34,130 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:34,157 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-24 02:22:34,157 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:34,253 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2024-11-24 02:22:34,254 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:34,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [704831947] [2024-11-24 02:22:34,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [704831947] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:34,254 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:34,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-24 02:22:34,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [203153028] [2024-11-24 02:22:34,254 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:34,255 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-24 02:22:34,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:34,255 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-24 02:22:34,257 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-24 02:22:34,257 INFO L87 Difference]: Start difference. First operand 87 states and 102 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:34,386 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:34,386 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2024-11-24 02:22:34,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 02:22:34,387 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 122 [2024-11-24 02:22:34,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:34,388 INFO L225 Difference]: With dead ends: 146 [2024-11-24 02:22:34,389 INFO L226 Difference]: Without dead ends: 93 [2024-11-24 02:22:34,389 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-24 02:22:34,389 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:34,390 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:34,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2024-11-24 02:22:34,399 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2024-11-24 02:22:34,400 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 81 states have (on average 1.0864197530864197) internal successors, (88), 81 states have internal predecessors, (88), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-24 02:22:34,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 108 transitions. [2024-11-24 02:22:34,402 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 108 transitions. Word has length 122 [2024-11-24 02:22:34,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:34,402 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 108 transitions. [2024-11-24 02:22:34,403 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:34,403 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 108 transitions. [2024-11-24 02:22:34,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-11-24 02:22:34,404 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:34,405 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:34,430 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-24 02:22:34,605 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:34,606 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:34,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:34,606 INFO L85 PathProgramCache]: Analyzing trace with hash -651047657, now seen corresponding path program 6 times [2024-11-24 02:22:34,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:34,607 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [174218598] [2024-11-24 02:22:34,607 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-24 02:22:34,607 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:34,607 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:34,609 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:34,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-24 02:22:37,571 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-11-24 02:22:37,572 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:37,588 INFO L256 TraceCheckSpWp]: Trace formula consists of 1124 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-11-24 02:22:37,598 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:38,776 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 34 refuted. 0 times theorem prover too weak. 242 trivial. 0 not checked. [2024-11-24 02:22:38,777 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:38,902 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:38,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [174218598] [2024-11-24 02:22:38,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [174218598] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:22:38,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1057013362] [2024-11-24 02:22:38,903 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-24 02:22:38,903 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 02:22:38,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 02:22:38,918 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 02:22:38,920 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2024-11-24 02:22:41,832 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2024-11-24 02:22:41,833 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:41,884 INFO L256 TraceCheckSpWp]: Trace formula consists of 1124 conjuncts, 44 conjuncts are in the unsatisfiable core [2024-11-24 02:22:41,892 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:43,230 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 249 trivial. 0 not checked. [2024-11-24 02:22:43,230 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:43,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1057013362] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:22:43,400 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:43,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 11] total 17 [2024-11-24 02:22:43,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428384131] [2024-11-24 02:22:43,401 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:43,401 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2024-11-24 02:22:43,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:43,402 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2024-11-24 02:22:43,402 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=327, Unknown=0, NotChecked=0, Total=380 [2024-11-24 02:22:43,402 INFO L87 Difference]: Start difference. First operand 93 states and 108 transitions. Second operand has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-11-24 02:22:44,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:44,645 INFO L93 Difference]: Finished difference Result 169 states and 195 transitions. [2024-11-24 02:22:44,645 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-11-24 02:22:44,646 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) Word has length 128 [2024-11-24 02:22:44,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:44,647 INFO L225 Difference]: With dead ends: 169 [2024-11-24 02:22:44,647 INFO L226 Difference]: Without dead ends: 167 [2024-11-24 02:22:44,648 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 244 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=94, Invalid=506, Unknown=0, NotChecked=0, Total=600 [2024-11-24 02:22:44,648 INFO L435 NwaCegarLoop]: 39 mSDtfsCounter, 58 mSDsluCounter, 423 mSDsCounter, 0 mSdLazyCounter, 453 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 462 SdHoareTripleChecker+Invalid, 457 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 453 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:44,649 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 462 Invalid, 457 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 453 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-24 02:22:44,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2024-11-24 02:22:44,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 146. [2024-11-24 02:22:44,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 129 states have (on average 1.0852713178294573) internal successors, (140), 129 states have internal predecessors, (140), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-11-24 02:22:44,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 170 transitions. [2024-11-24 02:22:44,676 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 170 transitions. Word has length 128 [2024-11-24 02:22:44,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:44,678 INFO L471 AbstractCegarLoop]: Abstraction has 146 states and 170 transitions. [2024-11-24 02:22:44,678 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 15 states have (on average 5.133333333333334) internal successors, (77), 16 states have internal predecessors, (77), 5 states have call successors, (16), 1 states have call predecessors, (16), 2 states have return successors, (16), 5 states have call predecessors, (16), 5 states have call successors, (16) [2024-11-24 02:22:44,678 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 170 transitions. [2024-11-24 02:22:44,681 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 202 [2024-11-24 02:22:44,682 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:44,682 INFO L218 NwaCegarLoop]: trace histogram [15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:44,701 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-11-24 02:22:44,907 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (17)] Forceful destruction successful, exit code 0 [2024-11-24 02:22:45,083 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt [2024-11-24 02:22:45,083 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:45,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:45,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1549169454, now seen corresponding path program 7 times [2024-11-24 02:22:45,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:45,085 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [534194233] [2024-11-24 02:22:45,085 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-24 02:22:45,085 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:45,085 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:45,087 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:45,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-24 02:22:46,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 02:22:46,721 INFO L256 TraceCheckSpWp]: Trace formula consists of 2056 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-24 02:22:46,726 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:46,794 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 308 proven. 16 refuted. 0 times theorem prover too weak. 461 trivial. 0 not checked. [2024-11-24 02:22:46,795 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:47,036 INFO L134 CoverageAnalysis]: Checked inductivity of 785 backedges. 108 proven. 16 refuted. 0 times theorem prover too weak. 661 trivial. 0 not checked. [2024-11-24 02:22:47,036 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:47,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [534194233] [2024-11-24 02:22:47,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [534194233] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:47,036 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:47,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-11-24 02:22:47,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116983386] [2024-11-24 02:22:47,036 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:47,037 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-11-24 02:22:47,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:47,038 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-24 02:22:47,038 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:22:47,038 INFO L87 Difference]: Start difference. First operand 146 states and 170 transitions. Second operand has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:47,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:47,406 INFO L93 Difference]: Finished difference Result 262 states and 313 transitions. [2024-11-24 02:22:47,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-24 02:22:47,407 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 201 [2024-11-24 02:22:47,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:47,409 INFO L225 Difference]: With dead ends: 262 [2024-11-24 02:22:47,409 INFO L226 Difference]: Without dead ends: 170 [2024-11-24 02:22:47,410 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 404 GetRequests, 389 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-11-24 02:22:47,410 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 5 mSDsluCounter, 301 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 347 SdHoareTripleChecker+Invalid, 82 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:47,411 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 347 Invalid, 82 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-24 02:22:47,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 170 states. [2024-11-24 02:22:47,431 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 170 to 170. [2024-11-24 02:22:47,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 170 states, 153 states have (on average 1.0849673202614378) internal successors, (166), 153 states have internal predecessors, (166), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-11-24 02:22:47,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 196 transitions. [2024-11-24 02:22:47,433 INFO L78 Accepts]: Start accepts. Automaton has 170 states and 196 transitions. Word has length 201 [2024-11-24 02:22:47,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:47,434 INFO L471 AbstractCegarLoop]: Abstraction has 170 states and 196 transitions. [2024-11-24 02:22:47,434 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 5.615384615384615) internal successors, (73), 13 states have internal predecessors, (73), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-24 02:22:47,434 INFO L276 IsEmpty]: Start isEmpty. Operand 170 states and 196 transitions. [2024-11-24 02:22:47,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2024-11-24 02:22:47,437 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:47,437 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:47,462 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-11-24 02:22:47,638 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:47,638 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:47,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:47,638 INFO L85 PathProgramCache]: Analyzing trace with hash 831217618, now seen corresponding path program 8 times [2024-11-24 02:22:47,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:47,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1289487887] [2024-11-24 02:22:47,639 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-24 02:22:47,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:47,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:47,642 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:47,643 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-24 02:22:49,371 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-24 02:22:49,371 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:49,395 INFO L256 TraceCheckSpWp]: Trace formula consists of 2104 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-24 02:22:49,403 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:22:49,461 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-11-24 02:22:49,461 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:22:49,670 INFO L134 CoverageAnalysis]: Checked inductivity of 985 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 969 trivial. 0 not checked. [2024-11-24 02:22:49,670 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:22:49,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1289487887] [2024-11-24 02:22:49,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1289487887] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 02:22:49,670 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-24 02:22:49,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2024-11-24 02:22:49,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874248568] [2024-11-24 02:22:49,671 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-24 02:22:49,672 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-11-24 02:22:49,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-24 02:22:49,672 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-24 02:22:49,673 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-11-24 02:22:49,673 INFO L87 Difference]: Start difference. First operand 170 states and 196 transitions. Second operand has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:49,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 02:22:49,935 INFO L93 Difference]: Finished difference Result 341 states and 398 transitions. [2024-11-24 02:22:49,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-24 02:22:49,937 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 217 [2024-11-24 02:22:49,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 02:22:49,939 INFO L225 Difference]: With dead ends: 341 [2024-11-24 02:22:49,939 INFO L226 Difference]: Without dead ends: 182 [2024-11-24 02:22:49,940 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 436 GetRequests, 421 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=175, Unknown=0, NotChecked=0, Total=272 [2024-11-24 02:22:49,942 INFO L435 NwaCegarLoop]: 46 mSDtfsCounter, 6 mSDsluCounter, 264 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 310 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 02:22:49,943 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 310 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 02:22:49,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2024-11-24 02:22:49,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 182. [2024-11-24 02:22:49,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 165 states have (on average 1.084848484848485) internal successors, (179), 165 states have internal predecessors, (179), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-11-24 02:22:49,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 209 transitions. [2024-11-24 02:22:49,972 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 209 transitions. Word has length 217 [2024-11-24 02:22:49,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 02:22:49,973 INFO L471 AbstractCegarLoop]: Abstraction has 182 states and 209 transitions. [2024-11-24 02:22:49,973 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 4.461538461538462) internal successors, (58), 13 states have internal predecessors, (58), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-24 02:22:49,973 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 209 transitions. [2024-11-24 02:22:49,976 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 226 [2024-11-24 02:22:49,976 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 02:22:49,977 INFO L218 NwaCegarLoop]: trace histogram [16, 16, 15, 15, 15, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 02:22:50,002 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-11-24 02:22:50,177 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:50,178 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 02:22:50,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 02:22:50,178 INFO L85 PathProgramCache]: Analyzing trace with hash 958267074, now seen corresponding path program 9 times [2024-11-24 02:22:50,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-24 02:22:50,180 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [132254608] [2024-11-24 02:22:50,181 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-24 02:22:50,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 02:22:50,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 02:22:50,183 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 02:22:50,186 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-24 02:22:53,739 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-11-24 02:22:53,739 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:22:53,762 INFO L256 TraceCheckSpWp]: Trace formula consists of 1734 conjuncts, 146 conjuncts are in the unsatisfiable core [2024-11-24 02:22:53,786 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:23:01,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1033 backedges. 51 proven. 344 refuted. 0 times theorem prover too weak. 638 trivial. 0 not checked. [2024-11-24 02:23:01,488 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:23:02,719 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-24 02:23:02,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [132254608] [2024-11-24 02:23:02,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [132254608] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 02:23:02,720 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2086082437] [2024-11-24 02:23:02,720 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-24 02:23:02,720 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-11-24 02:23:02,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 [2024-11-24 02:23:02,724 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-11-24 02:23:02,726 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_190e9d57-128f-470a-a9d4-864fd157d17f/bin/uautomizer-verify-LYvppIcaGC/cvc4 --incremental --print-success --lang smt (21)] Waiting until timeout for monitored process [2024-11-24 02:23:07,394 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2024-11-24 02:23:07,394 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-24 02:23:07,498 INFO L256 TraceCheckSpWp]: Trace formula consists of 1734 conjuncts, 198 conjuncts are in the unsatisfiable core [2024-11-24 02:23:07,532 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 02:23:30,055 INFO L134 CoverageAnalysis]: Checked inductivity of 1033 backedges. 51 proven. 336 refuted. 0 times theorem prover too weak. 646 trivial. 0 not checked. [2024-11-24 02:23:30,055 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 02:23:35,455 WARN L851 $PredicateComparison]: unable to prove that (let ((.cse1 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|)) (.cse2 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_85~0#1|)) (.cse5 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_89~0#1|))) (or (let ((.cse0 (= (_ bv0 8) |c_ULTIMATE.start_main_~state_111~0#1|))) (and (or .cse0 (forall ((|v_ULTIMATE.start_main_~var_88_arg_1~0#1_59| (_ BitVec 8))) (= ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv255 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv1 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse2 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_88_arg_1~0#1_59|))))))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_110~0#1|)))))))) (_ bv0 8)))) (or (not .cse0) (forall ((|v_ULTIMATE.start_main_~var_88_arg_1~0#1_59| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_113_arg_2~0#1_58| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv255 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv1 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse2 ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_88_arg_1~0#1_59|))))))))))))))))))) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_113_arg_2~0#1_58|))))))))))))) (let ((.cse9 (= (_ bv0 8) |c_ULTIMATE.start_main_~input_9~0#1|)) (.cse7 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_15~0#1|))) (let ((.cse8 (bvsge ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_55~0#1|) ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse7 ((_ zero_extend 24) |c_ULTIMATE.start_main_~var_27~0#1|)))))) (.cse3 (or .cse9 (forall ((|v_ULTIMATE.start_main_~var_100_arg_1~0#1_57| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_100_arg_1~0#1_57|))) .cse7)))))))) (.cse6 ((_ zero_extend 24) ((_ extract 7 0) (bvnot .cse2)))) (.cse4 (not .cse9))) (and (or (and .cse3 (or .cse4 (forall ((|v_ULTIMATE.start_main_~var_58_arg_0~0#1_58| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_94_arg_0~0#1_57| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse5 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_94_arg_0~0#1_57|) .cse6))))))))) (bvneg ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_31~0#1|))))))) ((_ zero_extend 24) ((_ extract 7 0) (bvand (_ bv1 32) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_58_arg_0~0#1_58|))))))))))))))))))) .cse7)))))))) (not .cse8)) (or .cse8 (and .cse3 (or (forall ((|v_ULTIMATE.start_main_~var_94_arg_0~0#1_57| (_ BitVec 8))) (not (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvadd .cse5 ((_ zero_extend 24) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_94_arg_0~0#1_57|) .cse6))))))))))))) .cse7)))))) .cse4)))))) (= .cse5 (_ bv0 32)))) is different from false