./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 6497de01 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 8f31ff9fd5db46adb25147e0fbf291c418028d385863b43400756ebcfdf80a2d --- Real Ultimate output --- This is Ultimate 0.3.0-dev-6497de0 [2024-11-24 00:09:53,108 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-24 00:09:53,183 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-24 00:09:53,194 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-24 00:09:53,195 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-24 00:09:53,233 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-24 00:09:53,234 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-24 00:09:53,234 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-24 00:09:53,235 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-24 00:09:53,235 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-24 00:09:53,235 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-24 00:09:53,235 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-24 00:09:53,236 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-24 00:09:53,236 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-24 00:09:53,236 INFO L153 SettingsManager]: * Use SBE=true [2024-11-24 00:09:53,236 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-24 00:09:53,237 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-24 00:09:53,238 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:09:53,238 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-24 00:09:53,238 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-24 00:09:53,239 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-24 00:09:53,239 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-24 00:09:53,239 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:09:53,239 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-24 00:09:53,240 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-24 00:09:53,241 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-24 00:09:53,241 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-24 00:09:53,241 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8f31ff9fd5db46adb25147e0fbf291c418028d385863b43400756ebcfdf80a2d [2024-11-24 00:09:53,575 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-24 00:09:53,589 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-24 00:09:53,592 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-24 00:09:53,594 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-24 00:09:53,595 INFO L274 PluginConnector]: CDTParser initialized [2024-11-24 00:09:53,598 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c [2024-11-24 00:09:56,943 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/data/955d55b48/1ecf15a71da54980999f73ca822f8358/FLAGb3cb98187 [2024-11-24 00:09:57,357 INFO L384 CDTParser]: Found 1 translation units. [2024-11-24 00:09:57,361 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c [2024-11-24 00:09:57,383 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/data/955d55b48/1ecf15a71da54980999f73ca822f8358/FLAGb3cb98187 [2024-11-24 00:09:57,541 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/data/955d55b48/1ecf15a71da54980999f73ca822f8358 [2024-11-24 00:09:57,544 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-24 00:09:57,546 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-24 00:09:57,548 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-24 00:09:57,549 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-24 00:09:57,554 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-24 00:09:57,555 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:09:57" (1/1) ... [2024-11-24 00:09:57,557 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4ba04982 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:57, skipping insertion in model container [2024-11-24 00:09:57,558 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.11 12:09:57" (1/1) ... [2024-11-24 00:09:57,602 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-24 00:09:57,824 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c[1258,1271] [2024-11-24 00:09:58,055 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:09:58,066 INFO L200 MainTranslator]: Completed pre-run [2024-11-24 00:09:58,079 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.vis_QF_BV_fru32_p2.c[1258,1271] [2024-11-24 00:09:58,168 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-24 00:09:58,184 INFO L204 MainTranslator]: Completed translation [2024-11-24 00:09:58,185 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58 WrapperNode [2024-11-24 00:09:58,185 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-24 00:09:58,186 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-24 00:09:58,186 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-24 00:09:58,187 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-24 00:09:58,195 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,226 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,406 INFO L138 Inliner]: procedures = 17, calls = 8, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 940 [2024-11-24 00:09:58,407 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-24 00:09:58,408 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-24 00:09:58,408 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-24 00:09:58,408 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-24 00:09:58,421 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,422 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,444 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,488 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-24 00:09:58,488 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,488 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,522 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,525 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,534 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,544 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,553 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,570 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-24 00:09:58,571 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-24 00:09:58,571 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-24 00:09:58,571 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-24 00:09:58,573 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (1/1) ... [2024-11-24 00:09:58,579 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-24 00:09:58,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:09:58,612 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-24 00:09:58,615 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-24 00:09:58,645 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-24 00:09:58,646 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-24 00:09:58,646 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-24 00:09:58,646 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-24 00:09:58,865 INFO L234 CfgBuilder]: Building ICFG [2024-11-24 00:09:58,867 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-24 00:10:00,681 INFO L? ?]: Removed 456 outVars from TransFormulas that were not future-live. [2024-11-24 00:10:00,681 INFO L283 CfgBuilder]: Performing block encoding [2024-11-24 00:10:00,705 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-24 00:10:00,706 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-24 00:10:00,706 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:10:00 BoogieIcfgContainer [2024-11-24 00:10:00,707 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-24 00:10:00,709 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-24 00:10:00,709 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-24 00:10:00,718 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-24 00:10:00,718 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.11 12:09:57" (1/3) ... [2024-11-24 00:10:00,719 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d08c7aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:10:00, skipping insertion in model container [2024-11-24 00:10:00,719 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.11 12:09:58" (2/3) ... [2024-11-24 00:10:00,719 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d08c7aa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.11 12:10:00, skipping insertion in model container [2024-11-24 00:10:00,719 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:10:00" (3/3) ... [2024-11-24 00:10:00,720 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.vis_QF_BV_fru32_p2.c [2024-11-24 00:10:00,739 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-24 00:10:00,741 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.vis_QF_BV_fru32_p2.c that has 1 procedures, 246 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-24 00:10:00,820 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-24 00:10:00,839 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@68d7b936, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-24 00:10:00,839 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-24 00:10:00,845 INFO L276 IsEmpty]: Start isEmpty. Operand has 246 states, 244 states have (on average 1.4959016393442623) internal successors, (365), 245 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:00,857 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2024-11-24 00:10:00,857 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:00,858 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:00,859 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:00,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:00,864 INFO L85 PathProgramCache]: Analyzing trace with hash 311642819, now seen corresponding path program 1 times [2024-11-24 00:10:00,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:00,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095438398] [2024-11-24 00:10:00,874 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:00,874 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:01,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:03,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-24 00:10:03,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:03,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095438398] [2024-11-24 00:10:03,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095438398] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:10:03,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:10:03,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:10:03,027 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1085307158] [2024-11-24 00:10:03,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:10:03,034 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:10:03,035 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:03,062 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:10:03,063 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:03,067 INFO L87 Difference]: Start difference. First operand has 246 states, 244 states have (on average 1.4959016393442623) internal successors, (365), 245 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 4 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:03,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:03,174 INFO L93 Difference]: Finished difference Result 417 states and 621 transitions. [2024-11-24 00:10:03,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:10:03,177 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 28.25) internal successors, (113), 4 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 113 [2024-11-24 00:10:03,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:03,187 INFO L225 Difference]: With dead ends: 417 [2024-11-24 00:10:03,187 INFO L226 Difference]: Without dead ends: 245 [2024-11-24 00:10:03,191 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:03,194 INFO L435 NwaCegarLoop]: 359 mSDtfsCounter, 0 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1071 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:03,195 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1071 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:10:03,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2024-11-24 00:10:03,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 245. [2024-11-24 00:10:03,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 244 states have (on average 1.4877049180327868) internal successors, (363), 244 states have internal predecessors, (363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:03,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 363 transitions. [2024-11-24 00:10:03,263 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 363 transitions. Word has length 113 [2024-11-24 00:10:03,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:03,264 INFO L471 AbstractCegarLoop]: Abstraction has 245 states and 363 transitions. [2024-11-24 00:10:03,264 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 28.25) internal successors, (113), 4 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:03,264 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 363 transitions. [2024-11-24 00:10:03,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2024-11-24 00:10:03,268 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:03,268 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:03,268 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2024-11-24 00:10:03,269 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:03,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:03,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1072688652, now seen corresponding path program 1 times [2024-11-24 00:10:03,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:03,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745672237] [2024-11-24 00:10:03,270 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:03,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:03,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:04,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-24 00:10:04,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:04,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745672237] [2024-11-24 00:10:04,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745672237] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:10:04,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:10:04,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:10:04,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378542843] [2024-11-24 00:10:04,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:10:04,014 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:10:04,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:04,016 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:10:04,017 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:04,017 INFO L87 Difference]: Start difference. First operand 245 states and 363 transitions. Second operand has 4 states, 4 states have (on average 28.5) internal successors, (114), 4 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:04,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:04,102 INFO L93 Difference]: Finished difference Result 418 states and 619 transitions. [2024-11-24 00:10:04,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:10:04,106 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 28.5) internal successors, (114), 4 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 114 [2024-11-24 00:10:04,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:04,108 INFO L225 Difference]: With dead ends: 418 [2024-11-24 00:10:04,108 INFO L226 Difference]: Without dead ends: 247 [2024-11-24 00:10:04,109 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:04,114 INFO L435 NwaCegarLoop]: 359 mSDtfsCounter, 0 mSDsluCounter, 708 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1067 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:04,115 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1067 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:10:04,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2024-11-24 00:10:04,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2024-11-24 00:10:04,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 247 states, 246 states have (on average 1.483739837398374) internal successors, (365), 246 states have internal predecessors, (365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:04,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 365 transitions. [2024-11-24 00:10:04,136 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 365 transitions. Word has length 114 [2024-11-24 00:10:04,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:04,136 INFO L471 AbstractCegarLoop]: Abstraction has 247 states and 365 transitions. [2024-11-24 00:10:04,137 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 28.5) internal successors, (114), 4 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:04,137 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 365 transitions. [2024-11-24 00:10:04,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2024-11-24 00:10:04,139 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:04,140 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:04,140 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-24 00:10:04,140 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:04,141 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:04,141 INFO L85 PathProgramCache]: Analyzing trace with hash 2090611900, now seen corresponding path program 1 times [2024-11-24 00:10:04,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:04,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481656798] [2024-11-24 00:10:04,141 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:04,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:04,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:05,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-24 00:10:05,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:05,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481656798] [2024-11-24 00:10:05,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481656798] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:10:05,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:10:05,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-24 00:10:05,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [789255530] [2024-11-24 00:10:05,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:10:05,150 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-24 00:10:05,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:05,154 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-24 00:10:05,154 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:05,154 INFO L87 Difference]: Start difference. First operand 247 states and 365 transitions. Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:05,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:05,214 INFO L93 Difference]: Finished difference Result 422 states and 623 transitions. [2024-11-24 00:10:05,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-24 00:10:05,215 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 115 [2024-11-24 00:10:05,216 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:05,218 INFO L225 Difference]: With dead ends: 422 [2024-11-24 00:10:05,218 INFO L226 Difference]: Without dead ends: 249 [2024-11-24 00:10:05,219 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-24 00:10:05,222 INFO L435 NwaCegarLoop]: 359 mSDtfsCounter, 0 mSDsluCounter, 708 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1067 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:05,223 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1067 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-24 00:10:05,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2024-11-24 00:10:05,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 249. [2024-11-24 00:10:05,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 249 states, 248 states have (on average 1.4798387096774193) internal successors, (367), 248 states have internal predecessors, (367), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:05,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 367 transitions. [2024-11-24 00:10:05,246 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 367 transitions. Word has length 115 [2024-11-24 00:10:05,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:05,246 INFO L471 AbstractCegarLoop]: Abstraction has 249 states and 367 transitions. [2024-11-24 00:10:05,246 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 28.75) internal successors, (115), 4 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:05,246 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 367 transitions. [2024-11-24 00:10:05,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2024-11-24 00:10:05,248 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:05,248 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:05,249 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-24 00:10:05,249 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:05,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:05,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1293346963, now seen corresponding path program 1 times [2024-11-24 00:10:05,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:05,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533463690] [2024-11-24 00:10:05,250 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:05,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:05,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:06,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-24 00:10:06,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:06,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533463690] [2024-11-24 00:10:06,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533463690] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:10:06,483 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:10:06,483 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-24 00:10:06,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568613530] [2024-11-24 00:10:06,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:10:06,483 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-24 00:10:06,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:06,484 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-24 00:10:06,484 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-24 00:10:06,485 INFO L87 Difference]: Start difference. First operand 249 states and 367 transitions. Second operand has 6 states, 6 states have (on average 19.333333333333332) internal successors, (116), 6 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:06,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:06,616 INFO L93 Difference]: Finished difference Result 514 states and 759 transitions. [2024-11-24 00:10:06,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-24 00:10:06,617 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 19.333333333333332) internal successors, (116), 6 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 116 [2024-11-24 00:10:06,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:06,619 INFO L225 Difference]: With dead ends: 514 [2024-11-24 00:10:06,619 INFO L226 Difference]: Without dead ends: 339 [2024-11-24 00:10:06,620 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-24 00:10:06,621 INFO L435 NwaCegarLoop]: 354 mSDtfsCounter, 523 mSDsluCounter, 1051 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 523 SdHoareTripleChecker+Valid, 1405 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:06,621 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [523 Valid, 1405 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:10:06,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2024-11-24 00:10:06,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 339. [2024-11-24 00:10:06,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 339 states, 338 states have (on average 1.482248520710059) internal successors, (501), 338 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:06,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 501 transitions. [2024-11-24 00:10:06,641 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 501 transitions. Word has length 116 [2024-11-24 00:10:06,642 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:06,642 INFO L471 AbstractCegarLoop]: Abstraction has 339 states and 501 transitions. [2024-11-24 00:10:06,642 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 19.333333333333332) internal successors, (116), 6 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:06,642 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 501 transitions. [2024-11-24 00:10:06,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2024-11-24 00:10:06,645 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:06,645 INFO L218 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:06,645 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-11-24 00:10:06,645 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:06,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:06,646 INFO L85 PathProgramCache]: Analyzing trace with hash -850084197, now seen corresponding path program 1 times [2024-11-24 00:10:06,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:06,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898546002] [2024-11-24 00:10:06,647 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:06,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:07,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:07,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-24 00:10:07,452 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:07,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898546002] [2024-11-24 00:10:07,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898546002] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-24 00:10:07,453 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-24 00:10:07,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-24 00:10:07,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241827173] [2024-11-24 00:10:07,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-24 00:10:07,454 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-24 00:10:07,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:07,455 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-24 00:10:07,455 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-24 00:10:07,455 INFO L87 Difference]: Start difference. First operand 339 states and 501 transitions. Second operand has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:07,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:07,587 INFO L93 Difference]: Finished difference Result 646 states and 955 transitions. [2024-11-24 00:10:07,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-24 00:10:07,588 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 117 [2024-11-24 00:10:07,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:07,589 INFO L225 Difference]: With dead ends: 646 [2024-11-24 00:10:07,590 INFO L226 Difference]: Without dead ends: 381 [2024-11-24 00:10:07,590 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-24 00:10:07,594 INFO L435 NwaCegarLoop]: 348 mSDtfsCounter, 426 mSDsluCounter, 693 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 426 SdHoareTripleChecker+Valid, 1041 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:07,595 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [426 Valid, 1041 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-24 00:10:07,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2024-11-24 00:10:07,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 381. [2024-11-24 00:10:07,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 380 states have (on average 1.481578947368421) internal successors, (563), 380 states have internal predecessors, (563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:07,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 563 transitions. [2024-11-24 00:10:07,623 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 563 transitions. Word has length 117 [2024-11-24 00:10:07,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:07,623 INFO L471 AbstractCegarLoop]: Abstraction has 381 states and 563 transitions. [2024-11-24 00:10:07,624 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.4) internal successors, (117), 5 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:07,624 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 563 transitions. [2024-11-24 00:10:07,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 203 [2024-11-24 00:10:07,629 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:07,629 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:07,629 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-11-24 00:10:07,630 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:07,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:07,632 INFO L85 PathProgramCache]: Analyzing trace with hash 547509629, now seen corresponding path program 1 times [2024-11-24 00:10:07,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:07,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961898756] [2024-11-24 00:10:07,633 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:07,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:08,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:10,810 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 2 proven. 64 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-24 00:10:10,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-24 00:10:10,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961898756] [2024-11-24 00:10:10,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961898756] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-24 00:10:10,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [202818671] [2024-11-24 00:10:10,812 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:10,812 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:10:10,812 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 [2024-11-24 00:10:10,815 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-24 00:10:10,818 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-24 00:10:11,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-24 00:10:11,963 INFO L256 TraceCheckSpWp]: Trace formula consists of 1290 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-11-24 00:10:11,974 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-24 00:10:13,822 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 11 proven. 3 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:10:13,822 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-24 00:10:16,790 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 7 proven. 7 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-11-24 00:10:16,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [202818671] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-24 00:10:16,791 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-24 00:10:16,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 12] total 23 [2024-11-24 00:10:16,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011793803] [2024-11-24 00:10:16,791 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-24 00:10:16,792 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 23 states [2024-11-24 00:10:16,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-24 00:10:16,793 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2024-11-24 00:10:16,794 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=428, Unknown=0, NotChecked=0, Total=506 [2024-11-24 00:10:16,794 INFO L87 Difference]: Start difference. First operand 381 states and 563 transitions. Second operand has 23 states, 23 states have (on average 20.695652173913043) internal successors, (476), 23 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:18,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-24 00:10:18,351 INFO L93 Difference]: Finished difference Result 660 states and 976 transitions. [2024-11-24 00:10:18,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-11-24 00:10:18,353 INFO L78 Accepts]: Start accepts. Automaton has has 23 states, 23 states have (on average 20.695652173913043) internal successors, (476), 23 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 202 [2024-11-24 00:10:18,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-24 00:10:18,357 INFO L225 Difference]: With dead ends: 660 [2024-11-24 00:10:18,357 INFO L226 Difference]: Without dead ends: 395 [2024-11-24 00:10:18,358 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 417 GetRequests, 389 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=129, Invalid=741, Unknown=0, NotChecked=0, Total=870 [2024-11-24 00:10:18,359 INFO L435 NwaCegarLoop]: 222 mSDtfsCounter, 488 mSDsluCounter, 2191 mSDsCounter, 0 mSdLazyCounter, 1557 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 488 SdHoareTripleChecker+Valid, 2413 SdHoareTripleChecker+Invalid, 1565 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 1557 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-24 00:10:18,360 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [488 Valid, 2413 Invalid, 1565 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 1557 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-24 00:10:18,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 395 states. [2024-11-24 00:10:18,383 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 395 to 393. [2024-11-24 00:10:18,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 392 states have (on average 1.471938775510204) internal successors, (577), 392 states have internal predecessors, (577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:18,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 577 transitions. [2024-11-24 00:10:18,389 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 577 transitions. Word has length 202 [2024-11-24 00:10:18,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-24 00:10:18,389 INFO L471 AbstractCegarLoop]: Abstraction has 393 states and 577 transitions. [2024-11-24 00:10:18,390 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 23 states, 23 states have (on average 20.695652173913043) internal successors, (476), 23 states have internal predecessors, (476), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-24 00:10:18,390 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 577 transitions. [2024-11-24 00:10:18,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2024-11-24 00:10:18,395 INFO L210 NwaCegarLoop]: Found error trace [2024-11-24 00:10:18,396 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:18,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-24 00:10:18,596 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-24 00:10:18,596 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-24 00:10:18,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-24 00:10:18,597 INFO L85 PathProgramCache]: Analyzing trace with hash -611481975, now seen corresponding path program 1 times [2024-11-24 00:10:18,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-24 00:10:18,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306252891] [2024-11-24 00:10:18,597 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-24 00:10:18,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-24 00:10:19,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 00:10:19,799 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-24 00:10:20,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-24 00:10:21,092 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-24 00:10:21,094 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-24 00:10:21,095 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-24 00:10:21,097 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-11-24 00:10:21,101 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1] [2024-11-24 00:10:21,330 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-24 00:10:21,337 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.11 12:10:21 BoogieIcfgContainer [2024-11-24 00:10:21,337 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-24 00:10:21,338 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-24 00:10:21,338 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-24 00:10:21,338 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-24 00:10:21,340 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.11 12:10:00" (3/4) ... [2024-11-24 00:10:21,341 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-24 00:10:21,663 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 6. [2024-11-24 00:10:21,731 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/witness.graphml [2024-11-24 00:10:21,732 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/witness.yml [2024-11-24 00:10:21,732 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-24 00:10:21,735 INFO L158 Benchmark]: Toolchain (without parser) took 24187.27ms. Allocated memory was 142.6MB in the beginning and 520.1MB in the end (delta: 377.5MB). Free memory was 104.2MB in the beginning and 223.7MB in the end (delta: -119.5MB). Peak memory consumption was 252.5MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,735 INFO L158 Benchmark]: CDTParser took 0.50ms. Allocated memory is still 167.8MB. Free memory is still 103.3MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-24 00:10:21,736 INFO L158 Benchmark]: CACSL2BoogieTranslator took 637.04ms. Allocated memory is still 142.6MB. Free memory was 103.9MB in the beginning and 82.3MB in the end (delta: 21.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,736 INFO L158 Benchmark]: Boogie Procedure Inliner took 221.04ms. Allocated memory is still 142.6MB. Free memory was 82.3MB in the beginning and 62.8MB in the end (delta: 19.5MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,736 INFO L158 Benchmark]: Boogie Preprocessor took 162.72ms. Allocated memory is still 142.6MB. Free memory was 62.8MB in the beginning and 52.3MB in the end (delta: 10.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,737 INFO L158 Benchmark]: RCFGBuilder took 2135.54ms. Allocated memory is still 142.6MB. Free memory was 52.3MB in the beginning and 61.6MB in the end (delta: -9.3MB). Peak memory consumption was 45.6MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,738 INFO L158 Benchmark]: TraceAbstraction took 20628.31ms. Allocated memory was 142.6MB in the beginning and 520.1MB in the end (delta: 377.5MB). Free memory was 60.8MB in the beginning and 261.5MB in the end (delta: -200.6MB). Peak memory consumption was 271.2MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,738 INFO L158 Benchmark]: Witness Printer took 393.99ms. Allocated memory is still 520.1MB. Free memory was 261.5MB in the beginning and 223.7MB in the end (delta: 37.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2024-11-24 00:10:21,741 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.50ms. Allocated memory is still 167.8MB. Free memory is still 103.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 637.04ms. Allocated memory is still 142.6MB. Free memory was 103.9MB in the beginning and 82.3MB in the end (delta: 21.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 221.04ms. Allocated memory is still 142.6MB. Free memory was 82.3MB in the beginning and 62.8MB in the end (delta: 19.5MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 162.72ms. Allocated memory is still 142.6MB. Free memory was 62.8MB in the beginning and 52.3MB in the end (delta: 10.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2135.54ms. Allocated memory is still 142.6MB. Free memory was 52.3MB in the beginning and 61.6MB in the end (delta: -9.3MB). Peak memory consumption was 45.6MB. Max. memory is 16.1GB. * TraceAbstraction took 20628.31ms. Allocated memory was 142.6MB in the beginning and 520.1MB in the end (delta: 377.5MB). Free memory was 60.8MB in the beginning and 261.5MB in the end (delta: -200.6MB). Peak memory consumption was 271.2MB. Max. memory is 16.1GB. * Witness Printer took 393.99ms. Allocated memory is still 520.1MB. Free memory was 261.5MB in the beginning and 223.7MB in the end (delta: 37.7MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 6); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (6 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 1); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (1 - 1); [L32] const SORT_6 mask_SORT_6 = (SORT_6)-1 >> (sizeof(SORT_6) * 8 - 32); [L33] const SORT_6 msb_SORT_6 = (SORT_6)1 << (32 - 1); [L35] const SORT_24 mask_SORT_24 = (SORT_24)-1 >> (sizeof(SORT_24) * 8 - 5); [L36] const SORT_24 msb_SORT_24 = (SORT_24)1 << (5 - 1); [L38] const SORT_33 mask_SORT_33 = (SORT_33)-1 >> (sizeof(SORT_33) * 8 - 2); [L39] const SORT_33 msb_SORT_33 = (SORT_33)1 << (2 - 1); [L41] const SORT_1 var_21 = 0; [L42] const SORT_24 var_26 = 31; [L43] const SORT_6 var_28 = 0; [L44] const SORT_33 var_34 = 0; [L45] const SORT_33 var_35 = 1; [L46] const SORT_3 var_39 = 1; [L47] const SORT_3 var_45 = 0; [L48] const SORT_33 var_58 = 2; [L49] const SORT_33 var_75 = 3; [L51] SORT_1 input_2; [L52] SORT_3 input_4; [L53] SORT_1 input_5; [L54] SORT_6 input_7; [L55] SORT_3 input_8; [L56] SORT_6 input_9; [L57] SORT_1 input_10; [L58] SORT_1 input_11; [L59] SORT_1 input_12; [L60] SORT_3 input_13; [L61] SORT_3 input_14; [L62] SORT_3 input_15; [L63] SORT_3 input_16; [L64] SORT_3 input_17; [L65] SORT_3 input_18; [L66] SORT_3 input_19; [L67] SORT_3 input_20; [L68] SORT_3 input_120; [L69] SORT_3 input_124; [L70] SORT_3 input_126; [L71] SORT_33 input_129; [L72] SORT_3 input_131; [L73] SORT_6 input_134; [L74] SORT_3 input_136; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L76] SORT_1 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L77] EXPR __VERIFIER_nondet_uint() & mask_SORT_6 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L77] SORT_6 state_29 = __VERIFIER_nondet_uint() & mask_SORT_6; [L78] EXPR __VERIFIER_nondet_uint() & mask_SORT_6 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L78] SORT_6 state_31 = __VERIFIER_nondet_uint() & mask_SORT_6; [L79] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L79] SORT_1 state_36 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L80] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L81] SORT_3 state_46 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L82] SORT_3 state_50 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L83] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L83] SORT_1 state_60 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L84] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L84] SORT_3 state_64 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L85] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L85] SORT_3 state_68 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L86] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L86] SORT_1 state_77 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L87] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L87] SORT_3 state_81 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L88] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L88] SORT_3 state_85 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L89] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, mask_SORT_6=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L89] SORT_3 state_89 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L90] EXPR __VERIFIER_nondet_uint() & mask_SORT_6 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L90] SORT_6 state_98 = __VERIFIER_nondet_uint() & mask_SORT_6; [L91] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L91] SORT_1 state_116 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L92] SORT_3 state_118 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L93] EXPR __VERIFIER_nondet_uchar() & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_45=0, var_58=2, var_75=3] [L93] SORT_3 state_122 = __VERIFIER_nondet_uchar() & mask_SORT_3; [L95] SORT_1 init_23_arg_1 = var_21; [L96] state_22 = init_23_arg_1 [L97] SORT_6 init_30_arg_1 = var_28; [L98] state_29 = init_30_arg_1 [L99] SORT_6 init_32_arg_1 = var_28; [L100] state_31 = init_32_arg_1 [L101] SORT_1 init_37_arg_1 = var_21; [L102] state_36 = init_37_arg_1 [L103] SORT_1 init_42_arg_1 = var_21; [L104] state_41 = init_42_arg_1 [L105] SORT_3 init_47_arg_1 = var_45; [L106] state_46 = init_47_arg_1 [L107] SORT_3 init_51_arg_1 = var_45; [L108] state_50 = init_51_arg_1 [L109] SORT_1 init_61_arg_1 = var_21; [L110] state_60 = init_61_arg_1 [L111] SORT_3 init_65_arg_1 = var_45; [L112] state_64 = init_65_arg_1 [L113] SORT_3 init_69_arg_1 = var_45; [L114] state_68 = init_69_arg_1 [L115] SORT_1 init_78_arg_1 = var_21; [L116] state_77 = init_78_arg_1 [L117] SORT_3 init_82_arg_1 = var_45; [L118] state_81 = init_82_arg_1 [L119] SORT_3 init_86_arg_1 = var_45; [L120] state_85 = init_86_arg_1 [L121] SORT_3 init_90_arg_1 = var_45; [L122] state_89 = init_90_arg_1 [L123] SORT_6 init_99_arg_1 = var_28; [L124] state_98 = init_99_arg_1 [L125] SORT_1 init_117_arg_1 = var_21; [L126] state_116 = init_117_arg_1 [L127] SORT_3 init_119_arg_1 = var_45; [L128] state_118 = init_119_arg_1 [L129] SORT_3 init_123_arg_1 = var_45; [L130] state_122 = init_123_arg_1 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L133] input_2 = __VERIFIER_nondet_uchar() [L134] input_4 = __VERIFIER_nondet_uchar() [L135] EXPR input_4 & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L135] input_4 = input_4 & mask_SORT_3 [L136] input_5 = __VERIFIER_nondet_uchar() [L137] EXPR input_5 & mask_SORT_1 VAL [input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L137] input_5 = input_5 & mask_SORT_1 [L138] input_7 = __VERIFIER_nondet_uint() [L139] input_8 = __VERIFIER_nondet_uchar() [L140] EXPR input_8 & mask_SORT_3 VAL [input_4=0, input_5=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L140] input_8 = input_8 & mask_SORT_3 [L141] input_9 = __VERIFIER_nondet_uint() [L142] input_10 = __VERIFIER_nondet_uchar() [L143] EXPR input_10 & mask_SORT_1 VAL [input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L143] input_10 = input_10 & mask_SORT_1 [L144] input_11 = __VERIFIER_nondet_uchar() [L145] EXPR input_11 & mask_SORT_1 VAL [input_10=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L145] input_11 = input_11 & mask_SORT_1 [L146] input_12 = __VERIFIER_nondet_uchar() [L147] input_13 = __VERIFIER_nondet_uchar() [L148] input_14 = __VERIFIER_nondet_uchar() [L149] EXPR input_14 & mask_SORT_3 VAL [input_10=0, input_11=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L149] input_14 = input_14 & mask_SORT_3 [L150] input_15 = __VERIFIER_nondet_uchar() [L151] input_16 = __VERIFIER_nondet_uchar() [L152] EXPR input_16 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L152] input_16 = input_16 & mask_SORT_3 [L153] input_17 = __VERIFIER_nondet_uchar() [L154] EXPR input_17 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L154] input_17 = input_17 & mask_SORT_3 [L155] input_18 = __VERIFIER_nondet_uchar() [L156] EXPR input_18 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L156] input_18 = input_18 & mask_SORT_3 [L157] input_19 = __VERIFIER_nondet_uchar() [L158] EXPR input_19 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_22=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L158] input_19 = input_19 & mask_SORT_3 [L159] input_20 = __VERIFIER_nondet_uchar() [L160] input_120 = __VERIFIER_nondet_uchar() [L161] input_124 = __VERIFIER_nondet_uchar() [L162] input_126 = __VERIFIER_nondet_uchar() [L163] input_129 = __VERIFIER_nondet_uchar() [L164] input_131 = __VERIFIER_nondet_uchar() [L165] input_134 = __VERIFIER_nondet_uint() [L166] input_136 = __VERIFIER_nondet_uchar() [L169] SORT_1 var_25_arg_0 = state_22; [L170] SORT_24 var_25 = var_25_arg_0 >> 0; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_25=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L171] EXPR var_25 & mask_SORT_24 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L171] var_25 = var_25 & mask_SORT_24 [L172] SORT_24 var_27_arg_0 = var_25; [L173] SORT_24 var_27_arg_1 = var_26; [L174] SORT_3 var_27 = var_27_arg_0 == var_27_arg_1; [L175] SORT_1 var_54_arg_0 = state_36; [L176] SORT_24 var_54 = var_54_arg_0 >> 0; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_75=3] [L177] EXPR var_54 & mask_SORT_24 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L177] var_54 = var_54 & mask_SORT_24 [L178] SORT_24 var_105_arg_0 = var_54; [L179] SORT_24 var_105_arg_1 = var_26; [L180] SORT_3 var_105 = var_105_arg_0 == var_105_arg_1; [L181] SORT_1 var_38_arg_0 = state_36; [L182] SORT_3 var_38 = var_38_arg_0 >> 5; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L183] EXPR var_38 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_75=3] [L183] var_38 = var_38 & mask_SORT_3 [L184] SORT_3 var_76_arg_0 = var_38; [L185] SORT_3 var_76_arg_1 = var_39; [L186] SORT_3 var_76 = var_76_arg_0 == var_76_arg_1; [L187] SORT_1 var_79_arg_0 = state_36; [L188] SORT_1 var_79_arg_1 = state_77; [L189] SORT_3 var_79 = var_79_arg_0 == var_79_arg_1; [L190] SORT_3 var_80_arg_0 = var_76; [L191] SORT_3 var_80_arg_1 = var_79; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_80_arg_0=0, var_80_arg_1=1] [L192] EXPR var_80_arg_0 & var_80_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L192] SORT_3 var_80 = var_80_arg_0 & var_80_arg_1; [L193] SORT_3 var_83_arg_0 = state_81; [L194] SORT_3 var_83_arg_1 = var_39; [L195] SORT_3 var_83 = var_83_arg_0 != var_83_arg_1; [L196] SORT_3 var_84_arg_0 = var_80; [L197] SORT_3 var_84_arg_1 = var_83; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_84_arg_0=0, var_84_arg_1=1] [L198] EXPR var_84_arg_0 & var_84_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L198] SORT_3 var_84 = var_84_arg_0 & var_84_arg_1; [L199] SORT_3 var_87_arg_0 = state_85; [L200] SORT_3 var_87_arg_1 = var_39; [L201] SORT_3 var_87 = var_87_arg_0 == var_87_arg_1; [L202] SORT_3 var_88_arg_0 = var_84; [L203] SORT_3 var_88_arg_1 = var_87; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_88_arg_0=0, var_88_arg_1=0] [L204] EXPR var_88_arg_0 & var_88_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L204] SORT_3 var_88 = var_88_arg_0 & var_88_arg_1; [L205] SORT_3 var_91_arg_0 = state_89; [L206] SORT_3 var_91_arg_1 = var_39; [L207] SORT_3 var_91 = var_91_arg_0 == var_91_arg_1; [L208] SORT_3 var_92_arg_0 = var_88; [L209] SORT_3 var_92_arg_1 = var_91; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_92_arg_0=0, var_92_arg_1=0] [L210] EXPR var_92_arg_0 & var_92_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L210] SORT_3 var_92 = var_92_arg_0 & var_92_arg_1; [L211] SORT_24 var_93_arg_0 = var_54; [L212] SORT_24 var_93_arg_1 = var_26; [L213] SORT_3 var_93 = var_93_arg_0 != var_93_arg_1; [L214] SORT_3 var_94_arg_0 = var_92; [L215] SORT_3 var_94_arg_1 = var_93; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94_arg_0=0, var_94_arg_1=1] [L216] EXPR var_94_arg_0 & var_94_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L216] SORT_3 var_94 = var_94_arg_0 & var_94_arg_1; [L217] EXPR var_94 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L217] var_94 = var_94 & mask_SORT_3 [L218] SORT_3 var_59_arg_0 = var_38; [L219] SORT_3 var_59_arg_1 = var_39; [L220] SORT_3 var_59 = var_59_arg_0 == var_59_arg_1; [L221] SORT_1 var_62_arg_0 = state_36; [L222] SORT_1 var_62_arg_1 = state_60; [L223] SORT_3 var_62 = var_62_arg_0 == var_62_arg_1; [L224] SORT_3 var_63_arg_0 = var_59; [L225] SORT_3 var_63_arg_1 = var_62; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_63_arg_0=0, var_63_arg_1=1, var_75=3, var_94=0] [L226] EXPR var_63_arg_0 & var_63_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L226] SORT_3 var_63 = var_63_arg_0 & var_63_arg_1; [L227] SORT_3 var_66_arg_0 = state_64; [L228] SORT_3 var_66_arg_1 = var_39; [L229] SORT_3 var_66 = var_66_arg_0 == var_66_arg_1; [L230] SORT_3 var_67_arg_0 = var_63; [L231] SORT_3 var_67_arg_1 = var_66; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_67_arg_0=0, var_67_arg_1=0, var_75=3, var_94=0] [L232] EXPR var_67_arg_0 & var_67_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L232] SORT_3 var_67 = var_67_arg_0 & var_67_arg_1; [L233] SORT_3 var_70_arg_0 = state_68; [L234] SORT_3 var_70_arg_1 = var_39; [L235] SORT_3 var_70 = var_70_arg_0 == var_70_arg_1; [L236] SORT_3 var_71_arg_0 = var_67; [L237] SORT_3 var_71_arg_1 = var_70; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_71_arg_0=0, var_71_arg_1=0, var_75=3, var_94=0] [L238] EXPR var_71_arg_0 & var_71_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L238] SORT_3 var_71 = var_71_arg_0 & var_71_arg_1; [L239] SORT_24 var_72_arg_0 = var_54; [L240] SORT_24 var_72_arg_1 = var_26; [L241] SORT_3 var_72 = var_72_arg_0 != var_72_arg_1; [L242] SORT_3 var_73_arg_0 = var_71; [L243] SORT_3 var_73_arg_1 = var_72; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_73_arg_0=0, var_73_arg_1=1, var_75=3, var_94=0] [L244] EXPR var_73_arg_0 & var_73_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L244] SORT_3 var_73 = var_73_arg_0 & var_73_arg_1; [L245] EXPR var_73 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L245] var_73 = var_73 & mask_SORT_3 [L246] SORT_3 var_40_arg_0 = var_38; [L247] SORT_3 var_40_arg_1 = var_39; [L248] SORT_3 var_40 = var_40_arg_0 == var_40_arg_1; [L249] SORT_1 var_43_arg_0 = state_36; [L250] SORT_1 var_43_arg_1 = state_41; [L251] SORT_3 var_43 = var_43_arg_0 == var_43_arg_1; [L252] SORT_3 var_44_arg_0 = var_40; [L253] SORT_3 var_44_arg_1 = var_43; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_44_arg_0=0, var_44_arg_1=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L254] EXPR var_44_arg_0 & var_44_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L254] SORT_3 var_44 = var_44_arg_0 & var_44_arg_1; [L255] SORT_3 var_48_arg_0 = state_46; [L256] SORT_3 var_48_arg_1 = var_39; [L257] SORT_3 var_48 = var_48_arg_0 == var_48_arg_1; [L258] SORT_3 var_49_arg_0 = var_44; [L259] SORT_3 var_49_arg_1 = var_48; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_49_arg_0=0, var_49_arg_1=0, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L260] EXPR var_49_arg_0 & var_49_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L260] SORT_3 var_49 = var_49_arg_0 & var_49_arg_1; [L261] SORT_3 var_52_arg_0 = state_50; [L262] SORT_3 var_52_arg_1 = var_39; [L263] SORT_3 var_52 = var_52_arg_0 == var_52_arg_1; [L264] SORT_3 var_53_arg_0 = var_49; [L265] SORT_3 var_53_arg_1 = var_52; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_53_arg_0=0, var_53_arg_1=0, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L266] EXPR var_53_arg_0 & var_53_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L266] SORT_3 var_53 = var_53_arg_0 & var_53_arg_1; [L267] SORT_24 var_55_arg_0 = var_54; [L268] SORT_24 var_55_arg_1 = var_26; [L269] SORT_3 var_55 = var_55_arg_0 != var_55_arg_1; [L270] SORT_3 var_56_arg_0 = var_53; [L271] SORT_3 var_56_arg_1 = var_55; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_56_arg_0=0, var_56_arg_1=1, var_58=2, var_73=0, var_75=3, var_94=0] [L272] EXPR var_56_arg_0 & var_56_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_73=0, var_75=3, var_94=0] [L272] SORT_3 var_56 = var_56_arg_0 & var_56_arg_1; [L273] EXPR var_56 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_73=0, var_75=3, var_94=0] [L273] var_56 = var_56 & mask_SORT_3 [L274] SORT_3 var_57_arg_0 = var_56; [L275] SORT_33 var_57_arg_1 = var_35; [L276] SORT_33 var_57_arg_2 = var_34; [L277] SORT_33 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L278] SORT_3 var_74_arg_0 = var_73; [L279] SORT_33 var_74_arg_1 = var_58; [L280] SORT_33 var_74_arg_2 = var_57; [L281] SORT_33 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L282] SORT_3 var_95_arg_0 = var_94; [L283] SORT_33 var_95_arg_1 = var_75; [L284] SORT_33 var_95_arg_2 = var_74; [L285] SORT_33 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L286] EXPR var_95 & mask_SORT_33 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L286] var_95 = var_95 & mask_SORT_33 [L287] SORT_33 var_102_arg_0 = var_95; [L288] SORT_33 var_102_arg_1 = var_35; [L289] SORT_3 var_102 = var_102_arg_0 == var_102_arg_1; [L290] SORT_33 var_100_arg_0 = var_95; [L291] SORT_33 var_100_arg_1 = var_34; [L292] SORT_3 var_100 = var_100_arg_0 == var_100_arg_1; [L293] SORT_3 var_103_arg_0 = var_102; [L294] SORT_3 var_103_arg_1 = var_100; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_103_arg_0=0, var_103_arg_1=1, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L295] EXPR var_103_arg_0 | var_103_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L295] SORT_3 var_103 = var_103_arg_0 | var_103_arg_1; [L296] EXPR var_103 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_105=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L296] var_103 = var_103 & mask_SORT_3 [L297] SORT_3 var_101_arg_0 = var_100; [L298] SORT_6 var_101_arg_1 = var_28; [L299] SORT_6 var_101_arg_2 = state_98; [L300] SORT_6 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L301] SORT_33 var_96_arg_0 = var_95; [L302] SORT_33 var_96_arg_1 = var_58; [L303] SORT_3 var_96 = var_96_arg_0 == var_96_arg_1; [L304] SORT_3 var_97_arg_0 = var_96; [L305] SORT_6 var_97_arg_1 = state_31; [L306] SORT_6 var_97_arg_2 = state_29; [L307] SORT_6 var_97 = var_97_arg_0 ? var_97_arg_1 : var_97_arg_2; [L308] SORT_3 var_104_arg_0 = var_103; [L309] SORT_6 var_104_arg_1 = var_101; [L310] SORT_6 var_104_arg_2 = var_97; [L311] SORT_6 var_104 = var_104_arg_0 ? var_104_arg_1 : var_104_arg_2; [L312] SORT_3 var_106_arg_0 = var_105; [L313] SORT_6 var_106_arg_1 = var_28; [L314] SORT_6 var_106_arg_2 = var_104; [L315] SORT_6 var_106 = var_106_arg_0 ? var_106_arg_1 : var_106_arg_2; [L316] SORT_6 var_107_arg_0 = var_106; [L317] SORT_1 var_107 = var_107_arg_0 >> 26; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_107=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L318] EXPR var_107 & mask_SORT_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_27=0, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L318] var_107 = var_107 & mask_SORT_1 [L319] SORT_1 var_108_arg_0 = var_107; [L320] SORT_1 var_108_arg_1 = var_21; [L321] SORT_3 var_108 = var_108_arg_0 == var_108_arg_1; [L322] SORT_3 var_109_arg_0 = var_27; [L323] SORT_3 var_109_arg_1 = var_108; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_109_arg_0=0, var_109_arg_1=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L324] EXPR var_109_arg_0 & var_109_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L324] SORT_3 var_109 = var_109_arg_0 & var_109_arg_1; [L325] SORT_3 var_110_arg_0 = var_109; [L326] SORT_3 var_110 = ~var_110_arg_0; [L327] SORT_3 var_113_arg_0 = var_110; [L328] SORT_3 var_113 = ~var_113_arg_0; [L329] SORT_3 var_114_arg_0 = var_39; [L330] SORT_3 var_114_arg_1 = var_113; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_114_arg_0=1, var_114_arg_1=-256, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L331] EXPR var_114_arg_0 & var_114_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L331] SORT_3 var_114 = var_114_arg_0 & var_114_arg_1; [L332] EXPR var_114 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=0, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L332] var_114 = var_114 & mask_SORT_3 [L333] SORT_3 bad_115_arg_0 = var_114; [L334] CALL __VERIFIER_assert(!(bad_115_arg_0)) [L21] COND FALSE !(!(cond)) [L334] RET __VERIFIER_assert(!(bad_115_arg_0)) [L336] SORT_1 next_139_arg_1 = input_12; [L337] SORT_6 next_140_arg_1 = input_7; [L338] SORT_6 next_141_arg_1 = input_9; [L339] SORT_1 next_142_arg_1 = input_11; [L340] SORT_3 var_143_arg_0 = state_122; [L341] SORT_1 var_143_arg_1 = state_60; [L342] SORT_1 var_143_arg_2 = state_41; [L343] SORT_1 var_143 = var_143_arg_0 ? var_143_arg_1 : var_143_arg_2; VAL [input_10=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_50=0, state_64=0, state_81=0, state_98=0, var_143=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L344] EXPR var_143 & mask_SORT_1 VAL [input_10=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_50=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L344] var_143 = var_143 & mask_SORT_1 [L345] SORT_1 next_144_arg_1 = var_143; [L346] SORT_3 next_145_arg_1 = input_19; [L347] SORT_3 var_146_arg_0 = state_122; [L348] SORT_3 var_146_arg_1 = state_64; [L349] SORT_3 var_146_arg_2 = state_50; [L350] SORT_3 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; VAL [input_10=0, input_14=0, input_16=0, input_17=0, input_18=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_146=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L351] EXPR var_146 & mask_SORT_3 VAL [input_10=0, input_14=0, input_16=0, input_17=0, input_18=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L351] var_146 = var_146 & mask_SORT_3 [L352] SORT_3 next_147_arg_1 = var_146; [L353] SORT_1 next_148_arg_1 = input_10; [L354] SORT_3 next_149_arg_1 = input_8; [L355] SORT_3 next_150_arg_1 = input_18; [L356] SORT_1 next_151_arg_1 = input_5; [L357] SORT_1 var_152_arg_0 = state_116; [L358] SORT_3 var_152 = var_152_arg_0 >> 5; [L359] SORT_1 var_153_arg_0 = state_116; [L360] SORT_3 var_153 = var_153_arg_0 >> 2; [L361] SORT_3 var_154_arg_0 = var_152; [L362] SORT_3 var_154_arg_1 = var_153; VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_154_arg_0=0, var_154_arg_1=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L363] EXPR var_154_arg_0 & var_154_arg_1 VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_116=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L363] SORT_3 var_154 = var_154_arg_0 & var_154_arg_1; [L364] SORT_1 var_155_arg_0 = state_116; [L365] SORT_3 var_155 = var_155_arg_0 >> 0; [L366] SORT_3 var_156_arg_0 = var_155; [L367] SORT_3 var_156 = ~var_156_arg_0; [L368] SORT_3 var_157_arg_0 = var_154; [L369] SORT_3 var_157_arg_1 = var_156; VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_157_arg_0=0, var_157_arg_1=-1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L370] EXPR var_157_arg_0 & var_157_arg_1 VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_118=0, state_122=0, state_31=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L370] SORT_3 var_157 = var_157_arg_0 & var_157_arg_1; [L371] SORT_3 var_158_arg_0 = state_118; [L372] SORT_3 var_158_arg_1 = var_157; [L373] SORT_3 var_158_arg_2 = state_81; [L374] SORT_3 var_158 = var_158_arg_0 ? var_158_arg_1 : var_158_arg_2; VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_122=0, state_31=0, state_98=0, var_158=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L375] EXPR var_158 & mask_SORT_3 VAL [input_14=0, input_16=0, input_17=0, input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, next_139_arg_1=287, next_140_arg_1=0, next_141_arg_1=0, next_142_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_147_arg_1=0, next_148_arg_1=0, next_149_arg_1=0, next_150_arg_1=0, next_151_arg_1=0, state_122=0, state_31=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L375] var_158 = var_158 & mask_SORT_3 [L376] SORT_3 next_159_arg_1 = var_158; [L377] SORT_3 next_160_arg_1 = input_4; [L378] SORT_3 next_161_arg_1 = input_17; [L379] SORT_3 var_162_arg_0 = state_122; [L380] SORT_6 var_162_arg_1 = state_31; [L381] SORT_6 var_162_arg_2 = state_98; [L382] SORT_6 var_162 = var_162_arg_0 ? var_162_arg_1 : var_162_arg_2; [L383] SORT_6 next_163_arg_1 = var_162; [L384] SORT_1 next_164_arg_1 = input_2; [L385] SORT_3 next_165_arg_1 = input_14; [L386] SORT_3 next_166_arg_1 = input_16; [L388] state_22 = next_139_arg_1 [L389] state_29 = next_140_arg_1 [L390] state_31 = next_141_arg_1 [L391] state_36 = next_142_arg_1 [L392] state_41 = next_144_arg_1 [L393] state_46 = next_145_arg_1 [L394] state_50 = next_147_arg_1 [L395] state_60 = next_148_arg_1 [L396] state_64 = next_149_arg_1 [L397] state_68 = next_150_arg_1 [L398] state_77 = next_151_arg_1 [L399] state_81 = next_159_arg_1 [L400] state_85 = next_160_arg_1 [L401] state_89 = next_161_arg_1 [L402] state_98 = next_163_arg_1 [L403] state_116 = next_164_arg_1 [L404] state_118 = next_165_arg_1 [L405] state_122 = next_166_arg_1 [L133] input_2 = __VERIFIER_nondet_uchar() [L134] input_4 = __VERIFIER_nondet_uchar() [L135] EXPR input_4 & mask_SORT_3 VAL [mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L135] input_4 = input_4 & mask_SORT_3 [L136] input_5 = __VERIFIER_nondet_uchar() [L137] EXPR input_5 & mask_SORT_1 VAL [input_4=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L137] input_5 = input_5 & mask_SORT_1 [L138] input_7 = __VERIFIER_nondet_uint() [L139] input_8 = __VERIFIER_nondet_uchar() [L140] EXPR input_8 & mask_SORT_3 VAL [input_4=0, input_5=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L140] input_8 = input_8 & mask_SORT_3 [L141] input_9 = __VERIFIER_nondet_uint() [L142] input_10 = __VERIFIER_nondet_uchar() [L143] EXPR input_10 & mask_SORT_1 VAL [input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L143] input_10 = input_10 & mask_SORT_1 [L144] input_11 = __VERIFIER_nondet_uchar() [L145] EXPR input_11 & mask_SORT_1 VAL [input_10=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L145] input_11 = input_11 & mask_SORT_1 [L146] input_12 = __VERIFIER_nondet_uchar() [L147] input_13 = __VERIFIER_nondet_uchar() [L148] input_14 = __VERIFIER_nondet_uchar() [L149] EXPR input_14 & mask_SORT_3 VAL [input_10=0, input_11=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L149] input_14 = input_14 & mask_SORT_3 [L150] input_15 = __VERIFIER_nondet_uchar() [L151] input_16 = __VERIFIER_nondet_uchar() [L152] EXPR input_16 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L152] input_16 = input_16 & mask_SORT_3 [L153] input_17 = __VERIFIER_nondet_uchar() [L154] EXPR input_17 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L154] input_17 = input_17 & mask_SORT_3 [L155] input_18 = __VERIFIER_nondet_uchar() [L156] EXPR input_18 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L156] input_18 = input_18 & mask_SORT_3 [L157] input_19 = __VERIFIER_nondet_uchar() [L158] EXPR input_19 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_22=287, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L158] input_19 = input_19 & mask_SORT_3 [L159] input_20 = __VERIFIER_nondet_uchar() [L160] input_120 = __VERIFIER_nondet_uchar() [L161] input_124 = __VERIFIER_nondet_uchar() [L162] input_126 = __VERIFIER_nondet_uchar() [L163] input_129 = __VERIFIER_nondet_uchar() [L164] input_131 = __VERIFIER_nondet_uchar() [L165] input_134 = __VERIFIER_nondet_uint() [L166] input_136 = __VERIFIER_nondet_uchar() [L169] SORT_1 var_25_arg_0 = state_22; [L170] SORT_24 var_25 = var_25_arg_0 >> 0; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_25=31, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L171] EXPR var_25 & mask_SORT_24 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L171] var_25 = var_25 & mask_SORT_24 [L172] SORT_24 var_27_arg_0 = var_25; [L173] SORT_24 var_27_arg_1 = var_26; [L174] SORT_3 var_27 = var_27_arg_0 == var_27_arg_1; [L175] SORT_1 var_54_arg_0 = state_36; [L176] SORT_24 var_54 = var_54_arg_0 >> 0; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_75=3] [L177] EXPR var_54 & mask_SORT_24 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L177] var_54 = var_54 & mask_SORT_24 [L178] SORT_24 var_105_arg_0 = var_54; [L179] SORT_24 var_105_arg_1 = var_26; [L180] SORT_3 var_105 = var_105_arg_0 == var_105_arg_1; [L181] SORT_1 var_38_arg_0 = state_36; [L182] SORT_3 var_38 = var_38_arg_0 >> 5; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L183] EXPR var_38 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_77=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_75=3] [L183] var_38 = var_38 & mask_SORT_3 [L184] SORT_3 var_76_arg_0 = var_38; [L185] SORT_3 var_76_arg_1 = var_39; [L186] SORT_3 var_76 = var_76_arg_0 == var_76_arg_1; [L187] SORT_1 var_79_arg_0 = state_36; [L188] SORT_1 var_79_arg_1 = state_77; [L189] SORT_3 var_79 = var_79_arg_0 == var_79_arg_1; [L190] SORT_3 var_80_arg_0 = var_76; [L191] SORT_3 var_80_arg_1 = var_79; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_80_arg_0=0, var_80_arg_1=1] [L192] EXPR var_80_arg_0 & var_80_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L192] SORT_3 var_80 = var_80_arg_0 & var_80_arg_1; [L193] SORT_3 var_83_arg_0 = state_81; [L194] SORT_3 var_83_arg_1 = var_39; [L195] SORT_3 var_83 = var_83_arg_0 != var_83_arg_1; [L196] SORT_3 var_84_arg_0 = var_80; [L197] SORT_3 var_84_arg_1 = var_83; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_84_arg_0=0, var_84_arg_1=1] [L198] EXPR var_84_arg_0 & var_84_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_85=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L198] SORT_3 var_84 = var_84_arg_0 & var_84_arg_1; [L199] SORT_3 var_87_arg_0 = state_85; [L200] SORT_3 var_87_arg_1 = var_39; [L201] SORT_3 var_87 = var_87_arg_0 == var_87_arg_1; [L202] SORT_3 var_88_arg_0 = var_84; [L203] SORT_3 var_88_arg_1 = var_87; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_88_arg_0=0, var_88_arg_1=0] [L204] EXPR var_88_arg_0 & var_88_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_89=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L204] SORT_3 var_88 = var_88_arg_0 & var_88_arg_1; [L205] SORT_3 var_91_arg_0 = state_89; [L206] SORT_3 var_91_arg_1 = var_39; [L207] SORT_3 var_91 = var_91_arg_0 == var_91_arg_1; [L208] SORT_3 var_92_arg_0 = var_88; [L209] SORT_3 var_92_arg_1 = var_91; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_92_arg_0=0, var_92_arg_1=0] [L210] EXPR var_92_arg_0 & var_92_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L210] SORT_3 var_92 = var_92_arg_0 & var_92_arg_1; [L211] SORT_24 var_93_arg_0 = var_54; [L212] SORT_24 var_93_arg_1 = var_26; [L213] SORT_3 var_93 = var_93_arg_0 != var_93_arg_1; [L214] SORT_3 var_94_arg_0 = var_92; [L215] SORT_3 var_94_arg_1 = var_93; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94_arg_0=0, var_94_arg_1=1] [L216] EXPR var_94_arg_0 & var_94_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L216] SORT_3 var_94 = var_94_arg_0 & var_94_arg_1; [L217] EXPR var_94 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3] [L217] var_94 = var_94 & mask_SORT_3 [L218] SORT_3 var_59_arg_0 = var_38; [L219] SORT_3 var_59_arg_1 = var_39; [L220] SORT_3 var_59 = var_59_arg_0 == var_59_arg_1; [L221] SORT_1 var_62_arg_0 = state_36; [L222] SORT_1 var_62_arg_1 = state_60; [L223] SORT_3 var_62 = var_62_arg_0 == var_62_arg_1; [L224] SORT_3 var_63_arg_0 = var_59; [L225] SORT_3 var_63_arg_1 = var_62; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_63_arg_0=0, var_63_arg_1=1, var_75=3, var_94=0] [L226] EXPR var_63_arg_0 & var_63_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L226] SORT_3 var_63 = var_63_arg_0 & var_63_arg_1; [L227] SORT_3 var_66_arg_0 = state_64; [L228] SORT_3 var_66_arg_1 = var_39; [L229] SORT_3 var_66 = var_66_arg_0 == var_66_arg_1; [L230] SORT_3 var_67_arg_0 = var_63; [L231] SORT_3 var_67_arg_1 = var_66; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_67_arg_0=0, var_67_arg_1=0, var_75=3, var_94=0] [L232] EXPR var_67_arg_0 & var_67_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_68=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L232] SORT_3 var_67 = var_67_arg_0 & var_67_arg_1; [L233] SORT_3 var_70_arg_0 = state_68; [L234] SORT_3 var_70_arg_1 = var_39; [L235] SORT_3 var_70 = var_70_arg_0 == var_70_arg_1; [L236] SORT_3 var_71_arg_0 = var_67; [L237] SORT_3 var_71_arg_1 = var_70; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_71_arg_0=0, var_71_arg_1=0, var_75=3, var_94=0] [L238] EXPR var_71_arg_0 & var_71_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L238] SORT_3 var_71 = var_71_arg_0 & var_71_arg_1; [L239] SORT_24 var_72_arg_0 = var_54; [L240] SORT_24 var_72_arg_1 = var_26; [L241] SORT_3 var_72 = var_72_arg_0 != var_72_arg_1; [L242] SORT_3 var_73_arg_0 = var_71; [L243] SORT_3 var_73_arg_1 = var_72; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_73_arg_0=0, var_73_arg_1=1, var_75=3, var_94=0] [L244] EXPR var_73_arg_0 & var_73_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L244] SORT_3 var_73 = var_73_arg_0 & var_73_arg_1; [L245] EXPR var_73 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_36=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_38=0, var_39=1, var_54=0, var_58=2, var_75=3, var_94=0] [L245] var_73 = var_73 & mask_SORT_3 [L246] SORT_3 var_40_arg_0 = var_38; [L247] SORT_3 var_40_arg_1 = var_39; [L248] SORT_3 var_40 = var_40_arg_0 == var_40_arg_1; [L249] SORT_1 var_43_arg_0 = state_36; [L250] SORT_1 var_43_arg_1 = state_41; [L251] SORT_3 var_43 = var_43_arg_0 == var_43_arg_1; [L252] SORT_3 var_44_arg_0 = var_40; [L253] SORT_3 var_44_arg_1 = var_43; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_44_arg_0=0, var_44_arg_1=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L254] EXPR var_44_arg_0 & var_44_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_46=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L254] SORT_3 var_44 = var_44_arg_0 & var_44_arg_1; [L255] SORT_3 var_48_arg_0 = state_46; [L256] SORT_3 var_48_arg_1 = var_39; [L257] SORT_3 var_48 = var_48_arg_0 == var_48_arg_1; [L258] SORT_3 var_49_arg_0 = var_44; [L259] SORT_3 var_49_arg_1 = var_48; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_49_arg_0=0, var_49_arg_1=0, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L260] EXPR var_49_arg_0 & var_49_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L260] SORT_3 var_49 = var_49_arg_0 & var_49_arg_1; [L261] SORT_3 var_52_arg_0 = state_50; [L262] SORT_3 var_52_arg_1 = var_39; [L263] SORT_3 var_52 = var_52_arg_0 == var_52_arg_1; [L264] SORT_3 var_53_arg_0 = var_49; [L265] SORT_3 var_53_arg_1 = var_52; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_53_arg_0=0, var_53_arg_1=0, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L266] EXPR var_53_arg_0 & var_53_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_54=0, var_58=2, var_73=0, var_75=3, var_94=0] [L266] SORT_3 var_53 = var_53_arg_0 & var_53_arg_1; [L267] SORT_24 var_55_arg_0 = var_54; [L268] SORT_24 var_55_arg_1 = var_26; [L269] SORT_3 var_55 = var_55_arg_0 != var_55_arg_1; [L270] SORT_3 var_56_arg_0 = var_53; [L271] SORT_3 var_56_arg_1 = var_55; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_56_arg_0=0, var_56_arg_1=1, var_58=2, var_73=0, var_75=3, var_94=0] [L272] EXPR var_56_arg_0 & var_56_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_73=0, var_75=3, var_94=0] [L272] SORT_3 var_56 = var_56_arg_0 & var_56_arg_1; [L273] EXPR var_56 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_73=0, var_75=3, var_94=0] [L273] var_56 = var_56 & mask_SORT_3 [L274] SORT_3 var_57_arg_0 = var_56; [L275] SORT_33 var_57_arg_1 = var_35; [L276] SORT_33 var_57_arg_2 = var_34; [L277] SORT_33 var_57 = var_57_arg_0 ? var_57_arg_1 : var_57_arg_2; [L278] SORT_3 var_74_arg_0 = var_73; [L279] SORT_33 var_74_arg_1 = var_58; [L280] SORT_33 var_74_arg_2 = var_57; [L281] SORT_33 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L282] SORT_3 var_95_arg_0 = var_94; [L283] SORT_33 var_95_arg_1 = var_75; [L284] SORT_33 var_95_arg_2 = var_74; [L285] SORT_33 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L286] EXPR var_95 & mask_SORT_33 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L286] var_95 = var_95 & mask_SORT_33 [L287] SORT_33 var_102_arg_0 = var_95; [L288] SORT_33 var_102_arg_1 = var_35; [L289] SORT_3 var_102 = var_102_arg_0 == var_102_arg_1; [L290] SORT_33 var_100_arg_0 = var_95; [L291] SORT_33 var_100_arg_1 = var_34; [L292] SORT_3 var_100 = var_100_arg_0 == var_100_arg_1; [L293] SORT_3 var_103_arg_0 = var_102; [L294] SORT_3 var_103_arg_1 = var_100; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_103_arg_0=0, var_103_arg_1=1, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L295] EXPR var_103_arg_0 | var_103_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L295] SORT_3 var_103 = var_103_arg_0 | var_103_arg_1; [L296] EXPR var_103 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_29=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_100=1, var_105=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3, var_95=0] [L296] var_103 = var_103 & mask_SORT_3 [L297] SORT_3 var_101_arg_0 = var_100; [L298] SORT_6 var_101_arg_1 = var_28; [L299] SORT_6 var_101_arg_2 = state_98; [L300] SORT_6 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L301] SORT_33 var_96_arg_0 = var_95; [L302] SORT_33 var_96_arg_1 = var_58; [L303] SORT_3 var_96 = var_96_arg_0 == var_96_arg_1; [L304] SORT_3 var_97_arg_0 = var_96; [L305] SORT_6 var_97_arg_1 = state_31; [L306] SORT_6 var_97_arg_2 = state_29; [L307] SORT_6 var_97 = var_97_arg_0 ? var_97_arg_1 : var_97_arg_2; [L308] SORT_3 var_104_arg_0 = var_103; [L309] SORT_6 var_104_arg_1 = var_101; [L310] SORT_6 var_104_arg_2 = var_97; [L311] SORT_6 var_104 = var_104_arg_0 ? var_104_arg_1 : var_104_arg_2; [L312] SORT_3 var_106_arg_0 = var_105; [L313] SORT_6 var_106_arg_1 = var_28; [L314] SORT_6 var_106_arg_2 = var_104; [L315] SORT_6 var_106 = var_106_arg_0 ? var_106_arg_1 : var_106_arg_2; [L316] SORT_6 var_107_arg_0 = var_106; [L317] SORT_1 var_107 = var_107_arg_0 >> 26; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_107=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L318] EXPR var_107 & mask_SORT_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_27=1, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L318] var_107 = var_107 & mask_SORT_1 [L319] SORT_1 var_108_arg_0 = var_107; [L320] SORT_1 var_108_arg_1 = var_21; [L321] SORT_3 var_108 = var_108_arg_0 == var_108_arg_1; [L322] SORT_3 var_109_arg_0 = var_27; [L323] SORT_3 var_109_arg_1 = var_108; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_109_arg_0=1, var_109_arg_1=1, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L324] EXPR var_109_arg_0 & var_109_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L324] SORT_3 var_109 = var_109_arg_0 & var_109_arg_1; [L325] SORT_3 var_110_arg_0 = var_109; [L326] SORT_3 var_110 = ~var_110_arg_0; [L327] SORT_3 var_113_arg_0 = var_110; [L328] SORT_3 var_113 = ~var_113_arg_0; [L329] SORT_3 var_114_arg_0 = var_39; [L330] SORT_3 var_114_arg_1 = var_113; VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_114_arg_0=1, var_114_arg_1=-255, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L331] EXPR var_114_arg_0 & var_114_arg_1 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L331] SORT_3 var_114 = var_114_arg_0 & var_114_arg_1; [L332] EXPR var_114 & mask_SORT_3 VAL [input_10=0, input_11=0, input_14=0, input_16=0, input_17=0, input_18=0, input_19=0, input_4=0, input_5=0, input_8=0, mask_SORT_1=63, mask_SORT_24=31, mask_SORT_33=3, mask_SORT_3=1, state_116=2147483649, state_118=0, state_122=0, state_31=0, state_41=0, state_50=0, state_60=0, state_64=0, state_81=0, state_98=0, var_21=0, var_26=31, var_28=0, var_34=0, var_35=1, var_39=1, var_58=2, var_75=3] [L332] var_114 = var_114 & mask_SORT_3 [L333] SORT_3 bad_115_arg_0 = var_114; [L334] CALL __VERIFIER_assert(!(bad_115_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 246 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 20.3s, OverallIterations: 7, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 2.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1437 SdHoareTripleChecker+Valid, 1.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1437 mSDsluCounter, 8064 SdHoareTripleChecker+Invalid, 1.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6063 mSDsCounter, 9 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1679 IncrementalHoareTripleChecker+Invalid, 1688 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 9 mSolverCounterUnsat, 2001 mSDtfsCounter, 1679 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 447 GetRequests, 402 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 150 ImplicationChecksByTransitivity, 0.8s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=393occurred in iteration=6, InterpolantAutomatonStates: 34, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 6 MinimizatonAttempts, 2 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 4.1s SatisfiabilityAnalysisTime, 11.2s InterpolantComputationTime, 1183 NumberOfCodeBlocks, 1183 NumberOfCodeBlocksAsserted, 8 NumberOfCheckSat, 1173 ConstructedInterpolants, 0 QuantifiedInterpolants, 7555 SizeOfPredicates, 4 NumberOfNonLiveVariables, 1290 ConjunctsInSsa, 40 ConjunctsInUnsatCore, 8 InterpolantComputations, 5 PerfectInterpolantSequences, 148/222 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-24 00:10:21,779 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64876fde-f8d0-4543-9290-c2f2a3c4c499/bin/uautomizer-verify-LYvppIcaGC/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE