./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash d628f3524885345eb9e2318f2d0dbb026e233c3bcc51319b2ad8fc1a71d35580 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-27 23:36:15,103 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-27 23:36:15,193 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-11-27 23:36:15,198 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-27 23:36:15,198 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-27 23:36:15,221 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-27 23:36:15,222 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-27 23:36:15,222 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-27 23:36:15,222 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-27 23:36:15,222 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-27 23:36:15,223 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Use SBE=true [2024-11-27 23:36:15,223 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-27 23:36:15,223 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-27 23:36:15,224 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-27 23:36:15,224 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-27 23:36:15,225 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-27 23:36:15,225 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-27 23:36:15,225 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-27 23:36:15,225 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-27 23:36:15,225 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-27 23:36:15,225 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL_NO_AM [2024-11-27 23:36:15,225 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-27 23:36:15,225 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d628f3524885345eb9e2318f2d0dbb026e233c3bcc51319b2ad8fc1a71d35580 [2024-11-27 23:36:15,529 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-27 23:36:15,537 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-27 23:36:15,540 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-27 23:36:15,542 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-27 23:36:15,542 INFO L274 PluginConnector]: CDTParser initialized [2024-11-27 23:36:15,544 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i [2024-11-27 23:36:18,478 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/data/92638885c/9e563505f545491c9b0cf65e138b5b91/FLAGd5f89fa8c [2024-11-27 23:36:18,857 INFO L384 CDTParser]: Found 1 translation units. [2024-11-27 23:36:18,858 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i [2024-11-27 23:36:18,870 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/data/92638885c/9e563505f545491c9b0cf65e138b5b91/FLAGd5f89fa8c [2024-11-27 23:36:19,066 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/data/92638885c/9e563505f545491c9b0cf65e138b5b91 [2024-11-27 23:36:19,068 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-27 23:36:19,070 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-27 23:36:19,071 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-27 23:36:19,072 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-27 23:36:19,076 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-27 23:36:19,077 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,078 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35e1e3ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19, skipping insertion in model container [2024-11-27 23:36:19,078 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,106 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-27 23:36:19,384 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-27 23:36:19,395 INFO L200 MainTranslator]: Completed pre-run [2024-11-27 23:36:19,431 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-27 23:36:19,456 INFO L204 MainTranslator]: Completed translation [2024-11-27 23:36:19,457 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19 WrapperNode [2024-11-27 23:36:19,457 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-27 23:36:19,458 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-27 23:36:19,458 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-27 23:36:19,458 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-27 23:36:19,465 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,475 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,490 INFO L138 Inliner]: procedures = 109, calls = 25, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2024-11-27 23:36:19,491 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-27 23:36:19,491 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-27 23:36:19,492 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-27 23:36:19,492 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-27 23:36:19,500 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,500 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,502 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,513 INFO L175 MemorySlicer]: Split 14 memory accesses to 3 slices as follows [4, 4, 6]. 43 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0, 0]. The 7 writes are split as follows [2, 2, 3]. [2024-11-27 23:36:19,513 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,514 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,518 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,518 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,521 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,522 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,523 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,524 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-27 23:36:19,525 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-27 23:36:19,525 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-27 23:36:19,525 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-27 23:36:19,526 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (1/1) ... [2024-11-27 23:36:19,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:19,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:19,559 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:19,563 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-27 23:36:19,584 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-27 23:36:19,584 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-27 23:36:19,687 INFO L234 CfgBuilder]: Building ICFG [2024-11-27 23:36:19,689 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-27 23:36:19,843 INFO L? ?]: Removed 9 outVars from TransFormulas that were not future-live. [2024-11-27 23:36:19,843 INFO L283 CfgBuilder]: Performing block encoding [2024-11-27 23:36:19,853 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-27 23:36:19,854 INFO L312 CfgBuilder]: Removed 2 assume(true) statements. [2024-11-27 23:36:19,854 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.11 11:36:19 BoogieIcfgContainer [2024-11-27 23:36:19,854 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-27 23:36:19,855 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-27 23:36:19,856 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-27 23:36:19,862 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-27 23:36:19,863 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-27 23:36:19,864 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 27.11 11:36:19" (1/3) ... [2024-11-27 23:36:19,865 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39b43dd6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.11 11:36:19, skipping insertion in model container [2024-11-27 23:36:19,865 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-27 23:36:19,865 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.11 11:36:19" (2/3) ... [2024-11-27 23:36:19,867 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@39b43dd6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 27.11 11:36:19, skipping insertion in model container [2024-11-27 23:36:19,867 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-27 23:36:19,867 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.11 11:36:19" (3/3) ... [2024-11-27 23:36:19,869 INFO L363 chiAutomizerObserver]: Analyzing ICFG java_Sequence-alloca.i [2024-11-27 23:36:19,916 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-27 23:36:19,916 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-27 23:36:19,916 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-27 23:36:19,916 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-27 23:36:19,917 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-27 23:36:19,917 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-27 23:36:19,917 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-27 23:36:19,917 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-27 23:36:19,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:19,936 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-27 23:36:19,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:19,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:19,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-27 23:36:19,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:19,942 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-27 23:36:19,942 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:19,943 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-11-27 23:36:19,943 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:19,943 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:19,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-11-27 23:36:19,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:19,950 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" [2024-11-27 23:36:19,951 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" [2024-11-27 23:36:19,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:19,956 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-11-27 23:36:19,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:19,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61307325] [2024-11-27 23:36:19,964 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:19,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:20,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,074 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:20,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:20,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:20,133 INFO L85 PathProgramCache]: Analyzing trace with hash 35849, now seen corresponding path program 1 times [2024-11-27 23:36:20,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:20,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184552900] [2024-11-27 23:36:20,133 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:20,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,151 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:20,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,162 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:20,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:20,163 INFO L85 PathProgramCache]: Analyzing trace with hash 28694791, now seen corresponding path program 1 times [2024-11-27 23:36:20,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:20,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039014508] [2024-11-27 23:36:20,163 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:20,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:20,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,230 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:20,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:20,261 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:21,032 INFO L204 LassoAnalysis]: Preferences: [2024-11-27 23:36:21,034 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-27 23:36:21,034 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-27 23:36:21,035 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-27 23:36:21,035 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-27 23:36:21,035 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:21,035 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-27 23:36:21,035 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-27 23:36:21,036 INFO L132 ssoRankerPreferences]: Filename of dumped script: java_Sequence-alloca.i_Iteration1_Lasso [2024-11-27 23:36:21,036 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-27 23:36:21,036 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-27 23:36:21,056 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,068 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,070 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,073 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,078 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,082 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,086 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,089 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,093 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,102 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-27 23:36:21,960 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-27 23:36:21,965 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-27 23:36:21,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:21,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:21,970 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:21,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-11-27 23:36:21,973 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:21,988 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:21,988 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:21,989 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:21,989 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:21,989 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:21,996 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:21,996 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:21,999 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,008 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-11-27 23:36:22,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,010 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-11-27 23:36:22,016 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,030 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,030 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,030 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,030 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,030 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,031 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,031 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,033 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,042 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,042 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,042 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,044 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-11-27 23:36:22,048 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,063 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,063 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,063 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,063 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,063 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,064 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,064 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,067 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,075 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,076 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,078 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,081 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-11-27 23:36:22,082 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,097 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,097 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,097 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,097 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,098 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,098 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,098 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,103 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,112 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-11-27 23:36:22,113 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,115 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-11-27 23:36:22,121 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,135 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,136 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,136 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,136 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,141 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,141 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,145 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,154 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2024-11-27 23:36:22,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,154 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,156 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,161 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-11-27 23:36:22,161 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,175 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,175 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,175 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,175 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,179 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,179 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,186 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,195 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-11-27 23:36:22,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,195 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,199 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-11-27 23:36:22,202 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,217 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,217 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,217 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,217 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,220 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,220 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,225 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,234 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-11-27 23:36:22,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,237 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-11-27 23:36:22,241 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,255 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,255 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,256 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,256 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,256 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,256 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,257 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,261 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,269 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,270 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,272 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,276 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,276 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-11-27 23:36:22,290 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,291 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,291 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,291 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,291 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,292 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,293 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,295 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,303 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-11-27 23:36:22,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,305 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,307 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-11-27 23:36:22,311 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,325 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,325 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,326 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,326 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,326 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,326 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,326 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,331 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,340 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,340 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,340 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,342 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-11-27 23:36:22,346 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,360 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,361 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,361 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,361 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,365 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,365 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,371 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,380 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,381 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,381 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,383 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,386 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-11-27 23:36:22,387 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,401 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,402 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-27 23:36:22,402 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,402 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,402 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,402 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-27 23:36:22,403 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-27 23:36:22,405 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,414 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,415 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,417 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-11-27 23:36:22,421 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,435 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,436 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,436 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,436 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,448 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,448 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,461 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,470 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,471 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,471 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,473 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-11-27 23:36:22,477 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,492 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,493 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,493 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,493 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,499 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,500 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,511 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,520 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-11-27 23:36:22,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,522 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,527 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-11-27 23:36:22,542 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,542 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,542 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,543 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,546 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,546 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,551 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,560 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,561 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,562 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,565 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-11-27 23:36:22,566 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,581 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,581 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,581 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,581 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,585 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,585 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,589 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,598 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-11-27 23:36:22,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,599 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,601 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-11-27 23:36:22,606 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,620 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,620 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,620 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,620 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,623 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,623 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,631 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,640 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,642 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,645 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2024-11-27 23:36:22,647 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,660 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,660 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,660 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,660 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,669 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,669 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,677 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,686 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2024-11-27 23:36:22,687 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,687 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,689 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2024-11-27 23:36:22,693 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,708 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,708 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,708 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,708 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,712 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,712 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,719 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-27 23:36:22,729 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2024-11-27 23:36:22,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,734 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2024-11-27 23:36:22,739 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-27 23:36:22,753 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-27 23:36:22,753 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-27 23:36:22,754 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-27 23:36:22,754 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-27 23:36:22,759 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-11-27 23:36:22,759 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-11-27 23:36:22,768 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-27 23:36:22,793 INFO L443 ModelExtractionUtils]: Simplification made 6 calls to the SMT solver. [2024-11-27 23:36:22,796 INFO L444 ModelExtractionUtils]: 3 out of 10 variables were initially zero. Simplification set additionally 4 variables to zero. [2024-11-27 23:36:22,798 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-27 23:36:22,798 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:22,800 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-27 23:36:22,804 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-27 23:36:22,807 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2024-11-27 23:36:22,820 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-11-27 23:36:22,820 INFO L474 LassoAnalysis]: Proved termination. [2024-11-27 23:36:22,821 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select (select #memory_int#0 ULTIMATE.start_main_~i~0#1.base) 0)_1) = -2*v_rep(select (select #memory_int#0 ULTIMATE.start_main_~i~0#1.base) 0)_1 + 199 Supporting invariants [] [2024-11-27 23:36:22,830 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:22,909 INFO L156 tatePredicateManager]: 15 out of 16 supporting invariants were superfluous and have been removed [2024-11-27 23:36:22,918 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #memory_int#0 [2024-11-27 23:36:22,919 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#memory_int#0,GLOBAL] [2024-11-27 23:36:22,919 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array ArrayAccessExpression[IdentifierExpression[#memory_int#0,GLOBAL],[IdentifierExpression[~i~0!base,]]] [2024-11-27 23:36:22,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:22,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:22,998 INFO L256 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-27 23:36:23,002 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:23,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:23,030 INFO L256 TraceCheckSpWp]: Trace formula consists of 29 conjuncts, 9 conjuncts are in the unsatisfiable core [2024-11-27 23:36:23,031 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:23,109 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Forceful destruction successful, exit code 0 [2024-11-27 23:36:23,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-27 23:36:23,170 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-11-27 23:36:23,172 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:23,289 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 30 states and 37 transitions. Complement of second has 10 states. [2024-11-27 23:36:23,291 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 6 states 1 stem states 3 non-accepting loop states 1 accepting loop states [2024-11-27 23:36:23,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:23,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 23 transitions. [2024-11-27 23:36:23,302 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 2 letters. Loop has 3 letters. [2024-11-27 23:36:23,303 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-27 23:36:23,303 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 5 letters. Loop has 3 letters. [2024-11-27 23:36:23,303 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-27 23:36:23,306 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 2 letters. Loop has 6 letters. [2024-11-27 23:36:23,306 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-27 23:36:23,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2024-11-27 23:36:23,308 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:23,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 11 states and 13 transitions. [2024-11-27 23:36:23,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-11-27 23:36:23,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:23,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 13 transitions. [2024-11-27 23:36:23,318 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:23,318 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-11-27 23:36:23,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 13 transitions. [2024-11-27 23:36:23,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2024-11-27 23:36:23,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.1818181818181819) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:23,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 13 transitions. [2024-11-27 23:36:23,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-11-27 23:36:23,347 INFO L425 stractBuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-11-27 23:36:23,348 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-27 23:36:23,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 13 transitions. [2024-11-27 23:36:23,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:23,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:23,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:23,350 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2024-11-27 23:36:23,351 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:23,351 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:23,351 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:23,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:23,351 INFO L85 PathProgramCache]: Analyzing trace with hash 28694857, now seen corresponding path program 1 times [2024-11-27 23:36:23,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:23,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290401125] [2024-11-27 23:36:23,352 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:23,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:23,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:23,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:23,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290401125] [2024-11-27 23:36:23,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290401125] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:23,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [645984012] [2024-11-27 23:36:23,621 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:23,622 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:23,622 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:23,627 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:23,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-27 23:36:23,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:23,706 INFO L256 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-27 23:36:23,707 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:23,730 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:23,746 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:36:23,772 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [645984012] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:36:23,772 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:36:23,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2024-11-27 23:36:23,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [863969781] [2024-11-27 23:36:23,774 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:36:23,775 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:36:23,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:23,776 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 1 times [2024-11-27 23:36:23,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:23,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1878046713] [2024-11-27 23:36:23,776 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:23,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:23,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:23,787 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:23,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:23,794 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:23,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:36:23,903 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-27 23:36:23,904 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-27 23:36:23,905 INFO L87 Difference]: Start difference. First operand 11 states and 13 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:23,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:36:23,959 INFO L93 Difference]: Finished difference Result 18 states and 19 transitions. [2024-11-27 23:36:23,959 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 19 transitions. [2024-11-27 23:36:23,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:23,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 16 states and 17 transitions. [2024-11-27 23:36:23,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:36:23,961 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:23,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 17 transitions. [2024-11-27 23:36:23,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:23,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16 states and 17 transitions. [2024-11-27 23:36:23,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 17 transitions. [2024-11-27 23:36:23,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 14. [2024-11-27 23:36:23,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 13 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:23,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2024-11-27 23:36:23,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 15 transitions. [2024-11-27 23:36:23,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-27 23:36:23,964 INFO L425 stractBuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2024-11-27 23:36:23,964 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-27 23:36:23,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 15 transitions. [2024-11-27 23:36:23,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:23,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:23,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:23,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 1, 1, 1, 1] [2024-11-27 23:36:23,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:23,966 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:23,966 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:23,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:23,966 INFO L85 PathProgramCache]: Analyzing trace with hash -885219383, now seen corresponding path program 1 times [2024-11-27 23:36:23,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:23,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214578210] [2024-11-27 23:36:23,967 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:23,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:23,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:24,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:24,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1214578210] [2024-11-27 23:36:24,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1214578210] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:24,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [94141583] [2024-11-27 23:36:24,463 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:24,463 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:24,463 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:24,465 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:24,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-11-27 23:36:24,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:24,560 INFO L256 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-11-27 23:36:24,562 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:24,572 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:24,597 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-11-27 23:36:24,622 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:24,633 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-11-27 23:36:24,638 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:36:24,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [94141583] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:36:24,718 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:36:24,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 11 [2024-11-27 23:36:24,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908612216] [2024-11-27 23:36:24,718 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:36:24,719 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:36:24,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:24,719 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 2 times [2024-11-27 23:36:24,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:24,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957588298] [2024-11-27 23:36:24,719 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:24,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:24,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:24,732 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:24,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:24,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:24,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:36:24,853 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-11-27 23:36:24,853 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2024-11-27 23:36:24,853 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. cyclomatic complexity: 3 Second operand has 11 states, 11 states have (on average 2.0) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:24,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:36:24,968 INFO L93 Difference]: Finished difference Result 32 states and 33 transitions. [2024-11-27 23:36:24,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 33 transitions. [2024-11-27 23:36:24,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:24,970 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 28 states and 29 transitions. [2024-11-27 23:36:24,970 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:36:24,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:24,971 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 29 transitions. [2024-11-27 23:36:24,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:24,971 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 29 transitions. [2024-11-27 23:36:24,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 29 transitions. [2024-11-27 23:36:24,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2024-11-27 23:36:24,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.0384615384615385) internal successors, (27), 25 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:24,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2024-11-27 23:36:24,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 27 transitions. [2024-11-27 23:36:24,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-11-27 23:36:24,979 INFO L425 stractBuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2024-11-27 23:36:24,979 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-27 23:36:24,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 27 transitions. [2024-11-27 23:36:24,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:24,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:24,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:24,980 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 1, 1, 1, 1] [2024-11-27 23:36:24,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:24,981 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:24,981 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:24,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:24,981 INFO L85 PathProgramCache]: Analyzing trace with hash -1505391415, now seen corresponding path program 2 times [2024-11-27 23:36:24,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:24,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1902949818] [2024-11-27 23:36:24,982 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:24,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:25,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:26,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:26,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1902949818] [2024-11-27 23:36:26,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1902949818] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:26,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [955910430] [2024-11-27 23:36:26,067 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:26,067 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:26,068 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:26,078 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:26,080 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-11-27 23:36:26,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:26,183 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-27 23:36:26,189 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:26,195 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:26,220 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-11-27 23:36:26,238 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:26,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:26,275 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:26,290 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:26,310 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:26,319 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-11-27 23:36:26,323 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:36:26,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [955910430] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:36:26,522 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:36:26,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 19 [2024-11-27 23:36:26,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [381199303] [2024-11-27 23:36:26,523 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:36:26,523 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:36:26,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:26,525 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 3 times [2024-11-27 23:36:26,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:26,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2128804599] [2024-11-27 23:36:26,525 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:26,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:26,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:26,532 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:26,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:26,539 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:26,632 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:36:26,633 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2024-11-27 23:36:26,634 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2024-11-27 23:36:26,634 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. cyclomatic complexity: 3 Second operand has 19 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 19 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:26,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:36:26,934 INFO L93 Difference]: Finished difference Result 60 states and 61 transitions. [2024-11-27 23:36:26,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 61 transitions. [2024-11-27 23:36:26,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:26,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 52 states and 53 transitions. [2024-11-27 23:36:26,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:36:26,937 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:26,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 53 transitions. [2024-11-27 23:36:26,937 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:26,937 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 53 transitions. [2024-11-27 23:36:26,938 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 53 transitions. [2024-11-27 23:36:26,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 50. [2024-11-27 23:36:26,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.02) internal successors, (51), 49 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:26,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2024-11-27 23:36:26,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 51 transitions. [2024-11-27 23:36:26,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2024-11-27 23:36:26,947 INFO L425 stractBuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2024-11-27 23:36:26,947 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-27 23:36:26,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 51 transitions. [2024-11-27 23:36:26,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:26,948 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:26,948 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:26,949 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 14, 14, 1, 1, 1, 1] [2024-11-27 23:36:26,949 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:26,949 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:26,950 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:26,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:26,954 INFO L85 PathProgramCache]: Analyzing trace with hash 2091181769, now seen corresponding path program 3 times [2024-11-27 23:36:26,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:26,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364895742] [2024-11-27 23:36:26,954 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:26,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:27,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:28,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:28,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364895742] [2024-11-27 23:36:28,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364895742] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:28,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [464178552] [2024-11-27 23:36:28,975 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:28,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:28,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:28,977 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:28,981 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-27 23:36:29,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:29,127 INFO L256 TraceCheckSpWp]: Trace formula consists of 430 conjuncts, 46 conjuncts are in the unsatisfiable core [2024-11-27 23:36:29,132 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:29,138 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:29,156 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-11-27 23:36:29,169 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,181 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,194 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,207 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,219 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,231 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,244 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,276 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,292 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,304 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,316 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,329 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,342 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:29,349 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-11-27 23:36:29,353 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:36:30,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [464178552] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:36:30,029 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:36:30,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18, 18] total 36 [2024-11-27 23:36:30,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [310876021] [2024-11-27 23:36:30,029 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:36:30,030 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:36:30,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:30,031 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 4 times [2024-11-27 23:36:30,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:30,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112244804] [2024-11-27 23:36:30,032 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:30,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:30,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:30,043 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:30,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:30,052 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:30,145 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:36:30,146 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2024-11-27 23:36:30,147 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=560, Invalid=700, Unknown=0, NotChecked=0, Total=1260 [2024-11-27 23:36:30,148 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. cyclomatic complexity: 3 Second operand has 36 states, 36 states have (on average 2.6666666666666665) internal successors, (96), 36 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:30,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:36:30,949 INFO L93 Difference]: Finished difference Result 116 states and 117 transitions. [2024-11-27 23:36:30,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116 states and 117 transitions. [2024-11-27 23:36:30,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:30,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116 states to 100 states and 101 transitions. [2024-11-27 23:36:30,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:36:30,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:30,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 101 transitions. [2024-11-27 23:36:30,955 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:30,955 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 101 transitions. [2024-11-27 23:36:30,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 101 transitions. [2024-11-27 23:36:30,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 98. [2024-11-27 23:36:30,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.010204081632653) internal successors, (99), 97 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:30,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 99 transitions. [2024-11-27 23:36:30,961 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 99 transitions. [2024-11-27 23:36:30,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2024-11-27 23:36:30,962 INFO L425 stractBuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2024-11-27 23:36:30,962 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-27 23:36:30,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 99 transitions. [2024-11-27 23:36:30,964 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:30,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:30,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:30,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 30, 30, 1, 1, 1, 1] [2024-11-27 23:36:30,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:30,967 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:30,968 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:30,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:30,968 INFO L85 PathProgramCache]: Analyzing trace with hash 1033476809, now seen corresponding path program 4 times [2024-11-27 23:36:30,968 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:30,968 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [771602465] [2024-11-27 23:36:30,968 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:30,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:31,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:36,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:36,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [771602465] [2024-11-27 23:36:36,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [771602465] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:36,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [302375513] [2024-11-27 23:36:36,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:36,846 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:36,846 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:36,848 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:36,850 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-27 23:36:37,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:37,111 INFO L256 TraceCheckSpWp]: Trace formula consists of 830 conjuncts, 94 conjuncts are in the unsatisfiable core [2024-11-27 23:36:37,127 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:37,130 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:37,142 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-11-27 23:36:37,155 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,174 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,185 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,197 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,209 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,221 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,232 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,244 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,255 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,268 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,280 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,294 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,319 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,332 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,348 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,362 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,389 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,404 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,418 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,436 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,453 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,469 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,484 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,500 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,512 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,527 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,540 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:37,549 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-11-27 23:36:37,552 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:36:39,477 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [302375513] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:36:39,477 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:36:39,478 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 34, 34] total 68 [2024-11-27 23:36:39,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [627638943] [2024-11-27 23:36:39,479 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:36:39,479 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:36:39,480 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:39,480 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 5 times [2024-11-27 23:36:39,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:39,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415443777] [2024-11-27 23:36:39,480 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:39,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:39,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:39,486 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:36:39,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:36:39,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:36:39,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:36:39,568 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2024-11-27 23:36:39,570 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=2144, Invalid=2412, Unknown=0, NotChecked=0, Total=4556 [2024-11-27 23:36:39,571 INFO L87 Difference]: Start difference. First operand 98 states and 99 transitions. cyclomatic complexity: 3 Second operand has 68 states, 68 states have (on average 2.823529411764706) internal successors, (192), 68 states have internal predecessors, (192), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:42,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:36:42,030 INFO L93 Difference]: Finished difference Result 228 states and 229 transitions. [2024-11-27 23:36:42,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228 states and 229 transitions. [2024-11-27 23:36:42,033 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:42,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228 states to 196 states and 197 transitions. [2024-11-27 23:36:42,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:36:42,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:36:42,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 197 transitions. [2024-11-27 23:36:42,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:36:42,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 197 transitions. [2024-11-27 23:36:42,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 197 transitions. [2024-11-27 23:36:42,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2024-11-27 23:36:42,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 194 states have (on average 1.0051546391752577) internal successors, (195), 193 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:36:42,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 195 transitions. [2024-11-27 23:36:42,045 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 195 transitions. [2024-11-27 23:36:42,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2024-11-27 23:36:42,049 INFO L425 stractBuchiCegarLoop]: Abstraction has 194 states and 195 transitions. [2024-11-27 23:36:42,049 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-27 23:36:42,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 195 transitions. [2024-11-27 23:36:42,051 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:36:42,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:36:42,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:36:42,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [63, 62, 62, 1, 1, 1, 1] [2024-11-27 23:36:42,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:36:42,059 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:36:42,059 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:36:42,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:36:42,060 INFO L85 PathProgramCache]: Analyzing trace with hash -1470430519, now seen corresponding path program 5 times [2024-11-27 23:36:42,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:36:42,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942844070] [2024-11-27 23:36:42,060 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:42,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:36:42,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:55,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-27 23:36:55,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942844070] [2024-11-27 23:36:55,724 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942844070] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-27 23:36:55,724 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1586008673] [2024-11-27 23:36:55,724 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:36:55,724 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-27 23:36:55,724 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-27 23:36:55,729 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-27 23:36:55,730 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c7f57904-18c1-482f-88ce-49c74c50201b/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-27 23:36:56,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-27 23:36:56,134 INFO L256 TraceCheckSpWp]: Trace formula consists of 1630 conjuncts, 190 conjuncts are in the unsatisfiable core [2024-11-27 23:36:56,157 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-27 23:36:56,163 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-11-27 23:36:56,177 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-11-27 23:36:56,189 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,199 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,207 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,216 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,240 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,254 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,266 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,279 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,289 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,300 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,311 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,322 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,335 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,357 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,381 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,394 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,405 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,413 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,422 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,434 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,450 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,464 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,475 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,485 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,497 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,508 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,518 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,529 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,539 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,549 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,560 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,570 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,580 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,588 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,596 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,604 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,620 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,629 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,639 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,648 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,659 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,668 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,679 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,690 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,703 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,713 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,724 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,734 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,744 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,758 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,774 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,789 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,797 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,807 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,816 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,824 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,833 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,841 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-11-27 23:36:56,845 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-11-27 23:36:56,848 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-27 23:37:01,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1586008673] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-27 23:37:01,451 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-27 23:37:01,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 66, 66] total 107 [2024-11-27 23:37:01,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1322825137] [2024-11-27 23:37:01,452 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-27 23:37:01,453 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-27 23:37:01,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:37:01,453 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 6 times [2024-11-27 23:37:01,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:37:01,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415130513] [2024-11-27 23:37:01,453 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:37:01,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:37:01,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:01,458 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:37:01,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:01,462 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:37:01,539 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-27 23:37:01,541 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2024-11-27 23:37:01,547 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5420, Invalid=5922, Unknown=0, NotChecked=0, Total=11342 [2024-11-27 23:37:01,547 INFO L87 Difference]: Start difference. First operand 194 states and 195 transitions. cyclomatic complexity: 3 Second operand has 107 states, 107 states have (on average 2.9065420560747666) internal successors, (311), 107 states have internal predecessors, (311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:37:06,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-27 23:37:06,066 INFO L93 Difference]: Finished difference Result 348 states and 349 transitions. [2024-11-27 23:37:06,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 349 transitions. [2024-11-27 23:37:06,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:37:06,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 310 states and 311 transitions. [2024-11-27 23:37:06,071 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-11-27 23:37:06,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-11-27 23:37:06,071 INFO L73 IsDeterministic]: Start isDeterministic. Operand 310 states and 311 transitions. [2024-11-27 23:37:06,072 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-27 23:37:06,072 INFO L218 hiAutomatonCegarLoop]: Abstraction has 310 states and 311 transitions. [2024-11-27 23:37:06,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states and 311 transitions. [2024-11-27 23:37:06,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 308. [2024-11-27 23:37:06,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.0032467532467533) internal successors, (309), 307 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-27 23:37:06,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 309 transitions. [2024-11-27 23:37:06,085 INFO L240 hiAutomatonCegarLoop]: Abstraction has 308 states and 309 transitions. [2024-11-27 23:37:06,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2024-11-27 23:37:06,090 INFO L425 stractBuchiCegarLoop]: Abstraction has 308 states and 309 transitions. [2024-11-27 23:37:06,090 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-27 23:37:06,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 309 transitions. [2024-11-27 23:37:06,092 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-11-27 23:37:06,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-27 23:37:06,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-27 23:37:06,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [101, 100, 100, 1, 1, 1, 1] [2024-11-27 23:37:06,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-11-27 23:37:06,103 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#0(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#0(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#0(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#1(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-11-27 23:37:06,103 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#1(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#1(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-11-27 23:37:06,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:37:06,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1507507785, now seen corresponding path program 6 times [2024-11-27 23:37:06,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:37:06,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747193242] [2024-11-27 23:37:06,104 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:37:06,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:37:06,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:06,654 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:37:06,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:06,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:37:06,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:37:06,987 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 7 times [2024-11-27 23:37:06,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:37:06,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979343949] [2024-11-27 23:37:06,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:37:06,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:37:06,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:06,993 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:37:06,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:06,998 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-27 23:37:06,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-27 23:37:06,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1986396912, now seen corresponding path program 1 times [2024-11-27 23:37:06,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-27 23:37:06,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037476776] [2024-11-27 23:37:06,999 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-27 23:37:07,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-27 23:37:07,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:07,385 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-27 23:37:07,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-27 23:37:07,622 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace