./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 04:16:09,881 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 04:16:09,963 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-28 04:16:09,977 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 04:16:09,978 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 04:16:10,030 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 04:16:10,031 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 04:16:10,032 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 04:16:10,032 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 04:16:10,033 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 04:16:10,034 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 04:16:10,034 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 04:16:10,035 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 04:16:10,035 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-28 04:16:10,035 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-28 04:16:10,036 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-28 04:16:10,036 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-28 04:16:10,037 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-28 04:16:10,037 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-28 04:16:10,037 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 04:16:10,037 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-28 04:16:10,037 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-28 04:16:10,037 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-28 04:16:10,038 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-28 04:16:10,039 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 04:16:10,039 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-28 04:16:10,039 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 04:16:10,039 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 04:16:10,039 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 04:16:10,039 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 04:16:10,040 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 04:16:10,040 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL_NO_AM [2024-11-28 04:16:10,040 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-28 04:16:10,040 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2024-11-28 04:16:10,413 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 04:16:10,433 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 04:16:10,435 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 04:16:10,439 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 04:16:10,439 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 04:16:10,442 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2024-11-28 04:16:14,225 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/data/3ce0fc633/aba8e2ffc9f24bd6b518dea6f7aca8cc/FLAGcb5cb9680 [2024-11-28 04:16:14,551 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 04:16:14,552 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2024-11-28 04:16:14,565 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/data/3ce0fc633/aba8e2ffc9f24bd6b518dea6f7aca8cc/FLAGcb5cb9680 [2024-11-28 04:16:14,798 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/data/3ce0fc633/aba8e2ffc9f24bd6b518dea6f7aca8cc [2024-11-28 04:16:14,801 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 04:16:14,803 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 04:16:14,805 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 04:16:14,805 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 04:16:14,811 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 04:16:14,812 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 04:16:14" (1/1) ... [2024-11-28 04:16:14,813 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27c85473 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:14, skipping insertion in model container [2024-11-28 04:16:14,813 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 04:16:14" (1/1) ... [2024-11-28 04:16:14,850 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 04:16:15,191 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 04:16:15,220 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 04:16:15,321 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 04:16:15,352 INFO L204 MainTranslator]: Completed translation [2024-11-28 04:16:15,353 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15 WrapperNode [2024-11-28 04:16:15,353 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 04:16:15,355 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 04:16:15,355 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 04:16:15,355 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 04:16:15,372 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,387 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,481 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1346 [2024-11-28 04:16:15,481 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 04:16:15,482 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 04:16:15,482 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 04:16:15,483 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 04:16:15,494 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,495 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,501 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,539 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-28 04:16:15,543 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,544 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,580 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,583 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,618 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,625 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,635 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,642 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 04:16:15,643 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 04:16:15,643 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 04:16:15,643 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 04:16:15,644 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (1/1) ... [2024-11-28 04:16:15,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:15,677 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:15,693 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:15,697 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-28 04:16:15,736 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 04:16:15,736 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-28 04:16:15,737 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 04:16:15,737 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 04:16:15,853 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 04:16:15,855 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 04:16:17,693 INFO L? ?]: Removed 252 outVars from TransFormulas that were not future-live. [2024-11-28 04:16:17,694 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 04:16:17,744 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 04:16:17,744 INFO L312 CfgBuilder]: Removed 16 assume(true) statements. [2024-11-28 04:16:17,748 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 04:16:17 BoogieIcfgContainer [2024-11-28 04:16:17,748 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 04:16:17,749 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-28 04:16:17,749 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-28 04:16:17,756 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-28 04:16:17,757 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 04:16:17,757 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 04:16:14" (1/3) ... [2024-11-28 04:16:17,758 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c186dcd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 04:16:17, skipping insertion in model container [2024-11-28 04:16:17,758 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 04:16:17,759 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 04:16:15" (2/3) ... [2024-11-28 04:16:17,759 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7c186dcd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 04:16:17, skipping insertion in model container [2024-11-28 04:16:17,759 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 04:16:17,759 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 04:16:17" (3/3) ... [2024-11-28 04:16:17,761 INFO L363 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2024-11-28 04:16:17,852 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-28 04:16:17,852 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-28 04:16:17,852 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-28 04:16:17,852 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-28 04:16:17,852 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-28 04:16:17,853 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-28 04:16:17,853 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-28 04:16:17,853 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-28 04:16:17,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 551 states, 550 states have (on average 1.529090909090909) internal successors, (841), 550 states have internal predecessors, (841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:17,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 468 [2024-11-28 04:16:17,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:17,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:17,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:17,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:17,956 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-28 04:16:17,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 551 states, 550 states have (on average 1.529090909090909) internal successors, (841), 550 states have internal predecessors, (841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:17,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 468 [2024-11-28 04:16:17,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:17,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:17,991 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:17,991 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:18,004 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:18,005 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:18,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:18,018 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2024-11-28 04:16:18,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:18,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79289306] [2024-11-28 04:16:18,031 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:18,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:18,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:18,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:18,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [79289306] [2024-11-28 04:16:18,363 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [79289306] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:18,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [506684298] [2024-11-28 04:16:18,365 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:18,365 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:18,365 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:18,369 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:18,372 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 04:16:18,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:18,535 INFO L256 TraceCheckSpWp]: Trace formula consists of 225 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:18,541 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:18,652 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:18,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [506684298] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:18,782 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:18,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-28 04:16:18,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020512865] [2024-11-28 04:16:18,786 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:18,791 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:18,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:18,792 INFO L85 PathProgramCache]: Analyzing trace with hash -416790334, now seen corresponding path program 1 times [2024-11-28 04:16:18,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:18,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1346598444] [2024-11-28 04:16:18,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:18,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:18,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:18,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:18,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1346598444] [2024-11-28 04:16:18,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1346598444] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:18,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1062638470] [2024-11-28 04:16:18,883 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:18,883 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:18,883 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:18,888 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:18,891 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 04:16:19,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:19,032 INFO L256 TraceCheckSpWp]: Trace formula consists of 196 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 04:16:19,035 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:19,044 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:19,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1062638470] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:19,057 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:19,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-28 04:16:19,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1415741112] [2024-11-28 04:16:19,059 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:19,060 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:19,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:19,099 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 04:16:19,100 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 04:16:19,103 INFO L87 Difference]: Start difference. First operand has 551 states, 550 states have (on average 1.529090909090909) internal successors, (841), 550 states have internal predecessors, (841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 26.25) internal successors, (105), 4 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:19,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:19,288 INFO L93 Difference]: Finished difference Result 549 states and 808 transitions. [2024-11-28 04:16:19,292 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 549 states and 808 transitions. [2024-11-28 04:16:19,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 465 [2024-11-28 04:16:19,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 549 states to 544 states and 803 transitions. [2024-11-28 04:16:19,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 544 [2024-11-28 04:16:19,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 544 [2024-11-28 04:16:19,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 544 states and 803 transitions. [2024-11-28 04:16:19,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:19,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 544 states and 803 transitions. [2024-11-28 04:16:19,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states and 803 transitions. [2024-11-28 04:16:19,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 544. [2024-11-28 04:16:19,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 544 states, 544 states have (on average 1.4761029411764706) internal successors, (803), 543 states have internal predecessors, (803), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:19,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 803 transitions. [2024-11-28 04:16:19,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 544 states and 803 transitions. [2024-11-28 04:16:19,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:19,395 INFO L425 stractBuchiCegarLoop]: Abstraction has 544 states and 803 transitions. [2024-11-28 04:16:19,396 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-28 04:16:19,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 544 states and 803 transitions. [2024-11-28 04:16:19,400 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 465 [2024-11-28 04:16:19,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:19,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:19,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:19,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:19,404 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:19,404 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:19,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:19,405 INFO L85 PathProgramCache]: Analyzing trace with hash -939120955, now seen corresponding path program 1 times [2024-11-28 04:16:19,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:19,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1976723437] [2024-11-28 04:16:19,405 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:19,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:19,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:19,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:19,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1976723437] [2024-11-28 04:16:19,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1976723437] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:19,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1483230363] [2024-11-28 04:16:19,520 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:19,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:19,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:19,523 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:19,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 04:16:19,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:19,667 INFO L256 TraceCheckSpWp]: Trace formula consists of 220 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:19,669 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:19,771 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:19,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1483230363] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:19,865 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:19,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-28 04:16:19,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [320303380] [2024-11-28 04:16:19,866 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:19,866 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:19,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:19,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1186100565, now seen corresponding path program 1 times [2024-11-28 04:16:19,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:19,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151124857] [2024-11-28 04:16:19,867 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:19,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:19,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:20,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:20,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151124857] [2024-11-28 04:16:20,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151124857] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:20,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [106998111] [2024-11-28 04:16:20,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:20,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:20,046 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:20,051 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:20,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 04:16:20,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:20,168 INFO L256 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:20,172 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:20,330 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:20,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [106998111] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:20,468 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:20,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:20,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174640902] [2024-11-28 04:16:20,468 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:20,470 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:20,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:20,470 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 04:16:20,471 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 04:16:20,471 INFO L87 Difference]: Start difference. First operand 544 states and 803 transitions. cyclomatic complexity: 260 Second operand has 4 states, 4 states have (on average 27.5) internal successors, (110), 4 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:20,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:20,638 INFO L93 Difference]: Finished difference Result 956 states and 1395 transitions. [2024-11-28 04:16:20,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 956 states and 1395 transitions. [2024-11-28 04:16:20,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 876 [2024-11-28 04:16:20,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 956 states to 956 states and 1395 transitions. [2024-11-28 04:16:20,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 956 [2024-11-28 04:16:20,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 956 [2024-11-28 04:16:20,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 956 states and 1395 transitions. [2024-11-28 04:16:20,672 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:20,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 956 states and 1395 transitions. [2024-11-28 04:16:20,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 956 states and 1395 transitions. [2024-11-28 04:16:20,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 956 to 955. [2024-11-28 04:16:20,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 955 states, 955 states have (on average 1.4596858638743455) internal successors, (1394), 954 states have internal predecessors, (1394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:20,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 955 states to 955 states and 1394 transitions. [2024-11-28 04:16:20,725 INFO L240 hiAutomatonCegarLoop]: Abstraction has 955 states and 1394 transitions. [2024-11-28 04:16:20,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:20,727 INFO L425 stractBuchiCegarLoop]: Abstraction has 955 states and 1394 transitions. [2024-11-28 04:16:20,727 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-28 04:16:20,727 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 955 states and 1394 transitions. [2024-11-28 04:16:20,735 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:20,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:20,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:20,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:20,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:20,738 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:20,738 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:20,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:20,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1402292740, now seen corresponding path program 1 times [2024-11-28 04:16:20,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:20,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155301189] [2024-11-28 04:16:20,739 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:20,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:20,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:20,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:20,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155301189] [2024-11-28 04:16:20,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [155301189] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:20,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1247986737] [2024-11-28 04:16:20,798 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:20,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:20,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:20,803 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:20,806 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 04:16:20,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:20,935 INFO L256 TraceCheckSpWp]: Trace formula consists of 218 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:20,937 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:21,072 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:21,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1247986737] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:21,199 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:21,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-28 04:16:21,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099980098] [2024-11-28 04:16:21,199 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:21,200 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:21,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:21,200 INFO L85 PathProgramCache]: Analyzing trace with hash 882832919, now seen corresponding path program 1 times [2024-11-28 04:16:21,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:21,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487541261] [2024-11-28 04:16:21,201 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:21,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:21,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:21,361 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:21,361 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487541261] [2024-11-28 04:16:21,361 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487541261] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:21,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [618002929] [2024-11-28 04:16:21,362 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:21,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:21,362 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:21,365 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:21,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 04:16:21,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:21,483 INFO L256 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:21,486 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:21,643 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:21,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [618002929] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:21,774 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:21,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:21,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1192941763] [2024-11-28 04:16:21,775 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:21,775 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:21,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:21,776 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 04:16:21,776 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 04:16:21,777 INFO L87 Difference]: Start difference. First operand 955 states and 1394 transitions. cyclomatic complexity: 441 Second operand has 4 states, 4 states have (on average 30.75) internal successors, (123), 4 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:21,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:21,889 INFO L93 Difference]: Finished difference Result 955 states and 1371 transitions. [2024-11-28 04:16:21,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 955 states and 1371 transitions. [2024-11-28 04:16:21,903 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:21,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 955 states to 955 states and 1371 transitions. [2024-11-28 04:16:21,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 955 [2024-11-28 04:16:21,913 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 955 [2024-11-28 04:16:21,913 INFO L73 IsDeterministic]: Start isDeterministic. Operand 955 states and 1371 transitions. [2024-11-28 04:16:21,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:21,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 955 states and 1371 transitions. [2024-11-28 04:16:21,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 955 states and 1371 transitions. [2024-11-28 04:16:21,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 955 to 955. [2024-11-28 04:16:21,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 955 states, 955 states have (on average 1.4356020942408376) internal successors, (1371), 954 states have internal predecessors, (1371), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:21,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 955 states to 955 states and 1371 transitions. [2024-11-28 04:16:21,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 955 states and 1371 transitions. [2024-11-28 04:16:21,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:21,947 INFO L425 stractBuchiCegarLoop]: Abstraction has 955 states and 1371 transitions. [2024-11-28 04:16:21,947 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-28 04:16:21,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 955 states and 1371 transitions. [2024-11-28 04:16:21,955 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:21,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:21,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:21,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:21,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:21,958 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:21,958 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:21,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:21,959 INFO L85 PathProgramCache]: Analyzing trace with hash 76656135, now seen corresponding path program 1 times [2024-11-28 04:16:21,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:21,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275833248] [2024-11-28 04:16:21,959 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:21,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:21,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:22,018 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:22,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275833248] [2024-11-28 04:16:22,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275833248] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:22,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2070940040] [2024-11-28 04:16:22,018 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:22,018 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:22,019 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:22,023 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:22,027 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 04:16:22,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:22,129 INFO L256 TraceCheckSpWp]: Trace formula consists of 216 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:22,132 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:22,169 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:22,205 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2070940040] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:22,209 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:22,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-28 04:16:22,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065466955] [2024-11-28 04:16:22,209 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:22,210 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:22,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:22,210 INFO L85 PathProgramCache]: Analyzing trace with hash -1668207781, now seen corresponding path program 1 times [2024-11-28 04:16:22,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:22,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086825011] [2024-11-28 04:16:22,210 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:22,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:22,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:22,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:22,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086825011] [2024-11-28 04:16:22,333 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086825011] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:22,333 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [518091045] [2024-11-28 04:16:22,333 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:22,333 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:22,334 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:22,339 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:22,341 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 04:16:22,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:22,442 INFO L256 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:22,444 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:22,545 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:22,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [518091045] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:22,675 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:22,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:22,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544696254] [2024-11-28 04:16:22,677 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:22,677 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:22,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:22,678 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 04:16:22,679 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-28 04:16:22,680 INFO L87 Difference]: Start difference. First operand 955 states and 1371 transitions. cyclomatic complexity: 418 Second operand has 5 states, 5 states have (on average 19.4) internal successors, (97), 5 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:22,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:22,751 INFO L93 Difference]: Finished difference Result 955 states and 1364 transitions. [2024-11-28 04:16:22,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 955 states and 1364 transitions. [2024-11-28 04:16:22,760 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:22,767 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 955 states to 955 states and 1364 transitions. [2024-11-28 04:16:22,767 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 955 [2024-11-28 04:16:22,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 955 [2024-11-28 04:16:22,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 955 states and 1364 transitions. [2024-11-28 04:16:22,771 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:22,771 INFO L218 hiAutomatonCegarLoop]: Abstraction has 955 states and 1364 transitions. [2024-11-28 04:16:22,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 955 states and 1364 transitions. [2024-11-28 04:16:22,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 955 to 955. [2024-11-28 04:16:22,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 955 states, 955 states have (on average 1.4282722513089006) internal successors, (1364), 954 states have internal predecessors, (1364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:22,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 955 states to 955 states and 1364 transitions. [2024-11-28 04:16:22,797 INFO L240 hiAutomatonCegarLoop]: Abstraction has 955 states and 1364 transitions. [2024-11-28 04:16:22,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:22,800 INFO L425 stractBuchiCegarLoop]: Abstraction has 955 states and 1364 transitions. [2024-11-28 04:16:22,800 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-28 04:16:22,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 955 states and 1364 transitions. [2024-11-28 04:16:22,807 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:22,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:22,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:22,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:22,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:22,813 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:22,814 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:22,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:22,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1852859069, now seen corresponding path program 1 times [2024-11-28 04:16:22,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:22,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [898257612] [2024-11-28 04:16:22,815 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:22,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:22,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:22,890 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:22,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [898257612] [2024-11-28 04:16:22,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [898257612] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:22,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [335088042] [2024-11-28 04:16:22,891 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:22,891 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:22,892 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:22,896 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:22,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 04:16:23,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:23,005 INFO L256 TraceCheckSpWp]: Trace formula consists of 214 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:23,006 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:23,055 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:23,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [335088042] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:23,107 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:23,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-28 04:16:23,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883403863] [2024-11-28 04:16:23,108 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:23,108 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:23,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:23,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1756000666, now seen corresponding path program 1 times [2024-11-28 04:16:23,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:23,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724403628] [2024-11-28 04:16:23,111 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:23,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:23,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:23,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:23,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724403628] [2024-11-28 04:16:23,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724403628] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:23,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [681217114] [2024-11-28 04:16:23,200 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:23,201 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:23,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:23,204 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:23,207 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 04:16:23,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:23,337 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:23,339 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:23,450 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:23,557 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [681217114] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:23,557 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:23,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:23,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959823576] [2024-11-28 04:16:23,558 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:23,558 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:23,558 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:23,559 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 04:16:23,559 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-28 04:16:23,559 INFO L87 Difference]: Start difference. First operand 955 states and 1364 transitions. cyclomatic complexity: 411 Second operand has 5 states, 5 states have (on average 22.6) internal successors, (113), 5 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:23,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:23,655 INFO L93 Difference]: Finished difference Result 982 states and 1384 transitions. [2024-11-28 04:16:23,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 982 states and 1384 transitions. [2024-11-28 04:16:23,663 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 902 [2024-11-28 04:16:23,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 982 states to 982 states and 1384 transitions. [2024-11-28 04:16:23,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 982 [2024-11-28 04:16:23,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 982 [2024-11-28 04:16:23,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 982 states and 1384 transitions. [2024-11-28 04:16:23,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:23,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 982 states and 1384 transitions. [2024-11-28 04:16:23,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 982 states and 1384 transitions. [2024-11-28 04:16:23,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 982 to 955. [2024-11-28 04:16:23,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 955 states, 955 states have (on average 1.4115183246073297) internal successors, (1348), 954 states have internal predecessors, (1348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:23,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 955 states to 955 states and 1348 transitions. [2024-11-28 04:16:23,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 955 states and 1348 transitions. [2024-11-28 04:16:23,698 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:23,698 INFO L425 stractBuchiCegarLoop]: Abstraction has 955 states and 1348 transitions. [2024-11-28 04:16:23,698 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-28 04:16:23,699 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 955 states and 1348 transitions. [2024-11-28 04:16:23,706 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 875 [2024-11-28 04:16:23,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:23,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:23,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:23,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:23,708 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:23,709 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:23,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:23,710 INFO L85 PathProgramCache]: Analyzing trace with hash -922447165, now seen corresponding path program 1 times [2024-11-28 04:16:23,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:23,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139731524] [2024-11-28 04:16:23,710 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:23,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:23,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:23,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:23,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139731524] [2024-11-28 04:16:23,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139731524] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:23,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1515589116] [2024-11-28 04:16:23,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:23,861 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:23,862 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:23,865 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:23,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-28 04:16:23,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:23,967 INFO L256 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-28 04:16:23,969 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:23,995 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:24,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1515589116] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:24,011 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:24,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 04:16:24,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066217647] [2024-11-28 04:16:24,011 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:24,012 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:24,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:24,012 INFO L85 PathProgramCache]: Analyzing trace with hash -564314662, now seen corresponding path program 1 times [2024-11-28 04:16:24,013 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:24,013 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059142905] [2024-11-28 04:16:24,013 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:24,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:24,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:24,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:24,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2059142905] [2024-11-28 04:16:24,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2059142905] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:24,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1955967229] [2024-11-28 04:16:24,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:24,099 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:24,099 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:24,102 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:24,106 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-28 04:16:24,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:24,224 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:24,226 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:24,335 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:24,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1955967229] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:24,443 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:24,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:24,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254370649] [2024-11-28 04:16:24,443 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:24,444 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:24,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:24,444 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 04:16:24,445 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 04:16:24,445 INFO L87 Difference]: Start difference. First operand 955 states and 1348 transitions. cyclomatic complexity: 395 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:24,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:24,720 INFO L93 Difference]: Finished difference Result 1003 states and 1396 transitions. [2024-11-28 04:16:24,720 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1003 states and 1396 transitions. [2024-11-28 04:16:24,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 920 [2024-11-28 04:16:24,735 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1003 states to 1003 states and 1396 transitions. [2024-11-28 04:16:24,735 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1003 [2024-11-28 04:16:24,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1003 [2024-11-28 04:16:24,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1003 states and 1396 transitions. [2024-11-28 04:16:24,739 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:24,739 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1003 states and 1396 transitions. [2024-11-28 04:16:24,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1003 states and 1396 transitions. [2024-11-28 04:16:24,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1003 to 1003. [2024-11-28 04:16:24,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1003 states, 1003 states have (on average 1.3918245264207378) internal successors, (1396), 1002 states have internal predecessors, (1396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:24,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1003 states to 1003 states and 1396 transitions. [2024-11-28 04:16:24,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1003 states and 1396 transitions. [2024-11-28 04:16:24,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:24,767 INFO L425 stractBuchiCegarLoop]: Abstraction has 1003 states and 1396 transitions. [2024-11-28 04:16:24,767 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-28 04:16:24,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1003 states and 1396 transitions. [2024-11-28 04:16:24,776 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 920 [2024-11-28 04:16:24,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:24,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:24,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:24,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:24,781 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:24,781 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:24,782 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:24,782 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2024-11-28 04:16:24,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:24,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457661977] [2024-11-28 04:16:24,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:24,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:24,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:24,802 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:24,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:24,871 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:24,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:24,872 INFO L85 PathProgramCache]: Analyzing trace with hash -564314662, now seen corresponding path program 2 times [2024-11-28 04:16:24,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:24,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456544921] [2024-11-28 04:16:24,872 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:24,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:24,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:24,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:24,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456544921] [2024-11-28 04:16:24,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456544921] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:24,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1447140216] [2024-11-28 04:16:24,932 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:24,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:24,933 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:24,937 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:24,940 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-28 04:16:25,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:25,039 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:25,041 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:25,153 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:25,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1447140216] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:25,285 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:25,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:25,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501185548] [2024-11-28 04:16:25,285 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:25,286 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:25,286 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:25,286 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:25,286 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:25,287 INFO L87 Difference]: Start difference. First operand 1003 states and 1396 transitions. cyclomatic complexity: 395 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:25,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:25,328 INFO L93 Difference]: Finished difference Result 1175 states and 1632 transitions. [2024-11-28 04:16:25,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1175 states and 1632 transitions. [2024-11-28 04:16:25,338 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1035 [2024-11-28 04:16:25,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1175 states to 1175 states and 1632 transitions. [2024-11-28 04:16:25,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1175 [2024-11-28 04:16:25,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1175 [2024-11-28 04:16:25,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1175 states and 1632 transitions. [2024-11-28 04:16:25,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:25,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1632 transitions. [2024-11-28 04:16:25,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1175 states and 1632 transitions. [2024-11-28 04:16:25,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1175 to 1175. [2024-11-28 04:16:25,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1175 states, 1175 states have (on average 1.388936170212766) internal successors, (1632), 1174 states have internal predecessors, (1632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:25,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1175 states to 1175 states and 1632 transitions. [2024-11-28 04:16:25,384 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1175 states and 1632 transitions. [2024-11-28 04:16:25,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:25,385 INFO L425 stractBuchiCegarLoop]: Abstraction has 1175 states and 1632 transitions. [2024-11-28 04:16:25,385 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-28 04:16:25,385 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1175 states and 1632 transitions. [2024-11-28 04:16:25,395 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1035 [2024-11-28 04:16:25,395 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:25,395 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:25,397 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:25,397 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:25,397 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:25,398 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:25,398 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:25,399 INFO L85 PathProgramCache]: Analyzing trace with hash -113006587, now seen corresponding path program 1 times [2024-11-28 04:16:25,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:25,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54172672] [2024-11-28 04:16:25,399 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:25,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:25,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:25,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:25,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54172672] [2024-11-28 04:16:25,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54172672] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:25,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1992887436] [2024-11-28 04:16:25,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:25,489 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:25,489 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:25,495 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:25,498 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-28 04:16:25,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:25,607 INFO L256 TraceCheckSpWp]: Trace formula consists of 217 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:25,609 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:25,655 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:25,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1992887436] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:25,706 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:25,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5 [2024-11-28 04:16:25,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43845491] [2024-11-28 04:16:25,707 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:25,707 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:25,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:25,708 INFO L85 PathProgramCache]: Analyzing trace with hash 837617626, now seen corresponding path program 1 times [2024-11-28 04:16:25,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:25,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015989952] [2024-11-28 04:16:25,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:25,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:25,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:25,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:25,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1015989952] [2024-11-28 04:16:25,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1015989952] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:25,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [791240608] [2024-11-28 04:16:25,789 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:25,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:25,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:25,793 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:25,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-28 04:16:25,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:25,889 INFO L256 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 04:16:25,891 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:25,910 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:25,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [791240608] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:25,937 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:25,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 04:16:25,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758142585] [2024-11-28 04:16:25,937 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:25,937 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:25,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:25,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 04:16:25,938 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 04:16:25,938 INFO L87 Difference]: Start difference. First operand 1175 states and 1632 transitions. cyclomatic complexity: 459 Second operand has 6 states, 6 states have (on average 17.5) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:26,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:26,041 INFO L93 Difference]: Finished difference Result 1808 states and 2504 transitions. [2024-11-28 04:16:26,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1808 states and 2504 transitions. [2024-11-28 04:16:26,056 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1723 [2024-11-28 04:16:26,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1808 states to 1808 states and 2504 transitions. [2024-11-28 04:16:26,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1808 [2024-11-28 04:16:26,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1808 [2024-11-28 04:16:26,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1808 states and 2504 transitions. [2024-11-28 04:16:26,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:26,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1808 states and 2504 transitions. [2024-11-28 04:16:26,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1808 states and 2504 transitions. [2024-11-28 04:16:26,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1808 to 1003. [2024-11-28 04:16:26,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1003 states, 1003 states have (on average 1.3838484546360916) internal successors, (1388), 1002 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:26,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1003 states to 1003 states and 1388 transitions. [2024-11-28 04:16:26,146 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1003 states and 1388 transitions. [2024-11-28 04:16:26,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 04:16:26,147 INFO L425 stractBuchiCegarLoop]: Abstraction has 1003 states and 1388 transitions. [2024-11-28 04:16:26,148 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-28 04:16:26,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1003 states and 1388 transitions. [2024-11-28 04:16:26,154 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 920 [2024-11-28 04:16:26,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:26,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:26,156 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:26,156 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:26,156 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:26,156 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:26,157 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:26,157 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2024-11-28 04:16:26,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:26,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682946021] [2024-11-28 04:16:26,157 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:26,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:26,170 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:26,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:26,192 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:26,193 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:26,193 INFO L85 PathProgramCache]: Analyzing trace with hash -1126190054, now seen corresponding path program 1 times [2024-11-28 04:16:26,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:26,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594815032] [2024-11-28 04:16:26,193 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,194 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:26,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:26,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:26,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594815032] [2024-11-28 04:16:26,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594815032] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:26,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [260528976] [2024-11-28 04:16:26,272 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,272 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:26,273 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:26,277 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:26,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-28 04:16:26,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:26,377 INFO L256 TraceCheckSpWp]: Trace formula consists of 178 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 04:16:26,379 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:26,392 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:26,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [260528976] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:26,419 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:26,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 04:16:26,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [193151718] [2024-11-28 04:16:26,420 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:26,420 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:26,420 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:26,420 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 04:16:26,420 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 04:16:26,421 INFO L87 Difference]: Start difference. First operand 1003 states and 1388 transitions. cyclomatic complexity: 387 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:26,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:26,512 INFO L93 Difference]: Finished difference Result 1017 states and 1402 transitions. [2024-11-28 04:16:26,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1017 states and 1402 transitions. [2024-11-28 04:16:26,520 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 934 [2024-11-28 04:16:26,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1017 states to 1017 states and 1402 transitions. [2024-11-28 04:16:26,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1017 [2024-11-28 04:16:26,528 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1017 [2024-11-28 04:16:26,528 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1017 states and 1402 transitions. [2024-11-28 04:16:26,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:26,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1017 states and 1402 transitions. [2024-11-28 04:16:26,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017 states and 1402 transitions. [2024-11-28 04:16:26,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017 to 1009. [2024-11-28 04:16:26,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1009 states, 1009 states have (on average 1.3815659068384538) internal successors, (1394), 1008 states have internal predecessors, (1394), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:26,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1009 states to 1009 states and 1394 transitions. [2024-11-28 04:16:26,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1009 states and 1394 transitions. [2024-11-28 04:16:26,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:26,557 INFO L425 stractBuchiCegarLoop]: Abstraction has 1009 states and 1394 transitions. [2024-11-28 04:16:26,557 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-28 04:16:26,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1009 states and 1394 transitions. [2024-11-28 04:16:26,564 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 926 [2024-11-28 04:16:26,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:26,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:26,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:26,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:26,566 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:26,567 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:26,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:26,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2024-11-28 04:16:26,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:26,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047250205] [2024-11-28 04:16:26,568 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:26,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:26,581 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:26,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:26,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:26,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:26,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1052654199, now seen corresponding path program 1 times [2024-11-28 04:16:26,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:26,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158008540] [2024-11-28 04:16:26,603 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:26,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:26,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:26,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158008540] [2024-11-28 04:16:26,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158008540] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:26,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1819183892] [2024-11-28 04:16:26,697 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:26,697 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:26,697 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:26,702 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:26,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-28 04:16:26,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:26,827 INFO L256 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 04:16:26,828 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:26,844 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:26,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1819183892] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:26,873 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:26,874 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 04:16:26,874 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820430631] [2024-11-28 04:16:26,874 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:26,875 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:26,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:26,875 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 04:16:26,875 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 04:16:26,875 INFO L87 Difference]: Start difference. First operand 1009 states and 1394 transitions. cyclomatic complexity: 387 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:27,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:27,138 INFO L93 Difference]: Finished difference Result 1057 states and 1442 transitions. [2024-11-28 04:16:27,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1057 states and 1442 transitions. [2024-11-28 04:16:27,146 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 971 [2024-11-28 04:16:27,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1057 states to 1057 states and 1442 transitions. [2024-11-28 04:16:27,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1057 [2024-11-28 04:16:27,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1057 [2024-11-28 04:16:27,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1057 states and 1442 transitions. [2024-11-28 04:16:27,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:27,157 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1057 states and 1442 transitions. [2024-11-28 04:16:27,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1057 states and 1442 transitions. [2024-11-28 04:16:27,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1057 to 1057. [2024-11-28 04:16:27,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1057 states, 1057 states have (on average 1.3642384105960266) internal successors, (1442), 1056 states have internal predecessors, (1442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:27,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1057 states to 1057 states and 1442 transitions. [2024-11-28 04:16:27,182 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1057 states and 1442 transitions. [2024-11-28 04:16:27,183 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 04:16:27,184 INFO L425 stractBuchiCegarLoop]: Abstraction has 1057 states and 1442 transitions. [2024-11-28 04:16:27,184 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-28 04:16:27,184 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1057 states and 1442 transitions. [2024-11-28 04:16:27,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 971 [2024-11-28 04:16:27,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:27,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:27,192 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:27,192 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:27,193 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:27,193 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:27,194 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:27,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2024-11-28 04:16:27,194 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:27,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957659016] [2024-11-28 04:16:27,195 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:27,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:27,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:27,215 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:27,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:27,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:27,245 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:27,245 INFO L85 PathProgramCache]: Analyzing trace with hash -771979915, now seen corresponding path program 1 times [2024-11-28 04:16:27,245 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:27,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143816982] [2024-11-28 04:16:27,246 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:27,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:27,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:27,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:27,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143816982] [2024-11-28 04:16:27,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143816982] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:27,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2119555999] [2024-11-28 04:16:27,398 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:27,398 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:27,398 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:27,402 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:27,406 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-28 04:16:27,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:27,508 INFO L256 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-28 04:16:27,510 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:27,548 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:27,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2119555999] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:27,561 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:27,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-28 04:16:27,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888904529] [2024-11-28 04:16:27,561 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:27,562 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:27,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:27,562 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 04:16:27,563 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 04:16:27,563 INFO L87 Difference]: Start difference. First operand 1057 states and 1442 transitions. cyclomatic complexity: 387 Second operand has 8 states, 8 states have (on average 14.375) internal successors, (115), 8 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:28,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:28,074 INFO L93 Difference]: Finished difference Result 1111 states and 1482 transitions. [2024-11-28 04:16:28,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1111 states and 1482 transitions. [2024-11-28 04:16:28,082 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2024-11-28 04:16:28,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1111 states to 1111 states and 1482 transitions. [2024-11-28 04:16:28,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1111 [2024-11-28 04:16:28,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1111 [2024-11-28 04:16:28,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1111 states and 1482 transitions. [2024-11-28 04:16:28,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:28,092 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1482 transitions. [2024-11-28 04:16:28,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1111 states and 1482 transitions. [2024-11-28 04:16:28,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1111 to 1111. [2024-11-28 04:16:28,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1111 states, 1111 states have (on average 1.333933393339334) internal successors, (1482), 1110 states have internal predecessors, (1482), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:28,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1111 states to 1111 states and 1482 transitions. [2024-11-28 04:16:28,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1482 transitions. [2024-11-28 04:16:28,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 04:16:28,119 INFO L425 stractBuchiCegarLoop]: Abstraction has 1111 states and 1482 transitions. [2024-11-28 04:16:28,119 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-28 04:16:28,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1111 states and 1482 transitions. [2024-11-28 04:16:28,125 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1022 [2024-11-28 04:16:28,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:28,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:28,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:28,127 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:28,127 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:28,127 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:28,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:28,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2024-11-28 04:16:28,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:28,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679959922] [2024-11-28 04:16:28,129 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:28,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:28,141 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:28,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:28,159 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:28,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:28,160 INFO L85 PathProgramCache]: Analyzing trace with hash 416550777, now seen corresponding path program 1 times [2024-11-28 04:16:28,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:28,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123037620] [2024-11-28 04:16:28,160 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:28,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:28,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:28,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123037620] [2024-11-28 04:16:28,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123037620] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:28,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [788461880] [2024-11-28 04:16:28,216 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,217 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:28,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:28,220 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:28,224 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-28 04:16:28,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:28,323 INFO L256 TraceCheckSpWp]: Trace formula consists of 181 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:28,325 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:28,472 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:28,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [788461880] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:28,630 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:28,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:28,631 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867987042] [2024-11-28 04:16:28,631 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:28,631 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:28,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:28,632 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:28,632 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:28,632 INFO L87 Difference]: Start difference. First operand 1111 states and 1482 transitions. cyclomatic complexity: 373 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:28,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:28,702 INFO L93 Difference]: Finished difference Result 2021 states and 2663 transitions. [2024-11-28 04:16:28,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2021 states and 2663 transitions. [2024-11-28 04:16:28,715 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1930 [2024-11-28 04:16:28,727 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2021 states to 2021 states and 2663 transitions. [2024-11-28 04:16:28,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2021 [2024-11-28 04:16:28,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2021 [2024-11-28 04:16:28,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2021 states and 2663 transitions. [2024-11-28 04:16:28,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:28,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2021 states and 2663 transitions. [2024-11-28 04:16:28,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2021 states and 2663 transitions. [2024-11-28 04:16:28,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2021 to 1936. [2024-11-28 04:16:28,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1936 states, 1936 states have (on average 1.3197314049586777) internal successors, (2555), 1935 states have internal predecessors, (2555), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:28,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1936 states to 1936 states and 2555 transitions. [2024-11-28 04:16:28,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1936 states and 2555 transitions. [2024-11-28 04:16:28,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:28,781 INFO L425 stractBuchiCegarLoop]: Abstraction has 1936 states and 2555 transitions. [2024-11-28 04:16:28,782 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-28 04:16:28,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1936 states and 2555 transitions. [2024-11-28 04:16:28,792 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1845 [2024-11-28 04:16:28,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:28,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:28,794 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:28,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:28,794 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:28,795 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:28,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:28,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 6 times [2024-11-28 04:16:28,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:28,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [918109065] [2024-11-28 04:16:28,796 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:28,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:28,824 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:28,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:28,846 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:28,847 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:28,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1872898634, now seen corresponding path program 1 times [2024-11-28 04:16:28,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:28,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372977059] [2024-11-28 04:16:28,848 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:28,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:28,957 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:28,957 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372977059] [2024-11-28 04:16:28,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372977059] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:28,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [996211810] [2024-11-28 04:16:28,958 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:28,958 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:28,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:28,961 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:28,968 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-11-28 04:16:29,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:29,108 INFO L256 TraceCheckSpWp]: Trace formula consists of 185 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-28 04:16:29,111 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:29,153 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:29,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [996211810] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:29,169 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:29,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-28 04:16:29,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916299764] [2024-11-28 04:16:29,170 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:29,170 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:29,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:29,171 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 04:16:29,171 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 04:16:29,171 INFO L87 Difference]: Start difference. First operand 1936 states and 2555 transitions. cyclomatic complexity: 621 Second operand has 8 states, 8 states have (on average 12.125) internal successors, (97), 8 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:29,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:29,617 INFO L93 Difference]: Finished difference Result 1948 states and 2513 transitions. [2024-11-28 04:16:29,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1948 states and 2513 transitions. [2024-11-28 04:16:29,629 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1857 [2024-11-28 04:16:29,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1948 states to 1948 states and 2513 transitions. [2024-11-28 04:16:29,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1948 [2024-11-28 04:16:29,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1948 [2024-11-28 04:16:29,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1948 states and 2513 transitions. [2024-11-28 04:16:29,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:29,647 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1948 states and 2513 transitions. [2024-11-28 04:16:29,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1948 states and 2513 transitions. [2024-11-28 04:16:29,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1948 to 1948. [2024-11-28 04:16:29,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1948 states, 1948 states have (on average 1.290041067761807) internal successors, (2513), 1947 states have internal predecessors, (2513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:29,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1948 states to 1948 states and 2513 transitions. [2024-11-28 04:16:29,691 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1948 states and 2513 transitions. [2024-11-28 04:16:29,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 04:16:29,692 INFO L425 stractBuchiCegarLoop]: Abstraction has 1948 states and 2513 transitions. [2024-11-28 04:16:29,692 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-28 04:16:29,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1948 states and 2513 transitions. [2024-11-28 04:16:29,702 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1857 [2024-11-28 04:16:29,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:29,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:29,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:29,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:29,705 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:29,705 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:29,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:29,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 7 times [2024-11-28 04:16:29,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:29,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178448041] [2024-11-28 04:16:29,706 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:29,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:29,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:29,719 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:29,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:29,736 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:29,737 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:29,737 INFO L85 PathProgramCache]: Analyzing trace with hash 1188374970, now seen corresponding path program 1 times [2024-11-28 04:16:29,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:29,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902941244] [2024-11-28 04:16:29,738 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:29,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:29,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:29,753 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:29,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:29,776 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:29,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:29,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1397356298, now seen corresponding path program 1 times [2024-11-28 04:16:29,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:29,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919133111] [2024-11-28 04:16:29,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:29,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:29,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:29,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:29,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919133111] [2024-11-28 04:16:29,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1919133111] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:29,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1820884653] [2024-11-28 04:16:29,866 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:29,866 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:29,866 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:29,871 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:29,878 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-11-28 04:16:30,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:30,045 INFO L256 TraceCheckSpWp]: Trace formula consists of 392 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:30,048 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:30,345 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:30,647 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1820884653] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:30,647 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:30,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-28 04:16:30,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [157629351] [2024-11-28 04:16:30,648 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:32,296 INFO L204 LassoAnalysis]: Preferences: [2024-11-28 04:16:32,297 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-28 04:16:32,298 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-28 04:16:32,298 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-28 04:16:32,299 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2024-11-28 04:16:32,299 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:32,299 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-28 04:16:32,299 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-28 04:16:32,299 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration14_Loop [2024-11-28 04:16:32,300 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-28 04:16:32,300 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-28 04:16:32,332 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,340 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,349 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,354 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,357 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,409 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,425 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,443 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,488 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,494 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,499 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,507 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,531 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,543 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,587 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,594 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,604 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:32,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,285 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-28 04:16:33,286 INFO L365 LassoAnalysis]: Checking for nontermination... [2024-11-28 04:16:33,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,288 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,294 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,297 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2024-11-28 04:16:33,298 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,298 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,327 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,327 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet9#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,339 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Ended with exit code 0 [2024-11-28 04:16:33,340 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,340 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,343 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2024-11-28 04:16:33,350 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,351 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,384 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,385 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,396 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2024-11-28 04:16:33,397 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,397 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,401 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,404 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2024-11-28 04:16:33,405 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,406 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,430 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,430 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret20#1=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,441 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2024-11-28 04:16:33,441 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,441 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,443 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2024-11-28 04:16:33,446 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,447 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,463 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,463 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,470 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2024-11-28 04:16:33,470 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,470 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,472 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2024-11-28 04:16:33,475 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,476 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,499 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,499 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~6#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~6#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,511 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2024-11-28 04:16:33,511 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,512 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,514 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2024-11-28 04:16:33,522 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,523 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,546 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,546 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,557 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Ended with exit code 0 [2024-11-28 04:16:33,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,560 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,564 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2024-11-28 04:16:33,565 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,565 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,586 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,586 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret17#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret17#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,597 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:33,598 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,598 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,601 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2024-11-28 04:16:33,605 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,605 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,620 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2024-11-28 04:16:33,620 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet8#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet8#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2024-11-28 04:16:33,628 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2024-11-28 04:16:33,628 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,628 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,630 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,632 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2024-11-28 04:16:33,633 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2024-11-28 04:16:33,633 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,663 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2024-11-28 04:16:33,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,664 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:33,666 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:33,667 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2024-11-28 04:16:33,669 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2024-11-28 04:16:33,669 INFO L160 nArgumentSynthesizer]: Using integer mode. [2024-11-28 04:16:33,711 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2024-11-28 04:16:33,715 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2024-11-28 04:16:33,715 INFO L204 LassoAnalysis]: Preferences: [2024-11-28 04:16:33,715 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-11-28 04:16:33,715 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-11-28 04:16:33,715 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-11-28 04:16:33,715 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-11-28 04:16:33,715 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:33,715 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-11-28 04:16:33,715 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-11-28 04:16:33,715 INFO L132 ssoRankerPreferences]: Filename of dumped script: token_ring.05.cil-1.c_Iteration14_Loop [2024-11-28 04:16:33,715 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-11-28 04:16:33,715 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-11-28 04:16:33,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,888 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,894 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,897 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,903 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,905 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,909 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,933 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,943 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,948 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:33,980 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-11-28 04:16:34,555 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-11-28 04:16:34,560 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-11-28 04:16:34,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,562 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,565 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2024-11-28 04:16:34,569 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,583 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,583 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,583 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,583 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,584 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,588 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,588 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,591 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,601 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2024-11-28 04:16:34,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,605 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,609 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2024-11-28 04:16:34,610 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,624 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,624 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,625 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,625 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,627 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,635 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:34,635 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,635 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,637 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,640 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2024-11-28 04:16:34,644 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,657 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,657 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,657 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,657 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,657 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,658 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,658 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,659 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,667 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2024-11-28 04:16:34,667 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,669 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,670 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2024-11-28 04:16:34,672 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,684 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,685 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,685 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,685 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,685 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,685 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,685 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,687 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,694 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:34,694 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,695 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,697 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,700 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2024-11-28 04:16:34,703 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,720 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,720 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,720 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,720 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,720 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,721 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,721 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,723 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,733 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:34,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,736 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2024-11-28 04:16:34,739 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,752 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,752 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,753 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,753 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,753 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,756 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,756 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,760 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,774 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2024-11-28 04:16:34,775 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,775 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,779 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,782 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,783 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2024-11-28 04:16:34,801 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,801 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,801 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,801 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,801 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,802 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,802 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,806 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,817 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:34,817 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,820 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,824 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2024-11-28 04:16:34,825 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,843 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,843 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,843 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,844 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,844 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,844 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,845 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,847 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,858 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2024-11-28 04:16:34,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,861 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,866 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2024-11-28 04:16:34,868 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,885 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,885 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,885 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,885 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-28 04:16:34,886 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,887 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-28 04:16:34,887 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,891 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,903 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:34,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,906 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,909 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2024-11-28 04:16:34,911 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,929 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,929 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,929 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,929 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,930 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,930 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,932 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,943 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Ended with exit code 0 [2024-11-28 04:16:34,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,946 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,949 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2024-11-28 04:16:34,950 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:34,968 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:34,968 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:34,968 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:34,968 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:34,968 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:34,969 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:34,969 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:34,973 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:34,985 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2024-11-28 04:16:34,985 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:34,985 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:34,989 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:34,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2024-11-28 04:16:34,999 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,017 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,017 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,017 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,017 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,017 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,018 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,018 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,023 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,034 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2024-11-28 04:16:35,035 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,036 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,038 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,041 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2024-11-28 04:16:35,043 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,060 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,060 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,060 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,061 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,061 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,061 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,061 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,066 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,077 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2024-11-28 04:16:35,078 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,078 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,084 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2024-11-28 04:16:35,089 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,106 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,106 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,107 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,107 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,107 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,107 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,108 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,110 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,121 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2024-11-28 04:16:35,122 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,122 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,125 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,129 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2024-11-28 04:16:35,130 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,147 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,148 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,148 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,148 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,148 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,150 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,150 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,153 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,166 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,166 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,166 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,169 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,174 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2024-11-28 04:16:35,175 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,192 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,192 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,193 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,193 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,193 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,193 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,194 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,197 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,208 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2024-11-28 04:16:35,209 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,213 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,215 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2024-11-28 04:16:35,217 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,235 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,235 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,235 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,235 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,236 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,236 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,236 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,238 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,249 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,250 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,250 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,253 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,258 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2024-11-28 04:16:35,259 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,276 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,276 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,277 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,277 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-28 04:16:35,277 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,278 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-28 04:16:35,279 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,281 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,292 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,295 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2024-11-28 04:16:35,301 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,316 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,317 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,317 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,317 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,317 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,317 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,317 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,319 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,326 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,327 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,329 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Waiting until timeout for monitored process [2024-11-28 04:16:35,332 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,346 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,346 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,346 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,346 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,346 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,347 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,347 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,348 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,355 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (52)] Ended with exit code 0 [2024-11-28 04:16:35,356 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,356 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,358 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,360 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Waiting until timeout for monitored process [2024-11-28 04:16:35,361 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,375 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,375 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,375 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,375 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,375 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,376 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,376 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,379 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,391 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (53)] Ended with exit code 0 [2024-11-28 04:16:35,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,392 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,394 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,397 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Waiting until timeout for monitored process [2024-11-28 04:16:35,399 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,417 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,417 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,417 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,417 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,417 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,418 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,418 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,419 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,427 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (54)] Ended with exit code 0 [2024-11-28 04:16:35,428 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,428 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,430 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,431 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Waiting until timeout for monitored process [2024-11-28 04:16:35,433 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,447 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,447 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,447 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,447 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,447 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,448 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,448 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,449 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,456 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (55)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,456 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,458 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Waiting until timeout for monitored process [2024-11-28 04:16:35,461 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,475 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,476 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,476 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,476 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,476 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,476 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,476 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,478 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,484 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (56)] Ended with exit code 0 [2024-11-28 04:16:35,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,487 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,489 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Waiting until timeout for monitored process [2024-11-28 04:16:35,490 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,504 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,504 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,504 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,504 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,504 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,505 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,505 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,507 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,514 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (57)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:35,514 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,514 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,517 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,519 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Waiting until timeout for monitored process [2024-11-28 04:16:35,520 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,533 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,533 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,533 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,534 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2024-11-28 04:16:35,534 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,534 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2024-11-28 04:16:35,535 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,537 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,543 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (58)] Ended with exit code 0 [2024-11-28 04:16:35,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,544 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,546 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Waiting until timeout for monitored process [2024-11-28 04:16:35,549 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,563 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,563 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,563 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,564 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,564 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,565 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,565 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,567 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,574 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (59)] Ended with exit code 0 [2024-11-28 04:16:35,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,577 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Waiting until timeout for monitored process [2024-11-28 04:16:35,581 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,595 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,595 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,595 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,595 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,595 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,596 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,596 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,598 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,605 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (60)] Ended with exit code 0 [2024-11-28 04:16:35,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,605 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,607 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,609 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Waiting until timeout for monitored process [2024-11-28 04:16:35,610 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,624 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,624 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,625 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,625 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,626 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-11-28 04:16:35,634 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (61)] Ended with exit code 0 [2024-11-28 04:16:35,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,634 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,636 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,637 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Waiting until timeout for monitored process [2024-11-28 04:16:35,639 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-11-28 04:16:35,653 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-11-28 04:16:35,653 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-11-28 04:16:35,653 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-11-28 04:16:35,653 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-11-28 04:16:35,653 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-11-28 04:16:35,654 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-11-28 04:16:35,654 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-11-28 04:16:35,657 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-11-28 04:16:35,661 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2024-11-28 04:16:35,665 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2024-11-28 04:16:35,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 04:16:35,667 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:35,670 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 04:16:35,672 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Waiting until timeout for monitored process [2024-11-28 04:16:35,672 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-11-28 04:16:35,673 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2024-11-28 04:16:35,673 INFO L474 LassoAnalysis]: Proved termination. [2024-11-28 04:16:35,673 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T2_E~0) = -2*~T2_E~0 + 3 Supporting invariants [] [2024-11-28 04:16:35,680 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (62)] Ended with exit code 0 [2024-11-28 04:16:35,683 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2024-11-28 04:16:35,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:35,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:35,777 INFO L256 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:35,779 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:36,007 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (63)] Ended with exit code 0 [2024-11-28 04:16:36,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:36,010 INFO L256 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 04:16:36,012 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:36,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-28 04:16:36,932 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2024-11-28 04:16:36,933 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1948 states and 2513 transitions. cyclomatic complexity: 567 Second operand has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:37,166 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1948 states and 2513 transitions. cyclomatic complexity: 567. Second operand has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 3831 states and 4956 transitions. Complement of second has 4 states. [2024-11-28 04:16:37,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2024-11-28 04:16:37,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 40.0) internal successors, (160), 4 states have internal predecessors, (160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:37,170 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 745 transitions. [2024-11-28 04:16:37,175 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 745 transitions. Stem has 73 letters. Loop has 87 letters. [2024-11-28 04:16:37,180 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-28 04:16:37,180 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 745 transitions. Stem has 160 letters. Loop has 87 letters. [2024-11-28 04:16:37,181 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-28 04:16:37,182 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 745 transitions. Stem has 73 letters. Loop has 174 letters. [2024-11-28 04:16:37,185 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-11-28 04:16:37,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3831 states and 4956 transitions. [2024-11-28 04:16:37,219 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1857 [2024-11-28 04:16:37,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3831 states to 3831 states and 4956 transitions. [2024-11-28 04:16:37,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1949 [2024-11-28 04:16:37,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1960 [2024-11-28 04:16:37,256 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3831 states and 4956 transitions. [2024-11-28 04:16:37,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-11-28 04:16:37,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3831 states and 4956 transitions. [2024-11-28 04:16:37,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3831 states and 4956 transitions. [2024-11-28 04:16:37,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3831 to 3820. [2024-11-28 04:16:37,330 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3820 states, 3820 states have (on average 1.294502617801047) internal successors, (4945), 3819 states have internal predecessors, (4945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:37,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3820 states to 3820 states and 4945 transitions. [2024-11-28 04:16:37,348 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3820 states and 4945 transitions. [2024-11-28 04:16:37,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:37,349 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 04:16:37,350 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 04:16:37,350 INFO L87 Difference]: Start difference. First operand 3820 states and 4945 transitions. Second operand has 4 states, 4 states have (on average 74.5) internal successors, (298), 4 states have internal predecessors, (298), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:37,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:37,481 INFO L93 Difference]: Finished difference Result 3992 states and 5101 transitions. [2024-11-28 04:16:37,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3992 states and 5101 transitions. [2024-11-28 04:16:37,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1948 [2024-11-28 04:16:37,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3992 states to 2040 states and 2606 transitions. [2024-11-28 04:16:37,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2040 [2024-11-28 04:16:37,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2040 [2024-11-28 04:16:37,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2040 states and 2606 transitions. [2024-11-28 04:16:37,529 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:37,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2040 states and 2606 transitions. [2024-11-28 04:16:37,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2040 states and 2606 transitions. [2024-11-28 04:16:37,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2040 to 1948. [2024-11-28 04:16:37,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1948 states, 1948 states have (on average 1.2797741273100616) internal successors, (2493), 1947 states have internal predecessors, (2493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:37,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1948 states to 1948 states and 2493 transitions. [2024-11-28 04:16:37,575 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1948 states and 2493 transitions. [2024-11-28 04:16:37,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 04:16:37,576 INFO L425 stractBuchiCegarLoop]: Abstraction has 1948 states and 2493 transitions. [2024-11-28 04:16:37,576 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-28 04:16:37,577 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1948 states and 2493 transitions. [2024-11-28 04:16:37,587 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1857 [2024-11-28 04:16:37,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:37,587 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:37,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:37,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:37,590 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 04:16:37,591 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet4#1;" "assume 0 == ~m_pc~0;" "havoc master_#t~nondet4#1;~token~0 := master_#t~nondet4#1;havoc master_#t~nondet4#1;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;" "assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2;" "havoc master_#t~nondet4#1;assume { :end_inline_master } true;" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume !(0 == ~T4_E~0);" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_M~0;~E_M~0 := 1;" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~T2_E~0);" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume !(1 == ~T4_E~0);" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_M~0;~E_M~0 := 2;" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 04:16:37,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:37,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 8 times [2024-11-28 04:16:37,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:37,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745284066] [2024-11-28 04:16:37,592 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:37,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:37,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:37,618 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:37,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:37,644 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:37,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:37,645 INFO L85 PathProgramCache]: Analyzing trace with hash 577154564, now seen corresponding path program 1 times [2024-11-28 04:16:37,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:37,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133560684] [2024-11-28 04:16:37,646 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:37,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:37,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:37,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:37,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133560684] [2024-11-28 04:16:37,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133560684] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:37,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1150007763] [2024-11-28 04:16:37,754 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:37,754 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:37,754 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:37,758 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:37,761 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2024-11-28 04:16:37,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:37,894 INFO L256 TraceCheckSpWp]: Trace formula consists of 286 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 04:16:37,897 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:37,916 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:37,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1150007763] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:37,936 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:37,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:37,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1282612109] [2024-11-28 04:16:37,937 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:37,938 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 04:16:37,938 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:37,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:37,939 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:37,939 INFO L87 Difference]: Start difference. First operand 1948 states and 2493 transitions. cyclomatic complexity: 547 Second operand has 3 states, 3 states have (on average 46.666666666666664) internal successors, (140), 3 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:38,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:38,024 INFO L93 Difference]: Finished difference Result 2582 states and 3271 transitions. [2024-11-28 04:16:38,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2582 states and 3271 transitions. [2024-11-28 04:16:38,042 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2488 [2024-11-28 04:16:38,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2582 states to 2582 states and 3271 transitions. [2024-11-28 04:16:38,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2582 [2024-11-28 04:16:38,065 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2582 [2024-11-28 04:16:38,065 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2582 states and 3271 transitions. [2024-11-28 04:16:38,070 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:38,070 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2582 states and 3271 transitions. [2024-11-28 04:16:38,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2582 states and 3271 transitions. [2024-11-28 04:16:38,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2582 to 2483. [2024-11-28 04:16:38,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2483 states, 2483 states have (on average 1.2690293999194522) internal successors, (3151), 2482 states have internal predecessors, (3151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:38,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2483 states to 2483 states and 3151 transitions. [2024-11-28 04:16:38,129 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2483 states and 3151 transitions. [2024-11-28 04:16:38,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:38,130 INFO L425 stractBuchiCegarLoop]: Abstraction has 2483 states and 3151 transitions. [2024-11-28 04:16:38,130 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-28 04:16:38,130 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2483 states and 3151 transitions. [2024-11-28 04:16:38,143 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2389 [2024-11-28 04:16:38,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:38,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:38,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:38,145 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:38,145 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:38,145 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:38,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:38,146 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 1 times [2024-11-28 04:16:38,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:38,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [774366421] [2024-11-28 04:16:38,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:38,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:38,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:38,160 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:38,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:38,183 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:38,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:38,183 INFO L85 PathProgramCache]: Analyzing trace with hash 641355441, now seen corresponding path program 1 times [2024-11-28 04:16:38,184 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:38,184 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [13395095] [2024-11-28 04:16:38,184 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:38,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:38,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:38,191 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:38,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:38,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:38,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:38,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1628724285, now seen corresponding path program 1 times [2024-11-28 04:16:38,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:38,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160245119] [2024-11-28 04:16:38,201 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:38,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:38,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:38,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:38,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160245119] [2024-11-28 04:16:38,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160245119] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:38,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [900654408] [2024-11-28 04:16:38,261 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:38,262 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:38,262 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:38,264 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:38,267 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2024-11-28 04:16:38,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:38,374 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:38,377 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:38,535 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:38,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [900654408] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:38,699 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:38,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:38,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840681472] [2024-11-28 04:16:38,700 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:38,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:38,784 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:38,784 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:38,784 INFO L87 Difference]: Start difference. First operand 2483 states and 3151 transitions. cyclomatic complexity: 672 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:38,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:38,847 INFO L93 Difference]: Finished difference Result 4286 states and 5412 transitions. [2024-11-28 04:16:38,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4286 states and 5412 transitions. [2024-11-28 04:16:38,877 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4104 [2024-11-28 04:16:38,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4286 states to 4286 states and 5412 transitions. [2024-11-28 04:16:38,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4286 [2024-11-28 04:16:38,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4286 [2024-11-28 04:16:38,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4286 states and 5412 transitions. [2024-11-28 04:16:38,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:38,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4286 states and 5412 transitions. [2024-11-28 04:16:38,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4286 states and 5412 transitions. [2024-11-28 04:16:38,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4286 to 4286. [2024-11-28 04:16:38,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4286 states, 4286 states have (on average 1.2627158189454037) internal successors, (5412), 4285 states have internal predecessors, (5412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:39,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4286 states to 4286 states and 5412 transitions. [2024-11-28 04:16:39,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4286 states and 5412 transitions. [2024-11-28 04:16:39,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:39,072 INFO L425 stractBuchiCegarLoop]: Abstraction has 4286 states and 5412 transitions. [2024-11-28 04:16:39,072 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-28 04:16:39,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4286 states and 5412 transitions. [2024-11-28 04:16:39,095 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4104 [2024-11-28 04:16:39,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:39,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:39,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:39,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:39,100 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:39,101 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:39,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:39,101 INFO L85 PathProgramCache]: Analyzing trace with hash 466810033, now seen corresponding path program 1 times [2024-11-28 04:16:39,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:39,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627941724] [2024-11-28 04:16:39,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:39,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:39,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:39,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627941724] [2024-11-28 04:16:39,137 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627941724] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:39,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1779442812] [2024-11-28 04:16:39,137 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,138 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:39,138 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:39,142 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:39,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2024-11-28 04:16:39,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:39,245 INFO L256 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:39,246 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:39,257 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:39,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1779442812] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:39,269 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:39,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:39,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592722882] [2024-11-28 04:16:39,269 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:39,269 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 04:16:39,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:39,270 INFO L85 PathProgramCache]: Analyzing trace with hash 641355441, now seen corresponding path program 2 times [2024-11-28 04:16:39,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:39,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208797200] [2024-11-28 04:16:39,270 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:39,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,277 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:39,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,282 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:39,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:39,348 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:39,348 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:39,349 INFO L87 Difference]: Start difference. First operand 4286 states and 5412 transitions. cyclomatic complexity: 1130 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:39,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:39,379 INFO L93 Difference]: Finished difference Result 4208 states and 5313 transitions. [2024-11-28 04:16:39,379 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4208 states and 5313 transitions. [2024-11-28 04:16:39,407 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4104 [2024-11-28 04:16:39,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4208 states to 4208 states and 5313 transitions. [2024-11-28 04:16:39,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4208 [2024-11-28 04:16:39,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4208 [2024-11-28 04:16:39,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4208 states and 5313 transitions. [2024-11-28 04:16:39,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:39,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4208 states and 5313 transitions. [2024-11-28 04:16:39,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4208 states and 5313 transitions. [2024-11-28 04:16:39,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4208 to 4208. [2024-11-28 04:16:39,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4208 states, 4208 states have (on average 1.2625950570342206) internal successors, (5313), 4207 states have internal predecessors, (5313), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:39,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4208 states to 4208 states and 5313 transitions. [2024-11-28 04:16:39,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4208 states and 5313 transitions. [2024-11-28 04:16:39,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:39,535 INFO L425 stractBuchiCegarLoop]: Abstraction has 4208 states and 5313 transitions. [2024-11-28 04:16:39,536 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-28 04:16:39,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4208 states and 5313 transitions. [2024-11-28 04:16:39,558 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4104 [2024-11-28 04:16:39,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:39,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:39,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:39,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:39,560 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:39,560 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:39,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:39,561 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 2 times [2024-11-28 04:16:39,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:39,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [795317238] [2024-11-28 04:16:39,561 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:39,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,574 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:39,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:39,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:39,594 INFO L85 PathProgramCache]: Analyzing trace with hash -737709789, now seen corresponding path program 1 times [2024-11-28 04:16:39,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:39,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51193350] [2024-11-28 04:16:39,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:39,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,598 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:39,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:39,603 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:39,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:39,604 INFO L85 PathProgramCache]: Analyzing trace with hash -440940107, now seen corresponding path program 1 times [2024-11-28 04:16:39,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:39,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232755625] [2024-11-28 04:16:39,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:39,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:39,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:39,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232755625] [2024-11-28 04:16:39,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232755625] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:39,672 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2093552178] [2024-11-28 04:16:39,672 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:39,672 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:39,672 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:39,677 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:39,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2024-11-28 04:16:39,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:39,786 INFO L256 TraceCheckSpWp]: Trace formula consists of 237 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:39,788 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:39,944 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:40,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2093552178] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:40,112 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:40,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:40,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1089839290] [2024-11-28 04:16:40,112 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:40,199 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:40,199 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:40,199 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:40,199 INFO L87 Difference]: Start difference. First operand 4208 states and 5313 transitions. cyclomatic complexity: 1109 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:40,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:40,313 INFO L93 Difference]: Finished difference Result 5370 states and 6753 transitions. [2024-11-28 04:16:40,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5370 states and 6753 transitions. [2024-11-28 04:16:40,352 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5262 [2024-11-28 04:16:40,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5370 states to 5370 states and 6753 transitions. [2024-11-28 04:16:40,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5370 [2024-11-28 04:16:40,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5370 [2024-11-28 04:16:40,388 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5370 states and 6753 transitions. [2024-11-28 04:16:40,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:40,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5370 states and 6753 transitions. [2024-11-28 04:16:40,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5370 states and 6753 transitions. [2024-11-28 04:16:40,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5370 to 5370. [2024-11-28 04:16:40,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5370 states, 5370 states have (on average 1.2575418994413408) internal successors, (6753), 5369 states have internal predecessors, (6753), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:40,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5370 states to 5370 states and 6753 transitions. [2024-11-28 04:16:40,498 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5370 states and 6753 transitions. [2024-11-28 04:16:40,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:40,499 INFO L425 stractBuchiCegarLoop]: Abstraction has 5370 states and 6753 transitions. [2024-11-28 04:16:40,499 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-28 04:16:40,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5370 states and 6753 transitions. [2024-11-28 04:16:40,529 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5262 [2024-11-28 04:16:40,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:40,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:40,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:40,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:40,531 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:40,531 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:40,531 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:40,531 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 3 times [2024-11-28 04:16:40,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:40,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956209172] [2024-11-28 04:16:40,532 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:40,532 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:40,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:40,545 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:40,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:40,568 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:40,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:40,569 INFO L85 PathProgramCache]: Analyzing trace with hash -1194283087, now seen corresponding path program 1 times [2024-11-28 04:16:40,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:40,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646570749] [2024-11-28 04:16:40,570 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:40,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:40,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:40,574 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:40,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:40,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:40,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:40,579 INFO L85 PathProgramCache]: Analyzing trace with hash 533539779, now seen corresponding path program 1 times [2024-11-28 04:16:40,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:40,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956783186] [2024-11-28 04:16:40,580 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:40,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:40,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:40,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:40,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956783186] [2024-11-28 04:16:40,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956783186] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:40,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1526994331] [2024-11-28 04:16:40,640 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:40,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:40,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:40,645 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:40,647 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2024-11-28 04:16:40,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:40,754 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:40,756 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:40,919 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:41,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1526994331] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:41,087 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:41,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:41,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494526731] [2024-11-28 04:16:41,087 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:41,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:41,184 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:41,184 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:41,184 INFO L87 Difference]: Start difference. First operand 5370 states and 6753 transitions. cyclomatic complexity: 1387 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:41,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:41,298 INFO L93 Difference]: Finished difference Result 9921 states and 12446 transitions. [2024-11-28 04:16:41,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9921 states and 12446 transitions. [2024-11-28 04:16:41,392 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9789 [2024-11-28 04:16:41,433 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9921 states to 9921 states and 12446 transitions. [2024-11-28 04:16:41,433 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9921 [2024-11-28 04:16:41,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9921 [2024-11-28 04:16:41,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9921 states and 12446 transitions. [2024-11-28 04:16:41,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:41,460 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9921 states and 12446 transitions. [2024-11-28 04:16:41,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9921 states and 12446 transitions. [2024-11-28 04:16:41,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9921 to 9507. [2024-11-28 04:16:41,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9507 states, 9507 states have (on average 1.2542337225202482) internal successors, (11924), 9506 states have internal predecessors, (11924), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:41,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9507 states to 9507 states and 11924 transitions. [2024-11-28 04:16:41,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9507 states and 11924 transitions. [2024-11-28 04:16:41,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:41,628 INFO L425 stractBuchiCegarLoop]: Abstraction has 9507 states and 11924 transitions. [2024-11-28 04:16:41,628 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-28 04:16:41,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9507 states and 11924 transitions. [2024-11-28 04:16:41,661 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9375 [2024-11-28 04:16:41,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:41,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:41,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:41,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:41,663 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:41,663 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:41,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:41,664 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 4 times [2024-11-28 04:16:41,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:41,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583521663] [2024-11-28 04:16:41,664 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:41,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:41,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:41,677 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:41,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:41,695 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:41,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:41,696 INFO L85 PathProgramCache]: Analyzing trace with hash -1118105949, now seen corresponding path program 1 times [2024-11-28 04:16:41,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:41,696 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705476070] [2024-11-28 04:16:41,696 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:41,696 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:41,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:41,701 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:41,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:41,705 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:41,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:41,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1462292021, now seen corresponding path program 1 times [2024-11-28 04:16:41,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:41,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90672842] [2024-11-28 04:16:41,707 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:41,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:41,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:41,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:41,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [90672842] [2024-11-28 04:16:41,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [90672842] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:41,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [781860070] [2024-11-28 04:16:41,763 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:41,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:41,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:41,767 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:41,770 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2024-11-28 04:16:41,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:41,874 INFO L256 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:41,876 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:42,038 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:42,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [781860070] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:42,216 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:42,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 04:16:42,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572176429] [2024-11-28 04:16:42,217 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:42,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:42,321 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:42,321 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:42,321 INFO L87 Difference]: Start difference. First operand 9507 states and 11924 transitions. cyclomatic complexity: 2421 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:42,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:42,485 INFO L93 Difference]: Finished difference Result 16046 states and 20087 transitions. [2024-11-28 04:16:42,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16046 states and 20087 transitions. [2024-11-28 04:16:42,579 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15866 [2024-11-28 04:16:42,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16046 states to 16046 states and 20087 transitions. [2024-11-28 04:16:42,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16046 [2024-11-28 04:16:42,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16046 [2024-11-28 04:16:42,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16046 states and 20087 transitions. [2024-11-28 04:16:42,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:42,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16046 states and 20087 transitions. [2024-11-28 04:16:42,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16046 states and 20087 transitions. [2024-11-28 04:16:42,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16046 to 16046. [2024-11-28 04:16:42,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16046 states, 16046 states have (on average 1.2518384644148075) internal successors, (20087), 16045 states have internal predecessors, (20087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:43,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16046 states to 16046 states and 20087 transitions. [2024-11-28 04:16:43,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16046 states and 20087 transitions. [2024-11-28 04:16:43,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:43,032 INFO L425 stractBuchiCegarLoop]: Abstraction has 16046 states and 20087 transitions. [2024-11-28 04:16:43,032 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-28 04:16:43,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16046 states and 20087 transitions. [2024-11-28 04:16:43,088 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 15866 [2024-11-28 04:16:43,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:43,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:43,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:43,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:43,090 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:43,090 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume !(0 == ~t5_st~0);" [2024-11-28 04:16:43,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:43,091 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 5 times [2024-11-28 04:16:43,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:43,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582482033] [2024-11-28 04:16:43,091 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:43,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:43,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:43,104 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:43,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:43,123 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:43,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:43,124 INFO L85 PathProgramCache]: Analyzing trace with hash -763371343, now seen corresponding path program 1 times [2024-11-28 04:16:43,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:43,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2058090049] [2024-11-28 04:16:43,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:43,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:43,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:43,130 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:43,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:43,135 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:43,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:43,136 INFO L85 PathProgramCache]: Analyzing trace with hash 802948035, now seen corresponding path program 1 times [2024-11-28 04:16:43,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:43,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370647725] [2024-11-28 04:16:43,136 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:43,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:43,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:43,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 04:16:43,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370647725] [2024-11-28 04:16:43,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370647725] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 04:16:43,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1808612903] [2024-11-28 04:16:43,261 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:43,261 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 04:16:43,261 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 04:16:43,265 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 04:16:43,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2024-11-28 04:16:43,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 04:16:43,381 INFO L256 TraceCheckSpWp]: Trace formula consists of 249 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 04:16:43,383 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 04:16:43,558 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 04:16:43,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1808612903] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 04:16:43,741 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 04:16:43,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-28 04:16:43,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [653225462] [2024-11-28 04:16:43,741 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 04:16:43,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 04:16:43,844 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 04:16:43,844 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 04:16:43,844 INFO L87 Difference]: Start difference. First operand 16046 states and 20087 transitions. cyclomatic complexity: 4045 Second operand has 3 states, 2 states have (on average 47.5) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:44,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 04:16:44,002 INFO L93 Difference]: Finished difference Result 28022 states and 34989 transitions. [2024-11-28 04:16:44,002 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28022 states and 34989 transitions. [2024-11-28 04:16:44,137 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27746 [2024-11-28 04:16:44,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28022 states to 28022 states and 34989 transitions. [2024-11-28 04:16:44,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28022 [2024-11-28 04:16:44,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28022 [2024-11-28 04:16:44,279 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28022 states and 34989 transitions. [2024-11-28 04:16:44,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 04:16:44,442 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28022 states and 34989 transitions. [2024-11-28 04:16:44,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28022 states and 34989 transitions. [2024-11-28 04:16:44,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28022 to 27290. [2024-11-28 04:16:44,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27290 states, 27290 states have (on average 1.2552949798460975) internal successors, (34257), 27289 states have internal predecessors, (34257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 04:16:44,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27290 states to 27290 states and 34257 transitions. [2024-11-28 04:16:44,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27290 states and 34257 transitions. [2024-11-28 04:16:44,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 04:16:44,976 INFO L425 stractBuchiCegarLoop]: Abstraction has 27290 states and 34257 transitions. [2024-11-28 04:16:44,976 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-28 04:16:44,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27290 states and 34257 transitions. [2024-11-28 04:16:45,073 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 27014 [2024-11-28 04:16:45,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 04:16:45,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 04:16:45,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:45,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 04:16:45,157 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_M~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_M~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 04:16:45,158 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp_ndt_6~0#1);" "havoc eval_~tmp_ndt_6~0#1;" [2024-11-28 04:16:45,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:45,159 INFO L85 PathProgramCache]: Analyzing trace with hash 959436207, now seen corresponding path program 6 times [2024-11-28 04:16:45,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:45,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617698058] [2024-11-28 04:16:45,159 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:45,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:45,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,191 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:45,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:45,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:45,238 INFO L85 PathProgramCache]: Analyzing trace with hash 839425059, now seen corresponding path program 1 times [2024-11-28 04:16:45,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:45,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2137967332] [2024-11-28 04:16:45,238 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:45,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:45,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,248 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:45,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:45,263 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 04:16:45,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1461173579, now seen corresponding path program 1 times [2024-11-28 04:16:45,263 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 04:16:45,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206886525] [2024-11-28 04:16:45,263 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 04:16:45,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 04:16:45,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,293 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:45,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:45,352 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 04:16:47,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:47,409 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 04:16:47,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 04:16:47,723 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 04:16:47 BoogieIcfgContainer [2024-11-28 04:16:47,723 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-28 04:16:47,724 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-28 04:16:47,724 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-28 04:16:47,725 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-28 04:16:47,726 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 04:16:17" (3/4) ... [2024-11-28 04:16:47,728 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-28 04:16:47,896 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/witness.graphml [2024-11-28 04:16:47,896 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-28 04:16:47,897 INFO L158 Benchmark]: Toolchain (without parser) took 33094.73ms. Allocated memory was 117.4MB in the beginning and 645.9MB in the end (delta: 528.5MB). Free memory was 92.5MB in the beginning and 322.2MB in the end (delta: -229.7MB). Peak memory consumption was 297.0MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,898 INFO L158 Benchmark]: CDTParser took 1.20ms. Allocated memory is still 117.4MB. Free memory is still 74.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 04:16:47,898 INFO L158 Benchmark]: CACSL2BoogieTranslator took 549.40ms. Allocated memory is still 117.4MB. Free memory was 92.3MB in the beginning and 76.5MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,898 INFO L158 Benchmark]: Boogie Procedure Inliner took 126.99ms. Allocated memory is still 117.4MB. Free memory was 76.5MB in the beginning and 71.8MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 04:16:47,899 INFO L158 Benchmark]: Boogie Preprocessor took 159.63ms. Allocated memory is still 117.4MB. Free memory was 71.7MB in the beginning and 66.0MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,899 INFO L158 Benchmark]: RCFGBuilder took 2105.32ms. Allocated memory is still 117.4MB. Free memory was 65.8MB in the beginning and 42.6MB in the end (delta: 23.2MB). Peak memory consumption was 32.4MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,899 INFO L158 Benchmark]: BuchiAutomizer took 29974.22ms. Allocated memory was 117.4MB in the beginning and 645.9MB in the end (delta: 528.5MB). Free memory was 42.6MB in the beginning and 336.6MB in the end (delta: -294.0MB). Peak memory consumption was 231.0MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,900 INFO L158 Benchmark]: Witness Printer took 172.50ms. Allocated memory is still 645.9MB. Free memory was 336.6MB in the beginning and 322.2MB in the end (delta: 14.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-28 04:16:47,905 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.20ms. Allocated memory is still 117.4MB. Free memory is still 74.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 549.40ms. Allocated memory is still 117.4MB. Free memory was 92.3MB in the beginning and 76.5MB in the end (delta: 15.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 126.99ms. Allocated memory is still 117.4MB. Free memory was 76.5MB in the beginning and 71.8MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 159.63ms. Allocated memory is still 117.4MB. Free memory was 71.7MB in the beginning and 66.0MB in the end (delta: 5.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2105.32ms. Allocated memory is still 117.4MB. Free memory was 65.8MB in the beginning and 42.6MB in the end (delta: 23.2MB). Peak memory consumption was 32.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 29974.22ms. Allocated memory was 117.4MB in the beginning and 645.9MB in the end (delta: 528.5MB). Free memory was 42.6MB in the beginning and 336.6MB in the end (delta: -294.0MB). Peak memory consumption was 231.0MB. Max. memory is 16.1GB. * Witness Printer took 172.50ms. Allocated memory is still 645.9MB. Free memory was 336.6MB in the beginning and 322.2MB in the end (delta: 14.3MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (21 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (3 + ((long long) -2 * T2_E)) and consists of 3 locations. 21 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 27290 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 29.6s and 22 iterations. TraceHistogramMax:2. Analysis of lassos took 20.5s. Construction of modules took 1.7s. Büchi inclusion checks took 6.5s. Highest rank in rank-based complementation 3. Minimization of det autom 21. Minimization of nondet autom 1. Automata minimization 2.0s AutomataMinimizationTime, 22 MinimizatonAttempts, 2274 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 1.1s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 18089 SdHoareTripleChecker+Valid, 2.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 18088 mSDsluCounter, 40263 SdHoareTripleChecker+Invalid, 1.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 22716 mSDsCounter, 388 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1562 IncrementalHoareTripleChecker+Invalid, 1950 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 388 mSolverCounterUnsat, 17547 mSDtfsCounter, 1562 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc5 concLT1 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital136 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 33ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 8 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.3s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE !(\read(tmp_ndt_1)) [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE !(\read(tmp_ndt_2)) [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE !(\read(tmp_ndt_3)) [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE !(\read(tmp_ndt_4)) [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE !(\read(tmp_ndt_5)) [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-28 04:16:47,932 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Ended with exit code 0 [2024-11-28 04:16:48,131 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Ended with exit code 0 [2024-11-28 04:16:48,327 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Ended with exit code 0 [2024-11-28 04:16:48,528 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:48,728 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Ended with exit code 0 [2024-11-28 04:16:48,928 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Ended with exit code 0 [2024-11-28 04:16:49,128 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Ended with exit code 0 [2024-11-28 04:16:49,328 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:49,528 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:49,729 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:49,929 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:50,130 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:50,329 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-11-28 04:16:50,530 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:50,730 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-28 04:16:50,930 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-11-28 04:16:51,130 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-28 04:16:51,331 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:51,531 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:51,732 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:51,931 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-28 04:16:52,132 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-28 04:16:52,332 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:52,532 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:52,732 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:52,932 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:53,133 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:53,333 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-28 04:16:53,534 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a6803939-e252-4536-8e9f-4961567812ff/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)