./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 03:51:08,495 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 03:51:08,576 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-28 03:51:08,582 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 03:51:08,582 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 03:51:08,605 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 03:51:08,606 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 03:51:08,606 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 03:51:08,607 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 03:51:08,607 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 03:51:08,607 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 03:51:08,607 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 03:51:08,607 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 03:51:08,608 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-28 03:51:08,608 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-28 03:51:08,608 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-28 03:51:08,608 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-28 03:51:08,608 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-28 03:51:08,608 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-28 03:51:08,609 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 03:51:08,609 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-28 03:51:08,609 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-28 03:51:08,609 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-28 03:51:08,609 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-28 03:51:08,609 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 03:51:08,610 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 03:51:08,611 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 03:51:08,611 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:51:08,611 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 03:51:08,611 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL_NO_AM [2024-11-28 03:51:08,611 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-28 03:51:08,611 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2024-11-28 03:51:08,898 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 03:51:08,907 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 03:51:08,909 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 03:51:08,911 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 03:51:08,911 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 03:51:08,912 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/systemc/transmitter.01.cil.c [2024-11-28 03:51:11,779 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/data/131288d49/be6ca048bb62485a81547cf510b0300d/FLAG97479b636 [2024-11-28 03:51:12,125 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 03:51:12,126 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/sv-benchmarks/c/systemc/transmitter.01.cil.c [2024-11-28 03:51:12,149 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/data/131288d49/be6ca048bb62485a81547cf510b0300d/FLAG97479b636 [2024-11-28 03:51:12,199 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/data/131288d49/be6ca048bb62485a81547cf510b0300d [2024-11-28 03:51:12,202 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 03:51:12,209 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 03:51:12,211 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 03:51:12,211 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 03:51:12,219 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 03:51:12,220 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,224 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@fb85f9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12, skipping insertion in model container [2024-11-28 03:51:12,224 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,263 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 03:51:12,557 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:51:12,576 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 03:51:12,617 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:51:12,644 INFO L204 MainTranslator]: Completed translation [2024-11-28 03:51:12,645 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12 WrapperNode [2024-11-28 03:51:12,645 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 03:51:12,647 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 03:51:12,647 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 03:51:12,647 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 03:51:12,655 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,664 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,694 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 356 [2024-11-28 03:51:12,694 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 03:51:12,695 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 03:51:12,695 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 03:51:12,695 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 03:51:12,706 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,706 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,709 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,723 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-28 03:51:12,723 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,724 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,730 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,731 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,739 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,741 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,742 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,746 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 03:51:12,747 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 03:51:12,747 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 03:51:12,747 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 03:51:12,749 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (1/1) ... [2024-11-28 03:51:12,757 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-28 03:51:12,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:12,812 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-28 03:51:12,821 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-28 03:51:12,854 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 03:51:12,854 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-28 03:51:12,855 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 03:51:12,855 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 03:51:12,966 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 03:51:12,969 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 03:51:13,649 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2024-11-28 03:51:13,649 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 03:51:13,665 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 03:51:13,665 INFO L312 CfgBuilder]: Removed 10 assume(true) statements. [2024-11-28 03:51:13,666 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:51:13 BoogieIcfgContainer [2024-11-28 03:51:13,666 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 03:51:13,667 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-28 03:51:13,667 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-28 03:51:13,675 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-28 03:51:13,676 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 03:51:13,676 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 03:51:12" (1/3) ... [2024-11-28 03:51:13,678 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e833cb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:51:13, skipping insertion in model container [2024-11-28 03:51:13,678 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 03:51:13,678 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:51:12" (2/3) ... [2024-11-28 03:51:13,679 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@e833cb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 03:51:13, skipping insertion in model container [2024-11-28 03:51:13,679 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-28 03:51:13,679 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:51:13" (3/3) ... [2024-11-28 03:51:13,680 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2024-11-28 03:51:13,745 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-28 03:51:13,746 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-28 03:51:13,746 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-28 03:51:13,746 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-28 03:51:13,746 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-28 03:51:13,746 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-28 03:51:13,746 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-28 03:51:13,747 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-28 03:51:13,753 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.5307692307692307) internal successors, (199), 130 states have internal predecessors, (199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:13,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2024-11-28 03:51:13,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:13,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:13,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:13,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:13,787 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-28 03:51:13,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 131 states, 130 states have (on average 1.5307692307692307) internal successors, (199), 130 states have internal predecessors, (199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:13,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2024-11-28 03:51:13,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:13,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:13,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:13,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:13,805 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:13,805 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:13,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:13,812 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2024-11-28 03:51:13,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:13,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939070561] [2024-11-28 03:51:13,822 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:13,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:13,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:14,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:14,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939070561] [2024-11-28 03:51:14,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939070561] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:14,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1315057187] [2024-11-28 03:51:14,057 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:14,057 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:14,057 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:14,067 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:14,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 03:51:14,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:14,170 INFO L256 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:51:14,204 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:14,317 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:14,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1315057187] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:14,422 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:14,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4 [2024-11-28 03:51:14,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692902476] [2024-11-28 03:51:14,429 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:14,440 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 03:51:14,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:14,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1553712566, now seen corresponding path program 1 times [2024-11-28 03:51:14,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:14,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197274045] [2024-11-28 03:51:14,441 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:14,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:14,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:14,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:14,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197274045] [2024-11-28 03:51:14,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [197274045] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:14,491 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [447840223] [2024-11-28 03:51:14,491 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:14,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:14,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:14,494 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:14,498 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 03:51:14,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:14,601 INFO L256 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 03:51:14,603 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:14,612 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:14,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [447840223] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:14,631 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:14,631 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2 [2024-11-28 03:51:14,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972538915] [2024-11-28 03:51:14,632 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:14,633 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:14,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:14,678 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:51:14,679 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:51:14,681 INFO L87 Difference]: Start difference. First operand has 131 states, 130 states have (on average 1.5307692307692307) internal successors, (199), 130 states have internal predecessors, (199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 11.5) internal successors, (46), 4 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:14,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:14,775 INFO L93 Difference]: Finished difference Result 129 states and 177 transitions. [2024-11-28 03:51:14,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 129 states and 177 transitions. [2024-11-28 03:51:14,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2024-11-28 03:51:14,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 129 states to 123 states and 171 transitions. [2024-11-28 03:51:14,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2024-11-28 03:51:14,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2024-11-28 03:51:14,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 171 transitions. [2024-11-28 03:51:14,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:14,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 171 transitions. [2024-11-28 03:51:14,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 171 transitions. [2024-11-28 03:51:14,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 123. [2024-11-28 03:51:14,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.3902439024390243) internal successors, (171), 122 states have internal predecessors, (171), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:14,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 171 transitions. [2024-11-28 03:51:14,831 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123 states and 171 transitions. [2024-11-28 03:51:14,832 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:51:14,836 INFO L425 stractBuchiCegarLoop]: Abstraction has 123 states and 171 transitions. [2024-11-28 03:51:14,837 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-28 03:51:14,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 171 transitions. [2024-11-28 03:51:14,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2024-11-28 03:51:14,840 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:14,840 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:14,841 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:14,841 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:14,841 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:14,842 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:14,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:14,843 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2024-11-28 03:51:14,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:14,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961759225] [2024-11-28 03:51:14,844 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:14,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:14,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:14,863 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:14,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:14,900 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:14,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:14,901 INFO L85 PathProgramCache]: Analyzing trace with hash -888579142, now seen corresponding path program 1 times [2024-11-28 03:51:14,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:14,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477633935] [2024-11-28 03:51:14,901 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:14,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:14,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,034 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:15,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477633935] [2024-11-28 03:51:15,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477633935] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:15,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [916613586] [2024-11-28 03:51:15,035 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,035 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:15,036 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:15,045 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:15,050 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 03:51:15,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,144 INFO L256 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 03:51:15,146 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:15,198 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:15,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [916613586] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:15,253 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:15,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 03:51:15,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108705417] [2024-11-28 03:51:15,253 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:15,254 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:15,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:15,254 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:51:15,255 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:51:15,255 INFO L87 Difference]: Start difference. First operand 123 states and 171 transitions. cyclomatic complexity: 49 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:15,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:15,342 INFO L93 Difference]: Finished difference Result 198 states and 269 transitions. [2024-11-28 03:51:15,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 269 transitions. [2024-11-28 03:51:15,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2024-11-28 03:51:15,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 269 transitions. [2024-11-28 03:51:15,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 198 [2024-11-28 03:51:15,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2024-11-28 03:51:15,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 269 transitions. [2024-11-28 03:51:15,350 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:15,351 INFO L218 hiAutomatonCegarLoop]: Abstraction has 198 states and 269 transitions. [2024-11-28 03:51:15,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 269 transitions. [2024-11-28 03:51:15,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2024-11-28 03:51:15,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 198 states, 198 states have (on average 1.3585858585858586) internal successors, (269), 197 states have internal predecessors, (269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:15,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 269 transitions. [2024-11-28 03:51:15,364 INFO L240 hiAutomatonCegarLoop]: Abstraction has 198 states and 269 transitions. [2024-11-28 03:51:15,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:51:15,365 INFO L425 stractBuchiCegarLoop]: Abstraction has 198 states and 269 transitions. [2024-11-28 03:51:15,366 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-28 03:51:15,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 198 states and 269 transitions. [2024-11-28 03:51:15,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2024-11-28 03:51:15,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:15,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:15,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:15,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:15,371 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:15,371 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:15,372 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:15,372 INFO L85 PathProgramCache]: Analyzing trace with hash -87065268, now seen corresponding path program 1 times [2024-11-28 03:51:15,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:15,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734118880] [2024-11-28 03:51:15,372 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:15,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,432 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:15,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734118880] [2024-11-28 03:51:15,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734118880] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:15,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1350173924] [2024-11-28 03:51:15,433 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,433 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:15,434 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:15,438 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:15,444 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 03:51:15,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,530 INFO L256 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:51:15,531 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:15,557 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:15,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1350173924] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:15,594 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:15,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 3 [2024-11-28 03:51:15,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [873635227] [2024-11-28 03:51:15,595 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:15,595 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 03:51:15,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:15,596 INFO L85 PathProgramCache]: Analyzing trace with hash -613819528, now seen corresponding path program 1 times [2024-11-28 03:51:15,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:15,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959162837] [2024-11-28 03:51:15,596 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:15,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,713 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:15,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1959162837] [2024-11-28 03:51:15,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1959162837] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:15,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1444864066] [2024-11-28 03:51:15,713 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,714 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:15,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:15,718 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:15,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 03:51:15,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:15,788 INFO L256 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:51:15,790 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:15,822 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:15,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1444864066] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:15,882 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:15,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 03:51:15,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259983547] [2024-11-28 03:51:15,882 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:15,883 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:15,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:15,884 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:51:15,884 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:51:15,884 INFO L87 Difference]: Start difference. First operand 198 states and 269 transitions. cyclomatic complexity: 72 Second operand has 4 states, 4 states have (on average 8.75) internal successors, (35), 3 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:15,947 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:15,950 INFO L93 Difference]: Finished difference Result 123 states and 162 transitions. [2024-11-28 03:51:15,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 162 transitions. [2024-11-28 03:51:15,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2024-11-28 03:51:15,953 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 162 transitions. [2024-11-28 03:51:15,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2024-11-28 03:51:15,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2024-11-28 03:51:15,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 162 transitions. [2024-11-28 03:51:15,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:15,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123 states and 162 transitions. [2024-11-28 03:51:15,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 162 transitions. [2024-11-28 03:51:15,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 123. [2024-11-28 03:51:15,973 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123 states, 123 states have (on average 1.3170731707317074) internal successors, (162), 122 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:15,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 162 transitions. [2024-11-28 03:51:15,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123 states and 162 transitions. [2024-11-28 03:51:15,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:51:15,976 INFO L425 stractBuchiCegarLoop]: Abstraction has 123 states and 162 transitions. [2024-11-28 03:51:15,978 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-28 03:51:15,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123 states and 162 transitions. [2024-11-28 03:51:15,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2024-11-28 03:51:15,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:15,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:15,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:15,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:15,982 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:15,982 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:15,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:15,983 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2024-11-28 03:51:15,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:15,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593317365] [2024-11-28 03:51:15,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:15,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,004 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:16,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:16,029 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:16,030 INFO L85 PathProgramCache]: Analyzing trace with hash -613819528, now seen corresponding path program 2 times [2024-11-28 03:51:16,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:16,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577287478] [2024-11-28 03:51:16,030 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,030 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:16,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:16,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577287478] [2024-11-28 03:51:16,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577287478] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:16,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1626360692] [2024-11-28 03:51:16,186 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,186 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:16,187 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:16,191 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:16,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 03:51:16,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:16,262 INFO L256 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:51:16,264 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:16,280 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:16,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1626360692] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:16,315 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:16,316 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5 [2024-11-28 03:51:16,316 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621338171] [2024-11-28 03:51:16,316 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:16,317 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:16,317 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:16,317 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 03:51:16,317 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:51:16,318 INFO L87 Difference]: Start difference. First operand 123 states and 162 transitions. cyclomatic complexity: 40 Second operand has 5 states, 5 states have (on average 8.0) internal successors, (40), 5 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:16,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:16,401 INFO L93 Difference]: Finished difference Result 130 states and 169 transitions. [2024-11-28 03:51:16,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 169 transitions. [2024-11-28 03:51:16,407 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 101 [2024-11-28 03:51:16,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 130 states and 169 transitions. [2024-11-28 03:51:16,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 130 [2024-11-28 03:51:16,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 130 [2024-11-28 03:51:16,412 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 169 transitions. [2024-11-28 03:51:16,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:16,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 169 transitions. [2024-11-28 03:51:16,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 169 transitions. [2024-11-28 03:51:16,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 126. [2024-11-28 03:51:16,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126 states, 126 states have (on average 1.3095238095238095) internal successors, (165), 125 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:16,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 165 transitions. [2024-11-28 03:51:16,429 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126 states and 165 transitions. [2024-11-28 03:51:16,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:51:16,431 INFO L425 stractBuchiCegarLoop]: Abstraction has 126 states and 165 transitions. [2024-11-28 03:51:16,434 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-28 03:51:16,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126 states and 165 transitions. [2024-11-28 03:51:16,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2024-11-28 03:51:16,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:16,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:16,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:16,441 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:16,442 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:16,442 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:16,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:16,442 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2024-11-28 03:51:16,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:16,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203870213] [2024-11-28 03:51:16,443 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,458 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:16,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,470 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:16,471 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:16,471 INFO L85 PathProgramCache]: Analyzing trace with hash -1256786305, now seen corresponding path program 1 times [2024-11-28 03:51:16,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:16,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328480341] [2024-11-28 03:51:16,472 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:16,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:16,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328480341] [2024-11-28 03:51:16,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328480341] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:16,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1945026744] [2024-11-28 03:51:16,531 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,531 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:16,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:16,536 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:16,541 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 03:51:16,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:16,605 INFO L256 TraceCheckSpWp]: Trace formula consists of 81 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 03:51:16,607 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:16,687 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:16,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1945026744] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:16,763 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:16,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 03:51:16,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218692979] [2024-11-28 03:51:16,767 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:16,768 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:16,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:16,768 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:51:16,768 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:51:16,769 INFO L87 Difference]: Start difference. First operand 126 states and 165 transitions. cyclomatic complexity: 40 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:16,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:16,832 INFO L93 Difference]: Finished difference Result 194 states and 249 transitions. [2024-11-28 03:51:16,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 194 states and 249 transitions. [2024-11-28 03:51:16,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 165 [2024-11-28 03:51:16,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 194 states to 194 states and 249 transitions. [2024-11-28 03:51:16,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 194 [2024-11-28 03:51:16,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194 [2024-11-28 03:51:16,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 194 states and 249 transitions. [2024-11-28 03:51:16,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:16,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 194 states and 249 transitions. [2024-11-28 03:51:16,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states and 249 transitions. [2024-11-28 03:51:16,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 184. [2024-11-28 03:51:16,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184 states, 184 states have (on average 1.2826086956521738) internal successors, (236), 183 states have internal predecessors, (236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:16,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 236 transitions. [2024-11-28 03:51:16,854 INFO L240 hiAutomatonCegarLoop]: Abstraction has 184 states and 236 transitions. [2024-11-28 03:51:16,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:51:16,855 INFO L425 stractBuchiCegarLoop]: Abstraction has 184 states and 236 transitions. [2024-11-28 03:51:16,855 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-28 03:51:16,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184 states and 236 transitions. [2024-11-28 03:51:16,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 155 [2024-11-28 03:51:16,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:16,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:16,859 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:16,859 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:16,859 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:16,860 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:16,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:16,860 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2024-11-28 03:51:16,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:16,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140908394] [2024-11-28 03:51:16,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,873 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:16,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:16,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:16,894 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:16,894 INFO L85 PathProgramCache]: Analyzing trace with hash -1122772799, now seen corresponding path program 1 times [2024-11-28 03:51:16,895 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:16,895 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1848822593] [2024-11-28 03:51:16,895 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:16,895 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:16,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:17,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:17,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1848822593] [2024-11-28 03:51:17,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1848822593] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:17,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [965476600] [2024-11-28 03:51:17,045 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,045 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:17,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:17,052 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:17,055 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 03:51:17,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:17,144 INFO L256 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-11-28 03:51:17,146 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:17,200 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:17,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [965476600] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:17,220 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:17,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8 [2024-11-28 03:51:17,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [757303783] [2024-11-28 03:51:17,221 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:17,223 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:17,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:17,224 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:51:17,224 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:51:17,224 INFO L87 Difference]: Start difference. First operand 184 states and 236 transitions. cyclomatic complexity: 53 Second operand has 8 states, 8 states have (on average 6.375) internal successors, (51), 8 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:17,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:17,456 INFO L93 Difference]: Finished difference Result 167 states and 205 transitions. [2024-11-28 03:51:17,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 205 transitions. [2024-11-28 03:51:17,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 138 [2024-11-28 03:51:17,460 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 167 states and 205 transitions. [2024-11-28 03:51:17,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 167 [2024-11-28 03:51:17,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 167 [2024-11-28 03:51:17,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 167 states and 205 transitions. [2024-11-28 03:51:17,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:17,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 167 states and 205 transitions. [2024-11-28 03:51:17,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states and 205 transitions. [2024-11-28 03:51:17,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2024-11-28 03:51:17,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 167 states, 167 states have (on average 1.2275449101796407) internal successors, (205), 166 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:17,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 205 transitions. [2024-11-28 03:51:17,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 167 states and 205 transitions. [2024-11-28 03:51:17,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 03:51:17,479 INFO L425 stractBuchiCegarLoop]: Abstraction has 167 states and 205 transitions. [2024-11-28 03:51:17,479 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-28 03:51:17,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 167 states and 205 transitions. [2024-11-28 03:51:17,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 138 [2024-11-28 03:51:17,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:17,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:17,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:17,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:17,487 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:17,487 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1;" "assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_time_events } true;" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:17,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:17,488 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2024-11-28 03:51:17,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:17,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1953617787] [2024-11-28 03:51:17,489 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:17,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:17,505 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:17,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:17,525 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:17,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:17,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1890938358, now seen corresponding path program 1 times [2024-11-28 03:51:17,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:17,529 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [701419803] [2024-11-28 03:51:17,529 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,530 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:17,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:17,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:17,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [701419803] [2024-11-28 03:51:17,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [701419803] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:17,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [831502351] [2024-11-28 03:51:17,592 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:17,592 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:17,595 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:17,602 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 03:51:17,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:17,675 INFO L256 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:51:17,677 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:17,746 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:17,811 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [831502351] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:17,811 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:17,811 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 4 [2024-11-28 03:51:17,811 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1479720181] [2024-11-28 03:51:17,812 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:17,812 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:17,812 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:17,812 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:51:17,813 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:51:17,813 INFO L87 Difference]: Start difference. First operand 167 states and 205 transitions. cyclomatic complexity: 39 Second operand has 4 states, 4 states have (on average 26.25) internal successors, (105), 4 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:17,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:17,886 INFO L93 Difference]: Finished difference Result 231 states and 272 transitions. [2024-11-28 03:51:17,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 231 states and 272 transitions. [2024-11-28 03:51:17,890 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2024-11-28 03:51:17,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 231 states to 231 states and 272 transitions. [2024-11-28 03:51:17,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2024-11-28 03:51:17,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2024-11-28 03:51:17,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 231 states and 272 transitions. [2024-11-28 03:51:17,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:17,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 231 states and 272 transitions. [2024-11-28 03:51:17,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 231 states and 272 transitions. [2024-11-28 03:51:17,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 231 to 231. [2024-11-28 03:51:17,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 231 states, 231 states have (on average 1.1774891774891776) internal successors, (272), 230 states have internal predecessors, (272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:17,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 272 transitions. [2024-11-28 03:51:17,913 INFO L240 hiAutomatonCegarLoop]: Abstraction has 231 states and 272 transitions. [2024-11-28 03:51:17,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:51:17,914 INFO L425 stractBuchiCegarLoop]: Abstraction has 231 states and 272 transitions. [2024-11-28 03:51:17,914 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-28 03:51:17,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 231 states and 272 transitions. [2024-11-28 03:51:17,916 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2024-11-28 03:51:17,918 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:17,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:17,920 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:17,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:17,924 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2024-11-28 03:51:17,925 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1;" "assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_time_events } true;" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2024-11-28 03:51:17,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:17,925 INFO L85 PathProgramCache]: Analyzing trace with hash -685799418, now seen corresponding path program 1 times [2024-11-28 03:51:17,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:17,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349689754] [2024-11-28 03:51:17,925 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:17,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:17,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:17,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349689754] [2024-11-28 03:51:17,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349689754] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:17,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [351346244] [2024-11-28 03:51:17,950 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:17,950 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:17,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:17,957 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:17,958 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 03:51:18,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:18,011 INFO L256 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 03:51:18,013 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:18,023 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:18,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [351346244] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:18,035 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:18,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 03:51:18,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [368848987] [2024-11-28 03:51:18,035 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:18,035 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-11-28 03:51:18,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:18,036 INFO L85 PathProgramCache]: Analyzing trace with hash 108424338, now seen corresponding path program 1 times [2024-11-28 03:51:18,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:18,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [157491102] [2024-11-28 03:51:18,036 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:18,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:18,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:18,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-11-28 03:51:18,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [157491102] [2024-11-28 03:51:18,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [157491102] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:51:18,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1742258604] [2024-11-28 03:51:18,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:18,124 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:51:18,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:51:18,129 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:51:18,131 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-28 03:51:18,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:51:18,203 INFO L256 TraceCheckSpWp]: Trace formula consists of 111 conjuncts, 3 conjuncts are in the unsatisfiable core [2024-11-28 03:51:18,205 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:51:18,285 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:51:18,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1742258604] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:51:18,350 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:51:18,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3 [2024-11-28 03:51:18,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499769196] [2024-11-28 03:51:18,352 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:51:18,353 INFO L764 eck$LassoCheckResult]: loop already infeasible [2024-11-28 03:51:18,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-11-28 03:51:18,354 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:51:18,354 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:51:18,354 INFO L87 Difference]: Start difference. First operand 231 states and 272 transitions. cyclomatic complexity: 43 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:18,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:51:18,364 INFO L93 Difference]: Finished difference Result 208 states and 246 transitions. [2024-11-28 03:51:18,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 246 transitions. [2024-11-28 03:51:18,369 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2024-11-28 03:51:18,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 208 states and 246 transitions. [2024-11-28 03:51:18,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 208 [2024-11-28 03:51:18,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 208 [2024-11-28 03:51:18,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208 states and 246 transitions. [2024-11-28 03:51:18,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-28 03:51:18,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 208 states and 246 transitions. [2024-11-28 03:51:18,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states and 246 transitions. [2024-11-28 03:51:18,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 208. [2024-11-28 03:51:18,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 208 states, 208 states have (on average 1.1826923076923077) internal successors, (246), 207 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-28 03:51:18,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 246 transitions. [2024-11-28 03:51:18,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 208 states and 246 transitions. [2024-11-28 03:51:18,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:51:18,384 INFO L425 stractBuchiCegarLoop]: Abstraction has 208 states and 246 transitions. [2024-11-28 03:51:18,388 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-28 03:51:18,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 208 states and 246 transitions. [2024-11-28 03:51:18,390 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 154 [2024-11-28 03:51:18,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-28 03:51:18,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-28 03:51:18,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:18,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:51:18,391 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2024-11-28 03:51:18,391 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" [2024-11-28 03:51:18,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:18,392 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492972, now seen corresponding path program 1 times [2024-11-28 03:51:18,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:18,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019066584] [2024-11-28 03:51:18,392 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:18,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:18,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,406 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:18,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:18,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:18,427 INFO L85 PathProgramCache]: Analyzing trace with hash 30645579, now seen corresponding path program 1 times [2024-11-28 03:51:18,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:18,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760900348] [2024-11-28 03:51:18,428 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:18,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:18,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,434 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:18,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,440 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:18,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:51:18,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1334250944, now seen corresponding path program 1 times [2024-11-28 03:51:18,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-11-28 03:51:18,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789708531] [2024-11-28 03:51:18,441 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:51:18,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:51:18,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,457 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:18,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:18,474 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-11-28 03:51:19,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:19,120 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:51:19,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:51:19,249 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 28.11 03:51:19 BoogieIcfgContainer [2024-11-28 03:51:19,249 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-28 03:51:19,249 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-28 03:51:19,250 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-28 03:51:19,250 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-28 03:51:19,258 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:51:13" (3/4) ... [2024-11-28 03:51:19,260 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-28 03:51:19,345 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/witness.graphml [2024-11-28 03:51:19,345 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-28 03:51:19,346 INFO L158 Benchmark]: Toolchain (without parser) took 7136.85ms. Allocated memory was 142.6MB in the beginning and 419.4MB in the end (delta: 276.8MB). Free memory was 119.4MB in the beginning and 191.5MB in the end (delta: -72.1MB). Peak memory consumption was 199.7MB. Max. memory is 16.1GB. [2024-11-28 03:51:19,346 INFO L158 Benchmark]: CDTParser took 0.39ms. Allocated memory is still 142.6MB. Free memory is still 80.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:51:19,347 INFO L158 Benchmark]: CACSL2BoogieTranslator took 435.08ms. Allocated memory is still 142.6MB. Free memory was 119.4MB in the beginning and 106.5MB in the end (delta: 12.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:51:19,347 INFO L158 Benchmark]: Boogie Procedure Inliner took 47.77ms. Allocated memory is still 142.6MB. Free memory was 106.5MB in the beginning and 104.6MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:51:19,348 INFO L158 Benchmark]: Boogie Preprocessor took 51.18ms. Allocated memory is still 142.6MB. Free memory was 104.6MB in the beginning and 102.3MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:51:19,349 INFO L158 Benchmark]: RCFGBuilder took 919.28ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 81.1MB in the end (delta: 21.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-28 03:51:19,350 INFO L158 Benchmark]: BuchiAutomizer took 5581.82ms. Allocated memory was 142.6MB in the beginning and 419.4MB in the end (delta: 276.8MB). Free memory was 81.1MB in the beginning and 195.9MB in the end (delta: -114.8MB). Peak memory consumption was 166.1MB. Max. memory is 16.1GB. [2024-11-28 03:51:19,351 INFO L158 Benchmark]: Witness Printer took 95.46ms. Allocated memory is still 419.4MB. Free memory was 195.9MB in the beginning and 191.5MB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:51:19,353 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.39ms. Allocated memory is still 142.6MB. Free memory is still 80.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 435.08ms. Allocated memory is still 142.6MB. Free memory was 119.4MB in the beginning and 106.5MB in the end (delta: 12.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 47.77ms. Allocated memory is still 142.6MB. Free memory was 106.5MB in the beginning and 104.6MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 51.18ms. Allocated memory is still 142.6MB. Free memory was 104.6MB in the beginning and 102.3MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 919.28ms. Allocated memory is still 142.6MB. Free memory was 102.3MB in the beginning and 81.1MB in the end (delta: 21.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 5581.82ms. Allocated memory was 142.6MB in the beginning and 419.4MB in the end (delta: 276.8MB). Free memory was 81.1MB in the beginning and 195.9MB in the end (delta: -114.8MB). Peak memory consumption was 166.1MB. Max. memory is 16.1GB. * Witness Printer took 95.46ms. Allocated memory is still 419.4MB. Free memory was 195.9MB in the beginning and 191.5MB in the end (delta: 4.4MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 8 terminating modules (8 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.8 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 208 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.4s and 9 iterations. TraceHistogramMax:1. Analysis of lassos took 4.3s. Construction of modules took 0.4s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 8. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 8 MinimizatonAttempts, 14 StatesRemovedByMinimization, 2 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1228 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1228 mSDsluCounter, 2891 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1560 mSDsCounter, 83 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 316 IncrementalHoareTripleChecker+Invalid, 399 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 83 mSolverCounterUnsat, 1331 mSDtfsCounter, 316 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc0 concLT0 SILN0 SILU0 SILI3 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-28 03:51:19,375 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-28 03:51:19,574 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-28 03:51:19,774 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-28 03:51:19,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-28 03:51:20,174 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-28 03:51:20,374 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-28 03:51:20,575 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-28 03:51:20,775 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-28 03:51:20,975 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-28 03:51:21,174 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-28 03:51:21,375 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-28 03:51:21,576 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b809460c-8ce6-4522-9837-7a2cda65aa0f/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)