./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 02:54:56,207 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 02:54:56,276 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-11-28 02:54:56,281 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 02:54:56,282 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 02:54:56,309 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 02:54:56,310 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 02:54:56,310 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 02:54:56,311 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 02:54:56,311 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 02:54:56,312 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-28 02:54:56,312 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-28 02:54:56,312 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 02:54:56,312 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 02:54:56,312 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 02:54:56,313 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 02:54:56,314 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 02:54:56,315 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 02:54:56,316 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 02:54:56,316 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-28 02:54:56,316 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 02:54:56,316 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 02:54:56,316 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 02:54:56,316 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 02:54:56,317 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 02:54:56,317 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-28 02:54:56,317 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-28 02:54:56,318 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-28 02:54:56,318 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-28 02:54:56,318 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-28 02:54:56,318 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-28 02:54:56,318 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-11-28 02:54:56,667 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 02:54:56,681 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 02:54:56,683 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 02:54:56,685 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 02:54:56,685 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 02:54:56,688 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 02:54:59,834 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/54a4c2390/291d71bab4864a67add1d6b962adb16c/FLAGebae9c627 [2024-11-28 02:55:00,223 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 02:55:00,224 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 02:55:00,237 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/54a4c2390/291d71bab4864a67add1d6b962adb16c/FLAGebae9c627 [2024-11-28 02:55:00,259 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/54a4c2390/291d71bab4864a67add1d6b962adb16c [2024-11-28 02:55:00,262 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 02:55:00,263 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 02:55:00,265 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 02:55:00,265 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 02:55:00,270 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 02:55:00,271 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:55:00" (1/1) ... [2024-11-28 02:55:00,272 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ed8c462 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:00, skipping insertion in model container [2024-11-28 02:55:00,272 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 02:55:00" (1/1) ... [2024-11-28 02:55:00,327 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 02:55:00,523 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-28 02:55:00,831 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 02:55:00,841 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 02:55:00,851 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-28 02:55:01,016 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 02:55:01,031 INFO L204 MainTranslator]: Completed translation [2024-11-28 02:55:01,031 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01 WrapperNode [2024-11-28 02:55:01,032 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 02:55:01,033 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 02:55:01,033 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 02:55:01,033 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 02:55:01,047 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,092 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,503 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2370 [2024-11-28 02:55:01,504 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 02:55:01,505 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 02:55:01,505 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 02:55:01,505 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 02:55:01,515 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,515 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,556 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,655 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-11-28 02:55:01,656 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,659 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,735 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,747 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,830 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,847 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,863 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,908 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 02:55:01,910 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 02:55:01,911 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 02:55:01,911 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 02:55:01,912 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (1/1) ... [2024-11-28 02:55:01,920 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 02:55:01,933 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:01,948 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-28 02:55:01,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-28 02:55:01,982 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 02:55:01,983 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-28 02:55:01,983 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-28 02:55:01,983 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-28 02:55:01,983 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2024-11-28 02:55:01,983 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 02:55:01,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-11-28 02:55:01,984 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-11-28 02:55:01,985 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-11-28 02:55:01,985 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-28 02:55:02,320 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 02:55:02,323 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 02:55:05,926 INFO L? ?]: Removed 1283 outVars from TransFormulas that were not future-live. [2024-11-28 02:55:05,926 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 02:55:05,966 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 02:55:05,966 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-28 02:55:05,967 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:55:05 BoogieIcfgContainer [2024-11-28 02:55:05,967 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 02:55:05,973 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-28 02:55:05,973 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-28 02:55:05,980 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-28 02:55:05,980 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 02:55:00" (1/3) ... [2024-11-28 02:55:05,981 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@260abff8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 02:55:05, skipping insertion in model container [2024-11-28 02:55:05,982 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 02:55:01" (2/3) ... [2024-11-28 02:55:05,983 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@260abff8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 02:55:05, skipping insertion in model container [2024-11-28 02:55:05,983 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:55:05" (3/3) ... [2024-11-28 02:55:05,985 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 02:55:06,008 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-28 02:55:06,010 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 752 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-11-28 02:55:06,156 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-28 02:55:06,174 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@74f13362, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-28 02:55:06,174 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-28 02:55:06,184 INFO L276 IsEmpty]: Start isEmpty. Operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 02:55:06,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-11-28 02:55:06,215 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:06,216 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:06,217 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:06,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:06,226 INFO L85 PathProgramCache]: Analyzing trace with hash -1021292254, now seen corresponding path program 1 times [2024-11-28 02:55:06,235 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:06,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [725864898] [2024-11-28 02:55:06,236 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:06,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:06,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:06,966 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-28 02:55:06,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:06,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [725864898] [2024-11-28 02:55:06,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [725864898] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:06,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [980198122] [2024-11-28 02:55:06,972 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:06,972 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:06,972 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:06,978 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:06,982 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 02:55:07,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:07,609 INFO L256 TraceCheckSpWp]: Trace formula consists of 1101 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 02:55:07,626 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:07,672 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-28 02:55:07,675 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 02:55:07,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [980198122] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:07,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 02:55:07,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-28 02:55:07,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [334891299] [2024-11-28 02:55:07,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:07,684 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-28 02:55:07,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:07,712 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-28 02:55:07,713 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 02:55:07,717 INFO L87 Difference]: Start difference. First operand has 752 states, 744 states have (on average 1.4973118279569892) internal successors, (1114), 745 states have internal predecessors, (1114), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:07,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:07,805 INFO L93 Difference]: Finished difference Result 1493 states and 2239 transitions. [2024-11-28 02:55:07,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-28 02:55:07,811 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 241 [2024-11-28 02:55:07,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:07,828 INFO L225 Difference]: With dead ends: 1493 [2024-11-28 02:55:07,833 INFO L226 Difference]: Without dead ends: 749 [2024-11-28 02:55:07,845 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 242 GetRequests, 242 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 02:55:07,848 INFO L435 NwaCegarLoop]: 1113 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 1113 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:07,850 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 1113 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:07,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states. [2024-11-28 02:55:07,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 749. [2024-11-28 02:55:07,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 749 states, 742 states have (on average 1.486522911051213) internal successors, (1103), 742 states have internal predecessors, (1103), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 02:55:07,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 749 states to 749 states and 1113 transitions. [2024-11-28 02:55:07,971 INFO L78 Accepts]: Start accepts. Automaton has 749 states and 1113 transitions. Word has length 241 [2024-11-28 02:55:07,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:07,972 INFO L471 AbstractCegarLoop]: Abstraction has 749 states and 1113 transitions. [2024-11-28 02:55:07,973 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 110.5) internal successors, (221), 2 states have internal predecessors, (221), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:07,973 INFO L276 IsEmpty]: Start isEmpty. Operand 749 states and 1113 transitions. [2024-11-28 02:55:07,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 242 [2024-11-28 02:55:07,985 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:07,985 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:08,002 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-28 02:55:08,186 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-11-28 02:55:08,186 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:08,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:08,187 INFO L85 PathProgramCache]: Analyzing trace with hash 526745560, now seen corresponding path program 1 times [2024-11-28 02:55:08,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:08,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775109495] [2024-11-28 02:55:08,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:08,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:08,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:09,341 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 02:55:09,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:09,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775109495] [2024-11-28 02:55:09,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775109495] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:09,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:09,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 02:55:09,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570466084] [2024-11-28 02:55:09,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:09,343 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:55:09,344 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:09,349 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:55:09,349 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 02:55:09,349 INFO L87 Difference]: Start difference. First operand 749 states and 1113 transitions. Second operand has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:09,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:09,435 INFO L93 Difference]: Finished difference Result 1496 states and 2224 transitions. [2024-11-28 02:55:09,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:55:09,436 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 241 [2024-11-28 02:55:09,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:09,444 INFO L225 Difference]: With dead ends: 1496 [2024-11-28 02:55:09,444 INFO L226 Difference]: Without dead ends: 755 [2024-11-28 02:55:09,445 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 02:55:09,446 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1108 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2219 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:09,449 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2219 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:09,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 755 states. [2024-11-28 02:55:09,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 755 to 750. [2024-11-28 02:55:09,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 750 states, 743 states have (on average 1.4858681022880216) internal successors, (1104), 743 states have internal predecessors, (1104), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 02:55:09,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 750 states to 750 states and 1114 transitions. [2024-11-28 02:55:09,499 INFO L78 Accepts]: Start accepts. Automaton has 750 states and 1114 transitions. Word has length 241 [2024-11-28 02:55:09,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:09,501 INFO L471 AbstractCegarLoop]: Abstraction has 750 states and 1114 transitions. [2024-11-28 02:55:09,501 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 73.0) internal successors, (219), 3 states have internal predecessors, (219), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:09,502 INFO L276 IsEmpty]: Start isEmpty. Operand 750 states and 1114 transitions. [2024-11-28 02:55:09,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2024-11-28 02:55:09,506 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:09,507 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:09,507 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-11-28 02:55:09,507 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:09,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:09,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1295801430, now seen corresponding path program 1 times [2024-11-28 02:55:09,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:09,509 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115134767] [2024-11-28 02:55:09,509 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:09,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:09,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:10,443 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 02:55:10,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:10,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115134767] [2024-11-28 02:55:10,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115134767] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:10,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1977340068] [2024-11-28 02:55:10,444 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:10,444 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:10,444 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:10,447 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:10,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 02:55:11,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:11,132 INFO L256 TraceCheckSpWp]: Trace formula consists of 1112 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-28 02:55:11,142 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:11,199 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 02:55:11,199 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:55:11,302 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 02:55:11,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1977340068] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:11,303 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:55:11,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 6 [2024-11-28 02:55:11,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763629120] [2024-11-28 02:55:11,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:11,304 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:55:11,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:11,307 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:55:11,307 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:11,308 INFO L87 Difference]: Start difference. First operand 750 states and 1114 transitions. Second operand has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:11,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:11,369 INFO L93 Difference]: Finished difference Result 1469 states and 2184 transitions. [2024-11-28 02:55:11,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:55:11,370 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 245 [2024-11-28 02:55:11,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:11,374 INFO L225 Difference]: With dead ends: 1469 [2024-11-28 02:55:11,374 INFO L226 Difference]: Without dead ends: 751 [2024-11-28 02:55:11,376 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 492 GetRequests, 488 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:11,379 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 7 mSDsluCounter, 1101 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 2212 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:11,380 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 2212 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:11,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 751 states. [2024-11-28 02:55:11,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 751 to 751. [2024-11-28 02:55:11,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 751 states, 744 states have (on average 1.4852150537634408) internal successors, (1105), 744 states have internal predecessors, (1105), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 02:55:11,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 751 states to 751 states and 1115 transitions. [2024-11-28 02:55:11,419 INFO L78 Accepts]: Start accepts. Automaton has 751 states and 1115 transitions. Word has length 245 [2024-11-28 02:55:11,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:11,420 INFO L471 AbstractCegarLoop]: Abstraction has 751 states and 1115 transitions. [2024-11-28 02:55:11,420 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 74.33333333333333) internal successors, (223), 3 states have internal predecessors, (223), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:11,420 INFO L276 IsEmpty]: Start isEmpty. Operand 751 states and 1115 transitions. [2024-11-28 02:55:11,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 250 [2024-11-28 02:55:11,425 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:11,426 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:11,439 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-28 02:55:11,630 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:11,630 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:11,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:11,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1377415492, now seen corresponding path program 1 times [2024-11-28 02:55:11,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:11,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124301616] [2024-11-28 02:55:11,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:11,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:11,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:12,383 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 02:55:12,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:12,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124301616] [2024-11-28 02:55:12,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124301616] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:12,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [458933781] [2024-11-28 02:55:12,385 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:12,385 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:12,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:12,392 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:12,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 02:55:13,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:13,156 INFO L256 TraceCheckSpWp]: Trace formula consists of 1123 conjuncts, 16 conjuncts are in the unsatisfiable core [2024-11-28 02:55:13,164 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:13,237 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 02:55:13,237 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:55:14,649 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 02:55:14,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [458933781] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:55:14,649 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:55:14,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 8] total 12 [2024-11-28 02:55:14,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220891049] [2024-11-28 02:55:14,650 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:55:14,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-28 02:55:14,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:14,653 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-28 02:55:14,653 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2024-11-28 02:55:14,653 INFO L87 Difference]: Start difference. First operand 751 states and 1115 transitions. Second operand has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:55:17,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:17,315 INFO L93 Difference]: Finished difference Result 2117 states and 3148 transitions. [2024-11-28 02:55:17,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-28 02:55:17,316 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 249 [2024-11-28 02:55:17,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:17,323 INFO L225 Difference]: With dead ends: 2117 [2024-11-28 02:55:17,323 INFO L226 Difference]: Without dead ends: 1375 [2024-11-28 02:55:17,326 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 501 GetRequests, 490 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=103, Unknown=0, NotChecked=0, Total=156 [2024-11-28 02:55:17,327 INFO L435 NwaCegarLoop]: 1385 mSDtfsCounter, 2019 mSDsluCounter, 6303 mSDsCounter, 0 mSdLazyCounter, 2637 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2024 SdHoareTripleChecker+Valid, 7688 SdHoareTripleChecker+Invalid, 2638 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2637 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:17,329 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2024 Valid, 7688 Invalid, 2638 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1 Valid, 2637 Invalid, 0 Unknown, 0 Unchecked, 2.4s Time] [2024-11-28 02:55:17,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1375 states. [2024-11-28 02:55:17,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1375 to 986. [2024-11-28 02:55:17,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 986 states, 974 states have (on average 1.482546201232033) internal successors, (1444), 974 states have internal predecessors, (1444), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:17,390 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 986 states to 986 states and 1464 transitions. [2024-11-28 02:55:17,390 INFO L78 Accepts]: Start accepts. Automaton has 986 states and 1464 transitions. Word has length 249 [2024-11-28 02:55:17,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:17,391 INFO L471 AbstractCegarLoop]: Abstraction has 986 states and 1464 transitions. [2024-11-28 02:55:17,391 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 30.666666666666668) internal successors, (368), 12 states have internal predecessors, (368), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:55:17,391 INFO L276 IsEmpty]: Start isEmpty. Operand 986 states and 1464 transitions. [2024-11-28 02:55:17,395 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2024-11-28 02:55:17,395 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:17,395 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:17,408 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-11-28 02:55:17,600 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:17,601 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:17,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:17,601 INFO L85 PathProgramCache]: Analyzing trace with hash 1657948098, now seen corresponding path program 1 times [2024-11-28 02:55:17,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:17,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875329278] [2024-11-28 02:55:17,602 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:17,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:17,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:18,281 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 02:55:18,281 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:18,281 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875329278] [2024-11-28 02:55:18,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875329278] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:18,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1577213588] [2024-11-28 02:55:18,282 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:18,282 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:18,282 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:18,284 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:18,289 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 02:55:18,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:18,860 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-28 02:55:18,868 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:18,931 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 02:55:18,935 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:55:19,013 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2024-11-28 02:55:19,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1577213588] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:55:19,013 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:55:19,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 6, 4] total 9 [2024-11-28 02:55:19,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579649352] [2024-11-28 02:55:19,014 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:55:19,016 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 02:55:19,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:19,017 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 02:55:19,018 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:55:19,018 INFO L87 Difference]: Start difference. First operand 986 states and 1464 transitions. Second operand has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:19,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:19,171 INFO L93 Difference]: Finished difference Result 2004 states and 2978 transitions. [2024-11-28 02:55:19,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-28 02:55:19,172 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 254 [2024-11-28 02:55:19,173 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:19,177 INFO L225 Difference]: With dead ends: 2004 [2024-11-28 02:55:19,177 INFO L226 Difference]: Without dead ends: 1033 [2024-11-28 02:55:19,178 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 512 GetRequests, 504 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:55:19,180 INFO L435 NwaCegarLoop]: 1121 mSDtfsCounter, 52 mSDsluCounter, 5563 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 52 SdHoareTripleChecker+Valid, 6684 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:19,181 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [52 Valid, 6684 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:55:19,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1033 states. [2024-11-28 02:55:19,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1033 to 1028. [2024-11-28 02:55:19,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1028 states, 1016 states have (on average 1.4763779527559056) internal successors, (1500), 1016 states have internal predecessors, (1500), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:19,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1028 states to 1028 states and 1520 transitions. [2024-11-28 02:55:19,224 INFO L78 Accepts]: Start accepts. Automaton has 1028 states and 1520 transitions. Word has length 254 [2024-11-28 02:55:19,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:19,225 INFO L471 AbstractCegarLoop]: Abstraction has 1028 states and 1520 transitions. [2024-11-28 02:55:19,225 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 29.22222222222222) internal successors, (263), 9 states have internal predecessors, (263), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:19,225 INFO L276 IsEmpty]: Start isEmpty. Operand 1028 states and 1520 transitions. [2024-11-28 02:55:19,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 271 [2024-11-28 02:55:19,230 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:19,230 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:19,245 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-28 02:55:19,431 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:19,431 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:19,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:19,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1935099494, now seen corresponding path program 2 times [2024-11-28 02:55:19,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:19,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1937022101] [2024-11-28 02:55:19,433 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:55:19,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:19,552 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:55:19,553 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:55:20,137 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 83 trivial. 0 not checked. [2024-11-28 02:55:20,137 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:20,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1937022101] [2024-11-28 02:55:20,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1937022101] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:20,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:20,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:55:20,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922587391] [2024-11-28 02:55:20,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:20,139 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:20,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:20,140 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:20,140 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:20,140 INFO L87 Difference]: Start difference. First operand 1028 states and 1520 transitions. Second operand has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:20,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:20,187 INFO L93 Difference]: Finished difference Result 1032 states and 1524 transitions. [2024-11-28 02:55:20,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:20,188 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 270 [2024-11-28 02:55:20,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:20,193 INFO L225 Difference]: With dead ends: 1032 [2024-11-28 02:55:20,193 INFO L226 Difference]: Without dead ends: 1030 [2024-11-28 02:55:20,194 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:20,195 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2216 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3327 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:20,195 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3327 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:20,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1030 states. [2024-11-28 02:55:20,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1030 to 1030. [2024-11-28 02:55:20,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1030 states, 1018 states have (on average 1.475442043222004) internal successors, (1502), 1018 states have internal predecessors, (1502), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:20,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1030 states to 1030 states and 1522 transitions. [2024-11-28 02:55:20,230 INFO L78 Accepts]: Start accepts. Automaton has 1030 states and 1522 transitions. Word has length 270 [2024-11-28 02:55:20,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:20,232 INFO L471 AbstractCegarLoop]: Abstraction has 1030 states and 1522 transitions. [2024-11-28 02:55:20,232 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.0) internal successors, (228), 4 states have internal predecessors, (228), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:20,233 INFO L276 IsEmpty]: Start isEmpty. Operand 1030 states and 1522 transitions. [2024-11-28 02:55:20,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 272 [2024-11-28 02:55:20,237 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:20,238 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:20,238 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-11-28 02:55:20,238 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:20,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:20,239 INFO L85 PathProgramCache]: Analyzing trace with hash -139761292, now seen corresponding path program 1 times [2024-11-28 02:55:20,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:20,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373650224] [2024-11-28 02:55:20,239 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:20,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:20,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:20,821 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-11-28 02:55:20,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:20,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373650224] [2024-11-28 02:55:20,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373650224] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:20,822 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1922419191] [2024-11-28 02:55:20,822 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:20,822 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:20,822 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:20,824 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:20,829 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 02:55:21,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:21,434 INFO L256 TraceCheckSpWp]: Trace formula consists of 1184 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-11-28 02:55:21,441 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:21,492 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 68 trivial. 0 not checked. [2024-11-28 02:55:21,492 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:55:21,729 INFO L134 CoverageAnalysis]: Checked inductivity of 83 backedges. 13 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 02:55:21,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1922419191] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:55:21,729 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:55:21,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 10] total 15 [2024-11-28 02:55:21,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1982843525] [2024-11-28 02:55:21,730 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:55:21,731 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-28 02:55:21,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:21,733 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-28 02:55:21,733 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=159, Unknown=0, NotChecked=0, Total=210 [2024-11-28 02:55:21,733 INFO L87 Difference]: Start difference. First operand 1030 states and 1522 transitions. Second operand has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:22,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:22,018 INFO L93 Difference]: Finished difference Result 2069 states and 3061 transitions. [2024-11-28 02:55:22,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 02:55:22,019 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 271 [2024-11-28 02:55:22,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:22,023 INFO L225 Difference]: With dead ends: 2069 [2024-11-28 02:55:22,024 INFO L226 Difference]: Without dead ends: 1060 [2024-11-28 02:55:22,025 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 549 GetRequests, 533 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=84, Invalid=222, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:55:22,028 INFO L435 NwaCegarLoop]: 1129 mSDtfsCounter, 86 mSDsluCounter, 11200 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 86 SdHoareTripleChecker+Valid, 12329 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:22,029 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [86 Valid, 12329 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:55:22,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1060 states. [2024-11-28 02:55:22,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1060 to 1060. [2024-11-28 02:55:22,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1060 states, 1048 states have (on average 1.4713740458015268) internal successors, (1542), 1048 states have internal predecessors, (1542), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:22,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1060 states to 1060 states and 1562 transitions. [2024-11-28 02:55:22,066 INFO L78 Accepts]: Start accepts. Automaton has 1060 states and 1562 transitions. Word has length 271 [2024-11-28 02:55:22,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:22,068 INFO L471 AbstractCegarLoop]: Abstraction has 1060 states and 1562 transitions. [2024-11-28 02:55:22,068 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 18.0) internal successors, (270), 15 states have internal predecessors, (270), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:22,068 INFO L276 IsEmpty]: Start isEmpty. Operand 1060 states and 1562 transitions. [2024-11-28 02:55:22,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 292 [2024-11-28 02:55:22,073 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:22,074 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:22,087 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-11-28 02:55:22,275 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable6 [2024-11-28 02:55:22,275 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:22,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:22,275 INFO L85 PathProgramCache]: Analyzing trace with hash 439580942, now seen corresponding path program 2 times [2024-11-28 02:55:22,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:22,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1923972093] [2024-11-28 02:55:22,276 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:55:22,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:22,380 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:55:22,381 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:55:22,721 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 188 trivial. 0 not checked. [2024-11-28 02:55:22,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:22,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1923972093] [2024-11-28 02:55:22,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1923972093] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:22,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:22,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:55:22,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2016051749] [2024-11-28 02:55:22,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:22,722 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:22,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:22,723 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:22,723 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:22,723 INFO L87 Difference]: Start difference. First operand 1060 states and 1562 transitions. Second operand has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:22,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:22,783 INFO L93 Difference]: Finished difference Result 1717 states and 2538 transitions. [2024-11-28 02:55:22,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:22,784 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 291 [2024-11-28 02:55:22,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:22,790 INFO L225 Difference]: With dead ends: 1717 [2024-11-28 02:55:22,790 INFO L226 Difference]: Without dead ends: 1062 [2024-11-28 02:55:22,791 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:22,792 INFO L435 NwaCegarLoop]: 1111 mSDtfsCounter, 0 mSDsluCounter, 2212 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3323 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:22,792 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3323 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:22,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1062 states. [2024-11-28 02:55:22,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1062 to 1062. [2024-11-28 02:55:22,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1062 states, 1050 states have (on average 1.4704761904761905) internal successors, (1544), 1050 states have internal predecessors, (1544), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:22,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1062 states to 1062 states and 1564 transitions. [2024-11-28 02:55:22,827 INFO L78 Accepts]: Start accepts. Automaton has 1062 states and 1564 transitions. Word has length 291 [2024-11-28 02:55:22,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:22,828 INFO L471 AbstractCegarLoop]: Abstraction has 1062 states and 1564 transitions. [2024-11-28 02:55:22,828 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.25) internal successors, (229), 4 states have internal predecessors, (229), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:22,829 INFO L276 IsEmpty]: Start isEmpty. Operand 1062 states and 1564 transitions. [2024-11-28 02:55:22,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2024-11-28 02:55:22,834 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:22,835 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:22,835 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-11-28 02:55:22,835 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:22,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:22,836 INFO L85 PathProgramCache]: Analyzing trace with hash -355857243, now seen corresponding path program 1 times [2024-11-28 02:55:22,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:22,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160961584] [2024-11-28 02:55:22,836 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:22,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:23,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:23,536 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-28 02:55:23,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:23,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160961584] [2024-11-28 02:55:23,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160961584] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:23,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [219691436] [2024-11-28 02:55:23,537 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:23,537 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:23,538 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:23,540 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:23,543 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 02:55:24,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:24,196 INFO L256 TraceCheckSpWp]: Trace formula consists of 1242 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-28 02:55:24,203 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:24,399 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 124 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2024-11-28 02:55:24,399 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:55:24,604 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-28 02:55:24,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [219691436] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:55:24,604 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:55:24,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-28 02:55:24,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299838135] [2024-11-28 02:55:24,605 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:55:24,606 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-28 02:55:24,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:24,607 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-28 02:55:24,607 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:55:24,608 INFO L87 Difference]: Start difference. First operand 1062 states and 1564 transitions. Second operand has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:24,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:24,965 INFO L93 Difference]: Finished difference Result 2053 states and 3038 transitions. [2024-11-28 02:55:24,965 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-28 02:55:24,965 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 292 [2024-11-28 02:55:24,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:24,971 INFO L225 Difference]: With dead ends: 2053 [2024-11-28 02:55:24,972 INFO L226 Difference]: Without dead ends: 1110 [2024-11-28 02:55:24,973 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 573 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:55:24,975 INFO L435 NwaCegarLoop]: 1157 mSDtfsCounter, 135 mSDsluCounter, 11475 mSDsCounter, 0 mSdLazyCounter, 232 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 135 SdHoareTripleChecker+Valid, 12632 SdHoareTripleChecker+Invalid, 233 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 232 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:24,976 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [135 Valid, 12632 Invalid, 233 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 232 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:24,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-28 02:55:25,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-28 02:55:25,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.46448087431694) internal successors, (1608), 1098 states have internal predecessors, (1608), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:25,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1628 transitions. [2024-11-28 02:55:25,026 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1628 transitions. Word has length 292 [2024-11-28 02:55:25,026 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:25,026 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1628 transitions. [2024-11-28 02:55:25,027 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 15.722222222222221) internal successors, (283), 18 states have internal predecessors, (283), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 02:55:25,027 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1628 transitions. [2024-11-28 02:55:25,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 309 [2024-11-28 02:55:25,034 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:25,034 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:25,048 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-28 02:55:25,238 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable8 [2024-11-28 02:55:25,238 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:25,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:25,240 INFO L85 PathProgramCache]: Analyzing trace with hash 1595157741, now seen corresponding path program 2 times [2024-11-28 02:55:25,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:25,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520754064] [2024-11-28 02:55:25,240 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:55:25,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:25,384 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:55:25,384 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:55:25,843 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:25,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:25,843 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520754064] [2024-11-28 02:55:25,843 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520754064] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:25,844 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:25,844 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:55:25,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1270785896] [2024-11-28 02:55:25,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:25,845 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:25,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:25,846 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:25,846 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:25,848 INFO L87 Difference]: Start difference. First operand 1110 states and 1628 transitions. Second operand has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:26,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:26,155 INFO L93 Difference]: Finished difference Result 1767 states and 2603 transitions. [2024-11-28 02:55:26,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:26,156 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 308 [2024-11-28 02:55:26,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:26,161 INFO L225 Difference]: With dead ends: 1767 [2024-11-28 02:55:26,161 INFO L226 Difference]: Without dead ends: 1110 [2024-11-28 02:55:26,163 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:55:26,164 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 955 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 955 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 204 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:26,164 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [955 Valid, 2026 Invalid, 204 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:26,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-28 02:55:26,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-28 02:55:26,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4635701275045538) internal successors, (1607), 1098 states have internal predecessors, (1607), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:26,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1627 transitions. [2024-11-28 02:55:26,209 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1627 transitions. Word has length 308 [2024-11-28 02:55:26,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:26,210 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1627 transitions. [2024-11-28 02:55:26,210 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 57.5) internal successors, (230), 4 states have internal predecessors, (230), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:26,211 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1627 transitions. [2024-11-28 02:55:26,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 310 [2024-11-28 02:55:26,216 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:26,216 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:26,216 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-11-28 02:55:26,216 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:26,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:26,217 INFO L85 PathProgramCache]: Analyzing trace with hash -663449310, now seen corresponding path program 1 times [2024-11-28 02:55:26,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:26,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979370486] [2024-11-28 02:55:26,217 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:26,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:26,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:26,881 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:26,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:26,881 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979370486] [2024-11-28 02:55:26,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979370486] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:26,881 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:26,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:55:26,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400080065] [2024-11-28 02:55:26,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:26,882 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:55:26,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:26,883 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:55:26,884 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:55:26,884 INFO L87 Difference]: Start difference. First operand 1110 states and 1627 transitions. Second operand has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:27,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:27,140 INFO L93 Difference]: Finished difference Result 1805 states and 2656 transitions. [2024-11-28 02:55:27,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 02:55:27,141 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 309 [2024-11-28 02:55:27,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:27,146 INFO L225 Difference]: With dead ends: 1805 [2024-11-28 02:55:27,146 INFO L226 Difference]: Without dead ends: 1110 [2024-11-28 02:55:27,148 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:27,148 INFO L435 NwaCegarLoop]: 1100 mSDtfsCounter, 1046 mSDsluCounter, 2118 mSDsCounter, 0 mSdLazyCounter, 123 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1046 SdHoareTripleChecker+Valid, 3218 SdHoareTripleChecker+Invalid, 124 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 123 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:27,148 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1046 Valid, 3218 Invalid, 124 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 123 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:27,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-28 02:55:27,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-28 02:55:27,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4617486338797814) internal successors, (1605), 1098 states have internal predecessors, (1605), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:27,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1625 transitions. [2024-11-28 02:55:27,192 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1625 transitions. Word has length 309 [2024-11-28 02:55:27,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:27,193 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1625 transitions. [2024-11-28 02:55:27,193 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.2) internal successors, (231), 5 states have internal predecessors, (231), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:27,194 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1625 transitions. [2024-11-28 02:55:27,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 311 [2024-11-28 02:55:27,199 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:27,200 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:27,200 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-11-28 02:55:27,200 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:27,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:27,201 INFO L85 PathProgramCache]: Analyzing trace with hash -280266578, now seen corresponding path program 1 times [2024-11-28 02:55:27,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:27,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159361678] [2024-11-28 02:55:27,201 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:27,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:27,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:28,189 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:28,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:28,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159361678] [2024-11-28 02:55:28,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159361678] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:28,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:28,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:55:28,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1254434490] [2024-11-28 02:55:28,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:28,191 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:55:28,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:28,192 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:55:28,192 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:55:28,192 INFO L87 Difference]: Start difference. First operand 1110 states and 1625 transitions. Second operand has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:28,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:28,532 INFO L93 Difference]: Finished difference Result 1773 states and 2606 transitions. [2024-11-28 02:55:28,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:28,533 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 310 [2024-11-28 02:55:28,534 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:28,538 INFO L225 Difference]: With dead ends: 1773 [2024-11-28 02:55:28,538 INFO L226 Difference]: Without dead ends: 1110 [2024-11-28 02:55:28,540 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:28,540 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 1090 mSDsluCounter, 1023 mSDsCounter, 0 mSdLazyCounter, 200 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1095 SdHoareTripleChecker+Valid, 2035 SdHoareTripleChecker+Invalid, 200 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 200 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:28,541 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1095 Valid, 2035 Invalid, 200 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 200 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 02:55:28,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-28 02:55:28,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-28 02:55:28,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.4599271402550091) internal successors, (1603), 1098 states have internal predecessors, (1603), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:28,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1623 transitions. [2024-11-28 02:55:28,581 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1623 transitions. Word has length 310 [2024-11-28 02:55:28,582 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:28,582 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1623 transitions. [2024-11-28 02:55:28,583 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 46.4) internal successors, (232), 5 states have internal predecessors, (232), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:28,583 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1623 transitions. [2024-11-28 02:55:28,586 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2024-11-28 02:55:28,586 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:28,587 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:28,587 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-11-28 02:55:28,587 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:28,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:28,588 INFO L85 PathProgramCache]: Analyzing trace with hash 260057573, now seen corresponding path program 1 times [2024-11-28 02:55:28,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:28,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664825702] [2024-11-28 02:55:28,588 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:28,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:28,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:29,599 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:29,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:29,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [664825702] [2024-11-28 02:55:29,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [664825702] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:29,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:29,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:55:29,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528407943] [2024-11-28 02:55:29,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:29,601 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:29,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:29,602 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:29,602 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:29,602 INFO L87 Difference]: Start difference. First operand 1110 states and 1623 transitions. Second operand has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:29,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:29,898 INFO L93 Difference]: Finished difference Result 1767 states and 2595 transitions. [2024-11-28 02:55:29,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:29,899 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 311 [2024-11-28 02:55:29,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:29,904 INFO L225 Difference]: With dead ends: 1767 [2024-11-28 02:55:29,904 INFO L226 Difference]: Without dead ends: 1110 [2024-11-28 02:55:29,906 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:55:29,907 INFO L435 NwaCegarLoop]: 1012 mSDtfsCounter, 949 mSDsluCounter, 1014 mSDsCounter, 0 mSdLazyCounter, 198 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 949 SdHoareTripleChecker+Valid, 2026 SdHoareTripleChecker+Invalid, 198 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 198 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:29,907 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [949 Valid, 2026 Invalid, 198 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 198 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:29,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1110 states. [2024-11-28 02:55:29,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1110 to 1110. [2024-11-28 02:55:29,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1110 states, 1098 states have (on average 1.459016393442623) internal successors, (1602), 1098 states have internal predecessors, (1602), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:29,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1110 states to 1110 states and 1622 transitions. [2024-11-28 02:55:29,948 INFO L78 Accepts]: Start accepts. Automaton has 1110 states and 1622 transitions. Word has length 311 [2024-11-28 02:55:29,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:29,949 INFO L471 AbstractCegarLoop]: Abstraction has 1110 states and 1622 transitions. [2024-11-28 02:55:29,949 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 58.25) internal successors, (233), 4 states have internal predecessors, (233), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:29,949 INFO L276 IsEmpty]: Start isEmpty. Operand 1110 states and 1622 transitions. [2024-11-28 02:55:29,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 313 [2024-11-28 02:55:29,952 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:29,952 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:29,952 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-11-28 02:55:29,953 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:29,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:29,953 INFO L85 PathProgramCache]: Analyzing trace with hash -815635257, now seen corresponding path program 1 times [2024-11-28 02:55:29,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:29,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074786297] [2024-11-28 02:55:29,954 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:29,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:30,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:32,438 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:32,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:32,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2074786297] [2024-11-28 02:55:32,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2074786297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:32,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:32,439 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:55:32,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938750881] [2024-11-28 02:55:32,439 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:32,440 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:55:32,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:32,441 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:55:32,442 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:55:32,442 INFO L87 Difference]: Start difference. First operand 1110 states and 1622 transitions. Second operand has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:32,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:32,726 INFO L93 Difference]: Finished difference Result 1879 states and 2758 transitions. [2024-11-28 02:55:32,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:55:32,727 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 312 [2024-11-28 02:55:32,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:32,733 INFO L225 Difference]: With dead ends: 1879 [2024-11-28 02:55:32,733 INFO L226 Difference]: Without dead ends: 1134 [2024-11-28 02:55:32,735 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:55:32,736 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1034 mSDsluCounter, 5381 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1037 SdHoareTripleChecker+Valid, 6469 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:32,736 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1037 Valid, 6469 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:32,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1134 states. [2024-11-28 02:55:32,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1134 to 1128. [2024-11-28 02:55:32,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1128 states, 1116 states have (on average 1.4587813620071686) internal successors, (1628), 1116 states have internal predecessors, (1628), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:32,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1128 states to 1128 states and 1648 transitions. [2024-11-28 02:55:32,791 INFO L78 Accepts]: Start accepts. Automaton has 1128 states and 1648 transitions. Word has length 312 [2024-11-28 02:55:32,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:32,791 INFO L471 AbstractCegarLoop]: Abstraction has 1128 states and 1648 transitions. [2024-11-28 02:55:32,792 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.25) internal successors, (234), 8 states have internal predecessors, (234), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:32,792 INFO L276 IsEmpty]: Start isEmpty. Operand 1128 states and 1648 transitions. [2024-11-28 02:55:32,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-11-28 02:55:32,796 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:32,797 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:32,797 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-11-28 02:55:32,797 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:32,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:32,798 INFO L85 PathProgramCache]: Analyzing trace with hash -395838274, now seen corresponding path program 1 times [2024-11-28 02:55:32,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:32,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778575690] [2024-11-28 02:55:32,798 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:32,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:32,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:33,502 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:33,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:33,502 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1778575690] [2024-11-28 02:55:33,502 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1778575690] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:33,502 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:33,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:55:33,503 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094920308] [2024-11-28 02:55:33,503 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:33,503 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:55:33,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:33,504 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:55:33,505 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:33,505 INFO L87 Difference]: Start difference. First operand 1128 states and 1648 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:34,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:34,608 INFO L93 Difference]: Finished difference Result 1886 states and 2767 transitions. [2024-11-28 02:55:34,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:55:34,609 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-11-28 02:55:34,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:34,614 INFO L225 Difference]: With dead ends: 1886 [2024-11-28 02:55:34,614 INFO L226 Difference]: Without dead ends: 1136 [2024-11-28 02:55:34,616 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:34,617 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1024 mSDsluCounter, 2423 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1027 SdHoareTripleChecker+Valid, 3239 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:34,617 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1027 Valid, 3239 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-28 02:55:34,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-11-28 02:55:34,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1132. [2024-11-28 02:55:34,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1132 states, 1120 states have (on average 1.457142857142857) internal successors, (1632), 1120 states have internal predecessors, (1632), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:34,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1132 states to 1132 states and 1652 transitions. [2024-11-28 02:55:34,660 INFO L78 Accepts]: Start accepts. Automaton has 1132 states and 1652 transitions. Word has length 313 [2024-11-28 02:55:34,660 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:34,661 INFO L471 AbstractCegarLoop]: Abstraction has 1132 states and 1652 transitions. [2024-11-28 02:55:34,661 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:34,661 INFO L276 IsEmpty]: Start isEmpty. Operand 1132 states and 1652 transitions. [2024-11-28 02:55:34,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 314 [2024-11-28 02:55:34,664 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:34,664 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:34,665 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-11-28 02:55:34,665 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:34,665 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:34,666 INFO L85 PathProgramCache]: Analyzing trace with hash -257926317, now seen corresponding path program 1 times [2024-11-28 02:55:34,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:34,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271084978] [2024-11-28 02:55:34,666 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:34,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:34,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:35,364 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:35,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:35,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271084978] [2024-11-28 02:55:35,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271084978] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:35,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:35,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:55:35,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568311160] [2024-11-28 02:55:35,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:35,366 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:55:35,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:35,367 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:55:35,368 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:35,369 INFO L87 Difference]: Start difference. First operand 1132 states and 1652 transitions. Second operand has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:36,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:36,513 INFO L93 Difference]: Finished difference Result 1908 states and 2796 transitions. [2024-11-28 02:55:36,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:55:36,514 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 313 [2024-11-28 02:55:36,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:36,520 INFO L225 Difference]: With dead ends: 1908 [2024-11-28 02:55:36,520 INFO L226 Difference]: Without dead ends: 1136 [2024-11-28 02:55:36,522 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:36,523 INFO L435 NwaCegarLoop]: 818 mSDtfsCounter, 1030 mSDsluCounter, 2426 mSDsCounter, 0 mSdLazyCounter, 1180 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1033 SdHoareTripleChecker+Valid, 3244 SdHoareTripleChecker+Invalid, 1182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:36,523 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1033 Valid, 3244 Invalid, 1182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1180 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-28 02:55:36,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1136 states. [2024-11-28 02:55:36,557 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1136 to 1136. [2024-11-28 02:55:36,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1124 states have (on average 1.4555160142348755) internal successors, (1636), 1124 states have internal predecessors, (1636), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:36,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1656 transitions. [2024-11-28 02:55:36,566 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1656 transitions. Word has length 313 [2024-11-28 02:55:36,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:36,566 INFO L471 AbstractCegarLoop]: Abstraction has 1136 states and 1656 transitions. [2024-11-28 02:55:36,567 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.166666666666664) internal successors, (235), 6 states have internal predecessors, (235), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:36,567 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1656 transitions. [2024-11-28 02:55:36,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2024-11-28 02:55:36,570 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:36,570 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:36,570 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-11-28 02:55:36,570 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:36,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:36,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1921876768, now seen corresponding path program 1 times [2024-11-28 02:55:36,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:36,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815365750] [2024-11-28 02:55:36,571 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:36,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:36,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:37,839 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:37,839 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:37,840 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815365750] [2024-11-28 02:55:37,840 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815365750] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:37,840 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:37,840 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:55:37,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489840932] [2024-11-28 02:55:37,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:37,841 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:55:37,841 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:37,842 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:55:37,843 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:37,843 INFO L87 Difference]: Start difference. First operand 1136 states and 1656 transitions. Second operand has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:39,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:39,166 INFO L93 Difference]: Finished difference Result 2363 states and 3467 transitions. [2024-11-28 02:55:39,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:55:39,167 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 314 [2024-11-28 02:55:39,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:39,174 INFO L225 Difference]: With dead ends: 2363 [2024-11-28 02:55:39,174 INFO L226 Difference]: Without dead ends: 1693 [2024-11-28 02:55:39,175 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:39,177 INFO L435 NwaCegarLoop]: 809 mSDtfsCounter, 2525 mSDsluCounter, 2343 mSDsCounter, 0 mSdLazyCounter, 1165 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2530 SdHoareTripleChecker+Valid, 3152 SdHoareTripleChecker+Invalid, 1168 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1165 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:39,177 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2530 Valid, 3152 Invalid, 1168 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1165 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-11-28 02:55:39,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1693 states. [2024-11-28 02:55:39,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1693 to 1022. [2024-11-28 02:55:39,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1022 states, 1010 states have (on average 1.4584158415841584) internal successors, (1473), 1010 states have internal predecessors, (1473), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:39,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 1493 transitions. [2024-11-28 02:55:39,223 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 1493 transitions. Word has length 314 [2024-11-28 02:55:39,224 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:39,224 INFO L471 AbstractCegarLoop]: Abstraction has 1022 states and 1493 transitions. [2024-11-28 02:55:39,224 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.333333333333336) internal successors, (236), 6 states have internal predecessors, (236), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:39,224 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 1493 transitions. [2024-11-28 02:55:39,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 316 [2024-11-28 02:55:39,226 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:39,227 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:39,227 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-11-28 02:55:39,227 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:39,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:39,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1323386401, now seen corresponding path program 1 times [2024-11-28 02:55:39,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:39,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299970266] [2024-11-28 02:55:39,228 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:39,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:39,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:41,356 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:41,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:41,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299970266] [2024-11-28 02:55:41,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299970266] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:41,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:41,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:55:41,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [754535451] [2024-11-28 02:55:41,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:41,360 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:55:41,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:41,361 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:55:41,362 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:55:41,363 INFO L87 Difference]: Start difference. First operand 1022 states and 1493 transitions. Second operand has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:41,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:41,628 INFO L93 Difference]: Finished difference Result 1767 states and 2590 transitions. [2024-11-28 02:55:41,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:55:41,628 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 315 [2024-11-28 02:55:41,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:41,633 INFO L225 Difference]: With dead ends: 1767 [2024-11-28 02:55:41,633 INFO L226 Difference]: Without dead ends: 1046 [2024-11-28 02:55:41,635 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:55:41,636 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 1010 mSDsluCounter, 5390 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1012 SdHoareTripleChecker+Valid, 6478 SdHoareTripleChecker+Invalid, 158 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:41,636 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1012 Valid, 6478 Invalid, 158 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 157 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:55:41,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1046 states. [2024-11-28 02:55:41,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1046 to 1040. [2024-11-28 02:55:41,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1040 states, 1028 states have (on average 1.4581712062256809) internal successors, (1499), 1028 states have internal predecessors, (1499), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:41,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1519 transitions. [2024-11-28 02:55:41,687 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1519 transitions. Word has length 315 [2024-11-28 02:55:41,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:41,688 INFO L471 AbstractCegarLoop]: Abstraction has 1040 states and 1519 transitions. [2024-11-28 02:55:41,689 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 29.625) internal successors, (237), 8 states have internal predecessors, (237), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:41,689 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1519 transitions. [2024-11-28 02:55:41,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-28 02:55:41,691 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:41,691 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:41,691 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-11-28 02:55:41,692 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:41,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:41,692 INFO L85 PathProgramCache]: Analyzing trace with hash 1658628649, now seen corresponding path program 1 times [2024-11-28 02:55:41,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:41,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920324225] [2024-11-28 02:55:41,692 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:41,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:41,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:42,543 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:42,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:42,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920324225] [2024-11-28 02:55:42,544 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920324225] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:42,544 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:42,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:55:42,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184623598] [2024-11-28 02:55:42,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:42,546 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:55:42,546 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:42,547 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:55:42,547 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:42,547 INFO L87 Difference]: Start difference. First operand 1040 states and 1519 transitions. Second operand has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-28 02:55:43,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:43,901 INFO L93 Difference]: Finished difference Result 1774 states and 2599 transitions. [2024-11-28 02:55:43,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:55:43,903 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) Word has length 316 [2024-11-28 02:55:43,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:43,908 INFO L225 Difference]: With dead ends: 1774 [2024-11-28 02:55:43,908 INFO L226 Difference]: Without dead ends: 1048 [2024-11-28 02:55:43,910 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:43,911 INFO L435 NwaCegarLoop]: 816 mSDtfsCounter, 1071 mSDsluCounter, 2414 mSDsCounter, 0 mSdLazyCounter, 1194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 3230 SdHoareTripleChecker+Invalid, 1195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:43,911 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 3230 Invalid, 1195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1194 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-28 02:55:43,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1048 states. [2024-11-28 02:55:43,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1048 to 1044. [2024-11-28 02:55:43,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1044 states, 1032 states have (on average 1.4563953488372092) internal successors, (1503), 1032 states have internal predecessors, (1503), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:43,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1044 states to 1044 states and 1523 transitions. [2024-11-28 02:55:43,954 INFO L78 Accepts]: Start accepts. Automaton has 1044 states and 1523 transitions. Word has length 316 [2024-11-28 02:55:43,955 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:43,955 INFO L471 AbstractCegarLoop]: Abstraction has 1044 states and 1523 transitions. [2024-11-28 02:55:43,956 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 3 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 3 states have call predecessors, (5), 3 states have call successors, (5) [2024-11-28 02:55:43,956 INFO L276 IsEmpty]: Start isEmpty. Operand 1044 states and 1523 transitions. [2024-11-28 02:55:43,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-28 02:55:43,959 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:43,959 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:43,959 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-11-28 02:55:43,960 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:43,960 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:43,961 INFO L85 PathProgramCache]: Analyzing trace with hash 874653310, now seen corresponding path program 1 times [2024-11-28 02:55:43,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:43,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321338766] [2024-11-28 02:55:43,961 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:43,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:44,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:45,867 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:45,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:45,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321338766] [2024-11-28 02:55:45,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321338766] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:45,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:45,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:55:45,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [734677283] [2024-11-28 02:55:45,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:45,868 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:55:45,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:45,869 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:55:45,869 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:45,870 INFO L87 Difference]: Start difference. First operand 1044 states and 1523 transitions. Second operand has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:47,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:47,004 INFO L93 Difference]: Finished difference Result 1849 states and 2705 transitions. [2024-11-28 02:55:47,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:55:47,005 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-11-28 02:55:47,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:47,013 INFO L225 Difference]: With dead ends: 1849 [2024-11-28 02:55:47,013 INFO L226 Difference]: Without dead ends: 1062 [2024-11-28 02:55:47,015 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:47,015 INFO L435 NwaCegarLoop]: 819 mSDtfsCounter, 1018 mSDsluCounter, 2410 mSDsCounter, 0 mSdLazyCounter, 1225 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1021 SdHoareTripleChecker+Valid, 3229 SdHoareTripleChecker+Invalid, 1226 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1225 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:47,015 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1021 Valid, 3229 Invalid, 1226 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1225 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-28 02:55:47,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1062 states. [2024-11-28 02:55:47,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1062 to 1054. [2024-11-28 02:55:47,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1054 states, 1042 states have (on average 1.4539347408829175) internal successors, (1515), 1042 states have internal predecessors, (1515), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:47,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1054 states to 1054 states and 1535 transitions. [2024-11-28 02:55:47,093 INFO L78 Accepts]: Start accepts. Automaton has 1054 states and 1535 transitions. Word has length 316 [2024-11-28 02:55:47,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:47,094 INFO L471 AbstractCegarLoop]: Abstraction has 1054 states and 1535 transitions. [2024-11-28 02:55:47,094 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 34.0) internal successors, (238), 7 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:47,098 INFO L276 IsEmpty]: Start isEmpty. Operand 1054 states and 1535 transitions. [2024-11-28 02:55:47,100 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-28 02:55:47,100 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:47,101 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:47,101 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-11-28 02:55:47,102 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:47,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:47,103 INFO L85 PathProgramCache]: Analyzing trace with hash 2027061502, now seen corresponding path program 1 times [2024-11-28 02:55:47,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:47,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751942846] [2024-11-28 02:55:47,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:47,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:47,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:47,993 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:47,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:47,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751942846] [2024-11-28 02:55:47,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751942846] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:47,994 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:47,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:55:47,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1506218631] [2024-11-28 02:55:47,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:47,996 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:47,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:47,997 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:47,997 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:55:47,998 INFO L87 Difference]: Start difference. First operand 1054 states and 1535 transitions. Second operand has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:48,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:48,078 INFO L93 Difference]: Finished difference Result 1836 states and 2684 transitions. [2024-11-28 02:55:48,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:48,079 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 316 [2024-11-28 02:55:48,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:48,084 INFO L225 Difference]: With dead ends: 1836 [2024-11-28 02:55:48,084 INFO L226 Difference]: Without dead ends: 1050 [2024-11-28 02:55:48,086 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:55:48,086 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1010 mSDsluCounter, 1100 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1013 SdHoareTripleChecker+Valid, 2193 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:48,087 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1013 Valid, 2193 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:48,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1050 states. [2024-11-28 02:55:48,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1050 to 1050. [2024-11-28 02:55:48,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1050 states, 1038 states have (on average 1.453757225433526) internal successors, (1509), 1038 states have internal predecessors, (1509), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:48,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1050 states to 1050 states and 1529 transitions. [2024-11-28 02:55:48,122 INFO L78 Accepts]: Start accepts. Automaton has 1050 states and 1529 transitions. Word has length 316 [2024-11-28 02:55:48,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:48,123 INFO L471 AbstractCegarLoop]: Abstraction has 1050 states and 1529 transitions. [2024-11-28 02:55:48,123 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 59.5) internal successors, (238), 4 states have internal predecessors, (238), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 02:55:48,124 INFO L276 IsEmpty]: Start isEmpty. Operand 1050 states and 1529 transitions. [2024-11-28 02:55:48,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2024-11-28 02:55:48,126 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:48,127 INFO L218 NwaCegarLoop]: trace histogram [8, 8, 8, 8, 8, 8, 8, 8, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:48,127 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-11-28 02:55:48,127 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:48,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:48,128 INFO L85 PathProgramCache]: Analyzing trace with hash -657479526, now seen corresponding path program 1 times [2024-11-28 02:55:48,128 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:48,128 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698291535] [2024-11-28 02:55:48,128 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:48,128 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:48,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:50,008 INFO L134 CoverageAnalysis]: Checked inductivity of 280 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 280 trivial. 0 not checked. [2024-11-28 02:55:50,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:50,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698291535] [2024-11-28 02:55:50,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698291535] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:50,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:50,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:55:50,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476396064] [2024-11-28 02:55:50,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:50,010 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:55:50,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:50,011 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:55:50,011 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:50,012 INFO L87 Difference]: Start difference. First operand 1050 states and 1529 transitions. Second operand has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:50,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:50,211 INFO L93 Difference]: Finished difference Result 1905 states and 2789 transitions. [2024-11-28 02:55:50,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:55:50,212 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 316 [2024-11-28 02:55:50,213 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:50,217 INFO L225 Difference]: With dead ends: 1905 [2024-11-28 02:55:50,218 INFO L226 Difference]: Without dead ends: 1221 [2024-11-28 02:55:50,219 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:55:50,223 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 1816 mSDsluCounter, 3267 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1821 SdHoareTripleChecker+Valid, 4358 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:50,223 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1821 Valid, 4358 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:55:50,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-28 02:55:50,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-28 02:55:50,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.457402812241522) internal successors, (1762), 1209 states have internal predecessors, (1762), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:50,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1782 transitions. [2024-11-28 02:55:50,263 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1782 transitions. Word has length 316 [2024-11-28 02:55:50,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:50,264 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1782 transitions. [2024-11-28 02:55:50,265 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 39.666666666666664) internal successors, (238), 6 states have internal predecessors, (238), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:55:50,265 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1782 transitions. [2024-11-28 02:55:50,272 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 677 [2024-11-28 02:55:50,272 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:50,273 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:50,273 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-11-28 02:55:50,273 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:50,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:50,275 INFO L85 PathProgramCache]: Analyzing trace with hash 231843785, now seen corresponding path program 1 times [2024-11-28 02:55:50,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:50,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646725961] [2024-11-28 02:55:50,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:50,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:51,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:51,957 INFO L134 CoverageAnalysis]: Checked inductivity of 601 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:55:51,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:51,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646725961] [2024-11-28 02:55:51,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646725961] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:51,958 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:55:51,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 02:55:51,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132301070] [2024-11-28 02:55:51,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:51,960 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:55:51,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:51,961 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:55:51,961 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 02:55:51,962 INFO L87 Difference]: Start difference. First operand 1221 states and 1782 transitions. Second operand has 3 states, 3 states have (on average 191.0) internal successors, (573), 3 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:55:52,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:52,004 INFO L93 Difference]: Finished difference Result 1907 states and 2791 transitions. [2024-11-28 02:55:52,005 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:55:52,006 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 191.0) internal successors, (573), 3 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 676 [2024-11-28 02:55:52,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:52,014 INFO L225 Difference]: With dead ends: 1907 [2024-11-28 02:55:52,018 INFO L226 Difference]: Without dead ends: 1223 [2024-11-28 02:55:52,020 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 02:55:52,021 INFO L435 NwaCegarLoop]: 1106 mSDtfsCounter, 1 mSDsluCounter, 1102 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2208 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:52,021 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2208 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:55:52,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1223 states. [2024-11-28 02:55:52,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1223 to 1222. [2024-11-28 02:55:52,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4570247933884297) internal successors, (1763), 1210 states have internal predecessors, (1763), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:52,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1783 transitions. [2024-11-28 02:55:52,062 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1783 transitions. Word has length 676 [2024-11-28 02:55:52,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:52,063 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1783 transitions. [2024-11-28 02:55:52,063 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 191.0) internal successors, (573), 3 states have internal predecessors, (573), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:55:52,063 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1783 transitions. [2024-11-28 02:55:52,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 679 [2024-11-28 02:55:52,070 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:52,071 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:52,071 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-11-28 02:55:52,071 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:52,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:52,072 INFO L85 PathProgramCache]: Analyzing trace with hash -1237278803, now seen corresponding path program 1 times [2024-11-28 02:55:52,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:52,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131152503] [2024-11-28 02:55:52,073 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:52,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:52,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:54,009 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:55:54,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:54,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [131152503] [2024-11-28 02:55:54,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [131152503] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:54,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [188270294] [2024-11-28 02:55:54,011 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:54,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:54,011 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:54,014 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:54,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 02:55:55,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:55,672 INFO L256 TraceCheckSpWp]: Trace formula consists of 3368 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-28 02:55:55,689 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:55:57,024 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-28 02:55:57,029 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 02:55:57,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [188270294] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:55:57,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 02:55:57,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-28 02:55:57,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636842146] [2024-11-28 02:55:57,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:55:57,030 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:55:57,030 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:55:57,031 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:55:57,031 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:55:57,032 INFO L87 Difference]: Start difference. First operand 1222 states and 1783 transitions. Second operand has 4 states, 4 states have (on average 144.5) internal successors, (578), 4 states have internal predecessors, (578), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:55:57,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:55:57,807 INFO L93 Difference]: Finished difference Result 1906 states and 2789 transitions. [2024-11-28 02:55:57,807 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:55:57,808 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 144.5) internal successors, (578), 4 states have internal predecessors, (578), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 678 [2024-11-28 02:55:57,809 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:55:57,813 INFO L225 Difference]: With dead ends: 1906 [2024-11-28 02:55:57,813 INFO L226 Difference]: Without dead ends: 1221 [2024-11-28 02:55:57,815 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 682 GetRequests, 677 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:55:57,816 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 831 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 601 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 831 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 602 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 601 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 02:55:57,816 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [831 Valid, 1616 Invalid, 602 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 601 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 02:55:57,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-28 02:55:57,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-28 02:55:57,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.455748552522746) internal successors, (1760), 1209 states have internal predecessors, (1760), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:55:57,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1780 transitions. [2024-11-28 02:55:57,868 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1780 transitions. Word has length 678 [2024-11-28 02:55:57,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:55:57,869 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1780 transitions. [2024-11-28 02:55:57,869 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 144.5) internal successors, (578), 4 states have internal predecessors, (578), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:55:57,870 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1780 transitions. [2024-11-28 02:55:57,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 680 [2024-11-28 02:55:57,880 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:55:57,881 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:55:57,899 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-28 02:55:58,081 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable23 [2024-11-28 02:55:58,082 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:55:58,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:55:58,083 INFO L85 PathProgramCache]: Analyzing trace with hash -1245576445, now seen corresponding path program 1 times [2024-11-28 02:55:58,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:55:58,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091355083] [2024-11-28 02:55:58,084 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:58,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:55:58,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:55:59,535 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:55:59,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:55:59,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2091355083] [2024-11-28 02:55:59,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2091355083] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:55:59,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [961872217] [2024-11-28 02:55:59,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:55:59,536 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:55:59,536 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:55:59,538 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:55:59,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 02:56:00,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:00,854 INFO L256 TraceCheckSpWp]: Trace formula consists of 3371 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-28 02:56:00,864 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:01,901 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-28 02:56:01,901 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 02:56:01,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [961872217] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:56:01,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 02:56:01,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-28 02:56:01,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665628854] [2024-11-28 02:56:01,902 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:01,903 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:56:01,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:01,904 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:56:01,904 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:56:01,904 INFO L87 Difference]: Start difference. First operand 1221 states and 1780 transitions. Second operand has 4 states, 4 states have (on average 144.75) internal successors, (579), 4 states have internal predecessors, (579), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:02,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:02,401 INFO L93 Difference]: Finished difference Result 1904 states and 2783 transitions. [2024-11-28 02:56:02,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:02,402 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 144.75) internal successors, (579), 4 states have internal predecessors, (579), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 679 [2024-11-28 02:56:02,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:02,406 INFO L225 Difference]: With dead ends: 1904 [2024-11-28 02:56:02,406 INFO L226 Difference]: Without dead ends: 1220 [2024-11-28 02:56:02,407 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 683 GetRequests, 678 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:02,408 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 823 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 595 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 823 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 596 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 595 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:02,408 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [823 Valid, 1616 Invalid, 596 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 595 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-28 02:56:02,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2024-11-28 02:56:02,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1220. [2024-11-28 02:56:02,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1220 states, 1208 states have (on average 1.4544701986754967) internal successors, (1757), 1208 states have internal predecessors, (1757), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:02,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 1220 states and 1777 transitions. [2024-11-28 02:56:02,440 INFO L78 Accepts]: Start accepts. Automaton has 1220 states and 1777 transitions. Word has length 679 [2024-11-28 02:56:02,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:02,440 INFO L471 AbstractCegarLoop]: Abstraction has 1220 states and 1777 transitions. [2024-11-28 02:56:02,441 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 144.75) internal successors, (579), 4 states have internal predecessors, (579), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:02,441 INFO L276 IsEmpty]: Start isEmpty. Operand 1220 states and 1777 transitions. [2024-11-28 02:56:02,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 681 [2024-11-28 02:56:02,447 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:02,447 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:02,464 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-28 02:56:02,648 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable24 [2024-11-28 02:56:02,648 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:02,648 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:02,649 INFO L85 PathProgramCache]: Analyzing trace with hash -1834577249, now seen corresponding path program 1 times [2024-11-28 02:56:02,649 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:02,649 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598774594] [2024-11-28 02:56:02,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:02,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:03,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:03,939 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:03,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:03,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598774594] [2024-11-28 02:56:03,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598774594] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:03,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2092834076] [2024-11-28 02:56:03,940 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:03,940 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:03,940 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:03,947 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:03,950 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 02:56:05,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:05,647 INFO L256 TraceCheckSpWp]: Trace formula consists of 3374 conjuncts, 8 conjuncts are in the unsatisfiable core [2024-11-28 02:56:05,659 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:06,801 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 0 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2024-11-28 02:56:06,802 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 02:56:06,802 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2092834076] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:56:06,802 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 02:56:06,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 6 [2024-11-28 02:56:06,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656923883] [2024-11-28 02:56:06,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:06,803 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:56:06,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:06,805 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:56:06,805 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:56:06,805 INFO L87 Difference]: Start difference. First operand 1220 states and 1777 transitions. Second operand has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:07,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:07,304 INFO L93 Difference]: Finished difference Result 1902 states and 2777 transitions. [2024-11-28 02:56:07,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:07,305 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 680 [2024-11-28 02:56:07,305 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:07,309 INFO L225 Difference]: With dead ends: 1902 [2024-11-28 02:56:07,309 INFO L226 Difference]: Without dead ends: 1219 [2024-11-28 02:56:07,310 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 684 GetRequests, 679 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:07,311 INFO L435 NwaCegarLoop]: 807 mSDtfsCounter, 809 mSDsluCounter, 809 mSDsCounter, 0 mSdLazyCounter, 589 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 809 SdHoareTripleChecker+Valid, 1616 SdHoareTripleChecker+Invalid, 590 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 589 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:07,311 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [809 Valid, 1616 Invalid, 590 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 589 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-28 02:56:07,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1219 states. [2024-11-28 02:56:07,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1219 to 1219. [2024-11-28 02:56:07,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1219 states, 1207 states have (on average 1.4531897265948632) internal successors, (1754), 1207 states have internal predecessors, (1754), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:07,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1219 states to 1219 states and 1774 transitions. [2024-11-28 02:56:07,347 INFO L78 Accepts]: Start accepts. Automaton has 1219 states and 1774 transitions. Word has length 680 [2024-11-28 02:56:07,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:07,348 INFO L471 AbstractCegarLoop]: Abstraction has 1219 states and 1774 transitions. [2024-11-28 02:56:07,348 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 145.0) internal successors, (580), 4 states have internal predecessors, (580), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:07,348 INFO L276 IsEmpty]: Start isEmpty. Operand 1219 states and 1774 transitions. [2024-11-28 02:56:07,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 682 [2024-11-28 02:56:07,355 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:07,355 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:07,375 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2024-11-28 02:56:07,556 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable25 [2024-11-28 02:56:07,559 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:07,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:07,560 INFO L85 PathProgramCache]: Analyzing trace with hash -1912161467, now seen corresponding path program 1 times [2024-11-28 02:56:07,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:07,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831498442] [2024-11-28 02:56:07,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:07,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:08,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:08,731 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:08,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:08,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831498442] [2024-11-28 02:56:08,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831498442] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:08,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1364455887] [2024-11-28 02:56:08,732 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:08,732 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:08,733 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:08,736 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:08,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 02:56:10,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:10,360 INFO L256 TraceCheckSpWp]: Trace formula consists of 3377 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-28 02:56:10,374 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:11,491 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-28 02:56:11,491 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:12,362 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:12,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1364455887] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:12,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:12,362 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-28 02:56:12,362 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [213643677] [2024-11-28 02:56:12,362 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:12,363 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:56:12,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:12,364 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:56:12,364 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-28 02:56:12,364 INFO L87 Difference]: Start difference. First operand 1219 states and 1774 transitions. Second operand has 5 states, 5 states have (on average 115.6) internal successors, (578), 5 states have internal predecessors, (578), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:12,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:12,637 INFO L93 Difference]: Finished difference Result 1901 states and 2772 transitions. [2024-11-28 02:56:12,637 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:12,638 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 115.6) internal successors, (578), 5 states have internal predecessors, (578), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 681 [2024-11-28 02:56:12,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:12,641 INFO L225 Difference]: With dead ends: 1901 [2024-11-28 02:56:12,641 INFO L226 Difference]: Without dead ends: 1219 [2024-11-28 02:56:12,642 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1365 GetRequests, 1347 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:56:12,643 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1827 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 196 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1832 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 203 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 196 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:12,644 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1832 Valid, 2006 Invalid, 203 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 196 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:56:12,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1219 states. [2024-11-28 02:56:12,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1219 to 1219. [2024-11-28 02:56:12,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1219 states, 1207 states have (on average 1.4523612261806131) internal successors, (1753), 1207 states have internal predecessors, (1753), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:12,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1219 states to 1219 states and 1773 transitions. [2024-11-28 02:56:12,678 INFO L78 Accepts]: Start accepts. Automaton has 1219 states and 1773 transitions. Word has length 681 [2024-11-28 02:56:12,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:12,679 INFO L471 AbstractCegarLoop]: Abstraction has 1219 states and 1773 transitions. [2024-11-28 02:56:12,679 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 115.6) internal successors, (578), 5 states have internal predecessors, (578), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:12,679 INFO L276 IsEmpty]: Start isEmpty. Operand 1219 states and 1773 transitions. [2024-11-28 02:56:12,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2024-11-28 02:56:12,685 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:12,685 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:12,705 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-28 02:56:12,886 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable26 [2024-11-28 02:56:12,887 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:12,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:12,887 INFO L85 PathProgramCache]: Analyzing trace with hash -703476681, now seen corresponding path program 1 times [2024-11-28 02:56:12,888 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:12,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238392605] [2024-11-28 02:56:12,888 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:12,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:13,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:13,966 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:13,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:13,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238392605] [2024-11-28 02:56:13,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238392605] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:13,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [55349610] [2024-11-28 02:56:13,966 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:13,967 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:13,967 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:13,969 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:13,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-28 02:56:15,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:15,505 INFO L256 TraceCheckSpWp]: Trace formula consists of 3380 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-28 02:56:15,516 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:16,678 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-28 02:56:16,679 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:17,621 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:17,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [55349610] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:17,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:17,622 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-28 02:56:17,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1352361881] [2024-11-28 02:56:17,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:17,623 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:56:17,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:17,623 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:56:17,624 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-28 02:56:17,624 INFO L87 Difference]: Start difference. First operand 1219 states and 1773 transitions. Second operand has 5 states, 5 states have (on average 115.8) internal successors, (579), 5 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:17,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:17,842 INFO L93 Difference]: Finished difference Result 1901 states and 2770 transitions. [2024-11-28 02:56:17,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:17,843 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 115.8) internal successors, (579), 5 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 682 [2024-11-28 02:56:17,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:17,845 INFO L225 Difference]: With dead ends: 1901 [2024-11-28 02:56:17,845 INFO L226 Difference]: Without dead ends: 1219 [2024-11-28 02:56:17,846 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1367 GetRequests, 1349 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:56:17,847 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 903 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 194 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 908 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 195 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:17,847 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [908 Valid, 2015 Invalid, 195 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 194 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:56:17,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1219 states. [2024-11-28 02:56:17,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1219 to 1219. [2024-11-28 02:56:17,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1219 states, 1207 states have (on average 1.4515327257663628) internal successors, (1752), 1207 states have internal predecessors, (1752), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:17,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1219 states to 1219 states and 1772 transitions. [2024-11-28 02:56:17,879 INFO L78 Accepts]: Start accepts. Automaton has 1219 states and 1772 transitions. Word has length 682 [2024-11-28 02:56:17,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:17,880 INFO L471 AbstractCegarLoop]: Abstraction has 1219 states and 1772 transitions. [2024-11-28 02:56:17,880 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 115.8) internal successors, (579), 5 states have internal predecessors, (579), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:17,880 INFO L276 IsEmpty]: Start isEmpty. Operand 1219 states and 1772 transitions. [2024-11-28 02:56:17,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 684 [2024-11-28 02:56:17,886 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:17,887 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:17,904 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-28 02:56:18,087 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable27 [2024-11-28 02:56:18,088 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:18,088 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:18,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1512909470, now seen corresponding path program 1 times [2024-11-28 02:56:18,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:18,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086722956] [2024-11-28 02:56:18,089 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:18,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:18,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:19,250 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:19,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:19,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086722956] [2024-11-28 02:56:19,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086722956] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:19,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1241052874] [2024-11-28 02:56:19,250 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:19,251 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:19,251 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:19,253 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:19,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-28 02:56:20,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:20,797 INFO L256 TraceCheckSpWp]: Trace formula consists of 3383 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-28 02:56:20,810 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:22,092 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-28 02:56:22,092 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:23,223 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:23,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1241052874] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:23,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:23,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-28 02:56:23,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642205604] [2024-11-28 02:56:23,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:23,224 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:56:23,224 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:23,225 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:56:23,225 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-28 02:56:23,225 INFO L87 Difference]: Start difference. First operand 1219 states and 1772 transitions. Second operand has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:23,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:23,459 INFO L93 Difference]: Finished difference Result 1901 states and 2768 transitions. [2024-11-28 02:56:23,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:23,459 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 683 [2024-11-28 02:56:23,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:23,463 INFO L225 Difference]: With dead ends: 1901 [2024-11-28 02:56:23,463 INFO L226 Difference]: Without dead ends: 1219 [2024-11-28 02:56:23,464 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1369 GetRequests, 1351 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:56:23,465 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 1791 mSDsluCounter, 1004 mSDsCounter, 0 mSdLazyCounter, 192 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1796 SdHoareTripleChecker+Valid, 2006 SdHoareTripleChecker+Invalid, 199 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 192 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:23,465 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1796 Valid, 2006 Invalid, 199 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 192 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:56:23,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1219 states. [2024-11-28 02:56:23,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1219 to 1219. [2024-11-28 02:56:23,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1219 states, 1207 states have (on average 1.4507042253521127) internal successors, (1751), 1207 states have internal predecessors, (1751), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:23,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1219 states to 1219 states and 1771 transitions. [2024-11-28 02:56:23,496 INFO L78 Accepts]: Start accepts. Automaton has 1219 states and 1771 transitions. Word has length 683 [2024-11-28 02:56:23,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:23,497 INFO L471 AbstractCegarLoop]: Abstraction has 1219 states and 1771 transitions. [2024-11-28 02:56:23,497 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.0) internal successors, (580), 5 states have internal predecessors, (580), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:23,497 INFO L276 IsEmpty]: Start isEmpty. Operand 1219 states and 1771 transitions. [2024-11-28 02:56:23,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 685 [2024-11-28 02:56:23,503 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:23,503 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:23,524 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-28 02:56:23,704 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable28 [2024-11-28 02:56:23,704 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:23,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:23,705 INFO L85 PathProgramCache]: Analyzing trace with hash -1623711415, now seen corresponding path program 1 times [2024-11-28 02:56:23,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:23,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579185246] [2024-11-28 02:56:23,705 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:23,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:24,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:24,810 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:24,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:24,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579185246] [2024-11-28 02:56:24,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579185246] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:24,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1841094890] [2024-11-28 02:56:24,810 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:24,810 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:24,810 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:24,812 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:24,813 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-28 02:56:26,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:26,487 INFO L256 TraceCheckSpWp]: Trace formula consists of 3386 conjuncts, 27 conjuncts are in the unsatisfiable core [2024-11-28 02:56:26,497 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:27,590 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 120 refuted. 0 times theorem prover too weak. 201 trivial. 0 not checked. [2024-11-28 02:56:27,591 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:28,543 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:28,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1841094890] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:28,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:28,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [4, 14] total 19 [2024-11-28 02:56:28,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158606190] [2024-11-28 02:56:28,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:28,544 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:56:28,544 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:28,545 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:56:28,545 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2024-11-28 02:56:28,545 INFO L87 Difference]: Start difference. First operand 1219 states and 1771 transitions. Second operand has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:28,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:28,808 INFO L93 Difference]: Finished difference Result 1901 states and 2766 transitions. [2024-11-28 02:56:28,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:56:28,809 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 684 [2024-11-28 02:56:28,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:28,812 INFO L225 Difference]: With dead ends: 1901 [2024-11-28 02:56:28,812 INFO L226 Difference]: Without dead ends: 1219 [2024-11-28 02:56:28,814 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1371 GetRequests, 1353 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=65, Invalid=315, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:56:28,815 INFO L435 NwaCegarLoop]: 1002 mSDtfsCounter, 885 mSDsluCounter, 1013 mSDsCounter, 0 mSdLazyCounter, 190 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 890 SdHoareTripleChecker+Valid, 2015 SdHoareTripleChecker+Invalid, 191 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 190 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:28,815 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [890 Valid, 2015 Invalid, 191 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 190 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:56:28,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1219 states. [2024-11-28 02:56:28,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1219 to 1219. [2024-11-28 02:56:28,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1219 states, 1207 states have (on average 1.4498757249378624) internal successors, (1750), 1207 states have internal predecessors, (1750), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:28,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1219 states to 1219 states and 1770 transitions. [2024-11-28 02:56:28,844 INFO L78 Accepts]: Start accepts. Automaton has 1219 states and 1770 transitions. Word has length 684 [2024-11-28 02:56:28,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:28,844 INFO L471 AbstractCegarLoop]: Abstraction has 1219 states and 1770 transitions. [2024-11-28 02:56:28,845 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 116.2) internal successors, (581), 5 states have internal predecessors, (581), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:28,845 INFO L276 IsEmpty]: Start isEmpty. Operand 1219 states and 1770 transitions. [2024-11-28 02:56:28,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 686 [2024-11-28 02:56:28,850 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:28,850 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:28,868 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-11-28 02:56:29,055 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:29,055 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:29,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:29,056 INFO L85 PathProgramCache]: Analyzing trace with hash 1460511967, now seen corresponding path program 1 times [2024-11-28 02:56:29,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:29,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014416096] [2024-11-28 02:56:29,056 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:29,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:29,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:29,865 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2024-11-28 02:56:29,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:29,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014416096] [2024-11-28 02:56:29,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014416096] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:29,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670586005] [2024-11-28 02:56:29,865 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:29,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:29,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:29,867 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:29,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-28 02:56:31,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:31,518 INFO L256 TraceCheckSpWp]: Trace formula consists of 3389 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-28 02:56:31,523 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:31,543 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 281 proven. 8 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2024-11-28 02:56:31,544 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:31,592 INFO L134 CoverageAnalysis]: Checked inductivity of 602 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:31,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [670586005] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:31,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:31,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-28 02:56:31,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1771913117] [2024-11-28 02:56:31,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:31,593 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:56:31,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:31,594 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:56:31,594 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:31,594 INFO L87 Difference]: Start difference. First operand 1219 states and 1770 transitions. Second operand has 3 states, 3 states have (on average 194.0) internal successors, (582), 3 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:31,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:31,617 INFO L93 Difference]: Finished difference Result 1902 states and 2766 transitions. [2024-11-28 02:56:31,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:56:31,618 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 194.0) internal successors, (582), 3 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 685 [2024-11-28 02:56:31,618 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:31,620 INFO L225 Difference]: With dead ends: 1902 [2024-11-28 02:56:31,620 INFO L226 Difference]: Without dead ends: 1220 [2024-11-28 02:56:31,621 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1372 GetRequests, 1367 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:31,621 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:31,621 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:56:31,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1220 states. [2024-11-28 02:56:31,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1220 to 1220. [2024-11-28 02:56:31,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1220 states, 1208 states have (on average 1.4495033112582782) internal successors, (1751), 1208 states have internal predecessors, (1751), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:31,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1220 states to 1220 states and 1771 transitions. [2024-11-28 02:56:31,645 INFO L78 Accepts]: Start accepts. Automaton has 1220 states and 1771 transitions. Word has length 685 [2024-11-28 02:56:31,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:31,646 INFO L471 AbstractCegarLoop]: Abstraction has 1220 states and 1771 transitions. [2024-11-28 02:56:31,646 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 194.0) internal successors, (582), 3 states have internal predecessors, (582), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:31,646 INFO L276 IsEmpty]: Start isEmpty. Operand 1220 states and 1771 transitions. [2024-11-28 02:56:31,651 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 688 [2024-11-28 02:56:31,651 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:31,652 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:31,669 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2024-11-28 02:56:31,852 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable30 [2024-11-28 02:56:31,853 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:31,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:31,853 INFO L85 PathProgramCache]: Analyzing trace with hash -70410205, now seen corresponding path program 1 times [2024-11-28 02:56:31,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:31,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806556140] [2024-11-28 02:56:31,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:31,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:32,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:32,984 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 421 trivial. 0 not checked. [2024-11-28 02:56:32,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:32,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806556140] [2024-11-28 02:56:32,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806556140] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:32,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [860629980] [2024-11-28 02:56:32,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:32,984 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:32,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:32,986 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:32,987 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2024-11-28 02:56:34,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:34,814 INFO L256 TraceCheckSpWp]: Trace formula consists of 3398 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-28 02:56:34,822 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:34,858 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 281 proven. 8 refuted. 0 times theorem prover too weak. 314 trivial. 0 not checked. [2024-11-28 02:56:34,859 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:34,919 INFO L134 CoverageAnalysis]: Checked inductivity of 603 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-11-28 02:56:34,919 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [860629980] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:34,919 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:34,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-28 02:56:34,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1235464708] [2024-11-28 02:56:34,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:34,920 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:56:34,920 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:34,922 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:56:34,922 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:34,922 INFO L87 Difference]: Start difference. First operand 1220 states and 1771 transitions. Second operand has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:34,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:34,959 INFO L93 Difference]: Finished difference Result 1904 states and 2768 transitions. [2024-11-28 02:56:34,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:56:34,960 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 687 [2024-11-28 02:56:34,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:34,963 INFO L225 Difference]: With dead ends: 1904 [2024-11-28 02:56:34,963 INFO L226 Difference]: Without dead ends: 1221 [2024-11-28 02:56:34,965 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1376 GetRequests, 1371 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:34,965 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:34,966 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:56:34,970 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states. [2024-11-28 02:56:34,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-28 02:56:34,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1209 states have (on average 1.4491315136476426) internal successors, (1752), 1209 states have internal predecessors, (1752), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:34,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1772 transitions. [2024-11-28 02:56:35,000 INFO L78 Accepts]: Start accepts. Automaton has 1221 states and 1772 transitions. Word has length 687 [2024-11-28 02:56:35,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:35,001 INFO L471 AbstractCegarLoop]: Abstraction has 1221 states and 1772 transitions. [2024-11-28 02:56:35,001 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 194.66666666666666) internal successors, (584), 3 states have internal predecessors, (584), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:35,001 INFO L276 IsEmpty]: Start isEmpty. Operand 1221 states and 1772 transitions. [2024-11-28 02:56:35,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 690 [2024-11-28 02:56:35,007 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:35,008 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:35,032 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2024-11-28 02:56:35,208 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:35,209 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:35,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:35,210 INFO L85 PathProgramCache]: Analyzing trace with hash -1420509849, now seen corresponding path program 1 times [2024-11-28 02:56:35,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:35,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1792150139] [2024-11-28 02:56:35,210 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:35,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:35,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:36,401 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 422 trivial. 0 not checked. [2024-11-28 02:56:36,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:36,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1792150139] [2024-11-28 02:56:36,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1792150139] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:36,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [646567039] [2024-11-28 02:56:36,402 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:36,402 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:36,402 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:36,404 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:36,405 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2024-11-28 02:56:38,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:38,177 INFO L256 TraceCheckSpWp]: Trace formula consists of 3407 conjuncts, 6 conjuncts are in the unsatisfiable core [2024-11-28 02:56:38,183 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:38,211 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 281 proven. 8 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2024-11-28 02:56:38,211 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:38,273 INFO L134 CoverageAnalysis]: Checked inductivity of 604 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-28 02:56:38,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [646567039] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:38,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:56:38,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [4, 4] total 7 [2024-11-28 02:56:38,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954946743] [2024-11-28 02:56:38,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:38,276 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 02:56:38,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:38,277 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 02:56:38,277 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:38,278 INFO L87 Difference]: Start difference. First operand 1221 states and 1772 transitions. Second operand has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:38,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:38,315 INFO L93 Difference]: Finished difference Result 1906 states and 2770 transitions. [2024-11-28 02:56:38,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 02:56:38,316 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 689 [2024-11-28 02:56:38,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:38,319 INFO L225 Difference]: With dead ends: 1906 [2024-11-28 02:56:38,319 INFO L226 Difference]: Without dead ends: 1222 [2024-11-28 02:56:38,320 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1380 GetRequests, 1375 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:56:38,321 INFO L435 NwaCegarLoop]: 1093 mSDtfsCounter, 1 mSDsluCounter, 1089 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2182 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:38,321 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2182 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:56:38,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1222 states. [2024-11-28 02:56:38,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1222 to 1222. [2024-11-28 02:56:38,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1222 states, 1210 states have (on average 1.4487603305785124) internal successors, (1753), 1210 states have internal predecessors, (1753), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:38,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1222 states to 1222 states and 1773 transitions. [2024-11-28 02:56:38,355 INFO L78 Accepts]: Start accepts. Automaton has 1222 states and 1773 transitions. Word has length 689 [2024-11-28 02:56:38,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:38,356 INFO L471 AbstractCegarLoop]: Abstraction has 1222 states and 1773 transitions. [2024-11-28 02:56:38,356 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 195.33333333333334) internal successors, (586), 3 states have internal predecessors, (586), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:56:38,356 INFO L276 IsEmpty]: Start isEmpty. Operand 1222 states and 1773 transitions. [2024-11-28 02:56:38,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 692 [2024-11-28 02:56:38,361 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:38,362 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:38,383 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2024-11-28 02:56:38,562 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:38,562 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:38,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:38,563 INFO L85 PathProgramCache]: Analyzing trace with hash 1845453547, now seen corresponding path program 1 times [2024-11-28 02:56:38,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:38,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965430286] [2024-11-28 02:56:38,563 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:38,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:38,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:39,327 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-28 02:56:39,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:39,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965430286] [2024-11-28 02:56:39,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965430286] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:39,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1999011566] [2024-11-28 02:56:39,328 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:39,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:39,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:39,330 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:39,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2024-11-28 02:56:41,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:41,186 INFO L256 TraceCheckSpWp]: Trace formula consists of 3416 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-28 02:56:41,191 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:41,230 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 281 proven. 37 refuted. 0 times theorem prover too weak. 287 trivial. 0 not checked. [2024-11-28 02:56:41,231 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:41,308 INFO L134 CoverageAnalysis]: Checked inductivity of 605 backedges. 181 proven. 1 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-28 02:56:41,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1999011566] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:56:41,308 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:56:41,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-28 02:56:41,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581720054] [2024-11-28 02:56:41,309 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:56:41,311 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 02:56:41,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:41,312 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 02:56:41,313 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:56:41,313 INFO L87 Difference]: Start difference. First operand 1222 states and 1773 transitions. Second operand has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:41,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:41,419 INFO L93 Difference]: Finished difference Result 1913 states and 2779 transitions. [2024-11-28 02:56:41,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:56:41,420 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 691 [2024-11-28 02:56:41,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:41,423 INFO L225 Difference]: With dead ends: 1913 [2024-11-28 02:56:41,423 INFO L226 Difference]: Without dead ends: 1228 [2024-11-28 02:56:41,425 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1385 GetRequests, 1377 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:56:41,425 INFO L435 NwaCegarLoop]: 1097 mSDtfsCounter, 16 mSDsluCounter, 5455 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 6552 SdHoareTripleChecker+Invalid, 59 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:41,425 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 6552 Invalid, 59 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:56:41,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1228 states. [2024-11-28 02:56:41,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1228 to 1228. [2024-11-28 02:56:41,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1228 states, 1216 states have (on average 1.446546052631579) internal successors, (1759), 1216 states have internal predecessors, (1759), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:41,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1228 states to 1228 states and 1779 transitions. [2024-11-28 02:56:41,455 INFO L78 Accepts]: Start accepts. Automaton has 1228 states and 1779 transitions. Word has length 691 [2024-11-28 02:56:41,456 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:41,456 INFO L471 AbstractCegarLoop]: Abstraction has 1228 states and 1779 transitions. [2024-11-28 02:56:41,456 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.0) internal successors, (603), 9 states have internal predecessors, (603), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:41,456 INFO L276 IsEmpty]: Start isEmpty. Operand 1228 states and 1779 transitions. [2024-11-28 02:56:41,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 698 [2024-11-28 02:56:41,461 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:41,462 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:41,482 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2024-11-28 02:56:41,662 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:41,662 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:41,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:41,663 INFO L85 PathProgramCache]: Analyzing trace with hash -100464449, now seen corresponding path program 2 times [2024-11-28 02:56:41,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:41,663 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133219025] [2024-11-28 02:56:41,663 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:56:41,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:41,846 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:56:41,846 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:56:42,105 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 2 proven. 174 refuted. 0 times theorem prover too weak. 444 trivial. 0 not checked. [2024-11-28 02:56:42,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:42,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133219025] [2024-11-28 02:56:42,105 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133219025] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:42,105 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1412554794] [2024-11-28 02:56:42,106 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:56:42,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:42,106 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:42,107 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:42,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-11-28 02:56:43,668 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:56:43,668 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:56:43,674 INFO L256 TraceCheckSpWp]: Trace formula consists of 795 conjuncts, 38 conjuncts are in the unsatisfiable core [2024-11-28 02:56:43,684 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:45,115 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 273 proven. 3 refuted. 0 times theorem prover too weak. 344 trivial. 0 not checked. [2024-11-28 02:56:45,115 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:48,601 INFO L134 CoverageAnalysis]: Checked inductivity of 620 backedges. 172 proven. 4 refuted. 0 times theorem prover too weak. 444 trivial. 0 not checked. [2024-11-28 02:56:48,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1412554794] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:56:48,601 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:56:48,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 8] total 16 [2024-11-28 02:56:48,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854094793] [2024-11-28 02:56:48,602 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:56:48,669 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2024-11-28 02:56:48,669 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:48,670 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2024-11-28 02:56:48,671 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=194, Unknown=0, NotChecked=0, Total=240 [2024-11-28 02:56:48,671 INFO L87 Difference]: Start difference. First operand 1228 states and 1779 transitions. Second operand has 16 states, 16 states have (on average 98.375) internal successors, (1574), 16 states have internal predecessors, (1574), 5 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-11-28 02:56:50,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:50,197 INFO L93 Difference]: Finished difference Result 2270 states and 3296 transitions. [2024-11-28 02:56:50,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:56:50,198 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 98.375) internal successors, (1574), 16 states have internal predecessors, (1574), 5 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) Word has length 697 [2024-11-28 02:56:50,198 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:50,201 INFO L225 Difference]: With dead ends: 2270 [2024-11-28 02:56:50,201 INFO L226 Difference]: Without dead ends: 1236 [2024-11-28 02:56:50,203 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1404 GetRequests, 1385 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=337, Unknown=0, NotChecked=0, Total=420 [2024-11-28 02:56:50,203 INFO L435 NwaCegarLoop]: 794 mSDtfsCounter, 1366 mSDsluCounter, 4735 mSDsCounter, 0 mSdLazyCounter, 2129 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1366 SdHoareTripleChecker+Valid, 5529 SdHoareTripleChecker+Invalid, 2133 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 2129 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:50,203 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1366 Valid, 5529 Invalid, 2133 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 2129 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2024-11-28 02:56:50,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1236 states. [2024-11-28 02:56:50,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1236 to 1234. [2024-11-28 02:56:50,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1234 states, 1222 states have (on average 1.4427168576104745) internal successors, (1763), 1222 states have internal predecessors, (1763), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:50,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1234 states to 1234 states and 1783 transitions. [2024-11-28 02:56:50,259 INFO L78 Accepts]: Start accepts. Automaton has 1234 states and 1783 transitions. Word has length 697 [2024-11-28 02:56:50,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:50,260 INFO L471 AbstractCegarLoop]: Abstraction has 1234 states and 1783 transitions. [2024-11-28 02:56:50,260 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 98.375) internal successors, (1574), 16 states have internal predecessors, (1574), 5 states have call successors, (25), 2 states have call predecessors, (25), 2 states have return successors, (25), 5 states have call predecessors, (25), 5 states have call successors, (25) [2024-11-28 02:56:50,260 INFO L276 IsEmpty]: Start isEmpty. Operand 1234 states and 1783 transitions. [2024-11-28 02:56:50,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 702 [2024-11-28 02:56:50,272 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:50,272 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:50,291 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2024-11-28 02:56:50,473 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:50,473 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:50,474 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:50,474 INFO L85 PathProgramCache]: Analyzing trace with hash -188486497, now seen corresponding path program 1 times [2024-11-28 02:56:50,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:50,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275630248] [2024-11-28 02:56:50,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:50,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:50,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:51,664 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-28 02:56:51,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:51,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275630248] [2024-11-28 02:56:51,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275630248] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:51,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [135733234] [2024-11-28 02:56:51,665 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:51,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:51,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:51,669 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:51,673 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-11-28 02:56:53,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:53,635 INFO L256 TraceCheckSpWp]: Trace formula consists of 3451 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-28 02:56:53,642 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:53,726 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 283 proven. 112 refuted. 0 times theorem prover too weak. 227 trivial. 0 not checked. [2024-11-28 02:56:53,726 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:53,864 INFO L134 CoverageAnalysis]: Checked inductivity of 622 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 423 trivial. 0 not checked. [2024-11-28 02:56:53,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [135733234] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:56:53,865 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:56:53,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-28 02:56:53,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265063952] [2024-11-28 02:56:53,865 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:56:53,866 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-28 02:56:53,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:53,867 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-28 02:56:53,867 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:56:53,868 INFO L87 Difference]: Start difference. First operand 1234 states and 1783 transitions. Second operand has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:54,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:54,096 INFO L93 Difference]: Finished difference Result 1936 states and 2800 transitions. [2024-11-28 02:56:54,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-28 02:56:54,097 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 701 [2024-11-28 02:56:54,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:54,101 INFO L225 Difference]: With dead ends: 1936 [2024-11-28 02:56:54,101 INFO L226 Difference]: Without dead ends: 1242 [2024-11-28 02:56:54,102 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1409 GetRequests, 1391 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:56:54,103 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 28 mSDsluCounter, 14405 mSDsCounter, 0 mSdLazyCounter, 279 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 15519 SdHoareTripleChecker+Invalid, 280 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 279 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:54,103 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 15519 Invalid, 280 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 279 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:56:54,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1242 states. [2024-11-28 02:56:54,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1242 to 1242. [2024-11-28 02:56:54,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1242 states, 1230 states have (on average 1.4398373983739838) internal successors, (1771), 1230 states have internal predecessors, (1771), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:54,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1242 states to 1242 states and 1791 transitions. [2024-11-28 02:56:54,136 INFO L78 Accepts]: Start accepts. Automaton has 1242 states and 1791 transitions. Word has length 701 [2024-11-28 02:56:54,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:54,137 INFO L471 AbstractCegarLoop]: Abstraction has 1242 states and 1791 transitions. [2024-11-28 02:56:54,137 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.05555555555556) internal successors, (631), 18 states have internal predecessors, (631), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:54,137 INFO L276 IsEmpty]: Start isEmpty. Operand 1242 states and 1791 transitions. [2024-11-28 02:56:54,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 710 [2024-11-28 02:56:54,144 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:54,145 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:54,168 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0 [2024-11-28 02:56:54,345 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:54,345 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:54,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:54,346 INFO L85 PathProgramCache]: Analyzing trace with hash -428346353, now seen corresponding path program 2 times [2024-11-28 02:56:54,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:54,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101066682] [2024-11-28 02:56:54,346 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:56:54,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:54,552 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:56:54,552 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:56:55,029 INFO L134 CoverageAnalysis]: Checked inductivity of 670 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 588 trivial. 0 not checked. [2024-11-28 02:56:55,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:55,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101066682] [2024-11-28 02:56:55,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101066682] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:56:55,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:56:55,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:56:55,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080190803] [2024-11-28 02:56:55,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:55,032 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:56:55,034 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:55,034 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:56:55,034 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:56:55,035 INFO L87 Difference]: Start difference. First operand 1242 states and 1791 transitions. Second operand has 5 states, 5 states have (on average 99.6) internal successors, (498), 5 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:56:55,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:55,141 INFO L93 Difference]: Finished difference Result 2242 states and 3246 transitions. [2024-11-28 02:56:55,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 02:56:55,141 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 99.6) internal successors, (498), 5 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 709 [2024-11-28 02:56:55,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:55,145 INFO L225 Difference]: With dead ends: 2242 [2024-11-28 02:56:55,145 INFO L226 Difference]: Without dead ends: 1538 [2024-11-28 02:56:55,146 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:56:55,147 INFO L435 NwaCegarLoop]: 1088 mSDtfsCounter, 142 mSDsluCounter, 3255 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 4343 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:55,147 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 4343 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:56:55,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1538 states. [2024-11-28 02:56:55,176 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1538 to 1534. [2024-11-28 02:56:55,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1534 states, 1522 states have (on average 1.447437582128778) internal successors, (2203), 1522 states have internal predecessors, (2203), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:55,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1534 states to 1534 states and 2223 transitions. [2024-11-28 02:56:55,180 INFO L78 Accepts]: Start accepts. Automaton has 1534 states and 2223 transitions. Word has length 709 [2024-11-28 02:56:55,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:55,180 INFO L471 AbstractCegarLoop]: Abstraction has 1534 states and 2223 transitions. [2024-11-28 02:56:55,181 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 99.6) internal successors, (498), 5 states have internal predecessors, (498), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:56:55,181 INFO L276 IsEmpty]: Start isEmpty. Operand 1534 states and 2223 transitions. [2024-11-28 02:56:55,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 712 [2024-11-28 02:56:55,187 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:55,188 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:55,189 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable36 [2024-11-28 02:56:55,189 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:55,190 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:55,190 INFO L85 PathProgramCache]: Analyzing trace with hash -2125747477, now seen corresponding path program 1 times [2024-11-28 02:56:55,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:55,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530059548] [2024-11-28 02:56:55,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:55,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:55,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:56,055 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:56:56,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:56,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530059548] [2024-11-28 02:56:56,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530059548] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:56:56,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [673901540] [2024-11-28 02:56:56,055 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:56,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:56:56,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:56:56,057 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:56:56,058 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-11-28 02:56:58,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:56:58,165 INFO L256 TraceCheckSpWp]: Trace formula consists of 3493 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-28 02:56:58,174 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:56:58,217 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 284 proven. 37 refuted. 0 times theorem prover too weak. 350 trivial. 0 not checked. [2024-11-28 02:56:58,217 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:56:58,282 INFO L134 CoverageAnalysis]: Checked inductivity of 671 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:56:58,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [673901540] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:56:58,282 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:56:58,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-28 02:56:58,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980868133] [2024-11-28 02:56:58,282 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:56:58,283 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 02:56:58,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:58,284 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 02:56:58,284 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:56:58,284 INFO L87 Difference]: Start difference. First operand 1534 states and 2223 transitions. Second operand has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:58,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:58,365 INFO L93 Difference]: Finished difference Result 2388 states and 3461 transitions. [2024-11-28 02:56:58,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:56:58,365 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 711 [2024-11-28 02:56:58,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:58,369 INFO L225 Difference]: With dead ends: 2388 [2024-11-28 02:56:58,370 INFO L226 Difference]: Without dead ends: 1540 [2024-11-28 02:56:58,371 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1425 GetRequests, 1417 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:56:58,371 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 15 mSDsluCounter, 5450 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 6546 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:58,372 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 6546 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:56:58,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1540 states. [2024-11-28 02:56:58,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1540 to 1540. [2024-11-28 02:56:58,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1540 states, 1528 states have (on average 1.4456806282722514) internal successors, (2209), 1528 states have internal predecessors, (2209), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:58,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1540 states to 1540 states and 2229 transitions. [2024-11-28 02:56:58,407 INFO L78 Accepts]: Start accepts. Automaton has 1540 states and 2229 transitions. Word has length 711 [2024-11-28 02:56:58,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:58,408 INFO L471 AbstractCegarLoop]: Abstraction has 1540 states and 2229 transitions. [2024-11-28 02:56:58,408 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.66666666666667) internal successors, (609), 9 states have internal predecessors, (609), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:56:58,408 INFO L276 IsEmpty]: Start isEmpty. Operand 1540 states and 2229 transitions. [2024-11-28 02:56:58,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-11-28 02:56:58,414 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:58,414 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:58,437 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2024-11-28 02:56:58,615 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable37 [2024-11-28 02:56:58,615 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:58,616 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:58,616 INFO L85 PathProgramCache]: Analyzing trace with hash -777066913, now seen corresponding path program 2 times [2024-11-28 02:56:58,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:58,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962996067] [2024-11-28 02:56:58,617 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:56:58,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:58,808 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:56:58,808 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:56:59,280 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 83 proven. 0 refuted. 0 times theorem prover too weak. 603 trivial. 0 not checked. [2024-11-28 02:56:59,280 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:56:59,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962996067] [2024-11-28 02:56:59,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962996067] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:56:59,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:56:59,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:56:59,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [316947534] [2024-11-28 02:56:59,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:56:59,282 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:56:59,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:56:59,282 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:56:59,283 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:56:59,283 INFO L87 Difference]: Start difference. First operand 1540 states and 2229 transitions. Second operand has 8 states, 8 states have (on average 62.5) internal successors, (500), 8 states have internal predecessors, (500), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:56:59,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:56:59,380 INFO L93 Difference]: Finished difference Result 2402 states and 3475 transitions. [2024-11-28 02:56:59,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:56:59,381 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 62.5) internal successors, (500), 8 states have internal predecessors, (500), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 717 [2024-11-28 02:56:59,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:56:59,384 INFO L225 Difference]: With dead ends: 2402 [2024-11-28 02:56:59,384 INFO L226 Difference]: Without dead ends: 1548 [2024-11-28 02:56:59,385 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:56:59,386 INFO L435 NwaCegarLoop]: 1087 mSDtfsCounter, 141 mSDsluCounter, 6499 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 7586 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:56:59,386 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 7586 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:56:59,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1548 states. [2024-11-28 02:56:59,418 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1548 to 1541. [2024-11-28 02:56:59,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1541 states, 1529 states have (on average 1.4460431654676258) internal successors, (2211), 1529 states have internal predecessors, (2211), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:56:59,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 1541 states and 2231 transitions. [2024-11-28 02:56:59,422 INFO L78 Accepts]: Start accepts. Automaton has 1541 states and 2231 transitions. Word has length 717 [2024-11-28 02:56:59,423 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:56:59,423 INFO L471 AbstractCegarLoop]: Abstraction has 1541 states and 2231 transitions. [2024-11-28 02:56:59,423 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 62.5) internal successors, (500), 8 states have internal predecessors, (500), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:56:59,423 INFO L276 IsEmpty]: Start isEmpty. Operand 1541 states and 2231 transitions. [2024-11-28 02:56:59,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 718 [2024-11-28 02:56:59,429 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:56:59,429 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:56:59,429 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2024-11-28 02:56:59,430 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:56:59,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:56:59,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1127888828, now seen corresponding path program 1 times [2024-11-28 02:56:59,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:56:59,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132837527] [2024-11-28 02:56:59,431 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:56:59,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:56:59,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:00,605 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:57:00,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:00,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132837527] [2024-11-28 02:57:00,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132837527] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:00,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [894725300] [2024-11-28 02:57:00,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:00,606 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:00,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:00,607 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:00,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-11-28 02:57:02,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:02,774 INFO L256 TraceCheckSpWp]: Trace formula consists of 3520 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-28 02:57:02,784 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:03,078 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 108 proven. 24 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-11-28 02:57:03,079 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:03,280 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 108 proven. 0 refuted. 0 times theorem prover too weak. 577 trivial. 0 not checked. [2024-11-28 02:57:03,281 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [894725300] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:03,281 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:57:03,281 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7, 8] total 16 [2024-11-28 02:57:03,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927409692] [2024-11-28 02:57:03,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:57:03,283 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:57:03,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:03,284 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:57:03,285 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2024-11-28 02:57:03,285 INFO L87 Difference]: Start difference. First operand 1541 states and 2231 transitions. Second operand has 5 states, 5 states have (on average 105.0) internal successors, (525), 5 states have internal predecessors, (525), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:57:03,354 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:03,354 INFO L93 Difference]: Finished difference Result 2640 states and 3825 transitions. [2024-11-28 02:57:03,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 02:57:03,355 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 105.0) internal successors, (525), 5 states have internal predecessors, (525), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 717 [2024-11-28 02:57:03,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:03,359 INFO L225 Difference]: With dead ends: 2640 [2024-11-28 02:57:03,359 INFO L226 Difference]: Without dead ends: 1633 [2024-11-28 02:57:03,361 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1439 GetRequests, 1425 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=38, Invalid=202, Unknown=0, NotChecked=0, Total=240 [2024-11-28 02:57:03,361 INFO L435 NwaCegarLoop]: 1091 mSDtfsCounter, 40 mSDsluCounter, 3261 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 4352 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:03,361 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 4352 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:57:03,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1633 states. [2024-11-28 02:57:03,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1633 to 1633. [2024-11-28 02:57:03,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1633 states, 1621 states have (on average 1.4441702652683528) internal successors, (2341), 1621 states have internal predecessors, (2341), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:57:03,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1633 states to 1633 states and 2361 transitions. [2024-11-28 02:57:03,429 INFO L78 Accepts]: Start accepts. Automaton has 1633 states and 2361 transitions. Word has length 717 [2024-11-28 02:57:03,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:03,430 INFO L471 AbstractCegarLoop]: Abstraction has 1633 states and 2361 transitions. [2024-11-28 02:57:03,431 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 105.0) internal successors, (525), 5 states have internal predecessors, (525), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:57:03,431 INFO L276 IsEmpty]: Start isEmpty. Operand 1633 states and 2361 transitions. [2024-11-28 02:57:03,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 719 [2024-11-28 02:57:03,444 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:03,444 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:03,470 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0 [2024-11-28 02:57:03,645 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable39 [2024-11-28 02:57:03,646 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:03,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:03,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1640838573, now seen corresponding path program 1 times [2024-11-28 02:57:03,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:03,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986168785] [2024-11-28 02:57:03,647 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:03,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:04,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:04,946 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 183 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:57:04,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:04,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986168785] [2024-11-28 02:57:04,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986168785] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:04,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [578158435] [2024-11-28 02:57:04,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:04,947 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:04,947 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:04,949 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:04,950 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-11-28 02:57:07,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:07,497 INFO L256 TraceCheckSpWp]: Trace formula consists of 3523 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-11-28 02:57:07,504 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:07,618 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 110 proven. 24 refuted. 0 times theorem prover too weak. 551 trivial. 0 not checked. [2024-11-28 02:57:07,618 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:07,695 INFO L134 CoverageAnalysis]: Checked inductivity of 685 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 575 trivial. 0 not checked. [2024-11-28 02:57:07,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [578158435] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:07,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 02:57:07,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7, 7] total 14 [2024-11-28 02:57:07,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359628113] [2024-11-28 02:57:07,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:57:07,696 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:57:07,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:07,697 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:57:07,697 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2024-11-28 02:57:07,697 INFO L87 Difference]: Start difference. First operand 1633 states and 2361 transitions. Second operand has 4 states, 4 states have (on average 132.0) internal successors, (528), 4 states have internal predecessors, (528), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:57:07,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:07,734 INFO L93 Difference]: Finished difference Result 2884 states and 4179 transitions. [2024-11-28 02:57:07,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:57:07,735 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 132.0) internal successors, (528), 4 states have internal predecessors, (528), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 718 [2024-11-28 02:57:07,735 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:07,738 INFO L225 Difference]: With dead ends: 2884 [2024-11-28 02:57:07,738 INFO L226 Difference]: Without dead ends: 1637 [2024-11-28 02:57:07,740 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1441 GetRequests, 1429 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=149, Unknown=0, NotChecked=0, Total=182 [2024-11-28 02:57:07,740 INFO L435 NwaCegarLoop]: 1092 mSDtfsCounter, 0 mSDsluCounter, 2174 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3266 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:07,740 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3266 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:57:07,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1637 states. [2024-11-28 02:57:07,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1637 to 1637. [2024-11-28 02:57:07,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1637 states, 1625 states have (on average 1.4430769230769231) internal successors, (2345), 1625 states have internal predecessors, (2345), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:57:07,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1637 states to 1637 states and 2365 transitions. [2024-11-28 02:57:07,777 INFO L78 Accepts]: Start accepts. Automaton has 1637 states and 2365 transitions. Word has length 718 [2024-11-28 02:57:07,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:07,778 INFO L471 AbstractCegarLoop]: Abstraction has 1637 states and 2365 transitions. [2024-11-28 02:57:07,778 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 132.0) internal successors, (528), 4 states have internal predecessors, (528), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 02:57:07,778 INFO L276 IsEmpty]: Start isEmpty. Operand 1637 states and 2365 transitions. [2024-11-28 02:57:07,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 719 [2024-11-28 02:57:07,784 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:07,784 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:07,807 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2024-11-28 02:57:07,985 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable40 [2024-11-28 02:57:07,985 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:07,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:07,986 INFO L85 PathProgramCache]: Analyzing trace with hash 2000077144, now seen corresponding path program 1 times [2024-11-28 02:57:07,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:07,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123545351] [2024-11-28 02:57:07,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:07,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:08,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:09,164 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:57:09,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:09,164 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123545351] [2024-11-28 02:57:09,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123545351] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:09,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1596255537] [2024-11-28 02:57:09,165 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:09,165 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:09,165 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:09,166 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:09,169 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-11-28 02:57:11,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:11,434 INFO L256 TraceCheckSpWp]: Trace formula consists of 3521 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-28 02:57:11,439 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:11,523 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 284 proven. 112 refuted. 0 times theorem prover too weak. 290 trivial. 0 not checked. [2024-11-28 02:57:11,523 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:11,650 INFO L134 CoverageAnalysis]: Checked inductivity of 686 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 486 trivial. 0 not checked. [2024-11-28 02:57:11,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1596255537] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:57:11,650 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:57:11,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-28 02:57:11,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908618006] [2024-11-28 02:57:11,651 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:57:11,651 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-28 02:57:11,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:11,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-28 02:57:11,652 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:57:11,652 INFO L87 Difference]: Start difference. First operand 1637 states and 2365 transitions. Second operand has 18 states, 18 states have (on average 35.22222222222222) internal successors, (634), 18 states have internal predecessors, (634), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:11,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:11,851 INFO L93 Difference]: Finished difference Result 2550 states and 3684 transitions. [2024-11-28 02:57:11,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-28 02:57:11,852 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.22222222222222) internal successors, (634), 18 states have internal predecessors, (634), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 718 [2024-11-28 02:57:11,852 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:11,854 INFO L225 Difference]: With dead ends: 2550 [2024-11-28 02:57:11,854 INFO L226 Difference]: Without dead ends: 1645 [2024-11-28 02:57:11,855 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1443 GetRequests, 1425 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:57:11,855 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 28 mSDsluCounter, 11075 mSDsCounter, 0 mSdLazyCounter, 234 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 12189 SdHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 234 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:11,856 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 12189 Invalid, 235 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 234 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:57:11,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1645 states. [2024-11-28 02:57:11,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1645 to 1645. [2024-11-28 02:57:11,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1645 states, 1633 states have (on average 1.4409063074096755) internal successors, (2353), 1633 states have internal predecessors, (2353), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 02:57:11,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 2373 transitions. [2024-11-28 02:57:11,895 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 2373 transitions. Word has length 718 [2024-11-28 02:57:11,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:11,895 INFO L471 AbstractCegarLoop]: Abstraction has 1645 states and 2373 transitions. [2024-11-28 02:57:11,896 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.22222222222222) internal successors, (634), 18 states have internal predecessors, (634), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:11,896 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 2373 transitions. [2024-11-28 02:57:11,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 727 [2024-11-28 02:57:11,902 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:11,902 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:11,925 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0 [2024-11-28 02:57:12,102 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:12,103 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:12,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:12,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1225894040, now seen corresponding path program 2 times [2024-11-28 02:57:12,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:12,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463388732] [2024-11-28 02:57:12,104 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:57:12,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:12,365 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:57:12,365 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:57:13,465 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 105 proven. 76 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-11-28 02:57:13,465 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:13,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463388732] [2024-11-28 02:57:13,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463388732] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:13,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [167613407] [2024-11-28 02:57:13,466 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:57:13,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:13,466 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:13,470 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:13,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2024-11-28 02:57:15,555 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:57:15,555 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:57:15,562 INFO L256 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 80 conjuncts are in the unsatisfiable core [2024-11-28 02:57:15,572 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:17,816 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 105 proven. 76 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-11-28 02:57:17,816 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:21,654 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 102 proven. 79 refuted. 0 times theorem prover too weak. 553 trivial. 0 not checked. [2024-11-28 02:57:21,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [167613407] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:57:21,654 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:57:21,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 10, 11] total 25 [2024-11-28 02:57:21,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692010543] [2024-11-28 02:57:21,655 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:57:21,656 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 25 states [2024-11-28 02:57:21,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:21,658 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-11-28 02:57:21,658 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=490, Unknown=0, NotChecked=0, Total=600 [2024-11-28 02:57:21,659 INFO L87 Difference]: Start difference. First operand 1645 states and 2373 transitions. Second operand has 25 states, 25 states have (on average 62.36) internal successors, (1559), 25 states have internal predecessors, (1559), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-11-28 02:57:25,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:25,853 INFO L93 Difference]: Finished difference Result 3620 states and 5230 transitions. [2024-11-28 02:57:25,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-11-28 02:57:25,854 INFO L78 Accepts]: Start accepts. Automaton has has 25 states, 25 states have (on average 62.36) internal successors, (1559), 25 states have internal predecessors, (1559), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) Word has length 726 [2024-11-28 02:57:25,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:25,857 INFO L225 Difference]: With dead ends: 3620 [2024-11-28 02:57:25,857 INFO L226 Difference]: Without dead ends: 2343 [2024-11-28 02:57:25,858 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1467 GetRequests, 1435 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 274 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=213, Invalid=909, Unknown=0, NotChecked=0, Total=1122 [2024-11-28 02:57:25,859 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 1311 mSDsluCounter, 11719 mSDsCounter, 0 mSdLazyCounter, 5285 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1311 SdHoareTripleChecker+Valid, 12516 SdHoareTripleChecker+Invalid, 5297 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 5285 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.8s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:25,859 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1311 Valid, 12516 Invalid, 5297 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 5285 Invalid, 0 Unknown, 0 Unchecked, 3.8s Time] [2024-11-28 02:57:25,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2343 states. [2024-11-28 02:57:25,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2343 to 2335. [2024-11-28 02:57:25,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2335 states, 2303 states have (on average 1.4342162396873643) internal successors, (3303), 2303 states have internal predecessors, (3303), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-28 02:57:25,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2335 states to 2335 states and 3363 transitions. [2024-11-28 02:57:25,894 INFO L78 Accepts]: Start accepts. Automaton has 2335 states and 3363 transitions. Word has length 726 [2024-11-28 02:57:25,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:25,894 INFO L471 AbstractCegarLoop]: Abstraction has 2335 states and 3363 transitions. [2024-11-28 02:57:25,895 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 25 states, 25 states have (on average 62.36) internal successors, (1559), 25 states have internal predecessors, (1559), 6 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 6 states have call predecessors, (30), 6 states have call successors, (30) [2024-11-28 02:57:25,895 INFO L276 IsEmpty]: Start isEmpty. Operand 2335 states and 3363 transitions. [2024-11-28 02:57:25,900 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 727 [2024-11-28 02:57:25,900 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:25,901 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:25,912 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0 [2024-11-28 02:57:26,101 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:26,101 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:26,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:26,102 INFO L85 PathProgramCache]: Analyzing trace with hash -174189528, now seen corresponding path program 1 times [2024-11-28 02:57:26,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:26,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018268824] [2024-11-28 02:57:26,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:26,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:26,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:27,012 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-28 02:57:27,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:27,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018268824] [2024-11-28 02:57:27,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018268824] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:27,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1121346894] [2024-11-28 02:57:27,013 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:27,013 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:27,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:27,015 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:27,016 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2024-11-28 02:57:29,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:29,433 INFO L256 TraceCheckSpWp]: Trace formula consists of 3557 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-28 02:57:29,439 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:29,477 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 284 proven. 37 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2024-11-28 02:57:29,477 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:29,553 INFO L134 CoverageAnalysis]: Checked inductivity of 734 backedges. 184 proven. 1 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-28 02:57:29,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1121346894] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:57:29,554 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:57:29,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-28 02:57:29,554 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488791001] [2024-11-28 02:57:29,554 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:57:29,555 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 02:57:29,556 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:29,556 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 02:57:29,557 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:57:29,557 INFO L87 Difference]: Start difference. First operand 2335 states and 3363 transitions. Second operand has 9 states, 9 states have (on average 67.77777777777777) internal successors, (610), 9 states have internal predecessors, (610), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:29,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:29,673 INFO L93 Difference]: Finished difference Result 3599 states and 5182 transitions. [2024-11-28 02:57:29,674 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:57:29,674 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 67.77777777777777) internal successors, (610), 9 states have internal predecessors, (610), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 726 [2024-11-28 02:57:29,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:29,677 INFO L225 Difference]: With dead ends: 3599 [2024-11-28 02:57:29,678 INFO L226 Difference]: Without dead ends: 2341 [2024-11-28 02:57:29,680 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1455 GetRequests, 1447 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:57:29,680 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 14 mSDsluCounter, 4358 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 14 SdHoareTripleChecker+Valid, 5454 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:29,680 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [14 Valid, 5454 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:57:29,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2341 states. [2024-11-28 02:57:29,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2341 to 2341. [2024-11-28 02:57:29,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2341 states, 2309 states have (on average 1.43308791684712) internal successors, (3309), 2309 states have internal predecessors, (3309), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-28 02:57:29,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2341 states to 2341 states and 3369 transitions. [2024-11-28 02:57:29,734 INFO L78 Accepts]: Start accepts. Automaton has 2341 states and 3369 transitions. Word has length 726 [2024-11-28 02:57:29,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:29,735 INFO L471 AbstractCegarLoop]: Abstraction has 2341 states and 3369 transitions. [2024-11-28 02:57:29,735 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 67.77777777777777) internal successors, (610), 9 states have internal predecessors, (610), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:29,735 INFO L276 IsEmpty]: Start isEmpty. Operand 2341 states and 3369 transitions. [2024-11-28 02:57:29,741 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 733 [2024-11-28 02:57:29,742 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:29,742 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:29,765 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0 [2024-11-28 02:57:29,942 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:29,943 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:29,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:29,943 INFO L85 PathProgramCache]: Analyzing trace with hash -877321420, now seen corresponding path program 2 times [2024-11-28 02:57:29,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:29,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [823536983] [2024-11-28 02:57:29,944 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:57:29,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:30,231 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:57:30,231 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:57:31,406 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 4 proven. 108 refuted. 0 times theorem prover too weak. 637 trivial. 0 not checked. [2024-11-28 02:57:31,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:31,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [823536983] [2024-11-28 02:57:31,406 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [823536983] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:31,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [805074893] [2024-11-28 02:57:31,407 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:57:31,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:31,407 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:31,410 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:31,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2024-11-28 02:57:33,636 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 02:57:33,636 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:57:33,712 INFO L256 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 90 conjuncts are in the unsatisfiable core [2024-11-28 02:57:33,722 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:38,396 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 8 proven. 108 refuted. 0 times theorem prover too weak. 633 trivial. 0 not checked. [2024-11-28 02:57:38,397 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:46,913 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 69 proven. 112 refuted. 0 times theorem prover too weak. 568 trivial. 0 not checked. [2024-11-28 02:57:46,913 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [805074893] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:57:46,913 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:57:46,913 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 21, 20] total 47 [2024-11-28 02:57:46,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794622672] [2024-11-28 02:57:46,914 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:57:46,914 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 47 states [2024-11-28 02:57:46,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:46,915 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2024-11-28 02:57:46,916 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=1900, Unknown=0, NotChecked=0, Total=2162 [2024-11-28 02:57:46,916 INFO L87 Difference]: Start difference. First operand 2341 states and 3369 transitions. Second operand has 47 states, 47 states have (on average 34.87234042553192) internal successors, (1639), 47 states have internal predecessors, (1639), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2024-11-28 02:57:51,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:51,812 INFO L93 Difference]: Finished difference Result 5958 states and 8647 transitions. [2024-11-28 02:57:51,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2024-11-28 02:57:51,813 INFO L78 Accepts]: Start accepts. Automaton has has 47 states, 47 states have (on average 34.87234042553192) internal successors, (1639), 47 states have internal predecessors, (1639), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) Word has length 732 [2024-11-28 02:57:51,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:51,817 INFO L225 Difference]: With dead ends: 5958 [2024-11-28 02:57:51,817 INFO L226 Difference]: Without dead ends: 4350 [2024-11-28 02:57:51,820 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1504 GetRequests, 1428 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1459 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=872, Invalid=5134, Unknown=0, NotChecked=0, Total=6006 [2024-11-28 02:57:51,821 INFO L435 NwaCegarLoop]: 768 mSDtfsCounter, 16458 mSDsluCounter, 11365 mSDsCounter, 0 mSdLazyCounter, 4910 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16458 SdHoareTripleChecker+Valid, 12133 SdHoareTripleChecker+Invalid, 4927 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 4910 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.5s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:51,821 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16458 Valid, 12133 Invalid, 4927 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 4910 Invalid, 0 Unknown, 0 Unchecked, 3.5s Time] [2024-11-28 02:57:51,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4350 states. [2024-11-28 02:57:51,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4350 to 2369. [2024-11-28 02:57:51,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2369 states, 2337 states have (on average 1.428326914848096) internal successors, (3338), 2337 states have internal predecessors, (3338), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-28 02:57:51,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2369 states to 2369 states and 3398 transitions. [2024-11-28 02:57:51,888 INFO L78 Accepts]: Start accepts. Automaton has 2369 states and 3398 transitions. Word has length 732 [2024-11-28 02:57:51,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:51,889 INFO L471 AbstractCegarLoop]: Abstraction has 2369 states and 3398 transitions. [2024-11-28 02:57:51,889 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 47 states, 47 states have (on average 34.87234042553192) internal successors, (1639), 47 states have internal predecessors, (1639), 4 states have call successors, (20), 1 states have call predecessors, (20), 1 states have return successors, (20), 4 states have call predecessors, (20), 4 states have call successors, (20) [2024-11-28 02:57:51,889 INFO L276 IsEmpty]: Start isEmpty. Operand 2369 states and 3398 transitions. [2024-11-28 02:57:51,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 734 [2024-11-28 02:57:51,896 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:51,896 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:51,915 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Ended with exit code 0 [2024-11-28 02:57:52,097 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable44 [2024-11-28 02:57:52,097 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:52,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:52,098 INFO L85 PathProgramCache]: Analyzing trace with hash 137386242, now seen corresponding path program 1 times [2024-11-28 02:57:52,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:52,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827454275] [2024-11-28 02:57:52,098 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:52,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:52,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:53,134 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-28 02:57:53,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:53,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827454275] [2024-11-28 02:57:53,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827454275] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:53,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1910511193] [2024-11-28 02:57:53,134 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:53,134 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:53,134 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:53,136 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:53,137 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2024-11-28 02:57:55,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:55,707 INFO L256 TraceCheckSpWp]: Trace formula consists of 3585 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-28 02:57:55,715 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:57:55,799 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 284 proven. 112 refuted. 0 times theorem prover too weak. 353 trivial. 0 not checked. [2024-11-28 02:57:55,799 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:57:55,941 INFO L134 CoverageAnalysis]: Checked inductivity of 749 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 549 trivial. 0 not checked. [2024-11-28 02:57:55,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1910511193] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:57:55,941 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:57:55,941 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-28 02:57:55,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1367470513] [2024-11-28 02:57:55,942 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:57:55,942 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-28 02:57:55,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:55,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-28 02:57:55,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:57:55,943 INFO L87 Difference]: Start difference. First operand 2369 states and 3398 transitions. Second operand has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:56,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:56,217 INFO L93 Difference]: Finished difference Result 3657 states and 5243 transitions. [2024-11-28 02:57:56,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-28 02:57:56,218 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 733 [2024-11-28 02:57:56,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:56,221 INFO L225 Difference]: With dead ends: 3657 [2024-11-28 02:57:56,221 INFO L226 Difference]: Without dead ends: 2377 [2024-11-28 02:57:56,223 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1473 GetRequests, 1455 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:57:56,223 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 28 mSDsluCounter, 14405 mSDsCounter, 0 mSdLazyCounter, 280 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 15519 SdHoareTripleChecker+Invalid, 281 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 280 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:56,223 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 15519 Invalid, 281 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 280 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:57:56,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2377 states. [2024-11-28 02:57:56,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2377 to 2377. [2024-11-28 02:57:56,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2377 states, 2345 states have (on average 1.4268656716417911) internal successors, (3346), 2345 states have internal predecessors, (3346), 30 states have call successors, (30), 1 states have call predecessors, (30), 1 states have return successors, (30), 30 states have call predecessors, (30), 30 states have call successors, (30) [2024-11-28 02:57:56,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2377 states to 2377 states and 3406 transitions. [2024-11-28 02:57:56,265 INFO L78 Accepts]: Start accepts. Automaton has 2377 states and 3406 transitions. Word has length 733 [2024-11-28 02:57:56,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:56,265 INFO L471 AbstractCegarLoop]: Abstraction has 2377 states and 3406 transitions. [2024-11-28 02:57:56,265 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.27777777777778) internal successors, (635), 18 states have internal predecessors, (635), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:57:56,266 INFO L276 IsEmpty]: Start isEmpty. Operand 2377 states and 3406 transitions. [2024-11-28 02:57:56,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 742 [2024-11-28 02:57:56,271 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:56,271 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:56,296 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Ended with exit code 0 [2024-11-28 02:57:56,471 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable45 [2024-11-28 02:57:56,472 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:56,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:56,472 INFO L85 PathProgramCache]: Analyzing trace with hash -900221710, now seen corresponding path program 2 times [2024-11-28 02:57:56,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:56,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351080327] [2024-11-28 02:57:56,472 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:57:56,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:56,999 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 02:57:56,999 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:57:58,040 INFO L134 CoverageAnalysis]: Checked inductivity of 797 backedges. 184 proven. 0 refuted. 0 times theorem prover too weak. 613 trivial. 0 not checked. [2024-11-28 02:57:58,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:58,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351080327] [2024-11-28 02:57:58,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351080327] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:57:58,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:57:58,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:57:58,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231775931] [2024-11-28 02:57:58,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:57:58,041 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:57:58,041 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:57:58,042 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:57:58,043 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:57:58,043 INFO L87 Difference]: Start difference. First operand 2377 states and 3406 transitions. Second operand has 7 states, 7 states have (on average 85.14285714285714) internal successors, (596), 7 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:57:58,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:57:58,701 INFO L93 Difference]: Finished difference Result 5347 states and 7663 transitions. [2024-11-28 02:57:58,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:57:58,702 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.14285714285714) internal successors, (596), 7 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 741 [2024-11-28 02:57:58,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:57:58,706 INFO L225 Difference]: With dead ends: 5347 [2024-11-28 02:57:58,706 INFO L226 Difference]: Without dead ends: 3658 [2024-11-28 02:57:58,708 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:57:58,709 INFO L435 NwaCegarLoop]: 1851 mSDtfsCounter, 1326 mSDsluCounter, 6949 mSDsCounter, 0 mSdLazyCounter, 586 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1326 SdHoareTripleChecker+Valid, 8800 SdHoareTripleChecker+Invalid, 594 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 586 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-28 02:57:58,709 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1326 Valid, 8800 Invalid, 594 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 586 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-28 02:57:58,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3658 states. [2024-11-28 02:57:58,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3658 to 3085. [2024-11-28 02:57:58,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3085 states, 3038 states have (on average 1.4210006583278472) internal successors, (4317), 3038 states have internal predecessors, (4317), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:57:58,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3085 states to 3085 states and 4407 transitions. [2024-11-28 02:57:58,758 INFO L78 Accepts]: Start accepts. Automaton has 3085 states and 4407 transitions. Word has length 741 [2024-11-28 02:57:58,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:57:58,759 INFO L471 AbstractCegarLoop]: Abstraction has 3085 states and 4407 transitions. [2024-11-28 02:57:58,759 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.14285714285714) internal successors, (596), 7 states have internal predecessors, (596), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:57:58,759 INFO L276 IsEmpty]: Start isEmpty. Operand 3085 states and 4407 transitions. [2024-11-28 02:57:58,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 743 [2024-11-28 02:57:58,764 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:57:58,765 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:57:58,765 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46 [2024-11-28 02:57:58,765 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:57:58,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:57:58,765 INFO L85 PathProgramCache]: Analyzing trace with hash -1239439450, now seen corresponding path program 1 times [2024-11-28 02:57:58,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:57:58,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839195137] [2024-11-28 02:57:58,765 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:58,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:57:59,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:57:59,639 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-28 02:57:59,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:57:59,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839195137] [2024-11-28 02:57:59,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839195137] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:57:59,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1705212655] [2024-11-28 02:57:59,639 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:57:59,640 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:57:59,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:57:59,643 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:57:59,645 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2024-11-28 02:58:02,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:02,330 INFO L256 TraceCheckSpWp]: Trace formula consists of 3624 conjuncts, 12 conjuncts are in the unsatisfiable core [2024-11-28 02:58:02,336 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:58:02,367 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 285 proven. 37 refuted. 0 times theorem prover too weak. 476 trivial. 0 not checked. [2024-11-28 02:58:02,367 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:58:02,425 INFO L134 CoverageAnalysis]: Checked inductivity of 798 backedges. 185 proven. 1 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-28 02:58:02,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1705212655] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:58:02,426 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:58:02,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6, 4] total 9 [2024-11-28 02:58:02,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116807825] [2024-11-28 02:58:02,426 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:58:02,427 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 02:58:02,427 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:02,427 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 02:58:02,427 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:58:02,428 INFO L87 Difference]: Start difference. First operand 3085 states and 4407 transitions. Second operand has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:58:02,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:02,520 INFO L93 Difference]: Finished difference Result 5093 states and 7267 transitions. [2024-11-28 02:58:02,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:58:02,521 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 742 [2024-11-28 02:58:02,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:02,524 INFO L225 Difference]: With dead ends: 5093 [2024-11-28 02:58:02,524 INFO L226 Difference]: Without dead ends: 3097 [2024-11-28 02:58:02,526 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1487 GetRequests, 1479 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:58:02,526 INFO L435 NwaCegarLoop]: 1096 mSDtfsCounter, 15 mSDsluCounter, 4358 mSDsCounter, 0 mSdLazyCounter, 51 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 5454 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 51 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:02,527 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 5454 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 51 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:58:02,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3097 states. [2024-11-28 02:58:02,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3097 to 3097. [2024-11-28 02:58:02,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3097 states, 3050 states have (on average 1.419344262295082) internal successors, (4329), 3050 states have internal predecessors, (4329), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:02,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3097 states to 3097 states and 4419 transitions. [2024-11-28 02:58:02,604 INFO L78 Accepts]: Start accepts. Automaton has 3097 states and 4419 transitions. Word has length 742 [2024-11-28 02:58:02,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:02,604 INFO L471 AbstractCegarLoop]: Abstraction has 3097 states and 4419 transitions. [2024-11-28 02:58:02,605 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 68.0) internal successors, (612), 9 states have internal predecessors, (612), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:58:02,605 INFO L276 IsEmpty]: Start isEmpty. Operand 3097 states and 4419 transitions. [2024-11-28 02:58:02,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 749 [2024-11-28 02:58:02,613 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:02,613 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:02,640 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Ended with exit code 0 [2024-11-28 02:58:02,814 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable47 [2024-11-28 02:58:02,814 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:02,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:02,815 INFO L85 PathProgramCache]: Analyzing trace with hash 1064618610, now seen corresponding path program 2 times [2024-11-28 02:58:02,815 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:02,815 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007081616] [2024-11-28 02:58:02,815 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:58:02,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:03,306 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 02:58:03,306 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:58:04,329 INFO L134 CoverageAnalysis]: Checked inductivity of 813 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 628 trivial. 0 not checked. [2024-11-28 02:58:04,329 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:04,329 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007081616] [2024-11-28 02:58:04,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007081616] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:04,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:04,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:58:04,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077761446] [2024-11-28 02:58:04,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:04,330 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:58:04,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:04,331 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:58:04,331 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:58:04,331 INFO L87 Difference]: Start difference. First operand 3097 states and 4419 transitions. Second operand has 7 states, 7 states have (on average 85.28571428571429) internal successors, (597), 7 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:05,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:05,691 INFO L93 Difference]: Finished difference Result 5678 states and 8103 transitions. [2024-11-28 02:58:05,691 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:58:05,691 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 85.28571428571429) internal successors, (597), 7 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 748 [2024-11-28 02:58:05,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:05,696 INFO L225 Difference]: With dead ends: 5678 [2024-11-28 02:58:05,696 INFO L226 Difference]: Without dead ends: 3670 [2024-11-28 02:58:05,698 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:58:05,698 INFO L435 NwaCegarLoop]: 1413 mSDtfsCounter, 1520 mSDsluCounter, 5010 mSDsCounter, 0 mSdLazyCounter, 2203 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1520 SdHoareTripleChecker+Valid, 6423 SdHoareTripleChecker+Invalid, 2203 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 2203 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:05,699 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1520 Valid, 6423 Invalid, 2203 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 2203 Invalid, 0 Unknown, 0 Unchecked, 1.2s Time] [2024-11-28 02:58:05,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3670 states. [2024-11-28 02:58:05,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3670 to 3099. [2024-11-28 02:58:05,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3099 states, 3052 states have (on average 1.4190694626474443) internal successors, (4331), 3052 states have internal predecessors, (4331), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:05,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3099 states to 3099 states and 4421 transitions. [2024-11-28 02:58:05,748 INFO L78 Accepts]: Start accepts. Automaton has 3099 states and 4421 transitions. Word has length 748 [2024-11-28 02:58:05,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:05,749 INFO L471 AbstractCegarLoop]: Abstraction has 3099 states and 4421 transitions. [2024-11-28 02:58:05,749 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 85.28571428571429) internal successors, (597), 7 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:05,749 INFO L276 IsEmpty]: Start isEmpty. Operand 3099 states and 4421 transitions. [2024-11-28 02:58:05,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 749 [2024-11-28 02:58:05,754 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:05,755 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:05,755 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable48 [2024-11-28 02:58:05,755 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:05,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:05,755 INFO L85 PathProgramCache]: Analyzing trace with hash 831468847, now seen corresponding path program 1 times [2024-11-28 02:58:05,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:05,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056989436] [2024-11-28 02:58:05,756 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:05,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:06,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:06,901 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-28 02:58:06,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:06,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056989436] [2024-11-28 02:58:06,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056989436] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:58:06,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1555489353] [2024-11-28 02:58:06,901 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:06,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:58:06,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:58:06,903 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:58:06,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2024-11-28 02:58:09,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:09,807 INFO L256 TraceCheckSpWp]: Trace formula consists of 3651 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-11-28 02:58:09,814 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 02:58:09,902 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 284 proven. 112 refuted. 0 times theorem prover too weak. 416 trivial. 0 not checked. [2024-11-28 02:58:09,902 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 02:58:10,076 INFO L134 CoverageAnalysis]: Checked inductivity of 812 backedges. 184 proven. 16 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2024-11-28 02:58:10,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1555489353] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 02:58:10,076 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 02:58:10,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 12, 7] total 18 [2024-11-28 02:58:10,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912339130] [2024-11-28 02:58:10,077 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 02:58:10,078 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2024-11-28 02:58:10,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:10,079 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2024-11-28 02:58:10,079 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2024-11-28 02:58:10,080 INFO L87 Difference]: Start difference. First operand 3099 states and 4421 transitions. Second operand has 18 states, 18 states have (on average 35.333333333333336) internal successors, (636), 18 states have internal predecessors, (636), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:58:10,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:10,363 INFO L93 Difference]: Finished difference Result 5125 states and 7301 transitions. [2024-11-28 02:58:10,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2024-11-28 02:58:10,364 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 35.333333333333336) internal successors, (636), 18 states have internal predecessors, (636), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 748 [2024-11-28 02:58:10,364 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:10,367 INFO L225 Difference]: With dead ends: 5125 [2024-11-28 02:58:10,367 INFO L226 Difference]: Without dead ends: 3115 [2024-11-28 02:58:10,369 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1503 GetRequests, 1485 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=292, Unknown=0, NotChecked=0, Total=380 [2024-11-28 02:58:10,369 INFO L435 NwaCegarLoop]: 1114 mSDtfsCounter, 29 mSDsluCounter, 11075 mSDsCounter, 0 mSdLazyCounter, 234 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 29 SdHoareTripleChecker+Valid, 12189 SdHoareTripleChecker+Invalid, 235 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 234 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:10,369 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [29 Valid, 12189 Invalid, 235 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 234 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:58:10,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-11-28 02:58:10,441 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3115. [2024-11-28 02:58:10,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.416883963494133) internal successors, (4347), 3068 states have internal predecessors, (4347), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:10,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4437 transitions. [2024-11-28 02:58:10,450 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4437 transitions. Word has length 748 [2024-11-28 02:58:10,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:10,451 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4437 transitions. [2024-11-28 02:58:10,451 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 35.333333333333336) internal successors, (636), 18 states have internal predecessors, (636), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 02:58:10,452 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4437 transitions. [2024-11-28 02:58:10,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 757 [2024-11-28 02:58:10,459 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:10,459 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:10,487 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Ended with exit code 0 [2024-11-28 02:58:10,660 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable49 [2024-11-28 02:58:10,660 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:10,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:10,661 INFO L85 PathProgramCache]: Analyzing trace with hash -1492963553, now seen corresponding path program 2 times [2024-11-28 02:58:10,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:10,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [875030136] [2024-11-28 02:58:10,661 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 02:58:10,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:11,338 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 02:58:11,339 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 02:58:13,317 INFO L134 CoverageAnalysis]: Checked inductivity of 860 backedges. 184 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:13,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:13,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [875030136] [2024-11-28 02:58:13,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [875030136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:13,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:13,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:58:13,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484084836] [2024-11-28 02:58:13,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:13,318 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:58:13,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:13,319 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:58:13,319 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:58:13,319 INFO L87 Difference]: Start difference. First operand 3115 states and 4437 transitions. Second operand has 8 states, 8 states have (on average 74.625) internal successors, (597), 8 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:14,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:14,754 INFO L93 Difference]: Finished difference Result 6436 states and 9156 transitions. [2024-11-28 02:58:14,754 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:58:14,754 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 74.625) internal successors, (597), 8 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 756 [2024-11-28 02:58:14,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:14,759 INFO L225 Difference]: With dead ends: 6436 [2024-11-28 02:58:14,759 INFO L226 Difference]: Without dead ends: 4410 [2024-11-28 02:58:14,761 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:58:14,761 INFO L435 NwaCegarLoop]: 1530 mSDtfsCounter, 2293 mSDsluCounter, 5328 mSDsCounter, 0 mSdLazyCounter, 2368 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2298 SdHoareTripleChecker+Valid, 6858 SdHoareTripleChecker+Invalid, 2369 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2368 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:14,761 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2298 Valid, 6858 Invalid, 2369 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2368 Invalid, 0 Unknown, 0 Unchecked, 1.3s Time] [2024-11-28 02:58:14,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4410 states. [2024-11-28 02:58:14,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4410 to 3115. [2024-11-28 02:58:14,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.416883963494133) internal successors, (4347), 3068 states have internal predecessors, (4347), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:14,814 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4437 transitions. [2024-11-28 02:58:14,815 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4437 transitions. Word has length 756 [2024-11-28 02:58:14,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:14,815 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4437 transitions. [2024-11-28 02:58:14,815 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 74.625) internal successors, (597), 8 states have internal predecessors, (597), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:14,815 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4437 transitions. [2024-11-28 02:58:14,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 758 [2024-11-28 02:58:14,820 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:14,820 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:14,820 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-11-28 02:58:14,820 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:14,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:14,821 INFO L85 PathProgramCache]: Analyzing trace with hash -1363443623, now seen corresponding path program 1 times [2024-11-28 02:58:14,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:14,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223557278] [2024-11-28 02:58:14,821 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:14,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:15,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:16,904 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:16,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:16,905 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223557278] [2024-11-28 02:58:16,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223557278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:16,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:16,905 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:58:16,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160393045] [2024-11-28 02:58:16,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:16,906 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:58:16,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:16,907 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:58:16,907 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:58:16,907 INFO L87 Difference]: Start difference. First operand 3115 states and 4437 transitions. Second operand has 5 states, 5 states have (on average 119.6) internal successors, (598), 5 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:17,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:17,144 INFO L93 Difference]: Finished difference Result 5141 states and 7309 transitions. [2024-11-28 02:58:17,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:58:17,145 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 119.6) internal successors, (598), 5 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 757 [2024-11-28 02:58:17,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:17,148 INFO L225 Difference]: With dead ends: 5141 [2024-11-28 02:58:17,148 INFO L226 Difference]: Without dead ends: 3115 [2024-11-28 02:58:17,150 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:17,150 INFO L435 NwaCegarLoop]: 1001 mSDtfsCounter, 1849 mSDsluCounter, 1003 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1854 SdHoareTripleChecker+Valid, 2004 SdHoareTripleChecker+Invalid, 188 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:17,150 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1854 Valid, 2004 Invalid, 188 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:58:17,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-11-28 02:58:17,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3115. [2024-11-28 02:58:17,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.4165580182529336) internal successors, (4346), 3068 states have internal predecessors, (4346), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:17,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4436 transitions. [2024-11-28 02:58:17,200 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4436 transitions. Word has length 757 [2024-11-28 02:58:17,200 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:17,200 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4436 transitions. [2024-11-28 02:58:17,200 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 119.6) internal successors, (598), 5 states have internal predecessors, (598), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:17,201 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4436 transitions. [2024-11-28 02:58:17,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 759 [2024-11-28 02:58:17,208 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:17,208 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:17,208 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51 [2024-11-28 02:58:17,209 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:17,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:17,209 INFO L85 PathProgramCache]: Analyzing trace with hash 64436838, now seen corresponding path program 1 times [2024-11-28 02:58:17,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:17,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806401820] [2024-11-28 02:58:17,210 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:17,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:18,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:19,550 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:19,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:19,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806401820] [2024-11-28 02:58:19,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806401820] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:19,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:19,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:58:19,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072754476] [2024-11-28 02:58:19,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:19,552 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:58:19,552 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:19,553 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:58:19,553 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:58:19,553 INFO L87 Difference]: Start difference. First operand 3115 states and 4436 transitions. Second operand has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:19,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:19,878 INFO L93 Difference]: Finished difference Result 5141 states and 7307 transitions. [2024-11-28 02:58:19,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:58:19,878 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 758 [2024-11-28 02:58:19,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:19,883 INFO L225 Difference]: With dead ends: 5141 [2024-11-28 02:58:19,883 INFO L226 Difference]: Without dead ends: 3115 [2024-11-28 02:58:19,885 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:58:19,885 INFO L435 NwaCegarLoop]: 1001 mSDtfsCounter, 764 mSDsluCounter, 1003 mSDsCounter, 0 mSdLazyCounter, 186 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 764 SdHoareTripleChecker+Valid, 2004 SdHoareTripleChecker+Invalid, 186 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 186 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:19,885 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [764 Valid, 2004 Invalid, 186 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 186 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:58:19,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-11-28 02:58:19,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3115. [2024-11-28 02:58:19,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.416232073011734) internal successors, (4345), 3068 states have internal predecessors, (4345), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:19,955 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4435 transitions. [2024-11-28 02:58:19,956 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4435 transitions. Word has length 758 [2024-11-28 02:58:19,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:19,956 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4435 transitions. [2024-11-28 02:58:19,956 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 149.75) internal successors, (599), 4 states have internal predecessors, (599), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:19,956 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4435 transitions. [2024-11-28 02:58:19,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 760 [2024-11-28 02:58:19,961 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:19,961 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:19,961 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-11-28 02:58:19,961 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:19,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:19,962 INFO L85 PathProgramCache]: Analyzing trace with hash 1190595964, now seen corresponding path program 1 times [2024-11-28 02:58:19,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:19,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058189691] [2024-11-28 02:58:19,962 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:19,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:20,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:21,693 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:21,693 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:21,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058189691] [2024-11-28 02:58:21,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058189691] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:21,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:21,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:58:21,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1764864415] [2024-11-28 02:58:21,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:21,694 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:58:21,694 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:21,695 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:58:21,695 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:58:21,695 INFO L87 Difference]: Start difference. First operand 3115 states and 4435 transitions. Second operand has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:21,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:21,932 INFO L93 Difference]: Finished difference Result 5141 states and 7305 transitions. [2024-11-28 02:58:21,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:58:21,933 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 759 [2024-11-28 02:58:21,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:21,935 INFO L225 Difference]: With dead ends: 5141 [2024-11-28 02:58:21,936 INFO L226 Difference]: Without dead ends: 3115 [2024-11-28 02:58:21,937 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:21,938 INFO L435 NwaCegarLoop]: 1001 mSDtfsCounter, 1071 mSDsluCounter, 1012 mSDsCounter, 0 mSdLazyCounter, 184 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1076 SdHoareTripleChecker+Valid, 2013 SdHoareTripleChecker+Invalid, 184 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 184 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:21,938 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1076 Valid, 2013 Invalid, 184 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 184 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:58:21,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-11-28 02:58:22,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3115. [2024-11-28 02:58:22,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.4159061277705345) internal successors, (4344), 3068 states have internal predecessors, (4344), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:22,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4434 transitions. [2024-11-28 02:58:22,038 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4434 transitions. Word has length 759 [2024-11-28 02:58:22,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:22,038 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4434 transitions. [2024-11-28 02:58:22,038 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 120.0) internal successors, (600), 5 states have internal predecessors, (600), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:22,038 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4434 transitions. [2024-11-28 02:58:22,043 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 761 [2024-11-28 02:58:22,043 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:22,043 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:22,043 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-11-28 02:58:22,043 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:22,044 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:22,044 INFO L85 PathProgramCache]: Analyzing trace with hash -155914802, now seen corresponding path program 1 times [2024-11-28 02:58:22,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:22,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848560136] [2024-11-28 02:58:22,044 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:22,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:22,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:23,836 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:23,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:23,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848560136] [2024-11-28 02:58:23,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848560136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:23,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:23,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 02:58:23,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223997993] [2024-11-28 02:58:23,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:23,838 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 02:58:23,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:23,838 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 02:58:23,838 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 02:58:23,839 INFO L87 Difference]: Start difference. First operand 3115 states and 4434 transitions. Second operand has 4 states, 4 states have (on average 150.25) internal successors, (601), 4 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:24,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:24,086 INFO L93 Difference]: Finished difference Result 5141 states and 7303 transitions. [2024-11-28 02:58:24,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 02:58:24,086 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 150.25) internal successors, (601), 4 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 760 [2024-11-28 02:58:24,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:24,090 INFO L225 Difference]: With dead ends: 5141 [2024-11-28 02:58:24,090 INFO L226 Difference]: Without dead ends: 3115 [2024-11-28 02:58:24,092 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:58:24,092 INFO L435 NwaCegarLoop]: 1001 mSDtfsCounter, 744 mSDsluCounter, 1003 mSDsCounter, 0 mSdLazyCounter, 182 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 744 SdHoareTripleChecker+Valid, 2004 SdHoareTripleChecker+Invalid, 182 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 182 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:24,092 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [744 Valid, 2004 Invalid, 182 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 182 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:58:24,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-11-28 02:58:24,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 3115. [2024-11-28 02:58:24,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3115 states, 3068 states have (on average 1.415580182529335) internal successors, (4343), 3068 states have internal predecessors, (4343), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:24,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3115 states to 3115 states and 4433 transitions. [2024-11-28 02:58:24,139 INFO L78 Accepts]: Start accepts. Automaton has 3115 states and 4433 transitions. Word has length 760 [2024-11-28 02:58:24,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:24,140 INFO L471 AbstractCegarLoop]: Abstraction has 3115 states and 4433 transitions. [2024-11-28 02:58:24,140 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 150.25) internal successors, (601), 4 states have internal predecessors, (601), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:24,140 INFO L276 IsEmpty]: Start isEmpty. Operand 3115 states and 4433 transitions. [2024-11-28 02:58:24,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 762 [2024-11-28 02:58:24,144 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:24,145 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:24,145 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-11-28 02:58:24,145 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:24,145 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:24,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1275906367, now seen corresponding path program 1 times [2024-11-28 02:58:24,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:24,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1986423071] [2024-11-28 02:58:24,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:24,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:26,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:28,235 INFO L134 CoverageAnalysis]: Checked inductivity of 862 backedges. 61 proven. 0 refuted. 0 times theorem prover too weak. 801 trivial. 0 not checked. [2024-11-28 02:58:28,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:28,235 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1986423071] [2024-11-28 02:58:28,235 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1986423071] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:28,235 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:28,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:58:28,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719668554] [2024-11-28 02:58:28,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:28,236 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:58:28,236 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:28,237 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:58:28,237 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:58:28,237 INFO L87 Difference]: Start difference. First operand 3115 states and 4433 transitions. Second operand has 7 states, 7 states have (on average 69.0) internal successors, (483), 7 states have internal predecessors, (483), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 02:58:28,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:28,390 INFO L93 Difference]: Finished difference Result 5802 states and 8254 transitions. [2024-11-28 02:58:28,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:58:28,391 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 69.0) internal successors, (483), 7 states have internal predecessors, (483), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 761 [2024-11-28 02:58:28,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:28,394 INFO L225 Difference]: With dead ends: 5802 [2024-11-28 02:58:28,394 INFO L226 Difference]: Without dead ends: 3232 [2024-11-28 02:58:28,396 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:58:28,397 INFO L435 NwaCegarLoop]: 1070 mSDtfsCounter, 979 mSDsluCounter, 4244 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 981 SdHoareTripleChecker+Valid, 5314 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:28,397 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [981 Valid, 5314 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:58:28,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3232 states. [2024-11-28 02:58:28,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3232 to 3142. [2024-11-28 02:58:28,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3142 states, 3095 states have (on average 1.4148626817447496) internal successors, (4379), 3095 states have internal predecessors, (4379), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:28,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3142 states to 3142 states and 4469 transitions. [2024-11-28 02:58:28,445 INFO L78 Accepts]: Start accepts. Automaton has 3142 states and 4469 transitions. Word has length 761 [2024-11-28 02:58:28,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:28,446 INFO L471 AbstractCegarLoop]: Abstraction has 3142 states and 4469 transitions. [2024-11-28 02:58:28,446 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 69.0) internal successors, (483), 7 states have internal predecessors, (483), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 02:58:28,446 INFO L276 IsEmpty]: Start isEmpty. Operand 3142 states and 4469 transitions. [2024-11-28 02:58:28,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 764 [2024-11-28 02:58:28,450 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:28,451 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:28,451 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-11-28 02:58:28,451 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:28,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:28,452 INFO L85 PathProgramCache]: Analyzing trace with hash 2044321753, now seen corresponding path program 1 times [2024-11-28 02:58:28,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:28,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683664021] [2024-11-28 02:58:28,452 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:28,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:30,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:31,981 INFO L134 CoverageAnalysis]: Checked inductivity of 863 backedges. 92 proven. 0 refuted. 0 times theorem prover too weak. 771 trivial. 0 not checked. [2024-11-28 02:58:31,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:31,981 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683664021] [2024-11-28 02:58:31,981 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683664021] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:31,981 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:31,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:58:31,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660502650] [2024-11-28 02:58:31,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:31,982 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:58:31,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:31,983 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:58:31,983 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:58:31,983 INFO L87 Difference]: Start difference. First operand 3142 states and 4469 transitions. Second operand has 7 states, 7 states have (on average 73.28571428571429) internal successors, (513), 7 states have internal predecessors, (513), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:58:32,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:32,523 INFO L93 Difference]: Finished difference Result 6443 states and 9154 transitions. [2024-11-28 02:58:32,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:58:32,523 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 73.28571428571429) internal successors, (513), 7 states have internal predecessors, (513), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 763 [2024-11-28 02:58:32,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:32,527 INFO L225 Difference]: With dead ends: 6443 [2024-11-28 02:58:32,527 INFO L226 Difference]: Without dead ends: 3178 [2024-11-28 02:58:32,530 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-28 02:58:32,531 INFO L435 NwaCegarLoop]: 1402 mSDtfsCounter, 1308 mSDsluCounter, 5001 mSDsCounter, 0 mSdLazyCounter, 435 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1309 SdHoareTripleChecker+Valid, 6403 SdHoareTripleChecker+Invalid, 447 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 435 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:32,531 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1309 Valid, 6403 Invalid, 447 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 435 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-28 02:58:32,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3178 states. [2024-11-28 02:58:32,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3178 to 3160. [2024-11-28 02:58:32,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3160 states, 3113 states have (on average 1.409572759396081) internal successors, (4388), 3113 states have internal predecessors, (4388), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:32,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3160 states to 3160 states and 4478 transitions. [2024-11-28 02:58:32,612 INFO L78 Accepts]: Start accepts. Automaton has 3160 states and 4478 transitions. Word has length 763 [2024-11-28 02:58:32,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:32,613 INFO L471 AbstractCegarLoop]: Abstraction has 3160 states and 4478 transitions. [2024-11-28 02:58:32,613 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 73.28571428571429) internal successors, (513), 7 states have internal predecessors, (513), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:58:32,613 INFO L276 IsEmpty]: Start isEmpty. Operand 3160 states and 4478 transitions. [2024-11-28 02:58:32,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 766 [2024-11-28 02:58:32,621 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:32,621 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:32,622 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-11-28 02:58:32,622 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:32,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:32,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1415430395, now seen corresponding path program 1 times [2024-11-28 02:58:32,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:32,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344548048] [2024-11-28 02:58:32,623 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:32,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:35,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:36,915 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:36,915 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:36,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344548048] [2024-11-28 02:58:36,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344548048] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:36,915 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:36,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:58:36,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852069157] [2024-11-28 02:58:36,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:36,916 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:58:36,916 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:36,917 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:58:36,917 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:36,917 INFO L87 Difference]: Start difference. First operand 3160 states and 4478 transitions. Second operand has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:37,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:37,019 INFO L93 Difference]: Finished difference Result 6098 states and 8655 transitions. [2024-11-28 02:58:37,019 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:58:37,019 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 765 [2024-11-28 02:58:37,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:37,024 INFO L225 Difference]: With dead ends: 6098 [2024-11-28 02:58:37,024 INFO L226 Difference]: Without dead ends: 4042 [2024-11-28 02:58:37,027 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:37,028 INFO L435 NwaCegarLoop]: 1080 mSDtfsCounter, 305 mSDsluCounter, 4303 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 305 SdHoareTripleChecker+Valid, 5383 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:37,028 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [305 Valid, 5383 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:58:37,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4042 states. [2024-11-28 02:58:37,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4042 to 4038. [2024-11-28 02:58:37,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4038 states, 3991 states have (on average 1.4186920571285393) internal successors, (5662), 3991 states have internal predecessors, (5662), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:37,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4038 states to 4038 states and 5752 transitions. [2024-11-28 02:58:37,122 INFO L78 Accepts]: Start accepts. Automaton has 4038 states and 5752 transitions. Word has length 765 [2024-11-28 02:58:37,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:37,122 INFO L471 AbstractCegarLoop]: Abstraction has 4038 states and 5752 transitions. [2024-11-28 02:58:37,123 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.0) internal successors, (606), 6 states have internal predecessors, (606), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:37,123 INFO L276 IsEmpty]: Start isEmpty. Operand 4038 states and 5752 transitions. [2024-11-28 02:58:37,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2024-11-28 02:58:37,132 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:37,132 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:37,132 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-11-28 02:58:37,132 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:37,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:37,133 INFO L85 PathProgramCache]: Analyzing trace with hash -721957035, now seen corresponding path program 1 times [2024-11-28 02:58:37,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:37,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116071900] [2024-11-28 02:58:37,133 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:37,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:39,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:41,158 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:41,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:41,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116071900] [2024-11-28 02:58:41,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116071900] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:41,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:41,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:58:41,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840850769] [2024-11-28 02:58:41,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:41,159 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:58:41,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:41,160 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:58:41,160 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:41,160 INFO L87 Difference]: Start difference. First operand 4038 states and 5752 transitions. Second operand has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:41,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:41,263 INFO L93 Difference]: Finished difference Result 8184 states and 11681 transitions. [2024-11-28 02:58:41,263 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:58:41,264 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 766 [2024-11-28 02:58:41,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:41,268 INFO L225 Difference]: With dead ends: 8184 [2024-11-28 02:58:41,269 INFO L226 Difference]: Without dead ends: 5590 [2024-11-28 02:58:41,271 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:41,271 INFO L435 NwaCegarLoop]: 1080 mSDtfsCounter, 294 mSDsluCounter, 4309 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 294 SdHoareTripleChecker+Valid, 5389 SdHoareTripleChecker+Invalid, 55 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:41,272 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [294 Valid, 5389 Invalid, 55 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:58:41,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5590 states. [2024-11-28 02:58:41,341 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5590 to 5586. [2024-11-28 02:58:41,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5586 states, 5539 states have (on average 1.4287777577179996) internal successors, (7914), 5539 states have internal predecessors, (7914), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:41,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5586 states to 5586 states and 8004 transitions. [2024-11-28 02:58:41,355 INFO L78 Accepts]: Start accepts. Automaton has 5586 states and 8004 transitions. Word has length 766 [2024-11-28 02:58:41,356 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:41,356 INFO L471 AbstractCegarLoop]: Abstraction has 5586 states and 8004 transitions. [2024-11-28 02:58:41,356 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.16666666666667) internal successors, (607), 6 states have internal predecessors, (607), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:41,357 INFO L276 IsEmpty]: Start isEmpty. Operand 5586 states and 8004 transitions. [2024-11-28 02:58:41,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 768 [2024-11-28 02:58:41,366 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:41,366 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:41,367 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-11-28 02:58:41,367 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:41,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:41,368 INFO L85 PathProgramCache]: Analyzing trace with hash -2100397406, now seen corresponding path program 1 times [2024-11-28 02:58:41,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:41,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008664772] [2024-11-28 02:58:41,368 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:41,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:43,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:44,584 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:44,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:44,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008664772] [2024-11-28 02:58:44,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008664772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:44,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:44,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:58:44,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [150873165] [2024-11-28 02:58:44,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:44,586 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:58:44,586 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:44,587 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:58:44,587 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:44,587 INFO L87 Difference]: Start difference. First operand 5586 states and 8004 transitions. Second operand has 6 states, 6 states have (on average 101.33333333333333) internal successors, (608), 6 states have internal predecessors, (608), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:58:45,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:45,384 INFO L93 Difference]: Finished difference Result 9546 states and 13618 transitions. [2024-11-28 02:58:45,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:58:45,384 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.33333333333333) internal successors, (608), 6 states have internal predecessors, (608), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 767 [2024-11-28 02:58:45,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:45,390 INFO L225 Difference]: With dead ends: 9546 [2024-11-28 02:58:45,390 INFO L226 Difference]: Without dead ends: 5976 [2024-11-28 02:58:45,393 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:45,393 INFO L435 NwaCegarLoop]: 803 mSDtfsCounter, 1017 mSDsluCounter, 2397 mSDsCounter, 0 mSdLazyCounter, 1164 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1021 SdHoareTripleChecker+Valid, 3200 SdHoareTripleChecker+Invalid, 1165 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:45,393 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1021 Valid, 3200 Invalid, 1165 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1164 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 02:58:45,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5976 states. [2024-11-28 02:58:45,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5976 to 5972. [2024-11-28 02:58:45,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5972 states, 5925 states have (on average 1.4251476793248945) internal successors, (8444), 5925 states have internal predecessors, (8444), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:45,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5972 states to 5972 states and 8534 transitions. [2024-11-28 02:58:45,480 INFO L78 Accepts]: Start accepts. Automaton has 5972 states and 8534 transitions. Word has length 767 [2024-11-28 02:58:45,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:45,481 INFO L471 AbstractCegarLoop]: Abstraction has 5972 states and 8534 transitions. [2024-11-28 02:58:45,481 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.33333333333333) internal successors, (608), 6 states have internal predecessors, (608), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:58:45,481 INFO L276 IsEmpty]: Start isEmpty. Operand 5972 states and 8534 transitions. [2024-11-28 02:58:45,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 769 [2024-11-28 02:58:45,491 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:45,491 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:45,492 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-11-28 02:58:45,492 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:45,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:45,492 INFO L85 PathProgramCache]: Analyzing trace with hash 860906890, now seen corresponding path program 1 times [2024-11-28 02:58:45,493 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:45,493 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11767433] [2024-11-28 02:58:45,493 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:45,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:48,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:49,500 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:49,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:49,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11767433] [2024-11-28 02:58:49,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11767433] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:49,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:49,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:58:49,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182328461] [2024-11-28 02:58:49,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:49,502 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:58:49,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:49,503 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:58:49,503 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:49,503 INFO L87 Difference]: Start difference. First operand 5972 states and 8534 transitions. Second operand has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:50,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:50,274 INFO L93 Difference]: Finished difference Result 9932 states and 14146 transitions. [2024-11-28 02:58:50,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:58:50,274 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 768 [2024-11-28 02:58:50,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:50,279 INFO L225 Difference]: With dead ends: 9932 [2024-11-28 02:58:50,279 INFO L226 Difference]: Without dead ends: 5976 [2024-11-28 02:58:50,282 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:50,282 INFO L435 NwaCegarLoop]: 803 mSDtfsCounter, 1017 mSDsluCounter, 2370 mSDsCounter, 0 mSdLazyCounter, 1164 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1017 SdHoareTripleChecker+Valid, 3173 SdHoareTripleChecker+Invalid, 1164 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:50,283 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1017 Valid, 3173 Invalid, 1164 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1164 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 02:58:50,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5976 states. [2024-11-28 02:58:50,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5976 to 5974. [2024-11-28 02:58:50,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5974 states, 5927 states have (on average 1.42500421798549) internal successors, (8446), 5927 states have internal predecessors, (8446), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:50,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5974 states to 5974 states and 8536 transitions. [2024-11-28 02:58:50,389 INFO L78 Accepts]: Start accepts. Automaton has 5974 states and 8536 transitions. Word has length 768 [2024-11-28 02:58:50,390 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:50,390 INFO L471 AbstractCegarLoop]: Abstraction has 5974 states and 8536 transitions. [2024-11-28 02:58:50,390 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:50,390 INFO L276 IsEmpty]: Start isEmpty. Operand 5974 states and 8536 transitions. [2024-11-28 02:58:50,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 769 [2024-11-28 02:58:50,399 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:50,400 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:50,400 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-11-28 02:58:50,400 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:50,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:50,400 INFO L85 PathProgramCache]: Analyzing trace with hash 514461033, now seen corresponding path program 1 times [2024-11-28 02:58:50,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:50,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658597799] [2024-11-28 02:58:50,401 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:50,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:52,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:53,837 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 188 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:58:53,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:53,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658597799] [2024-11-28 02:58:53,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658597799] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:53,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:53,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:58:53,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182480129] [2024-11-28 02:58:53,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:53,838 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:58:53,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:53,838 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:58:53,838 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:53,839 INFO L87 Difference]: Start difference. First operand 5974 states and 8536 transitions. Second operand has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:54,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:54,584 INFO L93 Difference]: Finished difference Result 9932 states and 14144 transitions. [2024-11-28 02:58:54,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:58:54,585 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 768 [2024-11-28 02:58:54,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:54,592 INFO L225 Difference]: With dead ends: 9932 [2024-11-28 02:58:54,592 INFO L226 Difference]: Without dead ends: 5974 [2024-11-28 02:58:54,596 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:58:54,597 INFO L435 NwaCegarLoop]: 803 mSDtfsCounter, 810 mSDsluCounter, 2228 mSDsCounter, 0 mSdLazyCounter, 1102 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 810 SdHoareTripleChecker+Valid, 3031 SdHoareTripleChecker+Invalid, 1105 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1102 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:54,597 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [810 Valid, 3031 Invalid, 1105 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1102 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 02:58:54,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5974 states. [2024-11-28 02:58:54,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5974 to 5586. [2024-11-28 02:58:54,711 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5586 states, 5539 states have (on average 1.428055605705001) internal successors, (7910), 5539 states have internal predecessors, (7910), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:54,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5586 states to 5586 states and 8000 transitions. [2024-11-28 02:58:54,720 INFO L78 Accepts]: Start accepts. Automaton has 5586 states and 8000 transitions. Word has length 768 [2024-11-28 02:58:54,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:54,721 INFO L471 AbstractCegarLoop]: Abstraction has 5586 states and 8000 transitions. [2024-11-28 02:58:54,721 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 101.5) internal successors, (609), 6 states have internal predecessors, (609), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:58:54,721 INFO L276 IsEmpty]: Start isEmpty. Operand 5586 states and 8000 transitions. [2024-11-28 02:58:54,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 770 [2024-11-28 02:58:54,812 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:54,813 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:54,813 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-11-28 02:58:54,813 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:54,813 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:54,814 INFO L85 PathProgramCache]: Analyzing trace with hash -1790945243, now seen corresponding path program 1 times [2024-11-28 02:58:54,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:54,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1232261224] [2024-11-28 02:58:54,814 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:54,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:58:57,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:58:58,968 INFO L134 CoverageAnalysis]: Checked inductivity of 864 backedges. 70 proven. 0 refuted. 0 times theorem prover too weak. 794 trivial. 0 not checked. [2024-11-28 02:58:58,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:58:58,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1232261224] [2024-11-28 02:58:58,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1232261224] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:58:58,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:58:58,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:58:58,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [598623976] [2024-11-28 02:58:58,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:58:58,969 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:58:58,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:58:58,970 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:58:58,970 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:58:58,970 INFO L87 Difference]: Start difference. First operand 5586 states and 8000 transitions. Second operand has 7 states, 7 states have (on average 71.0) internal successors, (497), 7 states have internal predecessors, (497), 3 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) [2024-11-28 02:58:59,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:58:59,520 INFO L93 Difference]: Finished difference Result 12792 states and 18300 transitions. [2024-11-28 02:58:59,520 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:58:59,520 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 71.0) internal successors, (497), 7 states have internal predecessors, (497), 3 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) Word has length 769 [2024-11-28 02:58:59,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:58:59,525 INFO L225 Difference]: With dead ends: 12792 [2024-11-28 02:58:59,525 INFO L226 Difference]: Without dead ends: 5622 [2024-11-28 02:58:59,530 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-28 02:58:59,530 INFO L435 NwaCegarLoop]: 1411 mSDtfsCounter, 1478 mSDsluCounter, 5031 mSDsCounter, 0 mSdLazyCounter, 473 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1482 SdHoareTripleChecker+Valid, 6442 SdHoareTripleChecker+Invalid, 499 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 473 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-28 02:58:59,530 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1482 Valid, 6442 Invalid, 499 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 473 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-28 02:58:59,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5622 states. [2024-11-28 02:58:59,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5622 to 5604. [2024-11-28 02:58:59,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5604 states, 5557 states have (on average 1.4250494871333452) internal successors, (7919), 5557 states have internal predecessors, (7919), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:58:59,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5604 states to 5604 states and 8009 transitions. [2024-11-28 02:58:59,624 INFO L78 Accepts]: Start accepts. Automaton has 5604 states and 8009 transitions. Word has length 769 [2024-11-28 02:58:59,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:58:59,624 INFO L471 AbstractCegarLoop]: Abstraction has 5604 states and 8009 transitions. [2024-11-28 02:58:59,624 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 71.0) internal successors, (497), 7 states have internal predecessors, (497), 3 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 3 states have call predecessors, (9), 3 states have call successors, (9) [2024-11-28 02:58:59,624 INFO L276 IsEmpty]: Start isEmpty. Operand 5604 states and 8009 transitions. [2024-11-28 02:58:59,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 772 [2024-11-28 02:58:59,630 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:58:59,630 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:58:59,630 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-11-28 02:58:59,630 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:58:59,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:58:59,631 INFO L85 PathProgramCache]: Analyzing trace with hash -946658663, now seen corresponding path program 1 times [2024-11-28 02:58:59,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:58:59,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1914603454] [2024-11-28 02:58:59,632 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:58:59,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:02,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:03,449 INFO L134 CoverageAnalysis]: Checked inductivity of 865 backedges. 72 proven. 0 refuted. 0 times theorem prover too weak. 793 trivial. 0 not checked. [2024-11-28 02:59:03,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:03,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1914603454] [2024-11-28 02:59:03,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1914603454] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:03,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:03,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 02:59:03,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [321735162] [2024-11-28 02:59:03,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:03,450 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 02:59:03,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:03,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 02:59:03,451 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:59:03,451 INFO L87 Difference]: Start difference. First operand 5604 states and 8009 transitions. Second operand has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-28 02:59:04,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:04,302 INFO L93 Difference]: Finished difference Result 10594 states and 15151 transitions. [2024-11-28 02:59:04,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 02:59:04,303 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 771 [2024-11-28 02:59:04,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:04,308 INFO L225 Difference]: With dead ends: 10594 [2024-11-28 02:59:04,308 INFO L226 Difference]: Without dead ends: 5622 [2024-11-28 02:59:04,311 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:59:04,312 INFO L435 NwaCegarLoop]: 791 mSDtfsCounter, 963 mSDsluCounter, 2362 mSDsCounter, 0 mSdLazyCounter, 1196 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 964 SdHoareTripleChecker+Valid, 3153 SdHoareTripleChecker+Invalid, 1196 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1196 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:04,312 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [964 Valid, 3153 Invalid, 1196 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1196 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 02:59:04,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5622 states. [2024-11-28 02:59:04,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5622 to 5613. [2024-11-28 02:59:04,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5613 states, 5566 states have (on average 1.4243621990657565) internal successors, (7928), 5566 states have internal predecessors, (7928), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:59:04,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5613 states to 5613 states and 8018 transitions. [2024-11-28 02:59:04,389 INFO L78 Accepts]: Start accepts. Automaton has 5613 states and 8018 transitions. Word has length 771 [2024-11-28 02:59:04,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:04,389 INFO L471 AbstractCegarLoop]: Abstraction has 5613 states and 8018 transitions. [2024-11-28 02:59:04,390 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 83.33333333333333) internal successors, (500), 6 states have internal predecessors, (500), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-28 02:59:04,390 INFO L276 IsEmpty]: Start isEmpty. Operand 5613 states and 8018 transitions. [2024-11-28 02:59:04,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 774 [2024-11-28 02:59:04,399 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:04,400 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:04,400 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable63 [2024-11-28 02:59:04,400 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:04,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:04,401 INFO L85 PathProgramCache]: Analyzing trace with hash 363225229, now seen corresponding path program 1 times [2024-11-28 02:59:04,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:04,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574004762] [2024-11-28 02:59:04,401 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:04,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:07,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:10,570 INFO L134 CoverageAnalysis]: Checked inductivity of 866 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 847 trivial. 0 not checked. [2024-11-28 02:59:10,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:10,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574004762] [2024-11-28 02:59:10,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574004762] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:10,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:10,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:59:10,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [111246188] [2024-11-28 02:59:10,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:10,572 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:59:10,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:10,573 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:59:10,573 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:59:10,573 INFO L87 Difference]: Start difference. First operand 5613 states and 8018 transitions. Second operand has 8 states, 8 states have (on average 56.375) internal successors, (451), 8 states have internal predecessors, (451), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 02:59:11,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:11,744 INFO L93 Difference]: Finished difference Result 11032 states and 15757 transitions. [2024-11-28 02:59:11,744 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:59:11,744 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 56.375) internal successors, (451), 8 states have internal predecessors, (451), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 773 [2024-11-28 02:59:11,745 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:11,749 INFO L225 Difference]: With dead ends: 11032 [2024-11-28 02:59:11,749 INFO L226 Difference]: Without dead ends: 5685 [2024-11-28 02:59:11,753 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:59:11,753 INFO L435 NwaCegarLoop]: 797 mSDtfsCounter, 1016 mSDsluCounter, 3933 mSDsCounter, 0 mSdLazyCounter, 1763 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1020 SdHoareTripleChecker+Valid, 4730 SdHoareTripleChecker+Invalid, 1764 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1763 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:11,753 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1020 Valid, 4730 Invalid, 1764 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1763 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-11-28 02:59:11,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5685 states. [2024-11-28 02:59:11,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5685 to 5658. [2024-11-28 02:59:11,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5658 states, 5611 states have (on average 1.4225628230261986) internal successors, (7982), 5611 states have internal predecessors, (7982), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:59:11,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5658 states to 5658 states and 8072 transitions. [2024-11-28 02:59:11,827 INFO L78 Accepts]: Start accepts. Automaton has 5658 states and 8072 transitions. Word has length 773 [2024-11-28 02:59:11,828 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:11,828 INFO L471 AbstractCegarLoop]: Abstraction has 5658 states and 8072 transitions. [2024-11-28 02:59:11,828 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 56.375) internal successors, (451), 8 states have internal predecessors, (451), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 02:59:11,828 INFO L276 IsEmpty]: Start isEmpty. Operand 5658 states and 8072 transitions. [2024-11-28 02:59:11,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 776 [2024-11-28 02:59:11,834 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:11,834 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:11,834 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64 [2024-11-28 02:59:11,834 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:11,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:11,835 INFO L85 PathProgramCache]: Analyzing trace with hash -388898439, now seen corresponding path program 1 times [2024-11-28 02:59:11,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:11,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607802001] [2024-11-28 02:59:11,835 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:11,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:16,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:18,404 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:18,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:18,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607802001] [2024-11-28 02:59:18,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607802001] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:18,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:18,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:59:18,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927484516] [2024-11-28 02:59:18,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:18,405 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:59:18,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:18,406 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:59:18,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:59:18,406 INFO L87 Difference]: Start difference. First operand 5658 states and 8072 transitions. Second operand has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:18,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:18,671 INFO L93 Difference]: Finished difference Result 9296 states and 13216 transitions. [2024-11-28 02:59:18,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:59:18,672 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 775 [2024-11-28 02:59:18,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:18,677 INFO L225 Difference]: With dead ends: 9296 [2024-11-28 02:59:18,677 INFO L226 Difference]: Without dead ends: 5678 [2024-11-28 02:59:18,680 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:59:18,680 INFO L435 NwaCegarLoop]: 1042 mSDtfsCounter, 810 mSDsluCounter, 4138 mSDsCounter, 0 mSdLazyCounter, 247 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 810 SdHoareTripleChecker+Valid, 5180 SdHoareTripleChecker+Invalid, 248 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 247 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:18,680 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [810 Valid, 5180 Invalid, 248 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 247 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:59:18,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5678 states. [2024-11-28 02:59:18,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5678 to 5678. [2024-11-28 02:59:18,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5678 states, 5631 states have (on average 1.4210619783342213) internal successors, (8002), 5631 states have internal predecessors, (8002), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:59:18,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5678 states to 5678 states and 8092 transitions. [2024-11-28 02:59:18,775 INFO L78 Accepts]: Start accepts. Automaton has 5678 states and 8092 transitions. Word has length 775 [2024-11-28 02:59:18,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:18,776 INFO L471 AbstractCegarLoop]: Abstraction has 5678 states and 8092 transitions. [2024-11-28 02:59:18,776 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.0) internal successors, (616), 7 states have internal predecessors, (616), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:18,776 INFO L276 IsEmpty]: Start isEmpty. Operand 5678 states and 8092 transitions. [2024-11-28 02:59:18,785 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-11-28 02:59:18,785 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:18,786 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:18,786 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65 [2024-11-28 02:59:18,786 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:18,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:18,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1518940034, now seen corresponding path program 1 times [2024-11-28 02:59:18,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:18,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198917200] [2024-11-28 02:59:18,787 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:18,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:22,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:24,804 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:24,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:24,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198917200] [2024-11-28 02:59:24,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198917200] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:24,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:24,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 02:59:24,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831232289] [2024-11-28 02:59:24,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:24,806 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 02:59:24,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:24,807 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 02:59:24,807 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 02:59:24,807 INFO L87 Difference]: Start difference. First operand 5678 states and 8092 transitions. Second operand has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:25,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:25,090 INFO L93 Difference]: Finished difference Result 9324 states and 13244 transitions. [2024-11-28 02:59:25,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:59:25,090 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-11-28 02:59:25,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:25,095 INFO L225 Difference]: With dead ends: 9324 [2024-11-28 02:59:25,095 INFO L226 Difference]: Without dead ends: 5686 [2024-11-28 02:59:25,099 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:59:25,099 INFO L435 NwaCegarLoop]: 1042 mSDtfsCounter, 811 mSDsluCounter, 4147 mSDsCounter, 0 mSdLazyCounter, 249 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 811 SdHoareTripleChecker+Valid, 5189 SdHoareTripleChecker+Invalid, 249 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 249 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:25,099 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [811 Valid, 5189 Invalid, 249 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 249 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 02:59:25,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5686 states. [2024-11-28 02:59:25,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5686 to 5682. [2024-11-28 02:59:25,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5682 states, 5635 states have (on average 1.420763087843833) internal successors, (8006), 5635 states have internal predecessors, (8006), 45 states have call successors, (45), 1 states have call predecessors, (45), 1 states have return successors, (45), 45 states have call predecessors, (45), 45 states have call successors, (45) [2024-11-28 02:59:25,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5682 states to 5682 states and 8096 transitions. [2024-11-28 02:59:25,192 INFO L78 Accepts]: Start accepts. Automaton has 5682 states and 8096 transitions. Word has length 776 [2024-11-28 02:59:25,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:25,192 INFO L471 AbstractCegarLoop]: Abstraction has 5682 states and 8096 transitions. [2024-11-28 02:59:25,192 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 88.14285714285714) internal successors, (617), 7 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:25,193 INFO L276 IsEmpty]: Start isEmpty. Operand 5682 states and 8096 transitions. [2024-11-28 02:59:25,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 777 [2024-11-28 02:59:25,198 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:25,199 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:25,199 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-11-28 02:59:25,199 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:25,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:25,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1997272610, now seen corresponding path program 1 times [2024-11-28 02:59:25,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:25,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199169405] [2024-11-28 02:59:25,200 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:25,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:25,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:26,462 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:26,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:26,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199169405] [2024-11-28 02:59:26,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199169405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:26,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:26,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 02:59:26,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1761922792] [2024-11-28 02:59:26,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:26,463 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 02:59:26,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:26,464 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 02:59:26,464 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 02:59:26,464 INFO L87 Difference]: Start difference. First operand 5682 states and 8096 transitions. Second operand has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:26,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:26,611 INFO L93 Difference]: Finished difference Result 12060 states and 17139 transitions. [2024-11-28 02:59:26,611 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 02:59:26,611 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 776 [2024-11-28 02:59:26,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:26,618 INFO L225 Difference]: With dead ends: 12060 [2024-11-28 02:59:26,618 INFO L226 Difference]: Without dead ends: 8418 [2024-11-28 02:59:26,621 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 02:59:26,622 INFO L435 NwaCegarLoop]: 1651 mSDtfsCounter, 606 mSDsluCounter, 4365 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 606 SdHoareTripleChecker+Valid, 6016 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:26,622 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [606 Valid, 6016 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 02:59:26,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8418 states. [2024-11-28 02:59:26,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8418 to 7951. [2024-11-28 02:59:26,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7951 states, 7889 states have (on average 1.4237545950057042) internal successors, (11232), 7889 states have internal predecessors, (11232), 60 states have call successors, (60), 1 states have call predecessors, (60), 1 states have return successors, (60), 60 states have call predecessors, (60), 60 states have call successors, (60) [2024-11-28 02:59:26,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7951 states to 7951 states and 11352 transitions. [2024-11-28 02:59:26,741 INFO L78 Accepts]: Start accepts. Automaton has 7951 states and 11352 transitions. Word has length 776 [2024-11-28 02:59:26,741 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:26,741 INFO L471 AbstractCegarLoop]: Abstraction has 7951 states and 11352 transitions. [2024-11-28 02:59:26,742 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 123.4) internal successors, (617), 5 states have internal predecessors, (617), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:26,742 INFO L276 IsEmpty]: Start isEmpty. Operand 7951 states and 11352 transitions. [2024-11-28 02:59:26,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-28 02:59:26,749 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:26,749 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:26,749 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable67 [2024-11-28 02:59:26,749 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:26,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:26,750 INFO L85 PathProgramCache]: Analyzing trace with hash 78526406, now seen corresponding path program 1 times [2024-11-28 02:59:26,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:26,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971789136] [2024-11-28 02:59:26,751 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:26,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:27,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:28,931 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:28,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:28,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971789136] [2024-11-28 02:59:28,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971789136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:28,931 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:28,931 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:59:28,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [816767864] [2024-11-28 02:59:28,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:28,932 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:59:28,932 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:28,933 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:59:28,933 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:59:28,933 INFO L87 Difference]: Start difference. First operand 7951 states and 11352 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:29,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:29,174 INFO L93 Difference]: Finished difference Result 14365 states and 20445 transitions. [2024-11-28 02:59:29,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:59:29,174 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 777 [2024-11-28 02:59:29,174 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:29,182 INFO L225 Difference]: With dead ends: 14365 [2024-11-28 02:59:29,183 INFO L226 Difference]: Without dead ends: 10723 [2024-11-28 02:59:29,187 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-28 02:59:29,187 INFO L435 NwaCegarLoop]: 1611 mSDtfsCounter, 541 mSDsluCounter, 7590 mSDsCounter, 0 mSdLazyCounter, 141 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 541 SdHoareTripleChecker+Valid, 9201 SdHoareTripleChecker+Invalid, 141 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 141 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:29,188 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [541 Valid, 9201 Invalid, 141 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 141 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:59:29,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10723 states. [2024-11-28 02:59:29,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10723 to 10699. [2024-11-28 02:59:29,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10699 states, 10622 states have (on average 1.4229900207117303) internal successors, (15115), 10622 states have internal predecessors, (15115), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 02:59:29,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10699 states to 10699 states and 15265 transitions. [2024-11-28 02:59:29,349 INFO L78 Accepts]: Start accepts. Automaton has 10699 states and 15265 transitions. Word has length 777 [2024-11-28 02:59:29,350 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:29,350 INFO L471 AbstractCegarLoop]: Abstraction has 10699 states and 15265 transitions. [2024-11-28 02:59:29,350 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 02:59:29,350 INFO L276 IsEmpty]: Start isEmpty. Operand 10699 states and 15265 transitions. [2024-11-28 02:59:29,360 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-28 02:59:29,360 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:29,361 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:29,361 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-11-28 02:59:29,361 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:29,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:29,361 INFO L85 PathProgramCache]: Analyzing trace with hash -2058843039, now seen corresponding path program 1 times [2024-11-28 02:59:29,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:29,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1476533751] [2024-11-28 02:59:29,361 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:29,362 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:31,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:33,091 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:33,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:33,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1476533751] [2024-11-28 02:59:33,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1476533751] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:33,091 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:33,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:59:33,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1353879225] [2024-11-28 02:59:33,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:33,092 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:59:33,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:33,093 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:59:33,093 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:59:33,093 INFO L87 Difference]: Start difference. First operand 10699 states and 15265 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:33,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:33,418 INFO L93 Difference]: Finished difference Result 17642 states and 25179 transitions. [2024-11-28 02:59:33,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 02:59:33,419 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 777 [2024-11-28 02:59:33,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:33,433 INFO L225 Difference]: With dead ends: 17642 [2024-11-28 02:59:33,433 INFO L226 Difference]: Without dead ends: 13735 [2024-11-28 02:59:33,438 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2024-11-28 02:59:33,439 INFO L435 NwaCegarLoop]: 1468 mSDtfsCounter, 429 mSDsluCounter, 8167 mSDsCounter, 0 mSdLazyCounter, 98 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 429 SdHoareTripleChecker+Valid, 9635 SdHoareTripleChecker+Invalid, 98 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 98 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:33,439 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [429 Valid, 9635 Invalid, 98 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 98 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 02:59:33,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13735 states. [2024-11-28 02:59:33,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13735 to 13413. [2024-11-28 02:59:33,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13413 states, 13336 states have (on average 1.4301889622075585) internal successors, (19073), 13336 states have internal predecessors, (19073), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 02:59:33,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13413 states to 13413 states and 19223 transitions. [2024-11-28 02:59:33,772 INFO L78 Accepts]: Start accepts. Automaton has 13413 states and 19223 transitions. Word has length 777 [2024-11-28 02:59:33,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:33,772 INFO L471 AbstractCegarLoop]: Abstraction has 13413 states and 19223 transitions. [2024-11-28 02:59:33,772 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:33,773 INFO L276 IsEmpty]: Start isEmpty. Operand 13413 states and 19223 transitions. [2024-11-28 02:59:33,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 778 [2024-11-28 02:59:33,793 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:33,793 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:33,793 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-11-28 02:59:33,793 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:33,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:33,794 INFO L85 PathProgramCache]: Analyzing trace with hash -134454666, now seen corresponding path program 1 times [2024-11-28 02:59:33,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:33,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135283700] [2024-11-28 02:59:33,794 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:33,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:38,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:40,697 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:40,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:40,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135283700] [2024-11-28 02:59:40,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135283700] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:40,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:40,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:59:40,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547528694] [2024-11-28 02:59:40,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:40,699 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:59:40,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:40,699 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:59:40,699 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:59:40,699 INFO L87 Difference]: Start difference. First operand 13413 states and 19223 transitions. Second operand has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:41,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:41,891 INFO L93 Difference]: Finished difference Result 18180 states and 25978 transitions. [2024-11-28 02:59:41,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:59:41,891 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 777 [2024-11-28 02:59:41,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:41,902 INFO L225 Difference]: With dead ends: 18180 [2024-11-28 02:59:41,902 INFO L226 Difference]: Without dead ends: 13413 [2024-11-28 02:59:41,908 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-11-28 02:59:41,908 INFO L435 NwaCegarLoop]: 765 mSDtfsCounter, 916 mSDsluCounter, 3042 mSDsCounter, 0 mSdLazyCounter, 1618 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 920 SdHoareTripleChecker+Valid, 3807 SdHoareTripleChecker+Invalid, 1621 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 1618 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:41,908 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [920 Valid, 3807 Invalid, 1621 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 1618 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-28 02:59:41,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13413 states. [2024-11-28 02:59:42,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13413 to 13413. [2024-11-28 02:59:42,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13413 states, 13336 states have (on average 1.4295890821835633) internal successors, (19065), 13336 states have internal predecessors, (19065), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 02:59:42,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13413 states to 13413 states and 19215 transitions. [2024-11-28 02:59:42,098 INFO L78 Accepts]: Start accepts. Automaton has 13413 states and 19215 transitions. Word has length 777 [2024-11-28 02:59:42,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:42,098 INFO L471 AbstractCegarLoop]: Abstraction has 13413 states and 19215 transitions. [2024-11-28 02:59:42,098 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.25) internal successors, (618), 8 states have internal predecessors, (618), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:42,098 INFO L276 IsEmpty]: Start isEmpty. Operand 13413 states and 19215 transitions. [2024-11-28 02:59:42,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 779 [2024-11-28 02:59:42,110 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:42,110 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:42,110 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-11-28 02:59:42,110 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:42,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:42,111 INFO L85 PathProgramCache]: Analyzing trace with hash -714393403, now seen corresponding path program 1 times [2024-11-28 02:59:42,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:42,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884623851] [2024-11-28 02:59:42,111 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:42,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:46,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:48,619 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 02:59:48,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:48,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884623851] [2024-11-28 02:59:48,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884623851] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 02:59:48,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 02:59:48,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 02:59:48,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430448082] [2024-11-28 02:59:48,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 02:59:48,620 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 02:59:48,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 02:59:48,621 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 02:59:48,621 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-11-28 02:59:48,621 INFO L87 Difference]: Start difference. First operand 13413 states and 19215 transitions. Second operand has 8 states, 8 states have (on average 77.375) internal successors, (619), 8 states have internal predecessors, (619), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:49,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 02:59:49,719 INFO L93 Difference]: Finished difference Result 18148 states and 25914 transitions. [2024-11-28 02:59:49,719 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 02:59:49,719 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 77.375) internal successors, (619), 8 states have internal predecessors, (619), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 778 [2024-11-28 02:59:49,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 02:59:49,733 INFO L225 Difference]: With dead ends: 18148 [2024-11-28 02:59:49,733 INFO L226 Difference]: Without dead ends: 13453 [2024-11-28 02:59:49,740 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-11-28 02:59:49,740 INFO L435 NwaCegarLoop]: 795 mSDtfsCounter, 909 mSDsluCounter, 3159 mSDsCounter, 0 mSdLazyCounter, 1477 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 913 SdHoareTripleChecker+Valid, 3954 SdHoareTripleChecker+Invalid, 1479 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1477 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-28 02:59:49,741 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [913 Valid, 3954 Invalid, 1479 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1477 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-28 02:59:49,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13453 states. [2024-11-28 02:59:49,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13453 to 13453. [2024-11-28 02:59:49,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13453 states, 13376 states have (on average 1.4283044258373205) internal successors, (19105), 13376 states have internal predecessors, (19105), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 02:59:49,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13453 states to 13453 states and 19255 transitions. [2024-11-28 02:59:49,939 INFO L78 Accepts]: Start accepts. Automaton has 13453 states and 19255 transitions. Word has length 778 [2024-11-28 02:59:49,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 02:59:49,939 INFO L471 AbstractCegarLoop]: Abstraction has 13453 states and 19255 transitions. [2024-11-28 02:59:49,939 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 77.375) internal successors, (619), 8 states have internal predecessors, (619), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 02:59:49,939 INFO L276 IsEmpty]: Start isEmpty. Operand 13453 states and 19255 transitions. [2024-11-28 02:59:49,953 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 780 [2024-11-28 02:59:49,953 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 02:59:49,954 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 02:59:49,954 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-11-28 02:59:49,954 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 02:59:49,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 02:59:49,954 INFO L85 PathProgramCache]: Analyzing trace with hash 486390502, now seen corresponding path program 1 times [2024-11-28 02:59:49,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 02:59:49,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1949002768] [2024-11-28 02:59:49,955 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:49,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 02:59:55,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 02:59:56,950 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 12 proven. 27 refuted. 0 times theorem prover too weak. 828 trivial. 0 not checked. [2024-11-28 02:59:56,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 02:59:56,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1949002768] [2024-11-28 02:59:56,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1949002768] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 02:59:56,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [256858676] [2024-11-28 02:59:56,951 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 02:59:56,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 02:59:56,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 02:59:56,953 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 02:59:56,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2024-11-28 03:00:03,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:03,034 INFO L256 TraceCheckSpWp]: Trace formula consists of 3730 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:00:03,040 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:00:03,061 INFO L134 CoverageAnalysis]: Checked inductivity of 867 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 819 trivial. 0 not checked. [2024-11-28 03:00:03,061 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:00:03,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [256858676] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:00:03,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:00:03,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-11-28 03:00:03,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1854772692] [2024-11-28 03:00:03,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:00:03,063 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:00:03,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:00:03,063 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:00:03,063 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:00:03,064 INFO L87 Difference]: Start difference. First operand 13453 states and 19255 transitions. Second operand has 6 states, 5 states have (on average 90.4) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:00:03,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:00:03,267 INFO L93 Difference]: Finished difference Result 25860 states and 37044 transitions. [2024-11-28 03:00:03,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:00:03,267 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 90.4) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) Word has length 779 [2024-11-28 03:00:03,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:00:03,282 INFO L225 Difference]: With dead ends: 25860 [2024-11-28 03:00:03,282 INFO L226 Difference]: Without dead ends: 13453 [2024-11-28 03:00:03,292 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 784 GetRequests, 779 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:00:03,293 INFO L435 NwaCegarLoop]: 1080 mSDtfsCounter, 0 mSDsluCounter, 4297 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5377 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:00:03,293 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5377 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:00:03,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13453 states. [2024-11-28 03:00:03,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13453 to 13453. [2024-11-28 03:00:03,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13453 states, 13376 states have (on average 1.4275568181818181) internal successors, (19095), 13376 states have internal predecessors, (19095), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 03:00:03,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13453 states to 13453 states and 19245 transitions. [2024-11-28 03:00:03,552 INFO L78 Accepts]: Start accepts. Automaton has 13453 states and 19245 transitions. Word has length 779 [2024-11-28 03:00:03,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:00:03,552 INFO L471 AbstractCegarLoop]: Abstraction has 13453 states and 19245 transitions. [2024-11-28 03:00:03,553 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 90.4) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 1 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:00:03,553 INFO L276 IsEmpty]: Start isEmpty. Operand 13453 states and 19245 transitions. [2024-11-28 03:00:03,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-11-28 03:00:03,563 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:00:03,564 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:00:03,589 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Ended with exit code 0 [2024-11-28 03:00:03,764 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:03,764 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:00:03,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:00:03,765 INFO L85 PathProgramCache]: Analyzing trace with hash 502610884, now seen corresponding path program 1 times [2024-11-28 03:00:03,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:00:03,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089407397] [2024-11-28 03:00:03,765 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:03,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:00:08,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:10,025 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 26 proven. 24 refuted. 0 times theorem prover too weak. 818 trivial. 0 not checked. [2024-11-28 03:00:10,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:00:10,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089407397] [2024-11-28 03:00:10,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089407397] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:00:10,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1109888368] [2024-11-28 03:00:10,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:10,025 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:10,025 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:00:10,027 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:00:10,029 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2024-11-28 03:00:18,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:18,506 INFO L256 TraceCheckSpWp]: Trace formula consists of 3736 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:00:18,518 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:00:18,566 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 185 proven. 0 refuted. 0 times theorem prover too weak. 683 trivial. 0 not checked. [2024-11-28 03:00:18,566 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:00:18,566 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1109888368] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:00:18,566 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:00:18,567 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-11-28 03:00:18,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642822560] [2024-11-28 03:00:18,567 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:00:18,568 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:00:18,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:00:18,569 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:00:18,569 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:00:18,569 INFO L87 Difference]: Start difference. First operand 13453 states and 19245 transitions. Second operand has 6 states, 5 states have (on average 113.0) internal successors, (565), 6 states have internal predecessors, (565), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:00:18,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:00:18,850 INFO L93 Difference]: Finished difference Result 25219 states and 36106 transitions. [2024-11-28 03:00:18,850 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:00:18,851 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 113.0) internal successors, (565), 6 states have internal predecessors, (565), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 781 [2024-11-28 03:00:18,851 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:00:18,865 INFO L225 Difference]: With dead ends: 25219 [2024-11-28 03:00:18,865 INFO L226 Difference]: Without dead ends: 13453 [2024-11-28 03:00:18,875 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 786 GetRequests, 779 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:00:18,875 INFO L435 NwaCegarLoop]: 1077 mSDtfsCounter, 0 mSDsluCounter, 4289 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5366 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:00:18,875 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5366 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:00:18,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13453 states. [2024-11-28 03:00:19,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13453 to 13423. [2024-11-28 03:00:19,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13423 states, 13346 states have (on average 1.4273939757230631) internal successors, (19050), 13346 states have internal predecessors, (19050), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 03:00:19,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13423 states to 13423 states and 19200 transitions. [2024-11-28 03:00:19,130 INFO L78 Accepts]: Start accepts. Automaton has 13423 states and 19200 transitions. Word has length 781 [2024-11-28 03:00:19,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:00:19,130 INFO L471 AbstractCegarLoop]: Abstraction has 13423 states and 19200 transitions. [2024-11-28 03:00:19,130 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 113.0) internal successors, (565), 6 states have internal predecessors, (565), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:00:19,130 INFO L276 IsEmpty]: Start isEmpty. Operand 13423 states and 19200 transitions. [2024-11-28 03:00:19,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 782 [2024-11-28 03:00:19,141 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:00:19,141 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:00:19,170 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Ended with exit code 0 [2024-11-28 03:00:19,341 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73,32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:19,342 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:00:19,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:00:19,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1693784692, now seen corresponding path program 1 times [2024-11-28 03:00:19,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:00:19,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933258770] [2024-11-28 03:00:19,343 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:19,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:00:21,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:22,066 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 64 proven. 0 refuted. 0 times theorem prover too weak. 804 trivial. 0 not checked. [2024-11-28 03:00:22,067 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:00:22,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933258770] [2024-11-28 03:00:22,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933258770] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:00:22,067 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:00:22,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 03:00:22,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916016098] [2024-11-28 03:00:22,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:00:22,068 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 03:00:22,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:00:22,068 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:00:22,068 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:00:22,068 INFO L87 Difference]: Start difference. First operand 13423 states and 19200 transitions. Second operand has 4 states, 4 states have (on average 125.0) internal successors, (500), 4 states have internal predecessors, (500), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 03:00:22,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:00:22,240 INFO L93 Difference]: Finished difference Result 25201 states and 36070 transitions. [2024-11-28 03:00:22,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:00:22,241 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 125.0) internal successors, (500), 4 states have internal predecessors, (500), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 781 [2024-11-28 03:00:22,241 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:00:22,252 INFO L225 Difference]: With dead ends: 25201 [2024-11-28 03:00:22,252 INFO L226 Difference]: Without dead ends: 13423 [2024-11-28 03:00:22,260 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:00:22,260 INFO L435 NwaCegarLoop]: 1067 mSDtfsCounter, 958 mSDsluCounter, 1074 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 960 SdHoareTripleChecker+Valid, 2141 SdHoareTripleChecker+Invalid, 29 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:00:22,260 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [960 Valid, 2141 Invalid, 29 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:00:22,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13423 states. [2024-11-28 03:00:22,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13423 to 13423. [2024-11-28 03:00:22,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13423 states, 13346 states have (on average 1.4262700434587143) internal successors, (19035), 13346 states have internal predecessors, (19035), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 03:00:22,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13423 states to 13423 states and 19185 transitions. [2024-11-28 03:00:22,449 INFO L78 Accepts]: Start accepts. Automaton has 13423 states and 19185 transitions. Word has length 781 [2024-11-28 03:00:22,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:00:22,450 INFO L471 AbstractCegarLoop]: Abstraction has 13423 states and 19185 transitions. [2024-11-28 03:00:22,450 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 125.0) internal successors, (500), 4 states have internal predecessors, (500), 2 states have call successors, (8), 1 states have call predecessors, (8), 1 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 03:00:22,450 INFO L276 IsEmpty]: Start isEmpty. Operand 13423 states and 19185 transitions. [2024-11-28 03:00:22,461 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 784 [2024-11-28 03:00:22,462 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:00:22,462 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:00:22,462 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74 [2024-11-28 03:00:22,462 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:00:22,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:00:22,463 INFO L85 PathProgramCache]: Analyzing trace with hash 912305510, now seen corresponding path program 1 times [2024-11-28 03:00:22,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:00:22,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565190701] [2024-11-28 03:00:22,463 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:22,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:00:28,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:29,261 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 26 proven. 24 refuted. 0 times theorem prover too weak. 819 trivial. 0 not checked. [2024-11-28 03:00:29,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:00:29,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565190701] [2024-11-28 03:00:29,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565190701] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:00:29,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1669587288] [2024-11-28 03:00:29,261 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:29,261 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:29,261 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:00:29,263 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:00:29,264 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2024-11-28 03:00:35,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:35,941 INFO L256 TraceCheckSpWp]: Trace formula consists of 3742 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:00:35,947 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:00:35,982 INFO L134 CoverageAnalysis]: Checked inductivity of 869 backedges. 233 proven. 0 refuted. 0 times theorem prover too weak. 636 trivial. 0 not checked. [2024-11-28 03:00:35,982 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:00:35,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1669587288] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:00:35,982 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:00:35,982 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 9 [2024-11-28 03:00:35,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [260670534] [2024-11-28 03:00:35,982 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:00:35,983 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:00:35,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:00:35,983 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:00:35,983 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:00:35,984 INFO L87 Difference]: Start difference. First operand 13423 states and 19185 transitions. Second operand has 6 states, 5 states have (on average 117.6) internal successors, (588), 6 states have internal predecessors, (588), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-11-28 03:00:36,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:00:36,188 INFO L93 Difference]: Finished difference Result 25627 states and 36670 transitions. [2024-11-28 03:00:36,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:00:36,189 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 117.6) internal successors, (588), 6 states have internal predecessors, (588), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) Word has length 783 [2024-11-28 03:00:36,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:00:36,205 INFO L225 Difference]: With dead ends: 25627 [2024-11-28 03:00:36,205 INFO L226 Difference]: Without dead ends: 13423 [2024-11-28 03:00:36,216 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 788 GetRequests, 781 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:00:36,216 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 0 mSDsluCounter, 4281 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5356 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:00:36,217 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5356 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:00:36,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13423 states. [2024-11-28 03:00:36,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13423 to 13423. [2024-11-28 03:00:36,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13423 states, 13346 states have (on average 1.4251461111943653) internal successors, (19020), 13346 states have internal predecessors, (19020), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 03:00:36,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13423 states to 13423 states and 19170 transitions. [2024-11-28 03:00:36,417 INFO L78 Accepts]: Start accepts. Automaton has 13423 states and 19170 transitions. Word has length 783 [2024-11-28 03:00:36,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:00:36,418 INFO L471 AbstractCegarLoop]: Abstraction has 13423 states and 19170 transitions. [2024-11-28 03:00:36,418 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 117.6) internal successors, (588), 6 states have internal predecessors, (588), 3 states have call successors, (8), 2 states have call predecessors, (8), 3 states have return successors, (8), 2 states have call predecessors, (8), 3 states have call successors, (8) [2024-11-28 03:00:36,418 INFO L276 IsEmpty]: Start isEmpty. Operand 13423 states and 19170 transitions. [2024-11-28 03:00:36,428 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-28 03:00:36,429 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:00:36,429 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:00:36,458 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Ended with exit code 0 [2024-11-28 03:00:36,629 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75,33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:36,629 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:00:36,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:00:36,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1619057186, now seen corresponding path program 1 times [2024-11-28 03:00:36,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:00:36,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077132076] [2024-11-28 03:00:36,630 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:36,630 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:00:42,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:43,219 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 26 proven. 24 refuted. 0 times theorem prover too weak. 820 trivial. 0 not checked. [2024-11-28 03:00:43,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:00:43,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077132076] [2024-11-28 03:00:43,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077132076] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:00:43,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [737318614] [2024-11-28 03:00:43,219 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:43,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:43,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:00:43,221 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:00:43,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2024-11-28 03:00:57,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:00:57,376 INFO L256 TraceCheckSpWp]: Trace formula consists of 3748 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:00:57,383 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:00:57,404 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 90 proven. 0 refuted. 0 times theorem prover too weak. 780 trivial. 0 not checked. [2024-11-28 03:00:57,404 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:00:57,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [737318614] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:00:57,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:00:57,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [6] total 7 [2024-11-28 03:00:57,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431947485] [2024-11-28 03:00:57,405 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:00:57,405 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:00:57,405 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:00:57,405 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:00:57,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:00:57,406 INFO L87 Difference]: Start difference. First operand 13423 states and 19170 transitions. Second operand has 6 states, 5 states have (on average 93.6) internal successors, (468), 6 states have internal predecessors, (468), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:00:57,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:00:57,589 INFO L93 Difference]: Finished difference Result 26149 states and 37387 transitions. [2024-11-28 03:00:57,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:00:57,590 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 93.6) internal successors, (468), 6 states have internal predecessors, (468), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) Word has length 785 [2024-11-28 03:00:57,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:00:57,601 INFO L225 Difference]: With dead ends: 26149 [2024-11-28 03:00:57,601 INFO L226 Difference]: Without dead ends: 13423 [2024-11-28 03:00:57,608 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 790 GetRequests, 785 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:00:57,609 INFO L435 NwaCegarLoop]: 1074 mSDtfsCounter, 0 mSDsluCounter, 4277 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5351 SdHoareTripleChecker+Invalid, 50 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:00:57,609 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5351 Invalid, 50 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:00:57,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13423 states. [2024-11-28 03:00:57,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13423 to 13393. [2024-11-28 03:00:57,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13393 states, 13316 states have (on average 1.4249774707119256) internal successors, (18975), 13316 states have internal predecessors, (18975), 75 states have call successors, (75), 1 states have call predecessors, (75), 1 states have return successors, (75), 75 states have call predecessors, (75), 75 states have call successors, (75) [2024-11-28 03:00:57,789 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13393 states to 13393 states and 19125 transitions. [2024-11-28 03:00:57,791 INFO L78 Accepts]: Start accepts. Automaton has 13393 states and 19125 transitions. Word has length 785 [2024-11-28 03:00:57,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:00:57,791 INFO L471 AbstractCegarLoop]: Abstraction has 13393 states and 19125 transitions. [2024-11-28 03:00:57,791 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 93.6) internal successors, (468), 6 states have internal predecessors, (468), 3 states have call successors, (7), 2 states have call predecessors, (7), 3 states have return successors, (7), 2 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:00:57,791 INFO L276 IsEmpty]: Start isEmpty. Operand 13393 states and 19125 transitions. [2024-11-28 03:00:57,802 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-28 03:00:57,803 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:00:57,803 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:00:57,830 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Ended with exit code 0 [2024-11-28 03:00:58,003 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76,34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:00:58,003 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:00:58,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:00:58,004 INFO L85 PathProgramCache]: Analyzing trace with hash -678494878, now seen corresponding path program 1 times [2024-11-28 03:00:58,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:00:58,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520381772] [2024-11-28 03:00:58,004 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:00:58,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:02,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:07,083 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 83 proven. 97 refuted. 0 times theorem prover too weak. 690 trivial. 0 not checked. [2024-11-28 03:01:07,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:07,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520381772] [2024-11-28 03:01:07,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520381772] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:07,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2007040684] [2024-11-28 03:01:07,084 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:07,084 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:07,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:07,085 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:07,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2024-11-28 03:01:12,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:12,397 INFO L256 TraceCheckSpWp]: Trace formula consists of 3748 conjuncts, 130 conjuncts are in the unsatisfiable core [2024-11-28 03:01:12,409 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:15,095 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 118 proven. 105 refuted. 0 times theorem prover too weak. 647 trivial. 0 not checked. [2024-11-28 03:01:15,095 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:01:17,313 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 191 proven. 0 refuted. 0 times theorem prover too weak. 679 trivial. 0 not checked. [2024-11-28 03:01:17,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2007040684] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:17,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:01:17,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [15] imperfect sequences [8, 23] total 41 [2024-11-28 03:01:17,313 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2007910261] [2024-11-28 03:01:17,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:17,314 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-28 03:01:17,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:17,314 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-28 03:01:17,315 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=1375, Unknown=0, NotChecked=0, Total=1640 [2024-11-28 03:01:17,315 INFO L87 Difference]: Start difference. First operand 13393 states and 19125 transitions. Second operand has 15 states, 15 states have (on average 41.6) internal successors, (624), 15 states have internal predecessors, (624), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-11-28 03:01:18,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:18,548 INFO L93 Difference]: Finished difference Result 22530 states and 32057 transitions. [2024-11-28 03:01:18,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-11-28 03:01:18,548 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 41.6) internal successors, (624), 15 states have internal predecessors, (624), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) Word has length 785 [2024-11-28 03:01:18,549 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:18,559 INFO L225 Difference]: With dead ends: 22530 [2024-11-28 03:01:18,559 INFO L226 Difference]: Without dead ends: 15895 [2024-11-28 03:01:18,565 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1586 GetRequests, 1541 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 639 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=348, Invalid=1814, Unknown=0, NotChecked=0, Total=2162 [2024-11-28 03:01:18,565 INFO L435 NwaCegarLoop]: 1299 mSDtfsCounter, 791 mSDsluCounter, 11524 mSDsCounter, 0 mSdLazyCounter, 554 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 795 SdHoareTripleChecker+Valid, 12823 SdHoareTripleChecker+Invalid, 567 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 554 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:18,565 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [795 Valid, 12823 Invalid, 567 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 554 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-28 03:01:18,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15895 states. [2024-11-28 03:01:18,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15895 to 14830. [2024-11-28 03:01:18,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14830 states, 14728 states have (on average 1.4189978272677892) internal successors, (20899), 14728 states have internal predecessors, (20899), 100 states have call successors, (100), 1 states have call predecessors, (100), 1 states have return successors, (100), 100 states have call predecessors, (100), 100 states have call successors, (100) [2024-11-28 03:01:18,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14830 states to 14830 states and 21099 transitions. [2024-11-28 03:01:18,788 INFO L78 Accepts]: Start accepts. Automaton has 14830 states and 21099 transitions. Word has length 785 [2024-11-28 03:01:18,789 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:18,789 INFO L471 AbstractCegarLoop]: Abstraction has 14830 states and 21099 transitions. [2024-11-28 03:01:18,789 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 41.6) internal successors, (624), 15 states have internal predecessors, (624), 4 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 4 states have call predecessors, (10), 4 states have call successors, (10) [2024-11-28 03:01:18,789 INFO L276 IsEmpty]: Start isEmpty. Operand 14830 states and 21099 transitions. [2024-11-28 03:01:18,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 786 [2024-11-28 03:01:18,800 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:18,801 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:18,825 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Ended with exit code 0 [2024-11-28 03:01:19,001 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable77 [2024-11-28 03:01:19,001 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:19,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:19,002 INFO L85 PathProgramCache]: Analyzing trace with hash 676440226, now seen corresponding path program 1 times [2024-11-28 03:01:19,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:19,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55017500] [2024-11-28 03:01:19,002 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:19,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:21,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:23,385 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 125 proven. 4 refuted. 0 times theorem prover too weak. 741 trivial. 0 not checked. [2024-11-28 03:01:23,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:23,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55017500] [2024-11-28 03:01:23,386 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55017500] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:23,386 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1622204523] [2024-11-28 03:01:23,386 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:23,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:23,386 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:23,388 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:23,389 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2024-11-28 03:01:28,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:28,578 INFO L256 TraceCheckSpWp]: Trace formula consists of 3748 conjuncts, 84 conjuncts are in the unsatisfiable core [2024-11-28 03:01:28,588 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:29,451 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 153 proven. 0 refuted. 0 times theorem prover too weak. 717 trivial. 0 not checked. [2024-11-28 03:01:29,451 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:01:29,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1622204523] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:29,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:01:29,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [6] total 12 [2024-11-28 03:01:29,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007429543] [2024-11-28 03:01:29,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:29,452 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 03:01:29,453 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:29,453 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 03:01:29,453 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:01:29,454 INFO L87 Difference]: Start difference. First operand 14830 states and 21099 transitions. Second operand has 9 states, 9 states have (on average 56.666666666666664) internal successors, (510), 9 states have internal predecessors, (510), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 03:01:30,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:30,722 INFO L93 Difference]: Finished difference Result 27142 states and 38689 transitions. [2024-11-28 03:01:30,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-28 03:01:30,722 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 56.666666666666664) internal successors, (510), 9 states have internal predecessors, (510), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) Word has length 785 [2024-11-28 03:01:30,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:30,735 INFO L225 Difference]: With dead ends: 27142 [2024-11-28 03:01:30,735 INFO L226 Difference]: Without dead ends: 14890 [2024-11-28 03:01:30,744 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 793 GetRequests, 783 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:01:30,745 INFO L435 NwaCegarLoop]: 783 mSDtfsCounter, 953 mSDsluCounter, 3770 mSDsCounter, 0 mSdLazyCounter, 1823 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 955 SdHoareTripleChecker+Valid, 4553 SdHoareTripleChecker+Invalid, 1823 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1823 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:30,745 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [955 Valid, 4553 Invalid, 1823 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1823 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-28 03:01:30,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14890 states. [2024-11-28 03:01:30,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14890 to 14875. [2024-11-28 03:01:30,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14875 states, 14773 states have (on average 1.4177215189873418) internal successors, (20944), 14773 states have internal predecessors, (20944), 100 states have call successors, (100), 1 states have call predecessors, (100), 1 states have return successors, (100), 100 states have call predecessors, (100), 100 states have call successors, (100) [2024-11-28 03:01:30,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14875 states to 14875 states and 21144 transitions. [2024-11-28 03:01:31,000 INFO L78 Accepts]: Start accepts. Automaton has 14875 states and 21144 transitions. Word has length 785 [2024-11-28 03:01:31,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:31,001 INFO L471 AbstractCegarLoop]: Abstraction has 14875 states and 21144 transitions. [2024-11-28 03:01:31,001 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 56.666666666666664) internal successors, (510), 9 states have internal predecessors, (510), 2 states have call successors, (8), 2 states have call predecessors, (8), 2 states have return successors, (8), 2 states have call predecessors, (8), 2 states have call successors, (8) [2024-11-28 03:01:31,001 INFO L276 IsEmpty]: Start isEmpty. Operand 14875 states and 21144 transitions. [2024-11-28 03:01:31,014 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-28 03:01:31,014 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:31,015 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:31,048 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Forceful destruction successful, exit code 0 [2024-11-28 03:01:31,215 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable78 [2024-11-28 03:01:31,215 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:31,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:31,216 INFO L85 PathProgramCache]: Analyzing trace with hash -839747202, now seen corresponding path program 1 times [2024-11-28 03:01:31,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:31,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155448664] [2024-11-28 03:01:31,216 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:31,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:34,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:37,918 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:01:37,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:37,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155448664] [2024-11-28 03:01:37,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155448664] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:37,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:01:37,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-28 03:01:37,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [490372919] [2024-11-28 03:01:37,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:37,919 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 03:01:37,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:37,920 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 03:01:37,920 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:01:37,920 INFO L87 Difference]: Start difference. First operand 14875 states and 21144 transitions. Second operand has 9 states, 9 states have (on average 69.77777777777777) internal successors, (628), 9 states have internal predecessors, (628), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:01:39,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:39,788 INFO L93 Difference]: Finished difference Result 20096 states and 28485 transitions. [2024-11-28 03:01:39,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 03:01:39,789 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 69.77777777777777) internal successors, (628), 9 states have internal predecessors, (628), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 787 [2024-11-28 03:01:39,789 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:39,801 INFO L225 Difference]: With dead ends: 20096 [2024-11-28 03:01:39,801 INFO L226 Difference]: Without dead ends: 14941 [2024-11-28 03:01:39,807 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-11-28 03:01:39,807 INFO L435 NwaCegarLoop]: 1615 mSDtfsCounter, 594 mSDsluCounter, 7545 mSDsCounter, 0 mSdLazyCounter, 2893 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 594 SdHoareTripleChecker+Valid, 9160 SdHoareTripleChecker+Invalid, 2894 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2893 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.6s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:39,807 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [594 Valid, 9160 Invalid, 2894 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2893 Invalid, 0 Unknown, 0 Unchecked, 1.6s Time] [2024-11-28 03:01:39,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14941 states. [2024-11-28 03:01:40,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14941 to 14907. [2024-11-28 03:01:40,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14907 states, 14805 states have (on average 1.417629179331307) internal successors, (20988), 14805 states have internal predecessors, (20988), 100 states have call successors, (100), 1 states have call predecessors, (100), 1 states have return successors, (100), 100 states have call predecessors, (100), 100 states have call successors, (100) [2024-11-28 03:01:40,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14907 states to 14907 states and 21188 transitions. [2024-11-28 03:01:40,028 INFO L78 Accepts]: Start accepts. Automaton has 14907 states and 21188 transitions. Word has length 787 [2024-11-28 03:01:40,028 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:40,028 INFO L471 AbstractCegarLoop]: Abstraction has 14907 states and 21188 transitions. [2024-11-28 03:01:40,028 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 69.77777777777777) internal successors, (628), 9 states have internal predecessors, (628), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:01:40,028 INFO L276 IsEmpty]: Start isEmpty. Operand 14907 states and 21188 transitions. [2024-11-28 03:01:40,041 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-28 03:01:40,041 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:40,041 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:40,041 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable79 [2024-11-28 03:01:40,042 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:40,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:40,042 INFO L85 PathProgramCache]: Analyzing trace with hash 47418406, now seen corresponding path program 1 times [2024-11-28 03:01:40,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:40,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697471031] [2024-11-28 03:01:40,042 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:40,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:43,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:48,598 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 757 trivial. 0 not checked. [2024-11-28 03:01:48,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:48,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697471031] [2024-11-28 03:01:48,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697471031] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:48,598 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:01:48,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 03:01:48,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238611118] [2024-11-28 03:01:48,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:48,599 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 03:01:48,599 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:48,599 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:01:48,600 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:01:48,600 INFO L87 Difference]: Start difference. First operand 14907 states and 21188 transitions. Second operand has 8 states, 8 states have (on average 68.875) internal successors, (551), 8 states have internal predecessors, (551), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:01:49,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:49,147 INFO L93 Difference]: Finished difference Result 25212 states and 35718 transitions. [2024-11-28 03:01:49,148 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 03:01:49,148 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 68.875) internal successors, (551), 8 states have internal predecessors, (551), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 787 [2024-11-28 03:01:49,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:49,165 INFO L225 Difference]: With dead ends: 25212 [2024-11-28 03:01:49,165 INFO L226 Difference]: Without dead ends: 18021 [2024-11-28 03:01:49,173 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-28 03:01:49,174 INFO L435 NwaCegarLoop]: 1184 mSDtfsCounter, 1220 mSDsluCounter, 5748 mSDsCounter, 0 mSdLazyCounter, 195 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1224 SdHoareTripleChecker+Valid, 6932 SdHoareTripleChecker+Invalid, 196 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 195 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:49,174 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1224 Valid, 6932 Invalid, 196 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 195 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 03:01:49,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18021 states. [2024-11-28 03:01:49,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18021 to 16522. [2024-11-28 03:01:49,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16522 states, 16385 states have (on average 1.413976197741837) internal successors, (23168), 16385 states have internal predecessors, (23168), 135 states have call successors, (135), 1 states have call predecessors, (135), 1 states have return successors, (135), 135 states have call predecessors, (135), 135 states have call successors, (135) [2024-11-28 03:01:49,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16522 states to 16522 states and 23438 transitions. [2024-11-28 03:01:49,461 INFO L78 Accepts]: Start accepts. Automaton has 16522 states and 23438 transitions. Word has length 787 [2024-11-28 03:01:49,461 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:49,461 INFO L471 AbstractCegarLoop]: Abstraction has 16522 states and 23438 transitions. [2024-11-28 03:01:49,461 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 68.875) internal successors, (551), 8 states have internal predecessors, (551), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:01:49,461 INFO L276 IsEmpty]: Start isEmpty. Operand 16522 states and 23438 transitions. [2024-11-28 03:01:49,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 788 [2024-11-28 03:01:49,477 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:49,478 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:49,478 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-11-28 03:01:49,478 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:49,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:49,479 INFO L85 PathProgramCache]: Analyzing trace with hash -967026906, now seen corresponding path program 1 times [2024-11-28 03:01:49,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:49,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277274722] [2024-11-28 03:01:49,479 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:49,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:56,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:58,804 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 189 proven. 0 refuted. 0 times theorem prover too weak. 682 trivial. 0 not checked. [2024-11-28 03:01:58,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:58,804 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277274722] [2024-11-28 03:01:58,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277274722] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:58,804 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:01:58,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 03:01:58,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1172811775] [2024-11-28 03:01:58,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:58,805 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:01:58,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:58,806 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:01:58,806 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:01:58,806 INFO L87 Difference]: Start difference. First operand 16522 states and 23438 transitions. Second operand has 6 states, 6 states have (on average 104.16666666666667) internal successors, (625), 6 states have internal predecessors, (625), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:01:59,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:59,307 INFO L93 Difference]: Finished difference Result 35410 states and 50048 transitions. [2024-11-28 03:01:59,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:01:59,308 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 104.16666666666667) internal successors, (625), 6 states have internal predecessors, (625), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 787 [2024-11-28 03:01:59,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:59,336 INFO L225 Difference]: With dead ends: 35410 [2024-11-28 03:01:59,336 INFO L226 Difference]: Without dead ends: 28465 [2024-11-28 03:01:59,348 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:01:59,348 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 759 mSDsluCounter, 4162 mSDsCounter, 0 mSdLazyCounter, 45 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 759 SdHoareTripleChecker+Valid, 5237 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 45 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:59,348 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [759 Valid, 5237 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 45 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:01:59,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28465 states. [2024-11-28 03:01:59,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28465 to 25708. [2024-11-28 03:01:59,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25708 states, 25490 states have (on average 1.4206355433503335) internal successors, (36212), 25490 states have internal predecessors, (36212), 216 states have call successors, (216), 1 states have call predecessors, (216), 1 states have return successors, (216), 216 states have call predecessors, (216), 216 states have call successors, (216) [2024-11-28 03:01:59,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25708 states to 25708 states and 36644 transitions. [2024-11-28 03:01:59,805 INFO L78 Accepts]: Start accepts. Automaton has 25708 states and 36644 transitions. Word has length 787 [2024-11-28 03:01:59,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:59,806 INFO L471 AbstractCegarLoop]: Abstraction has 25708 states and 36644 transitions. [2024-11-28 03:01:59,806 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 104.16666666666667) internal successors, (625), 6 states have internal predecessors, (625), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:01:59,806 INFO L276 IsEmpty]: Start isEmpty. Operand 25708 states and 36644 transitions. [2024-11-28 03:01:59,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-11-28 03:01:59,834 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:59,835 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:59,835 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81 [2024-11-28 03:01:59,835 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:59,836 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:59,836 INFO L85 PathProgramCache]: Analyzing trace with hash 502934057, now seen corresponding path program 1 times [2024-11-28 03:01:59,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:59,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821865779] [2024-11-28 03:01:59,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:59,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:05,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:06,481 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 186 proven. 0 refuted. 0 times theorem prover too weak. 685 trivial. 0 not checked. [2024-11-28 03:02:06,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:06,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821865779] [2024-11-28 03:02:06,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821865779] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:06,482 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:06,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 03:02:06,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661187528] [2024-11-28 03:02:06,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:06,483 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:02:06,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:06,483 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:02:06,484 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:02:06,484 INFO L87 Difference]: Start difference. First operand 25708 states and 36644 transitions. Second operand has 7 states, 7 states have (on average 89.14285714285714) internal successors, (624), 7 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:07,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:07,147 INFO L93 Difference]: Finished difference Result 33559 states and 47633 transitions. [2024-11-28 03:02:07,147 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 03:02:07,147 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 89.14285714285714) internal successors, (624), 7 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-11-28 03:02:07,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:07,170 INFO L225 Difference]: With dead ends: 33559 [2024-11-28 03:02:07,170 INFO L226 Difference]: Without dead ends: 26128 [2024-11-28 03:02:07,180 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:02:07,180 INFO L435 NwaCegarLoop]: 1015 mSDtfsCounter, 841 mSDsluCounter, 4037 mSDsCounter, 0 mSdLazyCounter, 356 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 841 SdHoareTripleChecker+Valid, 5052 SdHoareTripleChecker+Invalid, 358 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 356 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:07,180 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [841 Valid, 5052 Invalid, 358 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 356 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 03:02:07,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26128 states. [2024-11-28 03:02:07,552 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26128 to 26128. [2024-11-28 03:02:07,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26128 states, 25910 states have (on average 1.4170590505596294) internal successors, (36716), 25910 states have internal predecessors, (36716), 216 states have call successors, (216), 1 states have call predecessors, (216), 1 states have return successors, (216), 216 states have call predecessors, (216), 216 states have call successors, (216) [2024-11-28 03:02:07,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26128 states to 26128 states and 37148 transitions. [2024-11-28 03:02:07,604 INFO L78 Accepts]: Start accepts. Automaton has 26128 states and 37148 transitions. Word has length 788 [2024-11-28 03:02:07,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:07,605 INFO L471 AbstractCegarLoop]: Abstraction has 26128 states and 37148 transitions. [2024-11-28 03:02:07,605 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 89.14285714285714) internal successors, (624), 7 states have internal predecessors, (624), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:07,605 INFO L276 IsEmpty]: Start isEmpty. Operand 26128 states and 37148 transitions. [2024-11-28 03:02:07,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 789 [2024-11-28 03:02:07,630 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:07,630 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:07,630 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-11-28 03:02:07,630 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:07,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:07,631 INFO L85 PathProgramCache]: Analyzing trace with hash 1992408677, now seen corresponding path program 1 times [2024-11-28 03:02:07,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:07,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842971553] [2024-11-28 03:02:07,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:07,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:13,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:17,499 INFO L134 CoverageAnalysis]: Checked inductivity of 872 backedges. 90 proven. 0 refuted. 0 times theorem prover too weak. 782 trivial. 0 not checked. [2024-11-28 03:02:17,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:17,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842971553] [2024-11-28 03:02:17,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842971553] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:17,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:17,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-11-28 03:02:17,500 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [628518495] [2024-11-28 03:02:17,500 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:17,500 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-11-28 03:02:17,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:17,501 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-11-28 03:02:17,501 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:02:17,501 INFO L87 Difference]: Start difference. First operand 26128 states and 37148 transitions. Second operand has 9 states, 9 states have (on average 58.44444444444444) internal successors, (526), 9 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:18,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:18,625 INFO L93 Difference]: Finished difference Result 90003 states and 128199 transitions. [2024-11-28 03:02:18,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-11-28 03:02:18,626 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 58.44444444444444) internal successors, (526), 9 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 788 [2024-11-28 03:02:18,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:18,673 INFO L225 Difference]: With dead ends: 90003 [2024-11-28 03:02:18,673 INFO L226 Difference]: Without dead ends: 70752 [2024-11-28 03:02:18,685 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:02:18,685 INFO L435 NwaCegarLoop]: 1062 mSDtfsCounter, 1989 mSDsluCounter, 7349 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1999 SdHoareTripleChecker+Valid, 8411 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:18,685 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1999 Valid, 8411 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 03:02:18,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70752 states. [2024-11-28 03:02:19,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70752 to 26464. [2024-11-28 03:02:19,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26464 states, 26246 states have (on average 1.4180065533795625) internal successors, (37217), 26246 states have internal predecessors, (37217), 216 states have call successors, (216), 1 states have call predecessors, (216), 1 states have return successors, (216), 216 states have call predecessors, (216), 216 states have call successors, (216) [2024-11-28 03:02:19,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26464 states to 26464 states and 37649 transitions. [2024-11-28 03:02:19,414 INFO L78 Accepts]: Start accepts. Automaton has 26464 states and 37649 transitions. Word has length 788 [2024-11-28 03:02:19,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:19,414 INFO L471 AbstractCegarLoop]: Abstraction has 26464 states and 37649 transitions. [2024-11-28 03:02:19,415 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 58.44444444444444) internal successors, (526), 9 states have internal predecessors, (526), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:19,415 INFO L276 IsEmpty]: Start isEmpty. Operand 26464 states and 37649 transitions. [2024-11-28 03:02:19,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-28 03:02:19,446 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:19,447 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:19,447 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable83 [2024-11-28 03:02:19,447 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:19,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:19,448 INFO L85 PathProgramCache]: Analyzing trace with hash -2018749731, now seen corresponding path program 1 times [2024-11-28 03:02:19,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:19,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207748350] [2024-11-28 03:02:19,448 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:19,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:26,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:32,359 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 853 trivial. 0 not checked. [2024-11-28 03:02:32,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:32,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207748350] [2024-11-28 03:02:32,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207748350] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:32,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:32,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2024-11-28 03:02:32,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1307390327] [2024-11-28 03:02:32,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:32,360 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2024-11-28 03:02:32,360 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:32,361 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2024-11-28 03:02:32,361 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-11-28 03:02:32,361 INFO L87 Difference]: Start difference. First operand 26464 states and 37649 transitions. Second operand has 11 states, 11 states have (on average 42.0) internal successors, (462), 11 states have internal predecessors, (462), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:02:35,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:35,498 INFO L93 Difference]: Finished difference Result 87483 states and 125024 transitions. [2024-11-28 03:02:35,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 03:02:35,499 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 42.0) internal successors, (462), 11 states have internal predecessors, (462), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 789 [2024-11-28 03:02:35,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:35,582 INFO L225 Difference]: With dead ends: 87483 [2024-11-28 03:02:35,582 INFO L226 Difference]: Without dead ends: 66096 [2024-11-28 03:02:35,614 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=137, Unknown=0, NotChecked=0, Total=182 [2024-11-28 03:02:35,615 INFO L435 NwaCegarLoop]: 784 mSDtfsCounter, 2240 mSDsluCounter, 6300 mSDsCounter, 0 mSdLazyCounter, 2795 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2254 SdHoareTripleChecker+Valid, 7084 SdHoareTripleChecker+Invalid, 2796 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2795 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:35,615 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2254 Valid, 7084 Invalid, 2796 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2795 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2024-11-28 03:02:35,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66096 states. [2024-11-28 03:02:36,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66096 to 27644. [2024-11-28 03:02:36,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27644 states, 27408 states have (on average 1.4171044950379452) internal successors, (38840), 27408 states have internal predecessors, (38840), 234 states have call successors, (234), 1 states have call predecessors, (234), 1 states have return successors, (234), 234 states have call predecessors, (234), 234 states have call successors, (234) [2024-11-28 03:02:36,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27644 states to 27644 states and 39308 transitions. [2024-11-28 03:02:36,306 INFO L78 Accepts]: Start accepts. Automaton has 27644 states and 39308 transitions. Word has length 789 [2024-11-28 03:02:36,306 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:36,306 INFO L471 AbstractCegarLoop]: Abstraction has 27644 states and 39308 transitions. [2024-11-28 03:02:36,306 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 42.0) internal successors, (462), 11 states have internal predecessors, (462), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:02:36,307 INFO L276 IsEmpty]: Start isEmpty. Operand 27644 states and 39308 transitions. [2024-11-28 03:02:36,336 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-28 03:02:36,336 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:36,336 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:36,336 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84 [2024-11-28 03:02:36,336 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:36,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:36,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1530748357, now seen corresponding path program 1 times [2024-11-28 03:02:36,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:36,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432246123] [2024-11-28 03:02:36,338 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:36,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:40,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:42,177 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:02:42,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:42,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [432246123] [2024-11-28 03:02:42,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [432246123] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:42,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:42,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-28 03:02:42,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1041770112] [2024-11-28 03:02:42,178 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:42,178 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-28 03:02:42,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:42,179 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-28 03:02:42,179 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2024-11-28 03:02:42,179 INFO L87 Difference]: Start difference. First operand 27644 states and 39308 transitions. Second operand has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:02:43,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:43,065 INFO L93 Difference]: Finished difference Result 39802 states and 56318 transitions. [2024-11-28 03:02:43,065 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2024-11-28 03:02:43,065 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 789 [2024-11-28 03:02:43,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:43,092 INFO L225 Difference]: With dead ends: 39802 [2024-11-28 03:02:43,092 INFO L226 Difference]: Without dead ends: 33897 [2024-11-28 03:02:43,103 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=314, Unknown=0, NotChecked=0, Total=380 [2024-11-28 03:02:43,103 INFO L435 NwaCegarLoop]: 2545 mSDtfsCounter, 1471 mSDsluCounter, 18126 mSDsCounter, 0 mSdLazyCounter, 419 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1472 SdHoareTripleChecker+Valid, 20671 SdHoareTripleChecker+Invalid, 429 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 419 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:43,103 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1472 Valid, 20671 Invalid, 429 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 419 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 03:02:43,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33897 states. [2024-11-28 03:02:43,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33897 to 33397. [2024-11-28 03:02:43,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33397 states, 33107 states have (on average 1.4124807442534812) internal successors, (46763), 33107 states have internal predecessors, (46763), 288 states have call successors, (288), 1 states have call predecessors, (288), 1 states have return successors, (288), 288 states have call predecessors, (288), 288 states have call successors, (288) [2024-11-28 03:02:43,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33397 states to 33397 states and 47339 transitions. [2024-11-28 03:02:43,734 INFO L78 Accepts]: Start accepts. Automaton has 33397 states and 47339 transitions. Word has length 789 [2024-11-28 03:02:43,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:43,735 INFO L471 AbstractCegarLoop]: Abstraction has 33397 states and 47339 transitions. [2024-11-28 03:02:43,735 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 63.0) internal successors, (630), 10 states have internal predecessors, (630), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:02:43,735 INFO L276 IsEmpty]: Start isEmpty. Operand 33397 states and 47339 transitions. [2024-11-28 03:02:43,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-28 03:02:43,761 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:43,762 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:43,762 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-11-28 03:02:43,762 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:43,762 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:43,762 INFO L85 PathProgramCache]: Analyzing trace with hash -914449627, now seen corresponding path program 1 times [2024-11-28 03:02:43,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:43,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236841695] [2024-11-28 03:02:43,763 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:43,763 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:46,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:49,187 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:02:49,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:49,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236841695] [2024-11-28 03:02:49,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236841695] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:49,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:49,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-11-28 03:02:49,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898756153] [2024-11-28 03:02:49,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:49,189 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 03:02:49,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:49,190 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:02:49,190 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:02:49,190 INFO L87 Difference]: Start difference. First operand 33397 states and 47339 transitions. Second operand has 8 states, 8 states have (on average 78.75) internal successors, (630), 8 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:49,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:49,708 INFO L93 Difference]: Finished difference Result 46068 states and 65000 transitions. [2024-11-28 03:02:49,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 03:02:49,708 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 78.75) internal successors, (630), 8 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 789 [2024-11-28 03:02:49,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:49,741 INFO L225 Difference]: With dead ends: 46068 [2024-11-28 03:02:49,741 INFO L226 Difference]: Without dead ends: 34950 [2024-11-28 03:02:49,754 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:02:49,754 INFO L435 NwaCegarLoop]: 1067 mSDtfsCounter, 433 mSDsluCounter, 5321 mSDsCounter, 0 mSdLazyCounter, 85 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 433 SdHoareTripleChecker+Valid, 6388 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 85 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:49,755 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [433 Valid, 6388 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 85 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:02:49,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34950 states. [2024-11-28 03:02:50,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34950 to 33397. [2024-11-28 03:02:50,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33397 states, 33107 states have (on average 1.4124807442534812) internal successors, (46763), 33107 states have internal predecessors, (46763), 288 states have call successors, (288), 1 states have call predecessors, (288), 1 states have return successors, (288), 288 states have call predecessors, (288), 288 states have call successors, (288) [2024-11-28 03:02:50,439 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33397 states to 33397 states and 47339 transitions. [2024-11-28 03:02:50,442 INFO L78 Accepts]: Start accepts. Automaton has 33397 states and 47339 transitions. Word has length 789 [2024-11-28 03:02:50,442 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:50,442 INFO L471 AbstractCegarLoop]: Abstraction has 33397 states and 47339 transitions. [2024-11-28 03:02:50,443 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 78.75) internal successors, (630), 8 states have internal predecessors, (630), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:02:50,443 INFO L276 IsEmpty]: Start isEmpty. Operand 33397 states and 47339 transitions. [2024-11-28 03:02:50,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-28 03:02:50,469 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:50,469 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:50,470 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86 [2024-11-28 03:02:50,470 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:50,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:50,470 INFO L85 PathProgramCache]: Analyzing trace with hash 959729365, now seen corresponding path program 1 times [2024-11-28 03:02:50,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:50,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494070956] [2024-11-28 03:02:50,471 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:50,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:54,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:02:56,609 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 855 trivial. 0 not checked. [2024-11-28 03:02:56,609 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:56,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494070956] [2024-11-28 03:02:56,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494070956] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:02:56,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:02:56,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:02:56,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638065708] [2024-11-28 03:02:56,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:02:56,610 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:02:56,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:56,610 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:02:56,610 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:02:56,611 INFO L87 Difference]: Start difference. First operand 33397 states and 47339 transitions. Second operand has 3 states, 3 states have (on average 153.66666666666666) internal successors, (461), 3 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:02:57,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:57,243 INFO L93 Difference]: Finished difference Result 60477 states and 85895 transitions. [2024-11-28 03:02:57,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:02:57,243 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 153.66666666666666) internal successors, (461), 3 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 789 [2024-11-28 03:02:57,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:57,274 INFO L225 Difference]: With dead ends: 60477 [2024-11-28 03:02:57,274 INFO L226 Difference]: Without dead ends: 33211 [2024-11-28 03:02:57,292 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:02:57,293 INFO L435 NwaCegarLoop]: 1075 mSDtfsCounter, 1 mSDsluCounter, 1072 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 2147 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:57,293 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 2147 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:02:57,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33211 states. [2024-11-28 03:02:57,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33211 to 33193. [2024-11-28 03:02:57,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33193 states, 32903 states have (on average 1.412667537914476) internal successors, (46481), 32903 states have internal predecessors, (46481), 288 states have call successors, (288), 1 states have call predecessors, (288), 1 states have return successors, (288), 288 states have call predecessors, (288), 288 states have call successors, (288) [2024-11-28 03:02:57,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33193 states to 33193 states and 47057 transitions. [2024-11-28 03:02:57,852 INFO L78 Accepts]: Start accepts. Automaton has 33193 states and 47057 transitions. Word has length 789 [2024-11-28 03:02:57,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:57,853 INFO L471 AbstractCegarLoop]: Abstraction has 33193 states and 47057 transitions. [2024-11-28 03:02:57,853 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 153.66666666666666) internal successors, (461), 3 states have internal predecessors, (461), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:02:57,853 INFO L276 IsEmpty]: Start isEmpty. Operand 33193 states and 47057 transitions. [2024-11-28 03:02:57,882 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 790 [2024-11-28 03:02:57,883 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:57,883 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:57,883 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87 [2024-11-28 03:02:57,883 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:57,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:57,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1969694845, now seen corresponding path program 1 times [2024-11-28 03:02:57,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:57,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760796175] [2024-11-28 03:02:57,884 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:02:57,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:00,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:02,096 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 850 trivial. 0 not checked. [2024-11-28 03:03:02,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:02,097 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760796175] [2024-11-28 03:03:02,097 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760796175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:02,097 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:02,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 03:03:02,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282431384] [2024-11-28 03:03:02,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:02,098 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:03:02,098 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:02,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:03:02,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:03:02,099 INFO L87 Difference]: Start difference. First operand 33193 states and 47057 transitions. Second operand has 6 states, 6 states have (on average 77.33333333333333) internal successors, (464), 6 states have internal predecessors, (464), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:03:03,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:03,347 INFO L93 Difference]: Finished difference Result 60285 states and 85625 transitions. [2024-11-28 03:03:03,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:03:03,347 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 77.33333333333333) internal successors, (464), 6 states have internal predecessors, (464), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 789 [2024-11-28 03:03:03,347 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:03,380 INFO L225 Difference]: With dead ends: 60285 [2024-11-28 03:03:03,380 INFO L226 Difference]: Without dead ends: 33313 [2024-11-28 03:03:03,399 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-11-28 03:03:03,400 INFO L435 NwaCegarLoop]: 789 mSDtfsCounter, 1004 mSDsluCounter, 2356 mSDsCounter, 0 mSdLazyCounter, 1176 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1008 SdHoareTripleChecker+Valid, 3145 SdHoareTripleChecker+Invalid, 1176 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1176 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:03,400 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1008 Valid, 3145 Invalid, 1176 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1176 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-11-28 03:03:03,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33313 states. [2024-11-28 03:03:04,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33313 to 33283. [2024-11-28 03:03:04,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33283 states, 32993 states have (on average 1.4115418422089534) internal successors, (46571), 32993 states have internal predecessors, (46571), 288 states have call successors, (288), 1 states have call predecessors, (288), 1 states have return successors, (288), 288 states have call predecessors, (288), 288 states have call successors, (288) [2024-11-28 03:03:04,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33283 states to 33283 states and 47147 transitions. [2024-11-28 03:03:04,065 INFO L78 Accepts]: Start accepts. Automaton has 33283 states and 47147 transitions. Word has length 789 [2024-11-28 03:03:04,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:04,065 INFO L471 AbstractCegarLoop]: Abstraction has 33283 states and 47147 transitions. [2024-11-28 03:03:04,065 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 77.33333333333333) internal successors, (464), 6 states have internal predecessors, (464), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:03:04,065 INFO L276 IsEmpty]: Start isEmpty. Operand 33283 states and 47147 transitions. [2024-11-28 03:03:04,091 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-28 03:03:04,091 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:04,091 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:04,091 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88 [2024-11-28 03:03:04,092 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:04,092 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:04,092 INFO L85 PathProgramCache]: Analyzing trace with hash -99710164, now seen corresponding path program 1 times [2024-11-28 03:03:04,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:04,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138003353] [2024-11-28 03:03:04,092 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:03:04,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:07,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:12,253 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:03:12,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:12,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138003353] [2024-11-28 03:03:12,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138003353] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:12,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:12,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2024-11-28 03:03:12,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484487235] [2024-11-28 03:03:12,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:12,254 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-11-28 03:03:12,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:12,255 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-11-28 03:03:12,255 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=131, Unknown=0, NotChecked=0, Total=156 [2024-11-28 03:03:12,255 INFO L87 Difference]: Start difference. First operand 33283 states and 47147 transitions. Second operand has 13 states, 13 states have (on average 48.53846153846154) internal successors, (631), 13 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:13,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:13,514 INFO L93 Difference]: Finished difference Result 44928 states and 63653 transitions. [2024-11-28 03:03:13,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2024-11-28 03:03:13,515 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 48.53846153846154) internal successors, (631), 13 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 790 [2024-11-28 03:03:13,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:13,543 INFO L225 Difference]: With dead ends: 44928 [2024-11-28 03:03:13,543 INFO L226 Difference]: Without dead ends: 39195 [2024-11-28 03:03:13,553 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=63, Invalid=357, Unknown=0, NotChecked=0, Total=420 [2024-11-28 03:03:13,553 INFO L435 NwaCegarLoop]: 1502 mSDtfsCounter, 1519 mSDsluCounter, 14443 mSDsCounter, 0 mSdLazyCounter, 1081 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1523 SdHoareTripleChecker+Valid, 15945 SdHoareTripleChecker+Invalid, 1083 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 1081 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:13,553 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1523 Valid, 15945 Invalid, 1083 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 1081 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 03:03:13,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39195 states. [2024-11-28 03:03:14,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39195 to 37293. [2024-11-28 03:03:14,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37293 states, 37003 states have (on average 1.416506769721374) internal successors, (52415), 37003 states have internal predecessors, (52415), 288 states have call successors, (288), 1 states have call predecessors, (288), 1 states have return successors, (288), 288 states have call predecessors, (288), 288 states have call successors, (288) [2024-11-28 03:03:14,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37293 states to 37293 states and 52991 transitions. [2024-11-28 03:03:14,413 INFO L78 Accepts]: Start accepts. Automaton has 37293 states and 52991 transitions. Word has length 790 [2024-11-28 03:03:14,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:14,414 INFO L471 AbstractCegarLoop]: Abstraction has 37293 states and 52991 transitions. [2024-11-28 03:03:14,414 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 48.53846153846154) internal successors, (631), 13 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:14,414 INFO L276 IsEmpty]: Start isEmpty. Operand 37293 states and 52991 transitions. [2024-11-28 03:03:14,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-28 03:03:14,441 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:14,441 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:14,441 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable89 [2024-11-28 03:03:14,442 INFO L396 AbstractCegarLoop]: === Iteration 91 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:14,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:14,442 INFO L85 PathProgramCache]: Analyzing trace with hash 1424733571, now seen corresponding path program 1 times [2024-11-28 03:03:14,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:14,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423176077] [2024-11-28 03:03:14,442 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:03:14,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:20,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:24,489 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:03:24,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:24,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423176077] [2024-11-28 03:03:24,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423176077] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:24,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:24,490 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2024-11-28 03:03:24,490 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [806157911] [2024-11-28 03:03:24,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:24,490 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-28 03:03:24,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:24,491 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-28 03:03:24,491 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:03:24,491 INFO L87 Difference]: Start difference. First operand 37293 states and 52991 transitions. Second operand has 12 states, 12 states have (on average 52.583333333333336) internal successors, (631), 12 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:25,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:25,762 INFO L93 Difference]: Finished difference Result 68988 states and 97651 transitions. [2024-11-28 03:03:25,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-28 03:03:25,763 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 52.583333333333336) internal successors, (631), 12 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 790 [2024-11-28 03:03:25,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:25,816 INFO L225 Difference]: With dead ends: 68988 [2024-11-28 03:03:25,816 INFO L226 Difference]: Without dead ends: 55839 [2024-11-28 03:03:25,835 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2024-11-28 03:03:25,836 INFO L435 NwaCegarLoop]: 1031 mSDtfsCounter, 1557 mSDsluCounter, 9185 mSDsCounter, 0 mSdLazyCounter, 602 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1562 SdHoareTripleChecker+Valid, 10216 SdHoareTripleChecker+Invalid, 604 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 602 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:25,836 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1562 Valid, 10216 Invalid, 604 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 602 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-11-28 03:03:25,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55839 states. [2024-11-28 03:03:26,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55839 to 52151. [2024-11-28 03:03:26,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52151 states, 51723 states have (on average 1.4163331593295052) internal successors, (73257), 51723 states have internal predecessors, (73257), 426 states have call successors, (426), 1 states have call predecessors, (426), 1 states have return successors, (426), 426 states have call predecessors, (426), 426 states have call successors, (426) [2024-11-28 03:03:26,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52151 states to 52151 states and 74109 transitions. [2024-11-28 03:03:26,873 INFO L78 Accepts]: Start accepts. Automaton has 52151 states and 74109 transitions. Word has length 790 [2024-11-28 03:03:26,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:26,873 INFO L471 AbstractCegarLoop]: Abstraction has 52151 states and 74109 transitions. [2024-11-28 03:03:26,873 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 52.583333333333336) internal successors, (631), 12 states have internal predecessors, (631), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:26,873 INFO L276 IsEmpty]: Start isEmpty. Operand 52151 states and 74109 transitions. [2024-11-28 03:03:26,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-28 03:03:26,931 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:26,931 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:26,931 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable90 [2024-11-28 03:03:26,931 INFO L396 AbstractCegarLoop]: === Iteration 92 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:26,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:26,932 INFO L85 PathProgramCache]: Analyzing trace with hash 960393063, now seen corresponding path program 1 times [2024-11-28 03:03:26,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:26,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171331172] [2024-11-28 03:03:26,932 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:03:26,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:31,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:32,809 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:03:32,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:32,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [171331172] [2024-11-28 03:03:32,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [171331172] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:32,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:32,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 03:03:32,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408636363] [2024-11-28 03:03:32,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:32,810 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 03:03:32,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:32,811 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 03:03:32,811 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:03:32,812 INFO L87 Difference]: Start difference. First operand 52151 states and 74109 transitions. Second operand has 5 states, 5 states have (on average 126.2) internal successors, (631), 5 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:03:33,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:33,480 INFO L93 Difference]: Finished difference Result 67664 states and 95919 transitions. [2024-11-28 03:03:33,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:03:33,480 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 126.2) internal successors, (631), 5 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 790 [2024-11-28 03:03:33,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:33,529 INFO L225 Difference]: With dead ends: 67664 [2024-11-28 03:03:33,529 INFO L226 Difference]: Without dead ends: 52078 [2024-11-28 03:03:33,551 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:03:33,551 INFO L435 NwaCegarLoop]: 1072 mSDtfsCounter, 339 mSDsluCounter, 3203 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 339 SdHoareTripleChecker+Valid, 4275 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:33,551 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [339 Valid, 4275 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:03:33,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52078 states. [2024-11-28 03:03:34,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52078 to 52076. [2024-11-28 03:03:34,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52076 states, 51648 states have (on average 1.4160858116480792) internal successors, (73138), 51648 states have internal predecessors, (73138), 426 states have call successors, (426), 1 states have call predecessors, (426), 1 states have return successors, (426), 426 states have call predecessors, (426), 426 states have call successors, (426) [2024-11-28 03:03:34,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52076 states to 52076 states and 73990 transitions. [2024-11-28 03:03:34,511 INFO L78 Accepts]: Start accepts. Automaton has 52076 states and 73990 transitions. Word has length 790 [2024-11-28 03:03:34,511 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:34,511 INFO L471 AbstractCegarLoop]: Abstraction has 52076 states and 73990 transitions. [2024-11-28 03:03:34,511 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 126.2) internal successors, (631), 5 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:03:34,511 INFO L276 IsEmpty]: Start isEmpty. Operand 52076 states and 73990 transitions. [2024-11-28 03:03:34,554 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-28 03:03:34,554 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:34,554 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:34,555 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable91 [2024-11-28 03:03:34,555 INFO L396 AbstractCegarLoop]: === Iteration 93 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:34,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:34,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1878118544, now seen corresponding path program 1 times [2024-11-28 03:03:34,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:34,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387447026] [2024-11-28 03:03:34,555 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:03:34,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:40,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:45,419 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 110 proven. 0 refuted. 0 times theorem prover too weak. 758 trivial. 0 not checked. [2024-11-28 03:03:45,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:45,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387447026] [2024-11-28 03:03:45,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387447026] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:45,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:45,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-11-28 03:03:45,420 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977854860] [2024-11-28 03:03:45,420 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:45,421 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:03:45,421 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:45,421 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:03:45,421 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:03:45,422 INFO L87 Difference]: Start difference. First operand 52076 states and 73990 transitions. Second operand has 7 states, 7 states have (on average 78.85714285714286) internal successors, (552), 7 states have internal predecessors, (552), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:46,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:46,102 INFO L93 Difference]: Finished difference Result 71381 states and 101207 transitions. [2024-11-28 03:03:46,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-11-28 03:03:46,102 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 78.85714285714286) internal successors, (552), 7 states have internal predecessors, (552), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 790 [2024-11-28 03:03:46,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:46,140 INFO L225 Difference]: With dead ends: 71381 [2024-11-28 03:03:46,140 INFO L226 Difference]: Without dead ends: 39844 [2024-11-28 03:03:46,164 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:03:46,165 INFO L435 NwaCegarLoop]: 1070 mSDtfsCounter, 134 mSDsluCounter, 5328 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 134 SdHoareTripleChecker+Valid, 6398 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:46,165 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [134 Valid, 6398 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:03:46,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39844 states. [2024-11-28 03:03:46,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39844 to 39844. [2024-11-28 03:03:46,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39844 states, 39502 states have (on average 1.4105361753835248) internal successors, (55719), 39502 states have internal predecessors, (55719), 340 states have call successors, (340), 1 states have call predecessors, (340), 1 states have return successors, (340), 340 states have call predecessors, (340), 340 states have call successors, (340) [2024-11-28 03:03:46,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39844 states to 39844 states and 56399 transitions. [2024-11-28 03:03:46,794 INFO L78 Accepts]: Start accepts. Automaton has 39844 states and 56399 transitions. Word has length 790 [2024-11-28 03:03:46,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:46,794 INFO L471 AbstractCegarLoop]: Abstraction has 39844 states and 56399 transitions. [2024-11-28 03:03:46,794 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 78.85714285714286) internal successors, (552), 7 states have internal predecessors, (552), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:03:46,794 INFO L276 IsEmpty]: Start isEmpty. Operand 39844 states and 56399 transitions. [2024-11-28 03:03:46,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 791 [2024-11-28 03:03:46,827 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:46,827 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:46,827 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable92 [2024-11-28 03:03:46,827 INFO L396 AbstractCegarLoop]: === Iteration 94 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:46,828 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:46,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1138924976, now seen corresponding path program 1 times [2024-11-28 03:03:46,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:46,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252786523] [2024-11-28 03:03:46,828 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:03:46,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:53,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:03:58,444 INFO L134 CoverageAnalysis]: Checked inductivity of 868 backedges. 192 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:03:58,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:03:58,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252786523] [2024-11-28 03:03:58,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252786523] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:03:58,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:03:58,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-11-28 03:03:58,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160403415] [2024-11-28 03:03:58,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:03:58,445 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-11-28 03:03:58,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:58,446 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-11-28 03:03:58,446 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2024-11-28 03:03:58,446 INFO L87 Difference]: Start difference. First operand 39844 states and 56399 transitions. Second operand has 10 states, 10 states have (on average 63.1) internal successors, (631), 10 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:03:59,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:59,427 INFO L93 Difference]: Finished difference Result 66242 states and 93366 transitions. [2024-11-28 03:03:59,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 03:03:59,428 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 63.1) internal successors, (631), 10 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 790 [2024-11-28 03:03:59,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:59,488 INFO L225 Difference]: With dead ends: 66242 [2024-11-28 03:03:59,489 INFO L226 Difference]: Without dead ends: 53245 [2024-11-28 03:03:59,512 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2024-11-28 03:03:59,513 INFO L435 NwaCegarLoop]: 1944 mSDtfsCounter, 1163 mSDsluCounter, 12732 mSDsCounter, 0 mSdLazyCounter, 205 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1168 SdHoareTripleChecker+Valid, 14676 SdHoareTripleChecker+Invalid, 207 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 205 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:59,513 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1168 Valid, 14676 Invalid, 207 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 205 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 03:03:59,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53245 states. [2024-11-28 03:04:00,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53245 to 41116. [2024-11-28 03:04:00,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41116 states, 40754 states have (on average 1.4082298670069195) internal successors, (57391), 40754 states have internal predecessors, (57391), 360 states have call successors, (360), 1 states have call predecessors, (360), 1 states have return successors, (360), 360 states have call predecessors, (360), 360 states have call successors, (360) [2024-11-28 03:04:00,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41116 states to 41116 states and 58111 transitions. [2024-11-28 03:04:00,510 INFO L78 Accepts]: Start accepts. Automaton has 41116 states and 58111 transitions. Word has length 790 [2024-11-28 03:04:00,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:04:00,510 INFO L471 AbstractCegarLoop]: Abstraction has 41116 states and 58111 transitions. [2024-11-28 03:04:00,510 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 63.1) internal successors, (631), 10 states have internal predecessors, (631), 2 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:04:00,510 INFO L276 IsEmpty]: Start isEmpty. Operand 41116 states and 58111 transitions. [2024-11-28 03:04:00,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2024-11-28 03:04:00,544 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:04:00,545 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:04:00,545 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable93 [2024-11-28 03:04:00,545 INFO L396 AbstractCegarLoop]: === Iteration 95 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:04:00,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:04:00,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1223874564, now seen corresponding path program 1 times [2024-11-28 03:04:00,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:04:00,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [742830500] [2024-11-28 03:04:00,546 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:04:00,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:04:07,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:04:11,428 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 124 proven. 71 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:04:11,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:04:11,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [742830500] [2024-11-28 03:04:11,428 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [742830500] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:04:11,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [418786952] [2024-11-28 03:04:11,429 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:04:11,429 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:04:11,429 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:04:11,431 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:04:11,432 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2024-11-28 03:04:23,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:04:24,023 INFO L256 TraceCheckSpWp]: Trace formula consists of 3758 conjuncts, 137 conjuncts are in the unsatisfiable core [2024-11-28 03:04:24,036 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:04:27,163 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 275 proven. 52 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2024-11-28 03:04:27,163 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:04:29,888 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 195 proven. 0 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:04:29,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [418786952] provided 1 perfect and 1 imperfect interpolant sequences [2024-11-28 03:04:29,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:04:29,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [14] imperfect sequences [8, 27] total 45 [2024-11-28 03:04:29,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514924802] [2024-11-28 03:04:29,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:04:29,889 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2024-11-28 03:04:29,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:04:29,890 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2024-11-28 03:04:29,890 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=151, Invalid=1829, Unknown=0, NotChecked=0, Total=1980 [2024-11-28 03:04:29,890 INFO L87 Difference]: Start difference. First operand 41116 states and 58111 transitions. Second operand has 14 states, 14 states have (on average 45.142857142857146) internal successors, (632), 14 states have internal predecessors, (632), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:04:35,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:04:35,430 INFO L93 Difference]: Finished difference Result 78718 states and 110235 transitions. [2024-11-28 03:04:35,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2024-11-28 03:04:35,431 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 45.142857142857146) internal successors, (632), 14 states have internal predecessors, (632), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 791 [2024-11-28 03:04:35,432 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:04:35,479 INFO L225 Difference]: With dead ends: 78718 [2024-11-28 03:04:35,480 INFO L226 Difference]: Without dead ends: 62089 [2024-11-28 03:04:35,498 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1599 GetRequests, 1547 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 708 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=209, Invalid=2653, Unknown=0, NotChecked=0, Total=2862 [2024-11-28 03:04:35,498 INFO L435 NwaCegarLoop]: 1652 mSDtfsCounter, 1659 mSDsluCounter, 16462 mSDsCounter, 0 mSdLazyCounter, 3777 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1663 SdHoareTripleChecker+Valid, 18114 SdHoareTripleChecker+Invalid, 3780 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 3777 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 3.8s IncrementalHoareTripleChecker+Time [2024-11-28 03:04:35,499 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1663 Valid, 18114 Invalid, 3780 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [3 Valid, 3777 Invalid, 0 Unknown, 0 Unchecked, 3.8s Time] [2024-11-28 03:04:35,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62089 states. [2024-11-28 03:04:36,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62089 to 47253. [2024-11-28 03:04:36,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47253 states, 46839 states have (on average 1.3980443647387861) internal successors, (65483), 46839 states have internal predecessors, (65483), 412 states have call successors, (412), 1 states have call predecessors, (412), 1 states have return successors, (412), 412 states have call predecessors, (412), 412 states have call successors, (412) [2024-11-28 03:04:36,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47253 states to 47253 states and 66307 transitions. [2024-11-28 03:04:36,662 INFO L78 Accepts]: Start accepts. Automaton has 47253 states and 66307 transitions. Word has length 791 [2024-11-28 03:04:36,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:04:36,662 INFO L471 AbstractCegarLoop]: Abstraction has 47253 states and 66307 transitions. [2024-11-28 03:04:36,663 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 45.142857142857146) internal successors, (632), 14 states have internal predecessors, (632), 3 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-11-28 03:04:36,663 INFO L276 IsEmpty]: Start isEmpty. Operand 47253 states and 66307 transitions. [2024-11-28 03:04:36,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2024-11-28 03:04:36,701 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:04:36,701 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:04:36,734 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Forceful destruction successful, exit code 0 [2024-11-28 03:04:36,902 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable94 [2024-11-28 03:04:36,902 INFO L396 AbstractCegarLoop]: === Iteration 96 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:04:36,902 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:04:36,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1646000144, now seen corresponding path program 1 times [2024-11-28 03:04:36,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:04:36,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398405536] [2024-11-28 03:04:36,903 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:04:36,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:04:37,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:04:38,543 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 115 proven. 0 refuted. 0 times theorem prover too weak. 756 trivial. 0 not checked. [2024-11-28 03:04:38,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:04:38,543 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398405536] [2024-11-28 03:04:38,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398405536] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:04:38,543 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:04:38,543 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-11-28 03:04:38,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767493271] [2024-11-28 03:04:38,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:04:38,544 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:04:38,544 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:04:38,545 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:04:38,545 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:04:38,545 INFO L87 Difference]: Start difference. First operand 47253 states and 66307 transitions. Second operand has 6 states, 6 states have (on average 93.16666666666667) internal successors, (559), 6 states have internal predecessors, (559), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:04:40,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:04:40,071 INFO L93 Difference]: Finished difference Result 75794 states and 106198 transitions. [2024-11-28 03:04:40,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:04:40,071 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 93.16666666666667) internal successors, (559), 6 states have internal predecessors, (559), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 791 [2024-11-28 03:04:40,072 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:04:40,111 INFO L225 Difference]: With dead ends: 75794 [2024-11-28 03:04:40,111 INFO L226 Difference]: Without dead ends: 47525 [2024-11-28 03:04:40,133 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:04:40,134 INFO L435 NwaCegarLoop]: 802 mSDtfsCounter, 685 mSDsluCounter, 2358 mSDsCounter, 0 mSdLazyCounter, 1152 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 685 SdHoareTripleChecker+Valid, 3160 SdHoareTripleChecker+Invalid, 1153 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-11-28 03:04:40,134 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [685 Valid, 3160 Invalid, 1153 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1152 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-11-28 03:04:40,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47525 states. [2024-11-28 03:04:41,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47525 to 47389. [2024-11-28 03:04:41,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47389 states, 46975 states have (on average 1.3968919638105375) internal successors, (65619), 46975 states have internal predecessors, (65619), 412 states have call successors, (412), 1 states have call predecessors, (412), 1 states have return successors, (412), 412 states have call predecessors, (412), 412 states have call successors, (412) [2024-11-28 03:04:41,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47389 states to 47389 states and 66443 transitions. [2024-11-28 03:04:41,364 INFO L78 Accepts]: Start accepts. Automaton has 47389 states and 66443 transitions. Word has length 791 [2024-11-28 03:04:41,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:04:41,364 INFO L471 AbstractCegarLoop]: Abstraction has 47389 states and 66443 transitions. [2024-11-28 03:04:41,364 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 93.16666666666667) internal successors, (559), 6 states have internal predecessors, (559), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:04:41,364 INFO L276 IsEmpty]: Start isEmpty. Operand 47389 states and 66443 transitions. [2024-11-28 03:04:41,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 792 [2024-11-28 03:04:41,399 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:04:41,399 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:04:41,399 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable95 [2024-11-28 03:04:41,400 INFO L396 AbstractCegarLoop]: === Iteration 97 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:04:41,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:04:41,400 INFO L85 PathProgramCache]: Analyzing trace with hash -312404118, now seen corresponding path program 1 times [2024-11-28 03:04:41,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:04:41,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618554021] [2024-11-28 03:04:41,400 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:04:41,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:04:46,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:04:48,914 INFO L134 CoverageAnalysis]: Checked inductivity of 870 backedges. 181 proven. 0 refuted. 0 times theorem prover too weak. 689 trivial. 0 not checked. [2024-11-28 03:04:48,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:04:48,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1618554021] [2024-11-28 03:04:48,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1618554021] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:04:48,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:04:48,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 03:04:48,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094103143] [2024-11-28 03:04:48,914 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:04:48,915 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 03:04:48,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:04:48,915 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:04:48,915 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:04:48,916 INFO L87 Difference]: Start difference. First operand 47389 states and 66443 transitions. Second operand has 4 states, 4 states have (on average 155.5) internal successors, (622), 4 states have internal predecessors, (622), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-28 03:04:49,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:04:49,420 INFO L93 Difference]: Finished difference Result 55995 states and 78255 transitions. [2024-11-28 03:04:49,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:04:49,420 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 155.5) internal successors, (622), 4 states have internal predecessors, (622), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) Word has length 791 [2024-11-28 03:04:49,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:04:49,449 INFO L225 Difference]: With dead ends: 55995 [2024-11-28 03:04:49,449 INFO L226 Difference]: Without dead ends: 29329 [2024-11-28 03:04:49,467 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:04:49,467 INFO L435 NwaCegarLoop]: 1073 mSDtfsCounter, 129 mSDsluCounter, 1916 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 129 SdHoareTripleChecker+Valid, 2989 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:04:49,467 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [129 Valid, 2989 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:04:49,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29329 states. [2024-11-28 03:04:50,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29329 to 28481. [2024-11-28 03:04:50,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28481 states, 28175 states have (on average 1.3899201419698315) internal successors, (39161), 28175 states have internal predecessors, (39161), 304 states have call successors, (304), 1 states have call predecessors, (304), 1 states have return successors, (304), 304 states have call predecessors, (304), 304 states have call successors, (304) [2024-11-28 03:04:50,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28481 states to 28481 states and 39769 transitions. [2024-11-28 03:04:50,179 INFO L78 Accepts]: Start accepts. Automaton has 28481 states and 39769 transitions. Word has length 791 [2024-11-28 03:04:50,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:04:50,180 INFO L471 AbstractCegarLoop]: Abstraction has 28481 states and 39769 transitions. [2024-11-28 03:04:50,180 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 155.5) internal successors, (622), 4 states have internal predecessors, (622), 2 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 2 states have call predecessors, (9), 2 states have call successors, (9) [2024-11-28 03:04:50,180 INFO L276 IsEmpty]: Start isEmpty. Operand 28481 states and 39769 transitions. [2024-11-28 03:04:50,204 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-11-28 03:04:50,204 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:04:50,204 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:04:50,204 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable96 [2024-11-28 03:04:50,205 INFO L396 AbstractCegarLoop]: === Iteration 98 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:04:50,205 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:04:50,205 INFO L85 PathProgramCache]: Analyzing trace with hash 566832763, now seen corresponding path program 1 times [2024-11-28 03:04:50,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:04:50,205 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372309705] [2024-11-28 03:04:50,205 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:04:50,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:04:56,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:05:00,678 INFO L134 CoverageAnalysis]: Checked inductivity of 874 backedges. 121 proven. 77 refuted. 0 times theorem prover too weak. 676 trivial. 0 not checked. [2024-11-28 03:05:00,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:05:00,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372309705] [2024-11-28 03:05:00,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372309705] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:05:00,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [801686391] [2024-11-28 03:05:00,679 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:05:00,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:05:00,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:05:00,680 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:05:00,682 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2024-11-28 03:05:21,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:05:21,819 INFO L256 TraceCheckSpWp]: Trace formula consists of 3759 conjuncts, 129 conjuncts are in the unsatisfiable core [2024-11-28 03:05:21,837 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:05:25,732 INFO L134 CoverageAnalysis]: Checked inductivity of 874 backedges. 160 proven. 110 refuted. 0 times theorem prover too weak. 604 trivial. 0 not checked. [2024-11-28 03:05:25,732 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:05:33,232 INFO L134 CoverageAnalysis]: Checked inductivity of 874 backedges. 159 proven. 75 refuted. 0 times theorem prover too weak. 640 trivial. 0 not checked. [2024-11-28 03:05:33,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [801686391] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:05:33,233 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:05:33,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 28, 28] total 63 [2024-11-28 03:05:33,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081769319] [2024-11-28 03:05:33,233 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:05:33,235 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 63 states [2024-11-28 03:05:33,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:05:33,237 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2024-11-28 03:05:33,238 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=696, Invalid=3210, Unknown=0, NotChecked=0, Total=3906 [2024-11-28 03:05:33,239 INFO L87 Difference]: Start difference. First operand 28481 states and 39769 transitions. Second operand has 63 states, 63 states have (on average 26.238095238095237) internal successors, (1653), 63 states have internal predecessors, (1653), 9 states have call successors, (29), 2 states have call predecessors, (29), 2 states have return successors, (29), 9 states have call predecessors, (29), 9 states have call successors, (29) [2024-11-28 03:05:47,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:05:47,507 INFO L93 Difference]: Finished difference Result 107723 states and 150153 transitions. [2024-11-28 03:05:47,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2024-11-28 03:05:47,508 INFO L78 Accepts]: Start accepts. Automaton has has 63 states, 63 states have (on average 26.238095238095237) internal successors, (1653), 63 states have internal predecessors, (1653), 9 states have call successors, (29), 2 states have call predecessors, (29), 2 states have return successors, (29), 9 states have call predecessors, (29), 9 states have call successors, (29) Word has length 792 [2024-11-28 03:05:47,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:05:47,612 INFO L225 Difference]: With dead ends: 107723 [2024-11-28 03:05:47,612 INFO L226 Difference]: Without dead ends: 84665 [2024-11-28 03:05:47,652 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1653 GetRequests, 1536 SyntacticMatches, 0 SemanticMatches, 117 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3286 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=2554, Invalid=11488, Unknown=0, NotChecked=0, Total=14042 [2024-11-28 03:05:47,652 INFO L435 NwaCegarLoop]: 1048 mSDtfsCounter, 20357 mSDsluCounter, 27614 mSDsCounter, 0 mSdLazyCounter, 15652 mSolverCounterSat, 87 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20363 SdHoareTripleChecker+Valid, 28662 SdHoareTripleChecker+Invalid, 15739 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 87 IncrementalHoareTripleChecker+Valid, 15652 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 9.2s IncrementalHoareTripleChecker+Time [2024-11-28 03:05:47,653 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [20363 Valid, 28662 Invalid, 15739 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [87 Valid, 15652 Invalid, 0 Unknown, 0 Unchecked, 9.2s Time] [2024-11-28 03:05:47,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84665 states. [2024-11-28 03:05:49,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84665 to 34751. [2024-11-28 03:05:49,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34751 states, 34263 states have (on average 1.3825701193707498) internal successors, (47371), 34263 states have internal predecessors, (47371), 486 states have call successors, (486), 1 states have call predecessors, (486), 1 states have return successors, (486), 486 states have call predecessors, (486), 486 states have call successors, (486) [2024-11-28 03:05:49,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34751 states to 34751 states and 48343 transitions. [2024-11-28 03:05:49,213 INFO L78 Accepts]: Start accepts. Automaton has 34751 states and 48343 transitions. Word has length 792 [2024-11-28 03:05:49,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:05:49,214 INFO L471 AbstractCegarLoop]: Abstraction has 34751 states and 48343 transitions. [2024-11-28 03:05:49,214 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 63 states, 63 states have (on average 26.238095238095237) internal successors, (1653), 63 states have internal predecessors, (1653), 9 states have call successors, (29), 2 states have call predecessors, (29), 2 states have return successors, (29), 9 states have call predecessors, (29), 9 states have call successors, (29) [2024-11-28 03:05:49,214 INFO L276 IsEmpty]: Start isEmpty. Operand 34751 states and 48343 transitions. [2024-11-28 03:05:49,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 793 [2024-11-28 03:05:49,247 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:05:49,248 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:05:49,287 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2024-11-28 03:05:49,448 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable97 [2024-11-28 03:05:49,448 INFO L396 AbstractCegarLoop]: === Iteration 99 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:05:49,449 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:05:49,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1474435877, now seen corresponding path program 1 times [2024-11-28 03:05:49,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:05:49,449 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332316557] [2024-11-28 03:05:49,449 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:05:49,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:05:55,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:05:58,241 INFO L134 CoverageAnalysis]: Checked inductivity of 872 backedges. 128 proven. 3 refuted. 0 times theorem prover too weak. 741 trivial. 0 not checked. [2024-11-28 03:05:58,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:05:58,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332316557] [2024-11-28 03:05:58,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332316557] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:05:58,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [72656823] [2024-11-28 03:05:58,242 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:05:58,242 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:05:58,242 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:05:58,245 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:05:58,247 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2024-11-28 03:06:10,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:06:10,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 3759 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:06:10,088 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:06:10,145 INFO L134 CoverageAnalysis]: Checked inductivity of 872 backedges. 147 proven. 0 refuted. 0 times theorem prover too weak. 725 trivial. 0 not checked. [2024-11-28 03:06:10,146 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:06:10,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [72656823] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:06:10,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:06:10,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2024-11-28 03:06:10,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717714452] [2024-11-28 03:06:10,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:06:10,147 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:06:10,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:06:10,147 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:06:10,147 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:06:10,147 INFO L87 Difference]: Start difference. First operand 34751 states and 48343 transitions. Second operand has 6 states, 5 states have (on average 113.2) internal successors, (566), 6 states have internal predecessors, (566), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:06:10,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:06:10,958 INFO L93 Difference]: Finished difference Result 56937 states and 79353 transitions. [2024-11-28 03:06:10,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:06:10,958 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 113.2) internal successors, (566), 6 states have internal predecessors, (566), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 792 [2024-11-28 03:06:10,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:06:10,997 INFO L225 Difference]: With dead ends: 56937 [2024-11-28 03:06:10,998 INFO L226 Difference]: Without dead ends: 34751 [2024-11-28 03:06:11,017 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 799 GetRequests, 789 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:06:11,018 INFO L435 NwaCegarLoop]: 1073 mSDtfsCounter, 0 mSDsluCounter, 4269 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 5342 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:06:11,018 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 5342 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:06:11,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34751 states. [2024-11-28 03:06:12,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34751 to 34751. [2024-11-28 03:06:12,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34751 states, 34263 states have (on average 1.3811108192510873) internal successors, (47321), 34263 states have internal predecessors, (47321), 486 states have call successors, (486), 1 states have call predecessors, (486), 1 states have return successors, (486), 486 states have call predecessors, (486), 486 states have call successors, (486) [2024-11-28 03:06:12,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34751 states to 34751 states and 48293 transitions. [2024-11-28 03:06:12,101 INFO L78 Accepts]: Start accepts. Automaton has 34751 states and 48293 transitions. Word has length 792 [2024-11-28 03:06:12,102 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:06:12,102 INFO L471 AbstractCegarLoop]: Abstraction has 34751 states and 48293 transitions. [2024-11-28 03:06:12,102 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 113.2) internal successors, (566), 6 states have internal predecessors, (566), 2 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-11-28 03:06:12,102 INFO L276 IsEmpty]: Start isEmpty. Operand 34751 states and 48293 transitions. [2024-11-28 03:06:12,136 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 794 [2024-11-28 03:06:12,136 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:06:12,136 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:06:12,174 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Ended with exit code 0 [2024-11-28 03:06:12,337 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable98,39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:06:12,337 INFO L396 AbstractCegarLoop]: === Iteration 100 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:06:12,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:06:12,337 INFO L85 PathProgramCache]: Analyzing trace with hash -699996636, now seen corresponding path program 1 times [2024-11-28 03:06:12,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:06:12,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052382863] [2024-11-28 03:06:12,338 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:06:12,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:06:16,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:06:18,556 INFO L134 CoverageAnalysis]: Checked inductivity of 873 backedges. 120 proven. 4 refuted. 0 times theorem prover too weak. 749 trivial. 0 not checked. [2024-11-28 03:06:18,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:06:18,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052382863] [2024-11-28 03:06:18,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052382863] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:06:18,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1500425903] [2024-11-28 03:06:18,557 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:06:18,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:06:18,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:06:18,558 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:06:18,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2024-11-28 03:06:38,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:06:38,610 INFO L256 TraceCheckSpWp]: Trace formula consists of 3762 conjuncts, 167 conjuncts are in the unsatisfiable core [2024-11-28 03:06:38,629 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:06:45,331 INFO L134 CoverageAnalysis]: Checked inductivity of 873 backedges. 156 proven. 113 refuted. 0 times theorem prover too weak. 604 trivial. 0 not checked. [2024-11-28 03:06:45,331 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:06:53,958 INFO L134 CoverageAnalysis]: Checked inductivity of 873 backedges. 228 proven. 5 refuted. 0 times theorem prover too weak. 640 trivial. 0 not checked. [2024-11-28 03:06:53,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1500425903] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:06:53,958 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:06:53,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 26, 24] total 51 [2024-11-28 03:06:53,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794804649] [2024-11-28 03:06:53,959 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:06:53,960 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 51 states [2024-11-28 03:06:53,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:06:53,962 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2024-11-28 03:06:53,962 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=599, Invalid=1951, Unknown=0, NotChecked=0, Total=2550 [2024-11-28 03:06:53,963 INFO L87 Difference]: Start difference. First operand 34751 states and 48293 transitions. Second operand has 51 states, 51 states have (on average 27.862745098039216) internal successors, (1421), 51 states have internal predecessors, (1421), 9 states have call successors, (24), 2 states have call predecessors, (24), 2 states have return successors, (24), 9 states have call predecessors, (24), 9 states have call successors, (24) [2024-11-28 03:07:01,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:01,212 INFO L93 Difference]: Finished difference Result 68465 states and 95135 transitions. [2024-11-28 03:07:01,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2024-11-28 03:07:01,213 INFO L78 Accepts]: Start accepts. Automaton has has 51 states, 51 states have (on average 27.862745098039216) internal successors, (1421), 51 states have internal predecessors, (1421), 9 states have call successors, (24), 2 states have call predecessors, (24), 2 states have return successors, (24), 9 states have call predecessors, (24), 9 states have call successors, (24) Word has length 793 [2024-11-28 03:07:01,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:01,261 INFO L225 Difference]: With dead ends: 68465 [2024-11-28 03:07:01,261 INFO L226 Difference]: Without dead ends: 46307 [2024-11-28 03:07:01,281 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1607 GetRequests, 1542 SyntacticMatches, 1 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1387 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1064, Invalid=3226, Unknown=0, NotChecked=0, Total=4290 [2024-11-28 03:07:01,282 INFO L435 NwaCegarLoop]: 763 mSDtfsCounter, 4566 mSDsluCounter, 14567 mSDsCounter, 0 mSdLazyCounter, 6879 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4567 SdHoareTripleChecker+Valid, 15330 SdHoareTripleChecker+Invalid, 6896 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 6879 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:01,282 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4567 Valid, 15330 Invalid, 6896 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [17 Valid, 6879 Invalid, 0 Unknown, 0 Unchecked, 5.1s Time] [2024-11-28 03:07:01,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46307 states. [2024-11-28 03:07:02,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46307 to 34601. [2024-11-28 03:07:02,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34601 states, 34113 states have (on average 1.381320904054173) internal successors, (47121), 34113 states have internal predecessors, (47121), 486 states have call successors, (486), 1 states have call predecessors, (486), 1 states have return successors, (486), 486 states have call predecessors, (486), 486 states have call successors, (486) [2024-11-28 03:07:02,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34601 states to 34601 states and 48093 transitions. [2024-11-28 03:07:02,281 INFO L78 Accepts]: Start accepts. Automaton has 34601 states and 48093 transitions. Word has length 793 [2024-11-28 03:07:02,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:02,282 INFO L471 AbstractCegarLoop]: Abstraction has 34601 states and 48093 transitions. [2024-11-28 03:07:02,282 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 51 states, 51 states have (on average 27.862745098039216) internal successors, (1421), 51 states have internal predecessors, (1421), 9 states have call successors, (24), 2 states have call predecessors, (24), 2 states have return successors, (24), 9 states have call predecessors, (24), 9 states have call successors, (24) [2024-11-28 03:07:02,282 INFO L276 IsEmpty]: Start isEmpty. Operand 34601 states and 48093 transitions. [2024-11-28 03:07:02,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 794 [2024-11-28 03:07:02,314 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:02,315 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:02,356 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Ended with exit code 0 [2024-11-28 03:07:02,515 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable99,40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:02,515 INFO L396 AbstractCegarLoop]: === Iteration 101 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:02,516 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:02,516 INFO L85 PathProgramCache]: Analyzing trace with hash 1134932309, now seen corresponding path program 1 times [2024-11-28 03:07:02,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:07:02,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294039809] [2024-11-28 03:07:02,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:02,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:07:13,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:07:13,792 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:07:24,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:07:25,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-28 03:07:25,311 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-28 03:07:25,312 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-28 03:07:25,314 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable100 [2024-11-28 03:07:25,317 INFO L422 BasicCegarLoop]: Path program histogram: [2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:25,919 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-28 03:07:25,923 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 03:07:25 BoogieIcfgContainer [2024-11-28 03:07:25,923 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-28 03:07:25,924 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-28 03:07:25,924 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-28 03:07:25,925 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-28 03:07:25,926 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 02:55:05" (3/4) ... [2024-11-28 03:07:25,929 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-11-28 03:07:25,930 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-28 03:07:25,931 INFO L158 Benchmark]: Toolchain (without parser) took 745667.96ms. Allocated memory was 142.6MB in the beginning and 5.0GB in the end (delta: 4.9GB). Free memory was 99.5MB in the beginning and 1.9GB in the end (delta: -1.8GB). Peak memory consumption was 3.1GB. Max. memory is 16.1GB. [2024-11-28 03:07:25,931 INFO L158 Benchmark]: CDTParser took 1.92ms. Allocated memory is still 167.8MB. Free memory is still 103.2MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:07:25,931 INFO L158 Benchmark]: CACSL2BoogieTranslator took 767.55ms. Allocated memory is still 142.6MB. Free memory was 99.5MB in the beginning and 58.2MB in the end (delta: 41.3MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. [2024-11-28 03:07:25,935 INFO L158 Benchmark]: Boogie Procedure Inliner took 471.65ms. Allocated memory was 142.6MB in the beginning and 151.0MB in the end (delta: 8.4MB). Free memory was 58.2MB in the beginning and 68.4MB in the end (delta: -10.1MB). Peak memory consumption was 69.3MB. Max. memory is 16.1GB. [2024-11-28 03:07:25,935 INFO L158 Benchmark]: Boogie Preprocessor took 403.63ms. Allocated memory was 151.0MB in the beginning and 453.0MB in the end (delta: 302.0MB). Free memory was 68.4MB in the beginning and 376.0MB in the end (delta: -307.7MB). Peak memory consumption was 32.2MB. Max. memory is 16.1GB. [2024-11-28 03:07:25,935 INFO L158 Benchmark]: RCFGBuilder took 4057.10ms. Allocated memory is still 453.0MB. Free memory was 376.0MB in the beginning and 217.5MB in the end (delta: 158.5MB). Peak memory consumption was 164.1MB. Max. memory is 16.1GB. [2024-11-28 03:07:25,935 INFO L158 Benchmark]: TraceAbstraction took 739950.64ms. Allocated memory was 453.0MB in the beginning and 5.0GB in the end (delta: 4.6GB). Free memory was 217.5MB in the beginning and 1.9GB in the end (delta: -1.7GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. [2024-11-28 03:07:25,936 INFO L158 Benchmark]: Witness Printer took 6.05ms. Allocated memory is still 5.0GB. Free memory was 1.9GB in the beginning and 1.9GB in the end (delta: 211.5kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:07:25,937 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 1.92ms. Allocated memory is still 167.8MB. Free memory is still 103.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 767.55ms. Allocated memory is still 142.6MB. Free memory was 99.5MB in the beginning and 58.2MB in the end (delta: 41.3MB). Peak memory consumption was 41.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 471.65ms. Allocated memory was 142.6MB in the beginning and 151.0MB in the end (delta: 8.4MB). Free memory was 58.2MB in the beginning and 68.4MB in the end (delta: -10.1MB). Peak memory consumption was 69.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 403.63ms. Allocated memory was 151.0MB in the beginning and 453.0MB in the end (delta: 302.0MB). Free memory was 68.4MB in the beginning and 376.0MB in the end (delta: -307.7MB). Peak memory consumption was 32.2MB. Max. memory is 16.1GB. * RCFGBuilder took 4057.10ms. Allocated memory is still 453.0MB. Free memory was 376.0MB in the beginning and 217.5MB in the end (delta: 158.5MB). Peak memory consumption was 164.1MB. Max. memory is 16.1GB. * TraceAbstraction took 739950.64ms. Allocated memory was 453.0MB in the beginning and 5.0GB in the end (delta: 4.6GB). Free memory was 217.5MB in the beginning and 1.9GB in the end (delta: -1.7GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. * Witness Printer took 6.05ms. Allocated memory is still 5.0GB. Free memory was 1.9GB in the beginning and 1.9GB in the end (delta: 211.5kB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 21]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 187, overapproximation of bitwiseOr at line 142, overapproximation of bitwiseOr at line 403, overapproximation of bitwiseOr at line 226, overapproximation of bitwiseAnd at line 318, overapproximation of bitwiseAnd at line 238, overapproximation of bitwiseAnd at line 502, overapproximation of bitwiseAnd at line 578, overapproximation of bitwiseAnd at line 641, overapproximation of bitwiseAnd at line 274, overapproximation of bitwiseAnd at line 271, overapproximation of bitwiseAnd at line 128, overapproximation of bitwiseAnd at line 622, overapproximation of bitwiseAnd at line 657, overapproximation of bitwiseAnd at line 765, overapproximation of bitwiseAnd at line 148, overapproximation of bitwiseAnd at line 408, overapproximation of bitwiseAnd at line 284. Possible FailurePath: [L26] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L27] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L29] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L30] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L32] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 2); [L33] const SORT_5 msb_SORT_5 = (SORT_5)1 << (2 - 1); [L35] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 8); [L36] const SORT_11 msb_SORT_11 = (SORT_11)1 << (8 - 1); [L38] const SORT_12 mask_SORT_12 = (SORT_12)-1 >> (sizeof(SORT_12) * 8 - 3); [L39] const SORT_12 msb_SORT_12 = (SORT_12)1 << (3 - 1); [L42] const SORT_15 mask_SORT_15 = (SORT_15)-1 >> (sizeof(SORT_15) * 8 - 4); [L43] const SORT_15 msb_SORT_15 = (SORT_15)1 << (4 - 1); [L45] const SORT_36 mask_SORT_36 = (SORT_36)-1 >> (sizeof(SORT_36) * 8 - 5); [L46] const SORT_36 msb_SORT_36 = (SORT_36)1 << (5 - 1); [L48] const SORT_38 mask_SORT_38 = (SORT_38)-1 >> (sizeof(SORT_38) * 8 - 6); [L49] const SORT_38 msb_SORT_38 = (SORT_38)1 << (6 - 1); [L51] const SORT_40 mask_SORT_40 = (SORT_40)-1 >> (sizeof(SORT_40) * 8 - 7); [L52] const SORT_40 msb_SORT_40 = (SORT_40)1 << (7 - 1); [L54] const SORT_229 mask_SORT_229 = (SORT_229)-1 >> (sizeof(SORT_229) * 8 - 32); [L55] const SORT_229 msb_SORT_229 = (SORT_229)1 << (32 - 1); [L57] const SORT_15 var_27 = 8; [L58] const SORT_15 var_99 = 0; [L59] const SORT_1 var_109 = 1; [L60] const SORT_1 var_110 = 0; [L61] const SORT_11 var_183 = 0; [L62] const SORT_229 var_230 = 2; [L63] const SORT_11 var_410 = 255; [L65] SORT_1 input_2; [L66] SORT_3 input_4; [L67] SORT_5 input_6; [L68] SORT_3 input_7; [L69] SORT_5 input_8; [L70] SORT_1 input_9; [L71] SORT_1 input_10; [L73] SORT_13 state_14; [L74] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] state_14[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L74] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L74] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L75] SORT_15 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L76] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L76] SORT_15 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L77] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L77] SORT_11 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L78] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L78] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L79] SORT_13 state_44; [L80] unsigned char i = 0; VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND TRUE i < (1 << 3) VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] state_44[i] = __VERIFIER_nondet_uchar() & mask_SORT_11 [L80] ++i VAL [i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L80] COND FALSE !(i < (1 << 3)) VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L81] SORT_15 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L82] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L82] SORT_15 state_48 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L83] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L83] SORT_11 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L84] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L84] SORT_1 state_85 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L85] SORT_1 state_86 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] EXPR __VERIFIER_nondet_uchar() & mask_SORT_15 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L86] SORT_15 state_89 = __VERIFIER_nondet_uchar() & mask_SORT_15; [L87] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L87] SORT_11 state_105 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L88] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L88] SORT_1 state_111 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L89] SORT_1 state_333 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L90] SORT_1 state_334 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L91] SORT_1 state_335 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L92] SORT_1 state_336 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L93] SORT_1 state_337 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L94] SORT_1 state_338 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L95] SORT_1 state_339 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L96] SORT_1 state_340 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 init_112_arg_1 = var_109; [L99] state_111 = init_112_arg_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=-255, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=1, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=1, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=0, var_115_arg_1=-256, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND FALSE !(!(cond)) [L411] RET __VERIFIER_assert(!(bad_116_arg_0)) [L413] SORT_1 var_298_arg_0 = var_136; [L414] SORT_1 var_298_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_298_arg_0=0, var_298_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] EXPR var_298_arg_0 | var_298_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L415] SORT_1 var_298 = var_298_arg_0 | var_298_arg_1; [L416] SORT_1 var_299_arg_0 = var_298; [L417] SORT_1 var_299_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299_arg_0=0, var_299_arg_1=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] EXPR var_299_arg_0 | var_299_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L418] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L419] EXPR var_299 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L419] var_299 = var_299 & mask_SORT_1 [L420] SORT_1 var_310_arg_0 = var_136; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_310_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] EXPR var_310_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L421] var_310_arg_0 = var_310_arg_0 & mask_SORT_1 [L422] SORT_15 var_310 = var_310_arg_0; [L423] SORT_15 var_311_arg_0 = state_16; [L424] SORT_15 var_311_arg_1 = var_310; [L425] SORT_15 var_311 = var_311_arg_0 + var_311_arg_1; [L426] SORT_1 var_404_arg_0 = var_299; [L427] SORT_15 var_404_arg_1 = var_311; [L428] SORT_15 var_404_arg_2 = state_16; [L429] SORT_15 var_404 = var_404_arg_0 ? var_404_arg_1 : var_404_arg_2; [L430] SORT_1 var_405_arg_0 = input_9; [L431] SORT_15 var_405_arg_1 = var_99; [L432] SORT_15 var_405_arg_2 = var_404; [L433] SORT_15 var_405 = var_405_arg_0 ? var_405_arg_1 : var_405_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_405=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] EXPR var_405 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L434] var_405 = var_405 & mask_SORT_15 [L435] SORT_15 next_406_arg_1 = var_405; [L436] SORT_1 var_304_arg_0 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_304_arg_0=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] EXPR var_304_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_299=0, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L437] var_304_arg_0 = var_304_arg_0 & mask_SORT_1 [L438] SORT_15 var_304 = var_304_arg_0; [L439] SORT_15 var_305_arg_0 = state_19; [L440] SORT_15 var_305_arg_1 = var_304; [L441] SORT_15 var_305 = var_305_arg_0 + var_305_arg_1; [L442] SORT_1 var_407_arg_0 = var_299; [L443] SORT_15 var_407_arg_1 = var_305; [L444] SORT_15 var_407_arg_2 = state_19; [L445] SORT_15 var_407 = var_407_arg_0 ? var_407_arg_1 : var_407_arg_2; [L446] SORT_1 var_408_arg_0 = input_9; [L447] SORT_15 var_408_arg_1 = var_99; [L448] SORT_15 var_408_arg_2 = var_407; [L449] SORT_15 var_408 = var_408_arg_0 ? var_408_arg_1 : var_408_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_408=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] EXPR var_408 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L450] var_408 = var_408 & mask_SORT_15 [L451] SORT_15 next_409_arg_1 = var_408; [L452] SORT_11 var_417_arg_0 = var_410; [L453] SORT_1 var_417 = var_417_arg_0 != 0; [L454] SORT_3 var_258_arg_0 = input_4; [L455] SORT_11 var_258 = var_258_arg_0 >> 8; [L456] SORT_11* var_18_arg_0 = state_14; [L457] SORT_12 var_18_arg_1 = var_17; [L458] EXPR var_18_arg_0[(unsigned char) var_18_arg_1] [L458] SORT_11 var_18 = var_18_arg_0[(unsigned char) var_18_arg_1]; [L459] SORT_1 var_317_arg_0 = var_136; [L460] SORT_11 var_317_arg_1 = var_258; [L461] SORT_11 var_317_arg_2 = var_18; [L462] SORT_11 var_317 = var_317_arg_0 ? var_317_arg_1 : var_317_arg_2; [L463] SORT_11 var_414_arg_0 = var_317; [L464] SORT_11 var_414_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414_arg_0=0, var_414_arg_1=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] EXPR var_414_arg_0 & var_414_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L465] SORT_11 var_414 = var_414_arg_0 & var_414_arg_1; [L466] SORT_11* var_411_arg_0 = state_14; [L467] SORT_12 var_411_arg_1 = var_17; [L468] EXPR var_411_arg_0[(unsigned char) var_411_arg_1] [L468] SORT_11 var_411 = var_411_arg_0[(unsigned char) var_411_arg_1]; [L469] SORT_11 var_412_arg_0 = var_410; [L470] SORT_11 var_412 = ~var_412_arg_0; [L471] SORT_11 var_413_arg_0 = var_411; [L472] SORT_11 var_413_arg_1 = var_412; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_413_arg_0=0, var_413_arg_1=-256, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] EXPR var_413_arg_0 & var_413_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_414=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L473] SORT_11 var_413 = var_413_arg_0 & var_413_arg_1; [L474] SORT_11 var_415_arg_0 = var_414; [L475] SORT_11 var_415_arg_1 = var_413; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_415_arg_0=0, var_415_arg_1=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] EXPR var_415_arg_0 | var_415_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L476] SORT_11 var_415 = var_415_arg_0 | var_415_arg_1; [L477] SORT_11* var_416_arg_0 = state_14; [L478] SORT_12 var_416_arg_1 = var_17; [L479] SORT_11 var_416_arg_2 = var_415; [L480] SORT_13 var_416; [L481] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] EXPR var_416_arg_0[i] [L481] var_416[i] = var_416_arg_0[i] [L481] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L481] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416={13:0}, var_416_arg_0={10:0}, var_416_arg_1=0, var_416_arg_2=0, var_417=1, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L482] var_416[(unsigned char) var_416_arg_1] = var_416_arg_2 [L483] SORT_1 var_418_arg_0 = var_417; [L484] SORT_11* var_418_arg_1 = var_416; [L485] SORT_11* var_418_arg_2 = state_14; [L486] SORT_11* var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L487] SORT_11* next_419_arg_1 = var_418; [L488] SORT_1 var_157_arg_0 = var_25; [L489] SORT_1 var_157_arg_1 = var_54; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157_arg_0=0, var_157_arg_1=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] EXPR ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L490] SORT_5 var_157 = ((SORT_5)var_157_arg_0 << 1) | var_157_arg_1; [L491] EXPR var_157 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L491] var_157 = var_157 & mask_SORT_5 [L492] SORT_1 var_162_arg_0 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162_arg_0=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] EXPR var_162_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L493] var_162_arg_0 = var_162_arg_0 & mask_SORT_1 [L494] SORT_5 var_162 = var_162_arg_0; [L495] SORT_1 var_163_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_163_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] EXPR var_163_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_162=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L496] var_163_arg_0 = var_163_arg_0 & mask_SORT_1 [L497] SORT_5 var_163 = var_163_arg_0; [L498] SORT_5 var_164_arg_0 = var_162; [L499] SORT_5 var_164_arg_1 = var_163; [L500] SORT_5 var_164 = var_164_arg_0 + var_164_arg_1; [L501] SORT_5 var_165_arg_0 = var_164; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] EXPR var_165_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L502] var_165_arg_0 = var_165_arg_0 & mask_SORT_5 [L503] SORT_12 var_165 = var_165_arg_0; [L504] SORT_1 var_166_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_166_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] EXPR var_166_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_165=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L505] var_166_arg_0 = var_166_arg_0 & mask_SORT_1 [L506] SORT_12 var_166 = var_166_arg_0; [L507] SORT_12 var_167_arg_0 = var_165; [L508] SORT_12 var_167_arg_1 = var_166; [L509] SORT_12 var_167 = var_167_arg_0 + var_167_arg_1; [L510] SORT_12 var_168_arg_0 = var_167; [L511] SORT_1 var_168 = var_168_arg_0 >> 0; [L512] SORT_1 var_169_arg_0 = var_168; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_169_arg_0=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] EXPR var_169_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L513] var_169_arg_0 = var_169_arg_0 & mask_SORT_1 [L514] SORT_5 var_169 = var_169_arg_0; [L515] SORT_5 var_170_arg_0 = var_157; [L516] SORT_5 var_170_arg_1 = var_169; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_170_arg_0=0, var_170_arg_1=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] EXPR var_170_arg_0 >> var_170_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L517] SORT_5 var_170 = var_170_arg_0 >> var_170_arg_1; [L518] SORT_5 var_171_arg_0 = var_170; [L519] SORT_1 var_171 = var_171_arg_0 >> 0; [L520] SORT_1 var_152_arg_0 = var_110; [L521] SORT_1 var_152_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_152_arg_0=0, var_152_arg_1=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] EXPR ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L522] SORT_5 var_152 = ((SORT_5)var_152_arg_0 << 1) | var_152_arg_1; [L523] SORT_5 var_153_arg_0 = var_152; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153_arg_0=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] EXPR var_153_arg_0 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L524] var_153_arg_0 = var_153_arg_0 & mask_SORT_5 [L525] SORT_12 var_153 = var_153_arg_0; [L526] SORT_1 var_154_arg_0 = var_109; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_154_arg_0=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] EXPR var_154_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_153=0, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L527] var_154_arg_0 = var_154_arg_0 & mask_SORT_1 [L528] SORT_12 var_154 = var_154_arg_0; [L529] SORT_12 var_155_arg_0 = var_153; [L530] SORT_12 var_155_arg_1 = var_154; [L531] SORT_12 var_155 = var_155_arg_0 + var_155_arg_1; [L532] SORT_12 var_156_arg_0 = var_155; [L533] SORT_1 var_156 = var_156_arg_0 >> 0; [L534] SORT_1 var_158_arg_0 = var_156; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_158_arg_0=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] EXPR var_158_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_157=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L535] var_158_arg_0 = var_158_arg_0 & mask_SORT_1 [L536] SORT_5 var_158 = var_158_arg_0; [L537] SORT_5 var_159_arg_0 = var_157; [L538] SORT_5 var_159_arg_1 = var_158; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_159_arg_0=0, var_159_arg_1=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] EXPR var_159_arg_0 >> var_159_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L539] SORT_5 var_159 = var_159_arg_0 >> var_159_arg_1; [L540] SORT_5 var_160_arg_0 = var_159; [L541] SORT_1 var_160 = var_160_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] EXPR var_160 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_168=1, var_171=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L542] var_160 = var_160 & mask_SORT_1 [L543] SORT_1 var_172_arg_0 = var_160; [L544] SORT_1 var_172 = ~var_172_arg_0; [L545] SORT_1 var_173_arg_0 = var_171; [L546] SORT_1 var_173_arg_1 = var_172; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_173_arg_0=0, var_173_arg_1=-1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] EXPR var_173_arg_0 & var_173_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L547] SORT_1 var_173 = var_173_arg_0 & var_173_arg_1; [L548] EXPR var_173 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_156=1, var_160=0, var_168=1, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L548] var_173 = var_173 & mask_SORT_1 [L549] SORT_1 var_161_arg_0 = var_160; [L550] SORT_1 var_161_arg_1 = var_156; [L551] SORT_1 var_161_arg_2 = state_31; [L552] SORT_1 var_161 = var_161_arg_0 ? var_161_arg_1 : var_161_arg_2; [L553] SORT_1 var_174_arg_0 = var_173; [L554] SORT_1 var_174_arg_1 = var_168; [L555] SORT_1 var_174_arg_2 = var_161; [L556] SORT_1 var_174 = var_174_arg_0 ? var_174_arg_1 : var_174_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] EXPR var_174 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L557] var_174 = var_174 & mask_SORT_1 [L558] SORT_1 var_204_arg_0 = var_174; [L559] SORT_1 var_204_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_204_arg_0=0, var_204_arg_1=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] EXPR var_204_arg_0 | var_204_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L560] SORT_1 var_204 = var_204_arg_0 | var_204_arg_1; [L561] EXPR var_204 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L561] var_204 = var_204 & mask_SORT_1 [L562] SORT_1 var_198_arg_0 = var_25; [L563] SORT_1 var_198 = ~var_198_arg_0; [L564] SORT_1 var_199_arg_0 = state_31; [L565] SORT_1 var_199_arg_1 = var_198; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_199_arg_0=0, var_199_arg_1=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] EXPR var_199_arg_0 & var_199_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L566] SORT_1 var_199 = var_199_arg_0 & var_199_arg_1; [L567] EXPR var_199 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L567] var_199 = var_199 & mask_SORT_1 [L568] SORT_3 var_191_arg_0 = input_7; [L569] SORT_11 var_191 = var_191_arg_0 >> 8; [L570] SORT_11 var_192_arg_0 = state_26; [L571] SORT_11 var_192_arg_1 = var_191; [L572] SORT_11 var_192 = var_192_arg_0 + var_192_arg_1; [L573] SORT_1 var_193_arg_0 = var_174; [L574] SORT_11 var_193_arg_1 = var_192; [L575] SORT_11 var_193_arg_2 = state_26; [L576] SORT_11 var_193 = var_193_arg_0 ? var_193_arg_1 : var_193_arg_2; [L577] SORT_15 var_195_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_195_arg_0=8, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] EXPR var_195_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_193=0, var_198=-1, var_199=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L578] var_195_arg_0 = var_195_arg_0 & mask_SORT_15 [L579] SORT_11 var_195 = var_195_arg_0; [L580] SORT_11 var_196_arg_0 = var_193; [L581] SORT_11 var_196_arg_1 = var_195; [L582] SORT_11 var_196 = var_196_arg_0 - var_196_arg_1; [L583] SORT_1 var_197_arg_0 = var_32; [L584] SORT_11 var_197_arg_1 = var_196; [L585] SORT_11 var_197_arg_2 = var_193; [L586] SORT_11 var_197 = var_197_arg_0 ? var_197_arg_1 : var_197_arg_2; [L587] SORT_1 var_200_arg_0 = var_199; [L588] SORT_11 var_200_arg_1 = state_26; [L589] SORT_11 var_200_arg_2 = var_197; [L590] SORT_11 var_200 = var_200_arg_0 ? var_200_arg_1 : var_200_arg_2; [L591] SORT_1 var_201_arg_0 = input_9; [L592] SORT_11 var_201_arg_1 = var_183; [L593] SORT_11 var_201_arg_2 = var_200; [L594] SORT_11 var_201 = var_201_arg_0 ? var_201_arg_1 : var_201_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] EXPR var_201 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_204=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L595] var_201 = var_201 & mask_SORT_11 [L596] SORT_1 var_420_arg_0 = var_204; [L597] SORT_11 var_420_arg_1 = var_201; [L598] SORT_11 var_420_arg_2 = state_26; [L599] SORT_11 var_420 = var_420_arg_0 ? var_420_arg_1 : var_420_arg_2; [L600] SORT_1 var_421_arg_0 = input_9; [L601] SORT_11 var_421_arg_1 = var_183; [L602] SORT_11 var_421_arg_2 = var_420; [L603] SORT_11 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_421=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] EXPR var_421 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L604] var_421 = var_421 & mask_SORT_11 [L605] SORT_11 next_422_arg_1 = var_421; [L606] SORT_1 var_180_arg_0 = var_54; [L607] SORT_1 var_180 = ~var_180_arg_0; [L608] SORT_1 var_181_arg_0 = var_59; [L609] SORT_1 var_181_arg_1 = var_180; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_181_arg_0=0, var_181_arg_1=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] EXPR var_181_arg_0 & var_181_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L610] SORT_1 var_181 = var_181_arg_0 & var_181_arg_1; [L611] EXPR var_181 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_7=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L611] var_181 = var_181 & mask_SORT_1 [L612] SORT_3 var_150_arg_0 = input_7; [L613] SORT_11 var_150 = var_150_arg_0 >> 0; [L614] SORT_11 var_151_arg_0 = state_55; [L615] SORT_11 var_151_arg_1 = var_150; [L616] SORT_11 var_151 = var_151_arg_0 + var_151_arg_1; [L617] SORT_1 var_175_arg_0 = var_174; [L618] SORT_11 var_175_arg_1 = state_55; [L619] SORT_11 var_175_arg_2 = var_151; [L620] SORT_11 var_175 = var_175_arg_0 ? var_175_arg_1 : var_175_arg_2; [L621] SORT_15 var_177_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_177_arg_0=8, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] EXPR var_177_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_175=0, var_180=-1, var_181=0, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L622] var_177_arg_0 = var_177_arg_0 & mask_SORT_15 [L623] SORT_11 var_177 = var_177_arg_0; [L624] SORT_11 var_178_arg_0 = var_175; [L625] SORT_11 var_178_arg_1 = var_177; [L626] SORT_11 var_178 = var_178_arg_0 - var_178_arg_1; [L627] SORT_1 var_179_arg_0 = var_60; [L628] SORT_11 var_179_arg_1 = var_178; [L629] SORT_11 var_179_arg_2 = var_175; [L630] SORT_11 var_179 = var_179_arg_0 ? var_179_arg_1 : var_179_arg_2; [L631] SORT_1 var_182_arg_0 = var_181; [L632] SORT_11 var_182_arg_1 = state_55; [L633] SORT_11 var_182_arg_2 = var_179; [L634] SORT_11 var_182 = var_182_arg_0 ? var_182_arg_1 : var_182_arg_2; [L635] SORT_1 var_184_arg_0 = input_9; [L636] SORT_11 var_184_arg_1 = var_183; [L637] SORT_11 var_184_arg_2 = var_182; [L638] SORT_11 var_184 = var_184_arg_0 ? var_184_arg_1 : var_184_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] EXPR var_184 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L639] var_184 = var_184 & mask_SORT_11 [L640] SORT_15 var_212_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_212_arg_0=8, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] EXPR var_212_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_180=-1, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L641] var_212_arg_0 = var_212_arg_0 & mask_SORT_15 [L642] SORT_11 var_212 = var_212_arg_0; [L643] SORT_11 var_213_arg_0 = var_184; [L644] SORT_11 var_213_arg_1 = var_212; [L645] SORT_1 var_213 = var_213_arg_0 < var_213_arg_1; [L646] SORT_1 var_214_arg_0 = var_180; [L647] SORT_1 var_214_arg_1 = var_213; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_214_arg_0=-1, var_214_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] EXPR var_214_arg_0 | var_214_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L648] SORT_1 var_214 = var_214_arg_0 | var_214_arg_1; [L649] SORT_1 var_215_arg_0 = var_59; [L650] SORT_1 var_215_arg_1 = var_214; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_215_arg_0=0, var_215_arg_1=255, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] EXPR var_215_arg_0 & var_215_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L651] SORT_1 var_215 = var_215_arg_0 & var_215_arg_1; [L652] SORT_1 var_216_arg_0 = var_60; [L653] SORT_1 var_216_arg_1 = var_215; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216_arg_0=0, var_216_arg_1=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] EXPR var_216_arg_0 & var_216_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L654] SORT_1 var_216 = var_216_arg_0 & var_216_arg_1; [L655] EXPR var_216 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L655] var_216 = var_216 & mask_SORT_1 [L656] SORT_15 var_207_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_207_arg_0=8, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] EXPR var_207_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_198=-1, var_201=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L657] var_207_arg_0 = var_207_arg_0 & mask_SORT_15 [L658] SORT_11 var_207 = var_207_arg_0; [L659] SORT_11 var_208_arg_0 = var_201; [L660] SORT_11 var_208_arg_1 = var_207; [L661] SORT_1 var_208 = var_208_arg_0 < var_208_arg_1; [L662] SORT_1 var_209_arg_0 = var_198; [L663] SORT_1 var_209_arg_1 = var_208; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_209_arg_0=-1, var_209_arg_1=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] EXPR var_209_arg_0 | var_209_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L664] SORT_1 var_209 = var_209_arg_0 | var_209_arg_1; [L665] SORT_1 var_210_arg_0 = state_31; [L666] SORT_1 var_210_arg_1 = var_209; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_210_arg_0=0, var_210_arg_1=255, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] EXPR var_210_arg_0 & var_210_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_32=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L667] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L668] SORT_1 var_211_arg_0 = var_32; [L669] SORT_1 var_211_arg_1 = var_210; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_211_arg_0=0, var_211_arg_1=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] EXPR var_211_arg_0 & var_211_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L670] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L671] EXPR var_211 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_216=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L671] var_211 = var_211 & mask_SORT_1 [L672] SORT_1 var_217_arg_0 = var_216; [L673] SORT_1 var_217_arg_1 = var_211; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_217_arg_0=0, var_217_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] EXPR ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L674] SORT_5 var_217 = ((SORT_5)var_217_arg_0 << 1) | var_217_arg_1; [L675] EXPR var_217 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L675] var_217 = var_217 & mask_SORT_5 [L676] SORT_5 var_218_arg_0 = var_217; [L677] SORT_1 var_218 = var_218_arg_0 != 0; [L678] SORT_1 var_423_arg_0 = var_218; [L679] SORT_1 var_423_arg_1 = var_174; [L680] SORT_1 var_423_arg_2 = state_31; [L681] SORT_1 var_423 = var_423_arg_0 ? var_423_arg_1 : var_423_arg_2; [L682] SORT_1 var_424_arg_0 = input_9; [L683] SORT_1 var_424_arg_1 = var_110; [L684] SORT_1 var_424_arg_2 = var_423; [L685] SORT_1 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_424=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] EXPR var_424 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L686] var_424 = var_424 & mask_SORT_1 [L687] SORT_1 next_425_arg_1 = var_424; [L688] SORT_1 var_269_arg_0 = var_92; [L689] SORT_1 var_269_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_269_arg_0=0, var_269_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] EXPR var_269_arg_0 | var_269_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L690] SORT_1 var_269 = var_269_arg_0 | var_269_arg_1; [L691] SORT_1 var_270_arg_0 = var_269; [L692] SORT_1 var_270_arg_1 = input_9; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270_arg_0=0, var_270_arg_1=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] EXPR var_270_arg_0 | var_270_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L693] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L694] EXPR var_270 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L694] var_270 = var_270 & mask_SORT_1 [L695] SORT_1 var_281_arg_0 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_281_arg_0=0, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] EXPR var_281_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L696] var_281_arg_0 = var_281_arg_0 & mask_SORT_1 [L697] SORT_15 var_281 = var_281_arg_0; [L698] SORT_15 var_282_arg_0 = state_45; [L699] SORT_15 var_282_arg_1 = var_281; [L700] SORT_15 var_282 = var_282_arg_0 + var_282_arg_1; [L701] SORT_1 var_426_arg_0 = var_270; [L702] SORT_15 var_426_arg_1 = var_282; [L703] SORT_15 var_426_arg_2 = state_45; [L704] SORT_15 var_426 = var_426_arg_0 ? var_426_arg_1 : var_426_arg_2; [L705] SORT_1 var_427_arg_0 = input_9; [L706] SORT_15 var_427_arg_1 = var_99; [L707] SORT_15 var_427_arg_2 = var_426; [L708] SORT_15 var_427 = var_427_arg_0 ? var_427_arg_1 : var_427_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_427=0, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] EXPR var_427 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L709] var_427 = var_427 & mask_SORT_15 [L710] SORT_15 next_428_arg_1 = var_427; [L711] SORT_1 var_275_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_275_arg_0=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] EXPR var_275_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L712] var_275_arg_0 = var_275_arg_0 & mask_SORT_1 [L713] SORT_15 var_275 = var_275_arg_0; [L714] SORT_15 var_276_arg_0 = state_48; [L715] SORT_15 var_276_arg_1 = var_275; [L716] SORT_15 var_276 = var_276_arg_0 + var_276_arg_1; [L717] SORT_1 var_429_arg_0 = var_270; [L718] SORT_15 var_429_arg_1 = var_276; [L719] SORT_15 var_429_arg_2 = state_48; [L720] SORT_15 var_429 = var_429_arg_0 ? var_429_arg_1 : var_429_arg_2; [L721] SORT_1 var_430_arg_0 = input_9; [L722] SORT_15 var_430_arg_1 = var_99; [L723] SORT_15 var_430_arg_2 = var_429; [L724] SORT_15 var_430 = var_430_arg_0 ? var_430_arg_1 : var_430_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_430=0, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] EXPR var_430 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_4=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L725] var_430 = var_430 & mask_SORT_15 [L726] SORT_15 next_431_arg_1 = var_430; [L727] SORT_11 var_438_arg_0 = var_410; [L728] SORT_1 var_438 = var_438_arg_0 != 0; [L729] SORT_3 var_256_arg_0 = input_4; [L730] SORT_11 var_256 = var_256_arg_0 >> 0; [L731] SORT_11* var_47_arg_0 = state_44; [L732] SORT_12 var_47_arg_1 = var_46; [L733] EXPR var_47_arg_0[(unsigned char) var_47_arg_1] [L733] SORT_11 var_47 = var_47_arg_0[(unsigned char) var_47_arg_1]; [L734] SORT_1 var_288_arg_0 = var_92; [L735] SORT_11 var_288_arg_1 = var_256; [L736] SORT_11 var_288_arg_2 = var_47; [L737] SORT_11 var_288 = var_288_arg_0 ? var_288_arg_1 : var_288_arg_2; [L738] SORT_11 var_435_arg_0 = var_288; [L739] SORT_11 var_435_arg_1 = var_410; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435_arg_0=0, var_435_arg_1=255, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] EXPR var_435_arg_0 & var_435_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L740] SORT_11 var_435 = var_435_arg_0 & var_435_arg_1; [L741] SORT_11* var_432_arg_0 = state_44; [L742] SORT_12 var_432_arg_1 = var_46; [L743] EXPR var_432_arg_0[(unsigned char) var_432_arg_1] [L743] SORT_11 var_432 = var_432_arg_0[(unsigned char) var_432_arg_1]; [L744] SORT_11 var_433_arg_0 = var_410; [L745] SORT_11 var_433 = ~var_433_arg_0; [L746] SORT_11 var_434_arg_0 = var_432; [L747] SORT_11 var_434_arg_1 = var_433; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_434_arg_0=0, var_434_arg_1=-256, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] EXPR var_434_arg_0 & var_434_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_435=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L748] SORT_11 var_434 = var_434_arg_0 & var_434_arg_1; [L749] SORT_11 var_436_arg_0 = var_435; [L750] SORT_11 var_436_arg_1 = var_434; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_436_arg_0=0, var_436_arg_1=0, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] EXPR var_436_arg_0 | var_436_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_438=1, var_46=0, var_59=0, var_92=0, var_93=-1, var_99=0] [L751] SORT_11 var_436 = var_436_arg_0 | var_436_arg_1; [L752] SORT_11* var_437_arg_0 = state_44; [L753] SORT_12 var_437_arg_1 = var_46; [L754] SORT_11 var_437_arg_2 = var_436; [L755] SORT_13 var_437; [L756] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] EXPR var_437_arg_0[i] [L756] var_437[i] = var_437_arg_0[i] [L756] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L756] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_174=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437={9:0}, var_437_arg_0={11:0}, var_437_arg_1=0, var_437_arg_2=0, var_438=1, var_59=0, var_92=0, var_93=-1, var_99=0] [L757] var_437[(unsigned char) var_437_arg_1] = var_437_arg_2 [L758] SORT_1 var_439_arg_0 = var_438; [L759] SORT_11* var_439_arg_1 = var_437; [L760] SORT_11* var_439_arg_2 = state_44; [L761] SORT_11* var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L762] SORT_11* next_440_arg_1 = var_439; [L763] SORT_1 var_187_arg_0 = var_174; [L764] SORT_1 var_187 = ~var_187_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_187=-1, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] EXPR var_187 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_59=0, var_92=0, var_93=-1, var_99=0] [L765] var_187 = var_187 & mask_SORT_1 [L766] SORT_1 var_188_arg_0 = var_187; [L767] SORT_1 var_188_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_188_arg_0=0, var_188_arg_1=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] EXPR var_188_arg_0 | var_188_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L768] SORT_1 var_188 = var_188_arg_0 | var_188_arg_1; [L769] EXPR var_188 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_184=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L769] var_188 = var_188 & mask_SORT_1 [L770] SORT_1 var_441_arg_0 = var_188; [L771] SORT_11 var_441_arg_1 = var_184; [L772] SORT_11 var_441_arg_2 = state_55; [L773] SORT_11 var_441 = var_441_arg_0 ? var_441_arg_1 : var_441_arg_2; [L774] SORT_1 var_442_arg_0 = input_9; [L775] SORT_11 var_442_arg_1 = var_183; [L776] SORT_11 var_442_arg_2 = var_441; [L777] SORT_11 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_442=0, var_92=0, var_93=-1, var_99=0] [L778] EXPR var_442 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_92=0, var_93=-1, var_99=0] [L778] var_442 = var_442 & mask_SORT_11 [L779] SORT_11 next_443_arg_1 = var_442; [L780] SORT_1 var_365_arg_0 = input_10; [L781] SORT_1 var_365_arg_1 = var_92; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365_arg_0=0, var_365_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] EXPR var_365_arg_0 & var_365_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L782] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L783] SORT_1 var_366_arg_0 = state_85; [L784] SORT_1 var_366_arg_1 = var_365; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_366_arg_0=0, var_366_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] EXPR var_366_arg_0 | var_366_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L785] SORT_1 var_366 = var_366_arg_0 | var_366_arg_1; [L786] SORT_1 var_444_arg_0 = state_85; [L787] SORT_1 var_444_arg_1 = var_109; [L788] SORT_1 var_444_arg_2 = var_366; [L789] SORT_1 var_444 = var_444_arg_0 ? var_444_arg_1 : var_444_arg_2; [L790] SORT_1 var_445_arg_0 = input_9; [L791] SORT_1 var_445_arg_1 = var_110; [L792] SORT_1 var_445_arg_2 = var_444; [L793] SORT_1 var_445 = var_445_arg_0 ? var_445_arg_1 : var_445_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_445=0, var_93=-1, var_99=0] [L794] EXPR var_445 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L794] var_445 = var_445 & mask_SORT_1 [L795] SORT_1 next_446_arg_1 = var_445; [L796] SORT_1 var_376_arg_0 = var_103; [L797] SORT_1 var_376_arg_1 = state_86; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_376_arg_0=0, var_376_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] EXPR var_376_arg_0 | var_376_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_85=0, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_270=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L798] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L799] SORT_1 var_447_arg_0 = input_9; [L800] SORT_1 var_447_arg_1 = var_110; [L801] SORT_1 var_447_arg_2 = var_376; [L802] SORT_1 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L803] SORT_1 next_448_arg_1 = var_447; [L804] SORT_1 var_388_arg_0 = var_270; [L805] SORT_1 var_388_arg_1 = state_85; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_388_arg_0=0, var_388_arg_1=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] EXPR var_388_arg_0 | var_388_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L806] SORT_1 var_388 = var_388_arg_0 | var_388_arg_1; [L807] EXPR var_388 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, state_89=0, var_100=0, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L807] var_388 = var_388 & mask_SORT_1 [L808] SORT_1 var_449_arg_0 = var_388; [L809] SORT_15 var_449_arg_1 = var_100; [L810] SORT_15 var_449_arg_2 = state_89; [L811] SORT_15 var_449 = var_449_arg_0 ? var_449_arg_1 : var_449_arg_2; [L812] SORT_1 var_450_arg_0 = input_9; [L813] SORT_15 var_450_arg_1 = var_99; [L814] SORT_15 var_450_arg_2 = var_449; [L815] SORT_15 var_450 = var_450_arg_0 ? var_450_arg_1 : var_450_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_450=0, var_93=-1, var_99=0] [L816] EXPR var_450 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_365=0, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_93=-1, var_99=0] [L816] var_450 = var_450 & mask_SORT_15 [L817] SORT_15 next_451_arg_1 = var_450; [L818] SORT_1 var_373_arg_0 = var_365; [L819] SORT_1 var_373_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_373_arg_0=0, var_373_arg_1=-1, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] EXPR var_373_arg_0 & var_373_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L820] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L821] EXPR var_373 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_105=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_256=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L821] var_373 = var_373 & mask_SORT_1 [L822] SORT_1 var_452_arg_0 = var_373; [L823] SORT_11 var_452_arg_1 = var_256; [L824] SORT_11 var_452_arg_2 = state_105; [L825] SORT_11 var_452 = var_452_arg_0 ? var_452_arg_1 : var_452_arg_2; [L826] SORT_1 var_453_arg_0 = input_9; [L827] SORT_11 var_453_arg_1 = var_183; [L828] SORT_11 var_453_arg_2 = var_452; [L829] SORT_11 var_453 = var_453_arg_0 ? var_453_arg_1 : var_453_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_453=0, var_99=0] [L830] EXPR var_453 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_406_arg_1=0, next_409_arg_1=0, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, state_14={10:0}, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L830] var_453 = var_453 & mask_SORT_11 [L831] SORT_11 next_454_arg_1 = var_453; [L832] SORT_1 next_455_arg_1 = var_110; [L834] state_16 = next_406_arg_1 [L835] state_19 = next_409_arg_1 [L836] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] EXPR next_419_arg_1[i] [L836] state_14[i] = next_419_arg_1[i] [L836] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L836] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_422_arg_1=0, next_425_arg_1=0, next_428_arg_1=0, next_431_arg_1=0, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_44={11:0}, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L837] state_26 = next_422_arg_1 [L838] state_31 = next_425_arg_1 [L839] state_45 = next_428_arg_1 [L840] state_48 = next_431_arg_1 [L841] unsigned char i = 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=0, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=2, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=3, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=4, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=5, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=6, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND TRUE i < (1 << 3) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=7, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] EXPR next_440_arg_1[i] [L841] state_44[i] = next_440_arg_1[i] [L841] ++i VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, i=8, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L841] COND FALSE !(i < (1 << 3)) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, next_419_arg_1={13:0}, next_440_arg_1={9:0}, next_443_arg_1=0, next_446_arg_1=0, next_448_arg_1=0, next_451_arg_1=0, next_454_arg_1=0, next_455_arg_1=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_416_arg_0={10:0}, var_437_arg_0={11:0}, var_99=0] [L842] state_55 = next_443_arg_1 [L843] state_85 = next_446_arg_1 [L844] state_86 = next_448_arg_1 [L845] state_89 = next_451_arg_1 [L846] state_105 = next_454_arg_1 [L847] state_111 = next_455_arg_1 [L102] input_2 = __VERIFIER_nondet_uchar() [L103] input_4 = __VERIFIER_nondet_ushort() [L104] input_6 = __VERIFIER_nondet_uchar() [L105] input_7 = __VERIFIER_nondet_ushort() [L106] input_8 = __VERIFIER_nondet_uchar() [L107] input_9 = __VERIFIER_nondet_uchar() [L108] EXPR input_9 & mask_SORT_1 VAL [mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_99=0] [L108] input_9 = input_9 & mask_SORT_1 [L109] input_10 = __VERIFIER_nondet_uchar() [L111] SORT_15 var_52_arg_0 = state_48; [L112] SORT_15 var_52_arg_1 = state_45; [L113] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L114] SORT_1 var_117_arg_0 = var_52; [L115] SORT_1 var_117 = ~var_117_arg_0; [L116] SORT_5 var_51_arg_0 = input_8; [L117] SORT_1 var_51 = var_51_arg_0 >> 0; [L118] SORT_1 var_118_arg_0 = var_51; [L119] SORT_1 var_118 = ~var_118_arg_0; [L120] SORT_1 var_119_arg_0 = var_117; [L121] SORT_1 var_119_arg_1 = var_118; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_119_arg_0=-2, var_119_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] EXPR var_119_arg_0 | var_119_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L122] SORT_1 var_119 = var_119_arg_0 | var_119_arg_1; [L123] SORT_1 var_120_arg_0 = var_109; [L124] SORT_1 var_120 = ~var_120_arg_0; [L125] SORT_1 var_121_arg_0 = var_119; [L126] SORT_1 var_121_arg_1 = var_120; VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_121_arg_0=254, var_121_arg_1=-2, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] EXPR var_121_arg_0 | var_121_arg_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L127] SORT_1 var_121 = var_121_arg_0 | var_121_arg_1; [L128] EXPR var_121 & mask_SORT_1 VAL [input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L128] var_121 = var_121 & mask_SORT_1 [L129] SORT_1 constr_122_arg_0 = var_121; VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L130] CALL assume_abort_if_not(constr_122_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L130] RET assume_abort_if_not(constr_122_arg_0) VAL [constr_122_arg_0=1, input_8=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L131] SORT_15 var_23_arg_0 = state_19; [L132] SORT_15 var_23_arg_1 = state_16; [L133] SORT_1 var_23 = var_23_arg_0 == var_23_arg_1; [L134] SORT_1 var_123_arg_0 = var_23; [L135] SORT_1 var_123 = ~var_123_arg_0; [L136] SORT_5 var_22_arg_0 = input_8; [L137] SORT_1 var_22 = var_22_arg_0 >> 1; [L138] SORT_1 var_124_arg_0 = var_22; [L139] SORT_1 var_124 = ~var_124_arg_0; [L140] SORT_1 var_125_arg_0 = var_123; [L141] SORT_1 var_125_arg_1 = var_124; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_125_arg_0=-2, var_125_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] EXPR var_125_arg_0 | var_125_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L142] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L143] SORT_1 var_126_arg_0 = var_109; [L144] SORT_1 var_126 = ~var_126_arg_0; [L145] SORT_1 var_127_arg_0 = var_125; [L146] SORT_1 var_127_arg_1 = var_126; VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_127_arg_0=256, var_127_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] EXPR var_127_arg_0 | var_127_arg_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L147] SORT_1 var_127 = var_127_arg_0 | var_127_arg_1; [L148] EXPR var_127 & mask_SORT_1 VAL [constr_122_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L148] var_127 = var_127 & mask_SORT_1 [L149] SORT_1 constr_128_arg_0 = var_127; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L150] CALL assume_abort_if_not(constr_128_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L150] RET assume_abort_if_not(constr_128_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L151] SORT_15 var_49_arg_0 = state_48; [L152] SORT_12 var_49 = var_49_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L153] EXPR var_49 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_51=1, var_52=1, var_99=0] [L153] var_49 = var_49 & mask_SORT_12 [L154] SORT_15 var_46_arg_0 = state_45; [L155] SORT_12 var_46 = var_46_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L156] EXPR var_46 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_49=0, var_51=1, var_52=1, var_99=0] [L156] var_46 = var_46 & mask_SORT_12 [L157] SORT_12 var_73_arg_0 = var_49; [L158] SORT_12 var_73_arg_1 = var_46; [L159] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L160] SORT_15 var_74_arg_0 = state_48; [L161] SORT_1 var_74 = var_74_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L162] EXPR var_74 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_99=0] [L162] var_74 = var_74 & mask_SORT_1 [L163] SORT_15 var_75_arg_0 = state_45; [L164] SORT_1 var_75 = var_75_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_75=0, var_99=0] [L165] EXPR var_75 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_73=1, var_74=0, var_99=0] [L165] var_75 = var_75 & mask_SORT_1 [L166] SORT_1 var_76_arg_0 = var_74; [L167] SORT_1 var_76_arg_1 = var_75; [L168] SORT_1 var_76 = var_76_arg_0 != var_76_arg_1; [L169] SORT_1 var_77_arg_0 = var_73; [L170] SORT_1 var_77_arg_1 = var_76; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_77_arg_0=1, var_77_arg_1=0, var_99=0] [L171] EXPR var_77_arg_0 & var_77_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L171] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L172] EXPR var_77 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L172] var_77 = var_77 & mask_SORT_1 [L173] SORT_1 var_129_arg_0 = var_77; [L174] SORT_1 var_129 = ~var_129_arg_0; [L175] SORT_5 var_92_arg_0 = input_6; [L176] SORT_1 var_92 = var_92_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L177] EXPR var_92 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_129=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_99=0] [L177] var_92 = var_92 & mask_SORT_1 [L178] SORT_1 var_130_arg_0 = var_92; [L179] SORT_1 var_130 = ~var_130_arg_0; [L180] SORT_1 var_131_arg_0 = var_129; [L181] SORT_1 var_131_arg_1 = var_130; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_131_arg_0=-1, var_131_arg_1=-1, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] EXPR var_131_arg_0 | var_131_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L182] SORT_1 var_131 = var_131_arg_0 | var_131_arg_1; [L183] SORT_1 var_132_arg_0 = var_109; [L184] SORT_1 var_132 = ~var_132_arg_0; [L185] SORT_1 var_133_arg_0 = var_131; [L186] SORT_1 var_133_arg_1 = var_132; VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_133_arg_0=255, var_133_arg_1=-2, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] EXPR var_133_arg_0 | var_133_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L187] SORT_1 var_133 = var_133_arg_0 | var_133_arg_1; [L188] EXPR var_133 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L188] var_133 = var_133 & mask_SORT_1 [L189] SORT_1 constr_134_arg_0 = var_133; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L190] CALL assume_abort_if_not(constr_134_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L190] RET assume_abort_if_not(constr_134_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L191] SORT_15 var_20_arg_0 = state_19; [L192] SORT_12 var_20 = var_20_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] EXPR var_20 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L193] var_20 = var_20 & mask_SORT_12 [L194] SORT_15 var_17_arg_0 = state_16; [L195] SORT_12 var_17 = var_17_arg_0 >> 0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] EXPR var_17 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L196] var_17 = var_17 & mask_SORT_12 [L197] SORT_12 var_78_arg_0 = var_20; [L198] SORT_12 var_78_arg_1 = var_17; [L199] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L200] SORT_15 var_79_arg_0 = state_19; [L201] SORT_1 var_79 = var_79_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L202] EXPR var_79 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_92=0, var_99=0] [L202] var_79 = var_79 & mask_SORT_1 [L203] SORT_15 var_80_arg_0 = state_16; [L204] SORT_1 var_80 = var_80_arg_0 >> 3; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_80=0, var_92=0, var_99=0] [L205] EXPR var_80 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_78=1, var_79=0, var_92=0, var_99=0] [L205] var_80 = var_80 & mask_SORT_1 [L206] SORT_1 var_81_arg_0 = var_79; [L207] SORT_1 var_81_arg_1 = var_80; [L208] SORT_1 var_81 = var_81_arg_0 != var_81_arg_1; [L209] SORT_1 var_82_arg_0 = var_78; [L210] SORT_1 var_82_arg_1 = var_81; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_82_arg_0=1, var_82_arg_1=0, var_92=0, var_99=0] [L211] EXPR var_82_arg_0 & var_82_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_6=0, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L211] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L212] SORT_1 var_135_arg_0 = var_82; [L213] SORT_1 var_135 = ~var_135_arg_0; [L214] SORT_5 var_136_arg_0 = input_6; [L215] SORT_1 var_136 = var_136_arg_0 >> 1; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] EXPR var_136 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_135=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L216] var_136 = var_136 & mask_SORT_1 [L217] SORT_1 var_137_arg_0 = var_136; [L218] SORT_1 var_137 = ~var_137_arg_0; [L219] SORT_1 var_138_arg_0 = var_135; [L220] SORT_1 var_138_arg_1 = var_137; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_138_arg_0=-1, var_138_arg_1=-1, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] EXPR var_138_arg_0 | var_138_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L221] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L222] SORT_1 var_139_arg_0 = var_109; [L223] SORT_1 var_139 = ~var_139_arg_0; [L224] SORT_1 var_140_arg_0 = var_138; [L225] SORT_1 var_140_arg_1 = var_139; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_140_arg_0=255, var_140_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L226] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L227] EXPR var_140 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L227] var_140 = var_140 & mask_SORT_1 [L228] SORT_1 constr_141_arg_0 = var_140; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L229] CALL assume_abort_if_not(constr_141_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L229] RET assume_abort_if_not(constr_141_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L230] SORT_1 var_142_arg_0 = state_111; [L231] SORT_1 var_142_arg_1 = input_9; [L232] SORT_1 var_142 = var_142_arg_0 == var_142_arg_1; [L233] SORT_1 var_143_arg_0 = var_109; [L234] SORT_1 var_143 = ~var_143_arg_0; [L235] SORT_1 var_144_arg_0 = var_142; [L236] SORT_1 var_144_arg_1 = var_143; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_144_arg_0=0, var_144_arg_1=-2, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] EXPR var_144_arg_0 | var_144_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L237] SORT_1 var_144 = var_144_arg_0 | var_144_arg_1; [L238] EXPR var_144 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L238] var_144 = var_144 & mask_SORT_1 [L239] SORT_1 constr_145_arg_0 = var_144; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L240] CALL assume_abort_if_not(constr_145_arg_0) VAL [\old(cond)=1] [L22] COND FALSE !(!cond) VAL [\old(cond)=1] [L240] RET assume_abort_if_not(constr_145_arg_0) VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_111=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L242] SORT_1 var_113_arg_0 = state_111; [L243] SORT_1 var_113_arg_1 = var_110; [L244] SORT_1 var_113_arg_2 = var_109; [L245] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L246] SORT_1 var_87_arg_0 = state_86; [L247] SORT_1 var_87 = ~var_87_arg_0; [L248] SORT_1 var_88_arg_0 = state_85; [L249] SORT_1 var_88_arg_1 = var_87; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_88_arg_0=0, var_88_arg_1=-1, var_92=0, var_99=0] [L250] EXPR var_88_arg_0 & var_88_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L250] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L251] SORT_15 var_90_arg_0 = state_89; [L252] SORT_1 var_90 = var_90_arg_0 != 0; [L253] SORT_1 var_91_arg_0 = var_88; [L254] SORT_1 var_91_arg_1 = var_90; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_99=0] [L255] EXPR var_91_arg_0 & var_91_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_92=0, var_99=0] [L255] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L256] SORT_1 var_93_arg_0 = state_85; [L257] SORT_1 var_93 = ~var_93_arg_0; [L258] SORT_1 var_94_arg_0 = var_92; [L259] SORT_1 var_94_arg_1 = var_93; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_94_arg_0=0, var_94_arg_1=-1, var_99=0] [L260] EXPR var_94_arg_0 & var_94_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L260] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L261] SORT_1 var_95_arg_0 = var_94; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_95_arg_0=0, var_99=0] [L262] EXPR var_95_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_51=1, var_52=1, var_91=0, var_92=0, var_93=-1, var_99=0] [L262] var_95_arg_0 = var_95_arg_0 & mask_SORT_1 [L263] SORT_15 var_95 = var_95_arg_0; [L264] SORT_15 var_96_arg_0 = state_89; [L265] SORT_15 var_96_arg_1 = var_95; [L266] SORT_15 var_96 = var_96_arg_0 + var_96_arg_1; [L267] SORT_1 var_53_arg_0 = var_52; [L268] SORT_1 var_53 = ~var_53_arg_0; [L269] SORT_1 var_54_arg_0 = var_51; [L270] SORT_1 var_54_arg_1 = var_53; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54_arg_0=1, var_54_arg_1=-2, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] EXPR var_54_arg_0 & var_54_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L271] SORT_1 var_54 = var_54_arg_0 & var_54_arg_1; [L272] EXPR var_54 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L272] var_54 = var_54 & mask_SORT_1 [L273] SORT_15 var_56_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_56_arg_0=8, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] EXPR var_56_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L274] var_56_arg_0 = var_56_arg_0 & mask_SORT_15 [L275] SORT_11 var_56 = var_56_arg_0; [L276] SORT_11 var_57_arg_0 = state_55; [L277] SORT_11 var_57_arg_1 = var_56; [L278] SORT_1 var_57 = var_57_arg_0 >= var_57_arg_1; [L279] SORT_1 var_58_arg_0 = var_54; [L280] SORT_1 var_58_arg_1 = var_57; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58_arg_0=0, var_58_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] EXPR var_58_arg_0 & var_58_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L281] SORT_1 var_58 = var_58_arg_0 & var_58_arg_1; [L282] SORT_1 var_59_arg_0 = state_31; [L283] SORT_1 var_59 = ~var_59_arg_0; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_59=-1, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] EXPR var_59 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_58=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L284] var_59 = var_59 & mask_SORT_1 [L285] SORT_1 var_60_arg_0 = var_58; [L286] SORT_1 var_60_arg_1 = var_59; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60_arg_0=0, var_60_arg_1=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] EXPR var_60_arg_0 & var_60_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L287] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L288] EXPR var_60 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L288] var_60 = var_60 & mask_SORT_1 [L289] SORT_1 var_97_arg_0 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_97_arg_0=0, var_99=0] [L290] EXPR var_97_arg_0 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_96=0, var_99=0] [L290] var_97_arg_0 = var_97_arg_0 & mask_SORT_1 [L291] SORT_15 var_97 = var_97_arg_0; [L292] SORT_15 var_98_arg_0 = var_96; [L293] SORT_15 var_98_arg_1 = var_97; [L294] SORT_15 var_98 = var_98_arg_0 - var_98_arg_1; [L295] SORT_1 var_100_arg_0 = input_9; [L296] SORT_15 var_100_arg_1 = var_99; [L297] SORT_15 var_100_arg_2 = var_98; [L298] SORT_15 var_100 = var_100_arg_0 ? var_100_arg_1 : var_100_arg_2; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] EXPR var_100 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_91=0, var_92=0, var_93=-1, var_99=0] [L299] var_100 = var_100 & mask_SORT_15 [L300] SORT_15 var_101_arg_0 = var_100; [L301] SORT_1 var_101 = var_101_arg_0 != 0; [L302] SORT_1 var_102_arg_0 = var_101; [L303] SORT_1 var_102 = ~var_102_arg_0; [L304] SORT_1 var_103_arg_0 = var_91; [L305] SORT_1 var_103_arg_1 = var_102; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103_arg_0=0, var_103_arg_1=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] EXPR var_103_arg_0 & var_103_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_20=0, var_22=0, var_23=1, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L306] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L307] SORT_1 var_104_arg_0 = var_103; [L308] SORT_1 var_104 = ~var_104_arg_0; [L309] SORT_11* var_21_arg_0 = state_14; [L310] SORT_12 var_21_arg_1 = var_20; [L311] EXPR var_21_arg_0[(unsigned char) var_21_arg_1] [L311] SORT_11 var_21 = var_21_arg_0[(unsigned char) var_21_arg_1]; [L312] SORT_1 var_24_arg_0 = var_23; [L313] SORT_1 var_24 = ~var_24_arg_0; [L314] SORT_1 var_25_arg_0 = var_22; [L315] SORT_1 var_25_arg_1 = var_24; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25_arg_0=0, var_25_arg_1=-2, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] EXPR var_25_arg_0 & var_25_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L316] SORT_1 var_25 = var_25_arg_0 & var_25_arg_1; [L317] SORT_15 var_28_arg_0 = var_27; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_28_arg_0=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] EXPR var_28_arg_0 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L318] var_28_arg_0 = var_28_arg_0 & mask_SORT_15 [L319] SORT_11 var_28 = var_28_arg_0; [L320] SORT_11 var_29_arg_0 = state_26; [L321] SORT_11 var_29_arg_1 = var_28; [L322] SORT_1 var_29 = var_29_arg_0 >= var_29_arg_1; [L323] SORT_1 var_30_arg_0 = var_25; [L324] SORT_1 var_30_arg_1 = var_29; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_30_arg_0=0, var_30_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] EXPR var_30_arg_0 & var_30_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L325] SORT_1 var_30 = var_30_arg_0 & var_30_arg_1; [L326] SORT_1 var_32_arg_0 = var_30; [L327] SORT_1 var_32_arg_1 = state_31; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32_arg_0=0, var_32_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] EXPR var_32_arg_0 & var_32_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L328] SORT_1 var_32 = var_32_arg_0 & var_32_arg_1; [L329] EXPR var_32 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L329] var_32 = var_32 & mask_SORT_1 [L330] SORT_1 var_33_arg_0 = var_32; [L331] SORT_1 var_33_arg_1 = var_32; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_33_arg_0=0, var_33_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] EXPR ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L332] SORT_5 var_33 = ((SORT_5)var_33_arg_0 << 1) | var_33_arg_1; [L333] EXPR var_33 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L333] var_33 = var_33 & mask_SORT_5 [L334] SORT_1 var_34_arg_0 = var_32; [L335] SORT_5 var_34_arg_1 = var_33; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_34_arg_0=0, var_34_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] EXPR ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L336] SORT_12 var_34 = ((SORT_12)var_34_arg_0 << 2) | var_34_arg_1; [L337] EXPR var_34 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L337] var_34 = var_34 & mask_SORT_12 [L338] SORT_1 var_35_arg_0 = var_32; [L339] SORT_12 var_35_arg_1 = var_34; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_35_arg_0=0, var_35_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] EXPR ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L340] SORT_15 var_35 = ((SORT_15)var_35_arg_0 << 3) | var_35_arg_1; [L341] EXPR var_35 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L341] var_35 = var_35 & mask_SORT_15 [L342] SORT_1 var_37_arg_0 = var_32; [L343] SORT_15 var_37_arg_1 = var_35; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_37_arg_0=0, var_37_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] EXPR ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L344] SORT_36 var_37 = ((SORT_36)var_37_arg_0 << 4) | var_37_arg_1; [L345] EXPR var_37 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L345] var_37 = var_37 & mask_SORT_36 [L346] SORT_1 var_39_arg_0 = var_32; [L347] SORT_36 var_39_arg_1 = var_37; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_39_arg_0=0, var_39_arg_1=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] EXPR ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L348] SORT_38 var_39 = ((SORT_38)var_39_arg_0 << 5) | var_39_arg_1; [L349] EXPR var_39 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L349] var_39 = var_39 & mask_SORT_38 [L350] SORT_1 var_41_arg_0 = var_32; [L351] SORT_38 var_41_arg_1 = var_39; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_41_arg_0=0, var_41_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] EXPR ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L352] SORT_40 var_41 = ((SORT_40)var_41_arg_0 << 6) | var_41_arg_1; [L353] EXPR var_41 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L353] var_41 = var_41 & mask_SORT_40 [L354] SORT_1 var_42_arg_0 = var_32; [L355] SORT_40 var_42_arg_1 = var_41; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_42_arg_0=0, var_42_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] EXPR ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_21=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L356] SORT_11 var_42 = ((SORT_11)var_42_arg_0 << 7) | var_42_arg_1; [L357] SORT_11 var_43_arg_0 = var_21; [L358] SORT_11 var_43_arg_1 = var_42; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43_arg_0=0, var_43_arg_1=0, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] EXPR var_43_arg_0 & var_43_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_49=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L359] SORT_11 var_43 = var_43_arg_0 & var_43_arg_1; [L360] SORT_11* var_50_arg_0 = state_44; [L361] SORT_12 var_50_arg_1 = var_49; [L362] EXPR var_50_arg_0[(unsigned char) var_50_arg_1] [L362] SORT_11 var_50 = var_50_arg_0[(unsigned char) var_50_arg_1]; [L363] EXPR var_50 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L363] var_50 = var_50 & mask_SORT_11 [L364] SORT_1 var_61_arg_0 = var_60; [L365] SORT_1 var_61_arg_1 = var_60; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_61_arg_0=0, var_61_arg_1=0, var_92=0, var_93=-1, var_99=0] [L366] EXPR ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L366] SORT_5 var_61 = ((SORT_5)var_61_arg_0 << 1) | var_61_arg_1; [L367] EXPR var_61 & mask_SORT_5 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L367] var_61 = var_61 & mask_SORT_5 [L368] SORT_1 var_62_arg_0 = var_60; [L369] SORT_5 var_62_arg_1 = var_61; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_62_arg_0=0, var_62_arg_1=0, var_92=0, var_93=-1, var_99=0] [L370] EXPR ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L370] SORT_12 var_62 = ((SORT_12)var_62_arg_0 << 2) | var_62_arg_1; [L371] EXPR var_62 & mask_SORT_12 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L371] var_62 = var_62 & mask_SORT_12 [L372] SORT_1 var_63_arg_0 = var_60; [L373] SORT_12 var_63_arg_1 = var_62; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_63_arg_0=0, var_63_arg_1=0, var_92=0, var_93=-1, var_99=0] [L374] EXPR ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L374] SORT_15 var_63 = ((SORT_15)var_63_arg_0 << 3) | var_63_arg_1; [L375] EXPR var_63 & mask_SORT_15 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L375] var_63 = var_63 & mask_SORT_15 [L376] SORT_1 var_64_arg_0 = var_60; [L377] SORT_15 var_64_arg_1 = var_63; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_64_arg_0=0, var_64_arg_1=0, var_92=0, var_93=-1, var_99=0] [L378] EXPR ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L378] SORT_36 var_64 = ((SORT_36)var_64_arg_0 << 4) | var_64_arg_1; [L379] EXPR var_64 & mask_SORT_36 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L379] var_64 = var_64 & mask_SORT_36 [L380] SORT_1 var_65_arg_0 = var_60; [L381] SORT_36 var_65_arg_1 = var_64; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_65_arg_0=0, var_65_arg_1=0, var_92=0, var_93=-1, var_99=0] [L382] EXPR ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L382] SORT_38 var_65 = ((SORT_38)var_65_arg_0 << 5) | var_65_arg_1; [L383] EXPR var_65 & mask_SORT_38 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L383] var_65 = var_65 & mask_SORT_38 [L384] SORT_1 var_66_arg_0 = var_60; [L385] SORT_38 var_66_arg_1 = var_65; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_66_arg_0=0, var_66_arg_1=0, var_92=0, var_93=-1, var_99=0] [L386] EXPR ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L386] SORT_40 var_66 = ((SORT_40)var_66_arg_0 << 6) | var_66_arg_1; [L387] EXPR var_66 & mask_SORT_40 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L387] var_66 = var_66 & mask_SORT_40 [L388] SORT_1 var_67_arg_0 = var_60; [L389] SORT_40 var_67_arg_1 = var_66; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_67_arg_0=0, var_67_arg_1=0, var_92=0, var_93=-1, var_99=0] [L390] EXPR ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_50=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L390] SORT_11 var_67 = ((SORT_11)var_67_arg_0 << 7) | var_67_arg_1; [L391] SORT_11 var_68_arg_0 = var_50; [L392] SORT_11 var_68_arg_1 = var_67; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_68_arg_0=0, var_68_arg_1=0, var_92=0, var_93=-1, var_99=0] [L393] EXPR var_68_arg_0 & var_68_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_43=0, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L393] SORT_11 var_68 = var_68_arg_0 & var_68_arg_1; [L394] SORT_11 var_69_arg_0 = var_43; [L395] SORT_11 var_69_arg_1 = var_68; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_69_arg_0=0, var_69_arg_1=0, var_92=0, var_93=-1, var_99=0] [L396] EXPR var_69_arg_0 | var_69_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L396] SORT_11 var_69 = var_69_arg_0 | var_69_arg_1; [L397] EXPR var_69 & mask_SORT_11 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_104=-1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L397] var_69 = var_69 & mask_SORT_11 [L398] SORT_11 var_106_arg_0 = state_105; [L399] SORT_11 var_106_arg_1 = var_69; [L400] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L401] SORT_1 var_107_arg_0 = var_104; [L402] SORT_1 var_107_arg_1 = var_106; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_107_arg_0=-1, var_107_arg_1=1, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] EXPR var_107_arg_0 | var_107_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_113=1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L403] SORT_1 var_107 = var_107_arg_0 | var_107_arg_1; [L404] SORT_1 var_114_arg_0 = var_107; [L405] SORT_1 var_114 = ~var_114_arg_0; [L406] SORT_1 var_115_arg_0 = var_113; [L407] SORT_1 var_115_arg_1 = var_114; VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_115_arg_0=1, var_115_arg_1=-1, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L408] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L409] EXPR var_115 & mask_SORT_1 VAL [constr_122_arg_0=1, constr_128_arg_0=1, constr_134_arg_0=1, constr_141_arg_0=1, constr_145_arg_0=1, input_9=1, mask_SORT_11=255, mask_SORT_12=7, mask_SORT_15=15, mask_SORT_1=1, mask_SORT_36=31, mask_SORT_38=63, mask_SORT_40=127, mask_SORT_5=3, state_105=0, state_14={10:0}, state_16=0, state_19=0, state_26=0, state_31=0, state_44={11:0}, state_45=0, state_48=0, state_55=0, state_85=0, state_86=0, state_89=0, var_100=0, var_103=0, var_109=1, var_110=0, var_136=0, var_17=0, var_183=0, var_25=0, var_27=8, var_32=0, var_410=255, var_46=0, var_54=0, var_59=0, var_60=0, var_92=0, var_93=-1, var_99=0] [L409] var_115 = var_115 & mask_SORT_1 [L410] SORT_1 bad_116_arg_0 = var_115; [L411] CALL __VERIFIER_assert(!(bad_116_arg_0)) [L21] COND TRUE !(cond) [L21] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 752 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 739.2s, OverallIterations: 101, TraceHistogramMax: 10, PathProgramHistogramMax: 2, EmptinessCheckTime: 1.3s, AutomataDifference: 92.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 114692 SdHoareTripleChecker+Valid, 61.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 114526 mSDsluCounter, 606822 SdHoareTripleChecker+Invalid, 51.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 497619 mSDsCounter, 300 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 84068 IncrementalHoareTripleChecker+Invalid, 84368 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 300 mSolverCounterUnsat, 109203 mSDtfsCounter, 84068 mSolverCounterSat, 1.6s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 45098 GetRequests, 43992 SyntacticMatches, 2 SemanticMatches, 1104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8456 ImplicationChecksByTransitivity, 20.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=52151occurred in iteration=91, InterpolantAutomatonStates: 818, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 22.6s AutomataMinimizationTime, 100 MinimizatonAttempts, 192353 StatesRemovedByMinimization, 54 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 11.7s SsaConstructionTime, 283.2s SatisfiabilityAnalysisTime, 228.3s InterpolantComputationTime, 91559 NumberOfCodeBlocks, 86888 NumberOfCodeBlocksAsserted, 143 NumberOfCheckSat, 109221 ConstructedInterpolants, 0 QuantifiedInterpolants, 372075 SizeOfPredicates, 116 NumberOfNonLiveVariables, 115964 ConjunctsInSsa, 1303 ConjunctsInUnsatCore, 168 InterpolantComputations, 83 PerfectInterpolantSequences, 104923/108071 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-11-28 03:07:26,021 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 03:07:29,439 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 03:07:29,541 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-11-28 03:07:29,556 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 03:07:29,556 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 03:07:29,634 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 03:07:29,635 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 03:07:29,639 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 03:07:29,639 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 03:07:29,640 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 03:07:29,640 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-28 03:07:29,640 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-28 03:07:29,640 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 03:07:29,641 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-28 03:07:29,641 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 03:07:29,642 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 03:07:29,642 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-28 03:07:29,643 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:07:29,643 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:07:29,643 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:07:29,643 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:07:29,643 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 03:07:29,659 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:07:29,659 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:07:29,659 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:07:29,659 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:07:29,660 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-28 03:07:29,660 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-28 03:07:29,661 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-28 03:07:29,661 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1d054f79132e175b09d8c50472a4c24ca52f401c76e1d0704dd5609a369827e2 [2024-11-28 03:07:30,053 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 03:07:30,064 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 03:07:30,068 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 03:07:30,069 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 03:07:30,070 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 03:07:30,072 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 03:07:33,572 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/0ffbcd27e/0f80ca9b4da34789872d21d4acb4ac6c/FLAG2d36422af [2024-11-28 03:07:34,051 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 03:07:34,052 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 03:07:34,066 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/0ffbcd27e/0f80ca9b4da34789872d21d4acb4ac6c/FLAG2d36422af [2024-11-28 03:07:34,179 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/data/0ffbcd27e/0f80ca9b4da34789872d21d4acb4ac6c [2024-11-28 03:07:34,184 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 03:07:34,186 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 03:07:34,188 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 03:07:34,189 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 03:07:34,195 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 03:07:34,196 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:34,199 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@16d8856 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34, skipping insertion in model container [2024-11-28 03:07:34,199 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:34,271 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 03:07:34,487 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-28 03:07:34,779 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:07:34,791 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 03:07:34,806 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/sv-benchmarks/c/hardware-verification-array/btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c[1268,1281] [2024-11-28 03:07:34,981 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:07:34,997 INFO L204 MainTranslator]: Completed translation [2024-11-28 03:07:34,998 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34 WrapperNode [2024-11-28 03:07:34,998 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 03:07:34,999 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 03:07:34,999 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 03:07:34,999 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 03:07:35,007 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,033 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,144 INFO L138 Inliner]: procedures = 18, calls = 41, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 952 [2024-11-28 03:07:35,145 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 03:07:35,145 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 03:07:35,146 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 03:07:35,146 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 03:07:35,159 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,160 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,172 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,231 INFO L175 MemorySlicer]: Split 20 memory accesses to 3 slices as follows [2, 9, 9]. 45 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0, 0]. The 8 writes are split as follows [0, 4, 4]. [2024-11-28 03:07:35,239 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,239 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,297 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,302 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,312 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,321 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,326 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,343 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 03:07:35,347 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 03:07:35,348 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 03:07:35,348 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 03:07:35,349 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (1/1) ... [2024-11-28 03:07:35,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:07:35,384 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:35,401 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-28 03:07:35,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-28 03:07:35,445 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 03:07:35,446 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#0 [2024-11-28 03:07:35,446 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#1 [2024-11-28 03:07:35,446 INFO L130 BoogieDeclarations]: Found specification of procedure read~intINTTYPE1#2 [2024-11-28 03:07:35,446 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-11-28 03:07:35,446 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#1 [2024-11-28 03:07:35,447 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#2 [2024-11-28 03:07:35,447 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-28 03:07:35,447 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-28 03:07:35,448 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-11-28 03:07:35,448 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 03:07:35,448 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 03:07:35,448 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#0 [2024-11-28 03:07:35,448 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#1 [2024-11-28 03:07:35,448 INFO L130 BoogieDeclarations]: Found specification of procedure write~intINTTYPE1#2 [2024-11-28 03:07:35,450 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-11-28 03:07:35,758 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 03:07:35,761 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 03:07:36,947 INFO L? ?]: Removed 681 outVars from TransFormulas that were not future-live. [2024-11-28 03:07:36,948 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 03:07:36,962 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 03:07:36,962 INFO L312 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-28 03:07:36,963 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:07:36 BoogieIcfgContainer [2024-11-28 03:07:36,964 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 03:07:36,967 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-28 03:07:36,967 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-28 03:07:36,974 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-28 03:07:36,974 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 03:07:34" (1/3) ... [2024-11-28 03:07:36,975 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2cd521c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:07:36, skipping insertion in model container [2024-11-28 03:07:36,976 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:07:34" (2/3) ... [2024-11-28 03:07:36,976 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2cd521c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:07:36, skipping insertion in model container [2024-11-28 03:07:36,976 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:07:36" (3/3) ... [2024-11-28 03:07:36,978 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c [2024-11-28 03:07:37,000 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-28 03:07:37,002 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.safe_arbitrated_fifos_n2d8w8.c that has 2 procedures, 42 locations, 1 initial locations, 7 loop locations, and 1 error locations. [2024-11-28 03:07:37,078 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-28 03:07:37,098 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3c9d14b3, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-28 03:07:37,099 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-28 03:07:37,104 INFO L276 IsEmpty]: Start isEmpty. Operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:07:37,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-11-28 03:07:37,112 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:37,113 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:37,113 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:37,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:37,123 INFO L85 PathProgramCache]: Analyzing trace with hash -172425956, now seen corresponding path program 1 times [2024-11-28 03:07:37,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:37,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1095221361] [2024-11-28 03:07:37,142 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:37,142 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:37,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:37,146 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:37,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 03:07:37,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:37,783 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 03:07:37,793 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:37,831 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2024-11-28 03:07:37,831 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:37,832 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:37,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1095221361] [2024-11-28 03:07:37,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1095221361] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:37,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:37,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-28 03:07:37,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728122435] [2024-11-28 03:07:37,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:37,844 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-28 03:07:37,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:37,872 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-28 03:07:37,872 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:07:37,875 INFO L87 Difference]: Start difference. First operand has 42 states, 34 states have (on average 1.4705882352941178) internal successors, (50), 35 states have internal predecessors, (50), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) Second operand has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 03:07:37,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:37,905 INFO L93 Difference]: Finished difference Result 77 states and 117 transitions. [2024-11-28 03:07:37,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-28 03:07:37,908 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) Word has length 39 [2024-11-28 03:07:37,909 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:37,915 INFO L225 Difference]: With dead ends: 77 [2024-11-28 03:07:37,915 INFO L226 Difference]: Without dead ends: 39 [2024-11-28 03:07:37,918 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 38 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:07:37,924 INFO L435 NwaCegarLoop]: 49 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 49 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:37,926 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:37,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2024-11-28 03:07:37,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2024-11-28 03:07:37,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 32 states have (on average 1.21875) internal successors, (39), 32 states have internal predecessors, (39), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:07:37,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 49 transitions. [2024-11-28 03:07:37,971 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 49 transitions. Word has length 39 [2024-11-28 03:07:37,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:37,972 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 49 transitions. [2024-11-28 03:07:37,973 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 9.5) internal successors, (19), 2 states have internal predecessors, (19), 2 states have call successors, (5), 2 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 2 states have call successors, (5) [2024-11-28 03:07:37,973 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 49 transitions. [2024-11-28 03:07:37,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2024-11-28 03:07:37,975 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:37,975 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:37,988 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-28 03:07:38,179 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:38,180 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:38,180 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:38,180 INFO L85 PathProgramCache]: Analyzing trace with hash -1962528174, now seen corresponding path program 1 times [2024-11-28 03:07:38,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:38,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1644472731] [2024-11-28 03:07:38,182 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:38,182 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:38,182 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:38,185 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:38,191 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 03:07:38,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:38,806 INFO L256 TraceCheckSpWp]: Trace formula consists of 376 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:38,817 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:38,852 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2024-11-28 03:07:38,852 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:38,852 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:38,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1644472731] [2024-11-28 03:07:38,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1644472731] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:38,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:38,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:38,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509544421] [2024-11-28 03:07:38,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:38,857 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:38,858 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:38,858 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:38,858 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:38,858 INFO L87 Difference]: Start difference. First operand 39 states and 49 transitions. Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:38,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:38,888 INFO L93 Difference]: Finished difference Result 76 states and 96 transitions. [2024-11-28 03:07:38,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:38,890 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 39 [2024-11-28 03:07:38,890 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:38,891 INFO L225 Difference]: With dead ends: 76 [2024-11-28 03:07:38,891 INFO L226 Difference]: Without dead ends: 41 [2024-11-28 03:07:38,892 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:38,893 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 44 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 91 SdHoareTripleChecker+Invalid, 6 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:38,893 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 91 Invalid, 6 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:38,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2024-11-28 03:07:38,902 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2024-11-28 03:07:38,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 33 states have (on average 1.2121212121212122) internal successors, (40), 33 states have internal predecessors, (40), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:07:38,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 50 transitions. [2024-11-28 03:07:38,904 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 50 transitions. Word has length 39 [2024-11-28 03:07:38,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:38,904 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 50 transitions. [2024-11-28 03:07:38,904 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:38,905 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 50 transitions. [2024-11-28 03:07:38,906 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2024-11-28 03:07:38,908 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:38,908 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:38,923 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-28 03:07:39,108 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:39,109 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:39,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:39,110 INFO L85 PathProgramCache]: Analyzing trace with hash 482086798, now seen corresponding path program 1 times [2024-11-28 03:07:39,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:39,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [915011792] [2024-11-28 03:07:39,111 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:39,111 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:39,111 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:39,114 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:39,120 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 03:07:39,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:39,642 INFO L256 TraceCheckSpWp]: Trace formula consists of 381 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:39,649 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:39,668 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 03:07:39,668 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:39,668 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:39,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [915011792] [2024-11-28 03:07:39,669 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [915011792] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:39,669 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:39,669 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:39,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285624511] [2024-11-28 03:07:39,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:39,670 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:39,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:39,672 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:39,674 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:39,674 INFO L87 Difference]: Start difference. First operand 40 states and 50 transitions. Second operand has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:39,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:39,719 INFO L93 Difference]: Finished difference Result 74 states and 93 transitions. [2024-11-28 03:07:39,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:39,720 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 41 [2024-11-28 03:07:39,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:39,721 INFO L225 Difference]: With dead ends: 74 [2024-11-28 03:07:39,721 INFO L226 Difference]: Without dead ends: 42 [2024-11-28 03:07:39,721 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:39,722 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:39,722 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:39,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2024-11-28 03:07:39,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 41. [2024-11-28 03:07:39,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 34 states have (on average 1.2058823529411764) internal successors, (41), 34 states have internal predecessors, (41), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:07:39,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 51 transitions. [2024-11-28 03:07:39,736 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 51 transitions. Word has length 41 [2024-11-28 03:07:39,736 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:39,736 INFO L471 AbstractCegarLoop]: Abstraction has 41 states and 51 transitions. [2024-11-28 03:07:39,736 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 6.333333333333333) internal successors, (19), 3 states have internal predecessors, (19), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:39,736 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 51 transitions. [2024-11-28 03:07:39,737 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2024-11-28 03:07:39,739 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:39,739 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:39,752 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-28 03:07:39,943 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:39,944 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:39,944 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:39,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1508766582, now seen corresponding path program 1 times [2024-11-28 03:07:39,945 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:39,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1088798345] [2024-11-28 03:07:39,946 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:39,946 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:39,946 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:39,949 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:39,953 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 03:07:40,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:40,514 INFO L256 TraceCheckSpWp]: Trace formula consists of 386 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:07:40,523 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:40,569 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 03:07:40,573 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:07:40,696 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2024-11-28 03:07:40,697 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:40,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1088798345] [2024-11-28 03:07:40,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1088798345] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:07:40,697 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:07:40,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:07:40,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465616307] [2024-11-28 03:07:40,698 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:07:40,698 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:07:40,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:40,699 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:07:40,700 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:40,700 INFO L87 Difference]: Start difference. First operand 41 states and 51 transitions. Second operand has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 03:07:40,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:40,802 INFO L93 Difference]: Finished difference Result 83 states and 105 transitions. [2024-11-28 03:07:40,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:07:40,803 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 43 [2024-11-28 03:07:40,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:40,804 INFO L225 Difference]: With dead ends: 83 [2024-11-28 03:07:40,804 INFO L226 Difference]: Without dead ends: 47 [2024-11-28 03:07:40,805 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:07:40,805 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 132 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 179 SdHoareTripleChecker+Invalid, 23 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:40,806 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 179 Invalid, 23 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 21 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:40,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2024-11-28 03:07:40,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2024-11-28 03:07:40,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 40 states have (on average 1.175) internal successors, (47), 40 states have internal predecessors, (47), 5 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:07:40,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 57 transitions. [2024-11-28 03:07:40,812 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 57 transitions. Word has length 43 [2024-11-28 03:07:40,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:40,812 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 57 transitions. [2024-11-28 03:07:40,812 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 4.0) internal successors, (28), 7 states have internal predecessors, (28), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 03:07:40,812 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 57 transitions. [2024-11-28 03:07:40,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2024-11-28 03:07:40,814 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:40,814 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:40,827 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-11-28 03:07:41,018 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:41,019 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:41,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:41,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1082379582, now seen corresponding path program 2 times [2024-11-28 03:07:41,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:41,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [736944754] [2024-11-28 03:07:41,021 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:07:41,021 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:41,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:41,024 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:41,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 03:07:41,580 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2024-11-28 03:07:41,581 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:07:41,586 INFO L256 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 14 conjuncts are in the unsatisfiable core [2024-11-28 03:07:41,596 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:42,126 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2024-11-28 03:07:42,127 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:42,127 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:42,127 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [736944754] [2024-11-28 03:07:42,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [736944754] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:42,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:42,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 03:07:42,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [254752922] [2024-11-28 03:07:42,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:42,129 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 03:07:42,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:42,133 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 03:07:42,133 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:07:42,133 INFO L87 Difference]: Start difference. First operand 47 states and 57 transitions. Second operand has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:42,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:42,495 INFO L93 Difference]: Finished difference Result 61 states and 76 transitions. [2024-11-28 03:07:42,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:07:42,496 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) Word has length 49 [2024-11-28 03:07:42,496 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:42,497 INFO L225 Difference]: With dead ends: 61 [2024-11-28 03:07:42,497 INFO L226 Difference]: Without dead ends: 59 [2024-11-28 03:07:42,498 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:42,499 INFO L435 NwaCegarLoop]: 37 mSDtfsCounter, 34 mSDsluCounter, 75 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 39 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:42,499 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [39 Valid, 112 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 43 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 03:07:42,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2024-11-28 03:07:42,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2024-11-28 03:07:42,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 47 states have (on average 1.148936170212766) internal successors, (54), 47 states have internal predecessors, (54), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:42,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 74 transitions. [2024-11-28 03:07:42,517 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 74 transitions. Word has length 49 [2024-11-28 03:07:42,519 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:42,519 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 74 transitions. [2024-11-28 03:07:42,519 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.2) internal successors, (21), 5 states have internal predecessors, (21), 1 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 1 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:07:42,519 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 74 transitions. [2024-11-28 03:07:42,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2024-11-28 03:07:42,521 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:42,522 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:42,535 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-28 03:07:42,726 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:42,726 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:42,727 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:42,728 INFO L85 PathProgramCache]: Analyzing trace with hash -1262899509, now seen corresponding path program 1 times [2024-11-28 03:07:42,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:42,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1483831468] [2024-11-28 03:07:42,730 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:42,731 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:42,731 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:42,733 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:42,736 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 03:07:43,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:43,718 INFO L256 TraceCheckSpWp]: Trace formula consists of 1125 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:43,730 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:43,752 INFO L134 CoverageAnalysis]: Checked inductivity of 209 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 97 trivial. 0 not checked. [2024-11-28 03:07:43,753 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:43,753 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:43,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1483831468] [2024-11-28 03:07:43,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1483831468] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:43,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:43,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:43,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [833930071] [2024-11-28 03:07:43,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:43,754 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:43,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:43,755 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:43,755 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:43,756 INFO L87 Difference]: Start difference. First operand 59 states and 74 transitions. Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:43,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:43,842 INFO L93 Difference]: Finished difference Result 92 states and 116 transitions. [2024-11-28 03:07:43,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:43,849 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 90 [2024-11-28 03:07:43,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:43,852 INFO L225 Difference]: With dead ends: 92 [2024-11-28 03:07:43,852 INFO L226 Difference]: Without dead ends: 61 [2024-11-28 03:07:43,855 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:43,856 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:43,856 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:43,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2024-11-28 03:07:43,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2024-11-28 03:07:43,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 48 states have (on average 1.1458333333333333) internal successors, (55), 48 states have internal predecessors, (55), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:43,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2024-11-28 03:07:43,886 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 75 transitions. Word has length 90 [2024-11-28 03:07:43,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:43,887 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 75 transitions. [2024-11-28 03:07:43,887 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:43,887 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 75 transitions. [2024-11-28 03:07:43,891 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2024-11-28 03:07:43,892 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:43,892 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:43,911 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-28 03:07:44,092 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:44,092 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:44,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:44,093 INFO L85 PathProgramCache]: Analyzing trace with hash 1332255303, now seen corresponding path program 1 times [2024-11-28 03:07:44,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:44,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [91770745] [2024-11-28 03:07:44,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:44,094 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:44,094 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:44,095 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:44,096 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 03:07:45,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:45,043 INFO L256 TraceCheckSpWp]: Trace formula consists of 1131 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:45,049 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:45,067 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2024-11-28 03:07:45,067 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:45,067 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:45,067 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [91770745] [2024-11-28 03:07:45,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [91770745] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:45,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:45,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:45,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672028374] [2024-11-28 03:07:45,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:45,069 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:45,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:45,070 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:45,070 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:45,070 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:45,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:45,116 INFO L93 Difference]: Finished difference Result 94 states and 118 transitions. [2024-11-28 03:07:45,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:45,118 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 92 [2024-11-28 03:07:45,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:45,119 INFO L225 Difference]: With dead ends: 94 [2024-11-28 03:07:45,119 INFO L226 Difference]: Without dead ends: 62 [2024-11-28 03:07:45,120 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:45,121 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:45,121 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:45,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2024-11-28 03:07:45,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 61. [2024-11-28 03:07:45,133 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 49 states have (on average 1.1428571428571428) internal successors, (56), 49 states have internal predecessors, (56), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:45,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 76 transitions. [2024-11-28 03:07:45,135 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 76 transitions. Word has length 92 [2024-11-28 03:07:45,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:45,135 INFO L471 AbstractCegarLoop]: Abstraction has 61 states and 76 transitions. [2024-11-28 03:07:45,136 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:45,136 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 76 transitions. [2024-11-28 03:07:45,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2024-11-28 03:07:45,137 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:45,137 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:45,156 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-28 03:07:45,342 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:45,342 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:45,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:45,343 INFO L85 PathProgramCache]: Analyzing trace with hash -523258493, now seen corresponding path program 1 times [2024-11-28 03:07:45,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:45,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1575434297] [2024-11-28 03:07:45,344 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:45,344 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:45,344 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:45,348 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:45,350 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 03:07:46,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:46,274 INFO L256 TraceCheckSpWp]: Trace formula consists of 1137 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:46,280 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:46,296 INFO L134 CoverageAnalysis]: Checked inductivity of 211 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 99 trivial. 0 not checked. [2024-11-28 03:07:46,296 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:46,296 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:46,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1575434297] [2024-11-28 03:07:46,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1575434297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:46,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:46,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:46,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [134000940] [2024-11-28 03:07:46,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:46,298 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:46,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:46,298 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:46,299 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:46,299 INFO L87 Difference]: Start difference. First operand 61 states and 76 transitions. Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:46,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:46,334 INFO L93 Difference]: Finished difference Result 96 states and 120 transitions. [2024-11-28 03:07:46,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:46,335 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 94 [2024-11-28 03:07:46,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:46,336 INFO L225 Difference]: With dead ends: 96 [2024-11-28 03:07:46,336 INFO L226 Difference]: Without dead ends: 63 [2024-11-28 03:07:46,336 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:46,337 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:46,337 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:46,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2024-11-28 03:07:46,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 62. [2024-11-28 03:07:46,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 50 states have (on average 1.14) internal successors, (57), 50 states have internal predecessors, (57), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:46,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 77 transitions. [2024-11-28 03:07:46,351 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 77 transitions. Word has length 94 [2024-11-28 03:07:46,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:46,352 INFO L471 AbstractCegarLoop]: Abstraction has 62 states and 77 transitions. [2024-11-28 03:07:46,352 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:46,352 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 77 transitions. [2024-11-28 03:07:46,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2024-11-28 03:07:46,353 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:46,354 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:46,373 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-11-28 03:07:46,554 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:46,555 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:46,555 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:46,555 INFO L85 PathProgramCache]: Analyzing trace with hash 1675280511, now seen corresponding path program 1 times [2024-11-28 03:07:46,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:46,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [761983200] [2024-11-28 03:07:46,556 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:46,556 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:46,556 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:46,558 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:46,559 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 03:07:47,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:47,585 INFO L256 TraceCheckSpWp]: Trace formula consists of 1143 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-11-28 03:07:47,592 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:47,606 INFO L134 CoverageAnalysis]: Checked inductivity of 212 backedges. 112 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2024-11-28 03:07:47,607 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:07:47,607 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:47,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [761983200] [2024-11-28 03:07:47,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [761983200] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:07:47,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:07:47,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-28 03:07:47,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534983367] [2024-11-28 03:07:47,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:07:47,608 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2024-11-28 03:07:47,608 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:47,609 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-28 03:07:47,609 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:47,609 INFO L87 Difference]: Start difference. First operand 62 states and 77 transitions. Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:47,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:47,641 INFO L93 Difference]: Finished difference Result 98 states and 122 transitions. [2024-11-28 03:07:47,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-28 03:07:47,642 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) Word has length 96 [2024-11-28 03:07:47,642 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:47,643 INFO L225 Difference]: With dead ends: 98 [2024-11-28 03:07:47,643 INFO L226 Difference]: Without dead ends: 64 [2024-11-28 03:07:47,644 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-28 03:07:47,644 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 1 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 90 SdHoareTripleChecker+Invalid, 7 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:47,645 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 90 Invalid, 7 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:07:47,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2024-11-28 03:07:47,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2024-11-28 03:07:47,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 51 states have (on average 1.1372549019607843) internal successors, (58), 51 states have internal predecessors, (58), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:47,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 78 transitions. [2024-11-28 03:07:47,656 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 78 transitions. Word has length 96 [2024-11-28 03:07:47,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:47,657 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 78 transitions. [2024-11-28 03:07:47,657 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 2 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 2 states have call predecessors, (10), 2 states have call successors, (10) [2024-11-28 03:07:47,657 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 78 transitions. [2024-11-28 03:07:47,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2024-11-28 03:07:47,658 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:47,659 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:47,676 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-28 03:07:47,863 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:47,863 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:47,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:47,864 INFO L85 PathProgramCache]: Analyzing trace with hash -571376837, now seen corresponding path program 1 times [2024-11-28 03:07:47,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:47,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [466915005] [2024-11-28 03:07:47,865 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:07:47,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:47,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:47,868 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:47,869 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 03:07:48,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:07:48,889 INFO L256 TraceCheckSpWp]: Trace formula consists of 1149 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:07:48,894 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:48,922 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-11-28 03:07:48,922 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:07:49,037 INFO L134 CoverageAnalysis]: Checked inductivity of 213 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 212 trivial. 0 not checked. [2024-11-28 03:07:49,037 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:49,037 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [466915005] [2024-11-28 03:07:49,037 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [466915005] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:07:49,037 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:07:49,038 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:07:49,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [62190409] [2024-11-28 03:07:49,038 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:07:49,038 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:07:49,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:49,039 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:07:49,039 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:49,040 INFO L87 Difference]: Start difference. First operand 63 states and 78 transitions. Second operand has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 03:07:49,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:49,148 INFO L93 Difference]: Finished difference Result 117 states and 148 transitions. [2024-11-28 03:07:49,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:07:49,149 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) Word has length 98 [2024-11-28 03:07:49,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:49,150 INFO L225 Difference]: With dead ends: 117 [2024-11-28 03:07:49,150 INFO L226 Difference]: Without dead ends: 69 [2024-11-28 03:07:49,150 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 195 GetRequests, 189 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:07:49,151 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:49,151 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:49,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2024-11-28 03:07:49,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2024-11-28 03:07:49,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 57 states have (on average 1.1228070175438596) internal successors, (64), 57 states have internal predecessors, (64), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:49,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 84 transitions. [2024-11-28 03:07:49,163 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 84 transitions. Word has length 98 [2024-11-28 03:07:49,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:49,164 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 84 transitions. [2024-11-28 03:07:49,164 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 6.571428571428571) internal successors, (46), 7 states have internal predecessors, (46), 1 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 1 states have call predecessors, (10), 1 states have call successors, (10) [2024-11-28 03:07:49,164 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 84 transitions. [2024-11-28 03:07:49,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2024-11-28 03:07:49,168 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:49,169 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:49,182 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-28 03:07:49,369 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:49,369 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:49,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:49,370 INFO L85 PathProgramCache]: Analyzing trace with hash -327439417, now seen corresponding path program 2 times [2024-11-28 03:07:49,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:49,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2078820933] [2024-11-28 03:07:49,371 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:07:49,371 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:49,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:49,373 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:49,374 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-28 03:07:50,512 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 03:07:50,512 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:07:50,529 INFO L256 TraceCheckSpWp]: Trace formula consists of 1164 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:07:50,535 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:50,564 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 115 trivial. 0 not checked. [2024-11-28 03:07:50,564 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:07:50,667 INFO L134 CoverageAnalysis]: Checked inductivity of 228 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 215 trivial. 0 not checked. [2024-11-28 03:07:50,668 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:50,668 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2078820933] [2024-11-28 03:07:50,668 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2078820933] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:07:50,668 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:07:50,668 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:07:50,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799942755] [2024-11-28 03:07:50,669 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:07:50,670 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:07:50,670 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:50,671 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:07:50,671 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:50,671 INFO L87 Difference]: Start difference. First operand 69 states and 84 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:50,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:50,791 INFO L93 Difference]: Finished difference Result 110 states and 136 transitions. [2024-11-28 03:07:50,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:07:50,795 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 104 [2024-11-28 03:07:50,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:50,795 INFO L225 Difference]: With dead ends: 110 [2024-11-28 03:07:50,796 INFO L226 Difference]: Without dead ends: 75 [2024-11-28 03:07:50,796 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 207 GetRequests, 201 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:07:50,796 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:50,797 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:50,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2024-11-28 03:07:50,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2024-11-28 03:07:50,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 63 states have (on average 1.1111111111111112) internal successors, (70), 63 states have internal predecessors, (70), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:50,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 90 transitions. [2024-11-28 03:07:50,826 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 90 transitions. Word has length 104 [2024-11-28 03:07:50,826 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:50,826 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 90 transitions. [2024-11-28 03:07:50,826 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:50,826 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 90 transitions. [2024-11-28 03:07:50,827 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2024-11-28 03:07:50,827 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:50,828 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:50,842 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-28 03:07:51,032 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:51,032 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:51,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:51,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1578953669, now seen corresponding path program 3 times [2024-11-28 03:07:51,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:51,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [733389076] [2024-11-28 03:07:51,034 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-28 03:07:51,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:51,034 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:51,037 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:51,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-28 03:07:52,237 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2024-11-28 03:07:52,237 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:07:52,250 INFO L256 TraceCheckSpWp]: Trace formula consists of 977 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:07:52,255 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:52,308 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2024-11-28 03:07:52,308 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:07:52,431 INFO L134 CoverageAnalysis]: Checked inductivity of 243 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 230 trivial. 0 not checked. [2024-11-28 03:07:52,434 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:52,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [733389076] [2024-11-28 03:07:52,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [733389076] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:07:52,434 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:07:52,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:07:52,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [774494301] [2024-11-28 03:07:52,435 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:07:52,435 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:07:52,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:52,436 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:07:52,436 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:52,436 INFO L87 Difference]: Start difference. First operand 75 states and 90 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:52,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:52,530 INFO L93 Difference]: Finished difference Result 122 states and 148 transitions. [2024-11-28 03:07:52,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:07:52,531 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 110 [2024-11-28 03:07:52,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:52,532 INFO L225 Difference]: With dead ends: 122 [2024-11-28 03:07:52,533 INFO L226 Difference]: Without dead ends: 81 [2024-11-28 03:07:52,533 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 219 GetRequests, 213 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:07:52,534 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 19 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 19 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:52,535 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 133 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 19 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:52,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2024-11-28 03:07:52,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2024-11-28 03:07:52,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 69 states have (on average 1.1014492753623188) internal successors, (76), 69 states have internal predecessors, (76), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:52,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 96 transitions. [2024-11-28 03:07:52,551 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 96 transitions. Word has length 110 [2024-11-28 03:07:52,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:52,552 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 96 transitions. [2024-11-28 03:07:52,552 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:52,552 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 96 transitions. [2024-11-28 03:07:52,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2024-11-28 03:07:52,554 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:52,554 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:52,573 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-28 03:07:52,754 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:52,755 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:52,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:52,755 INFO L85 PathProgramCache]: Analyzing trace with hash 710782511, now seen corresponding path program 4 times [2024-11-28 03:07:52,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:52,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [111785223] [2024-11-28 03:07:52,757 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-28 03:07:52,757 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:52,757 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:52,759 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:52,761 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2024-11-28 03:07:53,927 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-28 03:07:53,927 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:07:53,940 INFO L256 TraceCheckSpWp]: Trace formula consists of 1154 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:07:53,945 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:07:53,977 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-11-28 03:07:53,977 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:07:54,100 INFO L134 CoverageAnalysis]: Checked inductivity of 258 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 245 trivial. 0 not checked. [2024-11-28 03:07:54,100 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:07:54,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [111785223] [2024-11-28 03:07:54,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [111785223] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:07:54,100 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:07:54,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:07:54,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949134226] [2024-11-28 03:07:54,101 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:07:54,101 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:07:54,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:07:54,102 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:07:54,102 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:07:54,103 INFO L87 Difference]: Start difference. First operand 81 states and 96 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:54,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:07:54,220 INFO L93 Difference]: Finished difference Result 134 states and 160 transitions. [2024-11-28 03:07:54,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:07:54,221 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 116 [2024-11-28 03:07:54,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:07:54,222 INFO L225 Difference]: With dead ends: 134 [2024-11-28 03:07:54,222 INFO L226 Difference]: Without dead ends: 87 [2024-11-28 03:07:54,223 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 231 GetRequests, 225 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:07:54,224 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 4 mSDsluCounter, 129 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 176 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:07:54,224 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 176 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:07:54,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2024-11-28 03:07:54,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2024-11-28 03:07:54,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 75 states have (on average 1.0933333333333333) internal successors, (82), 75 states have internal predecessors, (82), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:07:54,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 102 transitions. [2024-11-28 03:07:54,245 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 102 transitions. Word has length 116 [2024-11-28 03:07:54,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:07:54,246 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 102 transitions. [2024-11-28 03:07:54,246 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:07:54,246 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 102 transitions. [2024-11-28 03:07:54,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2024-11-28 03:07:54,248 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:07:54,248 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:07:54,272 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2024-11-28 03:07:54,449 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:54,449 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:07:54,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:07:54,450 INFO L85 PathProgramCache]: Analyzing trace with hash -739418781, now seen corresponding path program 5 times [2024-11-28 03:07:54,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-11-28 03:07:54,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1518694043] [2024-11-28 03:07:54,452 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-28 03:07:54,452 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:07:54,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:07:54,454 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:07:54,456 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2024-11-28 03:08:00,353 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2024-11-28 03:08:00,353 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:08:00,370 INFO L256 TraceCheckSpWp]: Trace formula consists of 963 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-11-28 03:08:00,376 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:08:00,404 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 112 proven. 1 refuted. 0 times theorem prover too weak. 160 trivial. 0 not checked. [2024-11-28 03:08:00,404 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:08:00,521 INFO L134 CoverageAnalysis]: Checked inductivity of 273 backedges. 12 proven. 1 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2024-11-28 03:08:00,521 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-11-28 03:08:00,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1518694043] [2024-11-28 03:08:00,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1518694043] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:08:00,521 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:08:00,521 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 7 [2024-11-28 03:08:00,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121252675] [2024-11-28 03:08:00,522 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:08:00,522 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-11-28 03:08:00,523 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-11-28 03:08:00,523 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-11-28 03:08:00,524 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2024-11-28 03:08:00,524 INFO L87 Difference]: Start difference. First operand 87 states and 102 transitions. Second operand has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:08:00,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:08:00,698 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2024-11-28 03:08:00,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:08:00,700 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) Word has length 122 [2024-11-28 03:08:00,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:08:00,702 INFO L225 Difference]: With dead ends: 146 [2024-11-28 03:08:00,702 INFO L226 Difference]: Without dead ends: 93 [2024-11-28 03:08:00,702 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 243 GetRequests, 237 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=31, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:08:00,703 INFO L435 NwaCegarLoop]: 47 mSDtfsCounter, 3 mSDsluCounter, 215 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 262 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:08:00,704 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 262 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:08:00,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2024-11-28 03:08:00,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2024-11-28 03:08:00,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 81 states have (on average 1.0864197530864197) internal successors, (88), 81 states have internal predecessors, (88), 10 states have call successors, (10), 1 states have call predecessors, (10), 1 states have return successors, (10), 10 states have call predecessors, (10), 10 states have call successors, (10) [2024-11-28 03:08:00,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 108 transitions. [2024-11-28 03:08:00,718 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 108 transitions. Word has length 122 [2024-11-28 03:08:00,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:08:00,719 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 108 transitions. [2024-11-28 03:08:00,719 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 7.428571428571429) internal successors, (52), 7 states have internal predecessors, (52), 2 states have call successors, (15), 2 states have call predecessors, (15), 2 states have return successors, (15), 2 states have call predecessors, (15), 2 states have call successors, (15) [2024-11-28 03:08:00,719 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 108 transitions. [2024-11-28 03:08:00,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2024-11-28 03:08:00,720 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:08:00,721 INFO L218 NwaCegarLoop]: trace histogram [10, 10, 10, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:08:00,740 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_ce22402f-8633-4059-ac55-77a0570fb5df/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0