./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerReach.xml -i ../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 36da946a83103a61b88f0f1db9af94484aad5eefbde5313f974f53b267bd14bf --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 03:01:45,214 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 03:01:45,318 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-32bit-Automizer_Default.epf [2024-11-28 03:01:45,323 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 03:01:45,323 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 03:01:45,364 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 03:01:45,365 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 03:01:45,366 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 03:01:45,367 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 03:01:45,367 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 03:01:45,368 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-28 03:01:45,369 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-28 03:01:45,369 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 03:01:45,369 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 03:01:45,369 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 03:01:45,369 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 03:01:45,370 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 03:01:45,371 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-28 03:01:45,371 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:01:45,371 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:01:45,371 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:01:45,371 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:01:45,372 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 03:01:45,372 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:01:45,372 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:01:45,372 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:01:45,372 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:01:45,372 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 03:01:45,372 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-28 03:01:45,373 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-28 03:01:45,374 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 36da946a83103a61b88f0f1db9af94484aad5eefbde5313f974f53b267bd14bf [2024-11-28 03:01:45,688 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 03:01:45,697 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 03:01:45,700 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 03:01:45,702 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 03:01:45,702 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 03:01:45,703 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c [2024-11-28 03:01:48,719 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/data/671fd05ed/2685edf59e22454a8f291b4766eaa6b6/FLAGeaeebbeab [2024-11-28 03:01:49,034 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 03:01:49,035 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c [2024-11-28 03:01:49,057 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/data/671fd05ed/2685edf59e22454a8f291b4766eaa6b6/FLAGeaeebbeab [2024-11-28 03:01:49,080 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/data/671fd05ed/2685edf59e22454a8f291b4766eaa6b6 [2024-11-28 03:01:49,082 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 03:01:49,084 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 03:01:49,086 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 03:01:49,086 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 03:01:49,091 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 03:01:49,092 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,093 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3081df55 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49, skipping insertion in model container [2024-11-28 03:01:49,093 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,110 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 03:01:49,326 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c[524,537] [2024-11-28 03:01:49,361 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:01:49,375 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 03:01:49,391 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c[524,537] [2024-11-28 03:01:49,404 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:01:49,426 INFO L204 MainTranslator]: Completed translation [2024-11-28 03:01:49,431 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49 WrapperNode [2024-11-28 03:01:49,431 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 03:01:49,432 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 03:01:49,435 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 03:01:49,435 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 03:01:49,447 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,454 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,476 INFO L138 Inliner]: procedures = 14, calls = 11, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 46 [2024-11-28 03:01:49,477 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 03:01:49,478 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 03:01:49,478 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 03:01:49,478 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 03:01:49,489 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,490 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,491 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,511 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-28 03:01:49,513 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,513 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,517 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,518 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,522 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,523 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,524 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,526 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 03:01:49,527 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 03:01:49,527 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 03:01:49,527 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 03:01:49,528 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (1/1) ... [2024-11-28 03:01:49,535 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:01:49,551 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:49,567 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-28 03:01:49,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-28 03:01:49,600 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 03:01:49,600 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-28 03:01:49,600 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-28 03:01:49,600 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-28 03:01:49,600 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 03:01:49,600 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 03:01:49,601 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2024-11-28 03:01:49,601 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2024-11-28 03:01:49,661 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 03:01:49,663 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 03:01:49,893 INFO L? ?]: Removed 7 outVars from TransFormulas that were not future-live. [2024-11-28 03:01:49,893 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 03:01:49,906 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 03:01:49,908 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-28 03:01:49,909 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:01:49 BoogieIcfgContainer [2024-11-28 03:01:49,909 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 03:01:49,911 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-28 03:01:49,911 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-28 03:01:49,919 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-28 03:01:49,919 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 03:01:49" (1/3) ... [2024-11-28 03:01:49,920 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73862874 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:01:49, skipping insertion in model container [2024-11-28 03:01:49,921 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:01:49" (2/3) ... [2024-11-28 03:01:49,922 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@73862874 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:01:49, skipping insertion in model container [2024-11-28 03:01:49,922 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:01:49" (3/3) ... [2024-11-28 03:01:49,923 INFO L128 eAbstractionObserver]: Analyzing ICFG fermat2-ll_unwindbound100.c [2024-11-28 03:01:49,949 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-28 03:01:49,953 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG fermat2-ll_unwindbound100.c that has 3 procedures, 25 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-28 03:01:50,039 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-28 03:01:50,059 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@4680f67c, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-28 03:01:50,059 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-28 03:01:50,066 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:01:50,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2024-11-28 03:01:50,077 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:50,078 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:50,079 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:50,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:50,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1086166160, now seen corresponding path program 1 times [2024-11-28 03:01:50,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:50,098 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164964480] [2024-11-28 03:01:50,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:50,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:50,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:50,281 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-28 03:01:50,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:50,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164964480] [2024-11-28 03:01:50,283 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164964480] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:50,283 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1591055973] [2024-11-28 03:01:50,283 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:50,283 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:50,283 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:50,286 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:50,289 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 03:01:50,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:50,364 INFO L256 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 03:01:50,368 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:50,378 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-28 03:01:50,378 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:01:50,379 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1591055973] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:50,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:01:50,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-28 03:01:50,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23314902] [2024-11-28 03:01:50,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:50,385 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-28 03:01:50,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:50,404 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-28 03:01:50,404 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:01:50,407 INFO L87 Difference]: Start difference. First operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-28 03:01:50,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:50,428 INFO L93 Difference]: Finished difference Result 47 states and 64 transitions. [2024-11-28 03:01:50,429 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-28 03:01:50,430 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 18 [2024-11-28 03:01:50,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:50,439 INFO L225 Difference]: With dead ends: 47 [2024-11-28 03:01:50,439 INFO L226 Difference]: Without dead ends: 21 [2024-11-28 03:01:50,443 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:01:50,446 INFO L435 NwaCegarLoop]: 29 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:50,447 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:01:50,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2024-11-28 03:01:50,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2024-11-28 03:01:50,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-28 03:01:50,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2024-11-28 03:01:50,485 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 18 [2024-11-28 03:01:50,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:50,486 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2024-11-28 03:01:50,486 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-28 03:01:50,486 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2024-11-28 03:01:50,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2024-11-28 03:01:50,488 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:50,488 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:50,500 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2024-11-28 03:01:50,692 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-11-28 03:01:50,693 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:50,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:50,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1316097620, now seen corresponding path program 1 times [2024-11-28 03:01:50,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:50,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864279943] [2024-11-28 03:01:50,694 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:50,694 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:50,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2024-11-28 03:01:50,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1151503297] [2024-11-28 03:01:50,752 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:50,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:50,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:50,755 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:50,757 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 03:01:50,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:50,816 INFO L256 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 9 conjuncts are in the unsatisfiable core [2024-11-28 03:01:50,819 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:51,211 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:51,211 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:01:51,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:51,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864279943] [2024-11-28 03:01:51,212 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2024-11-28 03:01:51,213 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1151503297] [2024-11-28 03:01:51,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1151503297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:51,213 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:01:51,213 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 03:01:51,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620703070] [2024-11-28 03:01:51,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:51,214 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 03:01:51,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:51,217 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 03:01:51,218 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:01:51,218 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:01:52,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:52,281 INFO L93 Difference]: Finished difference Result 33 states and 40 transitions. [2024-11-28 03:01:52,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:01:52,281 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2024-11-28 03:01:52,282 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:52,282 INFO L225 Difference]: With dead ends: 33 [2024-11-28 03:01:52,283 INFO L226 Difference]: Without dead ends: 31 [2024-11-28 03:01:52,283 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:01:52,284 INFO L435 NwaCegarLoop]: 18 mSDtfsCounter, 5 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 69 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:52,284 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 69 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-11-28 03:01:52,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2024-11-28 03:01:52,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2024-11-28 03:01:52,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 21 states have (on average 1.3333333333333333) internal successors, (28), 22 states have internal predecessors, (28), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:01:52,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 37 transitions. [2024-11-28 03:01:52,293 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 37 transitions. Word has length 19 [2024-11-28 03:01:52,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:52,294 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 37 transitions. [2024-11-28 03:01:52,294 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:01:52,294 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 37 transitions. [2024-11-28 03:01:52,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2024-11-28 03:01:52,295 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:52,295 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:52,304 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2024-11-28 03:01:52,495 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:52,495 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:52,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:52,496 INFO L85 PathProgramCache]: Analyzing trace with hash 1318004244, now seen corresponding path program 1 times [2024-11-28 03:01:52,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:52,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65449338] [2024-11-28 03:01:52,496 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:52,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:52,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:52,597 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:52,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:52,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65449338] [2024-11-28 03:01:52,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65449338] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:01:52,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:01:52,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 03:01:52,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101493565] [2024-11-28 03:01:52,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:01:52,598 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 03:01:52,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:52,599 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:01:52,599 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:01:52,599 INFO L87 Difference]: Start difference. First operand 30 states and 37 transitions. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:01:52,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:52,622 INFO L93 Difference]: Finished difference Result 39 states and 46 transitions. [2024-11-28 03:01:52,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:01:52,622 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2024-11-28 03:01:52,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:52,624 INFO L225 Difference]: With dead ends: 39 [2024-11-28 03:01:52,624 INFO L226 Difference]: Without dead ends: 32 [2024-11-28 03:01:52,624 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:01:52,625 INFO L435 NwaCegarLoop]: 23 mSDtfsCounter, 5 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 57 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:52,626 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 57 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:01:52,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2024-11-28 03:01:52,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2024-11-28 03:01:52,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 23 states have (on average 1.3043478260869565) internal successors, (30), 24 states have internal predecessors, (30), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:01:52,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 39 transitions. [2024-11-28 03:01:52,635 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 39 transitions. Word has length 19 [2024-11-28 03:01:52,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:52,636 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 39 transitions. [2024-11-28 03:01:52,636 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:01:52,636 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 39 transitions. [2024-11-28 03:01:52,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2024-11-28 03:01:52,637 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:52,637 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:52,637 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-28 03:01:52,637 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:52,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:52,638 INFO L85 PathProgramCache]: Analyzing trace with hash -1691684484, now seen corresponding path program 1 times [2024-11-28 03:01:52,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:52,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859486025] [2024-11-28 03:01:52,638 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:52,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:52,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:53,207 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:53,208 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:53,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859486025] [2024-11-28 03:01:53,208 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859486025] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:53,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [213802383] [2024-11-28 03:01:53,209 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:53,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:53,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:53,212 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:53,217 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 03:01:53,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:53,279 INFO L256 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-11-28 03:01:53,281 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:53,395 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:53,396 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:01:53,571 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:53,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [213802383] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:01:53,571 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:01:53,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8, 8] total 12 [2024-11-28 03:01:53,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500976475] [2024-11-28 03:01:53,572 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:01:53,572 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2024-11-28 03:01:53,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:53,573 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2024-11-28 03:01:53,573 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:01:53,574 INFO L87 Difference]: Start difference. First operand 32 states and 39 transitions. Second operand has 12 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 4 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:01:53,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:53,693 INFO L93 Difference]: Finished difference Result 39 states and 45 transitions. [2024-11-28 03:01:53,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 03:01:53,694 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 4 states have call predecessors, (5), 1 states have call successors, (5) Word has length 25 [2024-11-28 03:01:53,694 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:53,695 INFO L225 Difference]: With dead ends: 39 [2024-11-28 03:01:53,695 INFO L226 Difference]: Without dead ends: 34 [2024-11-28 03:01:53,696 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 45 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2024-11-28 03:01:53,697 INFO L435 NwaCegarLoop]: 18 mSDtfsCounter, 8 mSDsluCounter, 104 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 122 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:53,697 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [8 Valid, 122 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:01:53,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2024-11-28 03:01:53,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 25. [2024-11-28 03:01:53,706 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 18 states have (on average 1.1111111111111112) internal successors, (20), 18 states have internal predecessors, (20), 4 states have call successors, (4), 3 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-28 03:01:53,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 27 transitions. [2024-11-28 03:01:53,707 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 27 transitions. Word has length 25 [2024-11-28 03:01:53,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:53,707 INFO L471 AbstractCegarLoop]: Abstraction has 25 states and 27 transitions. [2024-11-28 03:01:53,708 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 4 states have call predecessors, (5), 1 states have call successors, (5) [2024-11-28 03:01:53,708 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 27 transitions. [2024-11-28 03:01:53,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2024-11-28 03:01:53,709 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:53,709 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:53,719 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-28 03:01:53,913 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:53,914 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:53,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:53,914 INFO L85 PathProgramCache]: Analyzing trace with hash -145551231, now seen corresponding path program 1 times [2024-11-28 03:01:53,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:53,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10984315] [2024-11-28 03:01:53,915 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:53,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:53,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:54,073 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:54,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:54,073 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10984315] [2024-11-28 03:01:54,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10984315] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:54,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [527842729] [2024-11-28 03:01:54,074 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:01:54,075 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:54,076 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:54,078 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:54,082 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 03:01:54,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:01:54,140 INFO L256 TraceCheckSpWp]: Trace formula consists of 85 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-28 03:01:54,141 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:54,211 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:54,211 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:01:54,295 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:54,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [527842729] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:01:54,296 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:01:54,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 5] total 8 [2024-11-28 03:01:54,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910826850] [2024-11-28 03:01:54,296 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:01:54,296 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 03:01:54,296 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:54,297 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:01:54,297 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:01:54,297 INFO L87 Difference]: Start difference. First operand 25 states and 27 transitions. Second operand has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) [2024-11-28 03:01:54,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:54,420 INFO L93 Difference]: Finished difference Result 57 states and 64 transitions. [2024-11-28 03:01:54,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 03:01:54,420 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) Word has length 28 [2024-11-28 03:01:54,421 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:54,421 INFO L225 Difference]: With dead ends: 57 [2024-11-28 03:01:54,421 INFO L226 Difference]: Without dead ends: 52 [2024-11-28 03:01:54,422 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2024-11-28 03:01:54,422 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 21 mSDsluCounter, 70 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 21 SdHoareTripleChecker+Valid, 92 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:54,423 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [21 Valid, 92 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:01:54,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2024-11-28 03:01:54,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2024-11-28 03:01:54,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 39 states have (on average 1.1282051282051282) internal successors, (44), 39 states have internal predecessors, (44), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-11-28 03:01:54,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2024-11-28 03:01:54,447 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 28 [2024-11-28 03:01:54,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:54,448 INFO L471 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2024-11-28 03:01:54,448 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) [2024-11-28 03:01:54,448 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2024-11-28 03:01:54,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2024-11-28 03:01:54,449 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:54,449 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:54,460 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-28 03:01:54,650 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:54,650 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:54,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:54,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1700883628, now seen corresponding path program 2 times [2024-11-28 03:01:54,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:54,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017909049] [2024-11-28 03:01:54,651 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:01:54,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:54,686 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 03:01:54,686 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:01:54,986 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 38 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-11-28 03:01:54,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:54,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017909049] [2024-11-28 03:01:54,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017909049] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:54,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1078961614] [2024-11-28 03:01:54,987 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:01:54,987 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:54,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:54,989 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:54,993 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 03:01:55,069 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 03:01:55,069 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:01:55,070 INFO L256 TraceCheckSpWp]: Trace formula consists of 145 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:01:55,073 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:55,196 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 62 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:55,197 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:01:55,391 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 38 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-11-28 03:01:55,391 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1078961614] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:01:55,391 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:01:55,391 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 8] total 15 [2024-11-28 03:01:55,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772042807] [2024-11-28 03:01:55,391 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:01:55,392 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-28 03:01:55,392 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:55,393 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-28 03:01:55,393 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=129, Unknown=0, NotChecked=0, Total=210 [2024-11-28 03:01:55,393 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-11-28 03:01:55,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:55,719 INFO L93 Difference]: Finished difference Result 111 states and 127 transitions. [2024-11-28 03:01:55,720 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2024-11-28 03:01:55,720 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) Word has length 55 [2024-11-28 03:01:55,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:55,722 INFO L225 Difference]: With dead ends: 111 [2024-11-28 03:01:55,722 INFO L226 Difference]: Without dead ends: 106 [2024-11-28 03:01:55,723 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=184, Invalid=322, Unknown=0, NotChecked=0, Total=506 [2024-11-28 03:01:55,724 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 63 mSDsluCounter, 114 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 136 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:55,724 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 136 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 48 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:01:55,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2024-11-28 03:01:55,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2024-11-28 03:01:55,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 81 states have (on average 1.1358024691358024) internal successors, (92), 81 states have internal predecessors, (92), 13 states have call successors, (13), 12 states have call predecessors, (13), 11 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-11-28 03:01:55,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 117 transitions. [2024-11-28 03:01:55,776 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 117 transitions. Word has length 55 [2024-11-28 03:01:55,776 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:55,776 INFO L471 AbstractCegarLoop]: Abstraction has 106 states and 117 transitions. [2024-11-28 03:01:55,776 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-11-28 03:01:55,777 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 117 transitions. [2024-11-28 03:01:55,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2024-11-28 03:01:55,784 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:55,784 INFO L218 NwaCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:55,797 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-28 03:01:55,984 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2024-11-28 03:01:55,985 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:55,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:55,985 INFO L85 PathProgramCache]: Analyzing trace with hash 592653108, now seen corresponding path program 3 times [2024-11-28 03:01:55,985 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:55,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067048053] [2024-11-28 03:01:55,986 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-28 03:01:55,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:56,118 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-28 03:01:56,118 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:01:57,438 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 245 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2024-11-28 03:01:57,438 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:01:57,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067048053] [2024-11-28 03:01:57,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067048053] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:01:57,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [686634499] [2024-11-28 03:01:57,439 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-28 03:01:57,439 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:57,439 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:01:57,444 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:01:57,448 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 03:01:57,782 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-28 03:01:57,782 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:01:57,784 INFO L256 TraceCheckSpWp]: Trace formula consists of 265 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-11-28 03:01:57,796 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:01:58,039 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 425 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:01:58,039 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:01:58,660 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 245 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2024-11-28 03:01:58,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [686634499] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:01:58,660 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:01:58,660 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 13, 14] total 33 [2024-11-28 03:01:58,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006929321] [2024-11-28 03:01:58,661 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:01:58,665 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2024-11-28 03:01:58,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:01:58,666 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2024-11-28 03:01:58,667 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=615, Unknown=0, NotChecked=0, Total=1056 [2024-11-28 03:01:58,667 INFO L87 Difference]: Start difference. First operand 106 states and 117 transitions. Second operand has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) [2024-11-28 03:01:59,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:01:59,458 INFO L93 Difference]: Finished difference Result 219 states and 253 transitions. [2024-11-28 03:01:59,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2024-11-28 03:01:59,459 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) Word has length 109 [2024-11-28 03:01:59,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:01:59,461 INFO L225 Difference]: With dead ends: 219 [2024-11-28 03:01:59,462 INFO L226 Difference]: Without dead ends: 214 [2024-11-28 03:01:59,463 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 251 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=796, Invalid=1366, Unknown=0, NotChecked=0, Total=2162 [2024-11-28 03:01:59,464 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 159 mSDsluCounter, 226 mSDsCounter, 0 mSdLazyCounter, 136 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 159 SdHoareTripleChecker+Valid, 248 SdHoareTripleChecker+Invalid, 152 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 136 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:01:59,464 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [159 Valid, 248 Invalid, 152 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 136 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 03:01:59,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2024-11-28 03:01:59,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 214. [2024-11-28 03:01:59,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214 states, 165 states have (on average 1.1393939393939394) internal successors, (188), 165 states have internal predecessors, (188), 25 states have call successors, (25), 24 states have call predecessors, (25), 23 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2024-11-28 03:01:59,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 237 transitions. [2024-11-28 03:01:59,557 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 237 transitions. Word has length 109 [2024-11-28 03:01:59,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:01:59,558 INFO L471 AbstractCegarLoop]: Abstraction has 214 states and 237 transitions. [2024-11-28 03:01:59,559 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) [2024-11-28 03:01:59,559 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 237 transitions. [2024-11-28 03:01:59,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2024-11-28 03:01:59,562 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:01:59,562 INFO L218 NwaCegarLoop]: trace histogram [23, 23, 22, 22, 22, 22, 22, 22, 22, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:01:59,567 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-28 03:01:59,766 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:01:59,766 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:01:59,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:01:59,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1359241972, now seen corresponding path program 4 times [2024-11-28 03:01:59,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:01:59,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1138764791] [2024-11-28 03:01:59,767 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-28 03:01:59,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:01:59,891 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-28 03:01:59,891 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:02:02,465 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 1199 refuted. 0 times theorem prover too weak. 928 trivial. 0 not checked. [2024-11-28 03:02:02,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:02,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1138764791] [2024-11-28 03:02:02,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1138764791] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:02:02,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1361473631] [2024-11-28 03:02:02,466 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-28 03:02:02,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:02:02,467 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:02:02,469 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:02:02,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 03:02:02,663 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-28 03:02:02,663 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:02:02,667 INFO L256 TraceCheckSpWp]: Trace formula consists of 505 conjuncts, 47 conjuncts are in the unsatisfiable core [2024-11-28 03:02:02,673 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:02:03,209 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 2123 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:02:03,209 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:02:04,913 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 1199 refuted. 0 times theorem prover too weak. 928 trivial. 0 not checked. [2024-11-28 03:02:04,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1361473631] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:02:04,914 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:02:04,914 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 25, 26] total 57 [2024-11-28 03:02:04,914 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508812569] [2024-11-28 03:02:04,914 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:02:04,915 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 57 states [2024-11-28 03:02:04,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:04,918 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2024-11-28 03:02:04,919 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1269, Invalid=1923, Unknown=0, NotChecked=0, Total=3192 [2024-11-28 03:02:04,920 INFO L87 Difference]: Start difference. First operand 214 states and 237 transitions. Second operand has 57 states, 56 states have (on average 4.892857142857143) internal successors, (274), 56 states have internal predecessors, (274), 49 states have call successors, (74), 26 states have call predecessors, (74), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) [2024-11-28 03:02:07,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:07,283 INFO L93 Difference]: Finished difference Result 435 states and 505 transitions. [2024-11-28 03:02:07,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-11-28 03:02:07,284 INFO L78 Accepts]: Start accepts. Automaton has has 57 states, 56 states have (on average 4.892857142857143) internal successors, (274), 56 states have internal predecessors, (274), 49 states have call successors, (74), 26 states have call predecessors, (74), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) Word has length 217 [2024-11-28 03:02:07,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:07,293 INFO L225 Difference]: With dead ends: 435 [2024-11-28 03:02:07,294 INFO L226 Difference]: Without dead ends: 430 [2024-11-28 03:02:07,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 507 GetRequests, 408 SyntacticMatches, 0 SemanticMatches, 99 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1578 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=3446, Invalid=6654, Unknown=0, NotChecked=0, Total=10100 [2024-11-28 03:02:07,299 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 361 mSDsluCounter, 413 mSDsCounter, 0 mSdLazyCounter, 226 mSolverCounterSat, 45 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 361 SdHoareTripleChecker+Valid, 435 SdHoareTripleChecker+Invalid, 271 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 45 IncrementalHoareTripleChecker+Valid, 226 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:07,300 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [361 Valid, 435 Invalid, 271 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [45 Valid, 226 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-11-28 03:02:07,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2024-11-28 03:02:07,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-28 03:02:07,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 333 states have (on average 1.1411411411411412) internal successors, (380), 333 states have internal predecessors, (380), 49 states have call successors, (49), 48 states have call predecessors, (49), 47 states have return successors, (48), 48 states have call predecessors, (48), 48 states have call successors, (48) [2024-11-28 03:02:07,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 477 transitions. [2024-11-28 03:02:07,403 INFO L78 Accepts]: Start accepts. Automaton has 430 states and 477 transitions. Word has length 217 [2024-11-28 03:02:07,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:07,404 INFO L471 AbstractCegarLoop]: Abstraction has 430 states and 477 transitions. [2024-11-28 03:02:07,404 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 57 states, 56 states have (on average 4.892857142857143) internal successors, (274), 56 states have internal predecessors, (274), 49 states have call successors, (74), 26 states have call predecessors, (74), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) [2024-11-28 03:02:07,404 INFO L276 IsEmpty]: Start isEmpty. Operand 430 states and 477 transitions. [2024-11-28 03:02:07,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 434 [2024-11-28 03:02:07,415 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:07,416 INFO L218 NwaCegarLoop]: trace histogram [47, 47, 46, 46, 46, 46, 46, 46, 46, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:07,427 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-11-28 03:02:07,616 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:02:07,616 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:07,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:07,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1200550516, now seen corresponding path program 5 times [2024-11-28 03:02:07,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:07,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720367343] [2024-11-28 03:02:07,617 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-28 03:02:07,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:08,026 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-28 03:02:08,026 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:02:13,781 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 5267 refuted. 0 times theorem prover too weak. 4144 trivial. 0 not checked. [2024-11-28 03:02:13,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:13,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [720367343] [2024-11-28 03:02:13,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [720367343] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:02:13,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [61415094] [2024-11-28 03:02:13,782 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-28 03:02:13,782 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:02:13,782 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:02:13,784 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:02:13,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 03:02:16,697 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-28 03:02:16,697 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:02:16,705 INFO L256 TraceCheckSpWp]: Trace formula consists of 985 conjuncts, 95 conjuncts are in the unsatisfiable core [2024-11-28 03:02:16,714 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:02:17,417 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 9407 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:02:17,417 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:02:21,522 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 5267 refuted. 0 times theorem prover too weak. 4144 trivial. 0 not checked. [2024-11-28 03:02:21,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [61415094] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:02:21,522 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:02:21,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 49, 50] total 99 [2024-11-28 03:02:21,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058841409] [2024-11-28 03:02:21,523 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:02:21,525 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 99 states [2024-11-28 03:02:21,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:02:21,529 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2024-11-28 03:02:21,531 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=4658, Invalid=5044, Unknown=0, NotChecked=0, Total=9702 [2024-11-28 03:02:21,532 INFO L87 Difference]: Start difference. First operand 430 states and 477 transitions. Second operand has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) [2024-11-28 03:02:28,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:02:28,904 INFO L93 Difference]: Finished difference Result 867 states and 1009 transitions. [2024-11-28 03:02:28,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2024-11-28 03:02:28,905 INFO L78 Accepts]: Start accepts. Automaton has has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) Word has length 433 [2024-11-28 03:02:28,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:02:28,910 INFO L225 Difference]: With dead ends: 867 [2024-11-28 03:02:28,911 INFO L226 Difference]: Without dead ends: 862 [2024-11-28 03:02:28,917 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1007 GetRequests, 818 SyntacticMatches, 0 SemanticMatches, 189 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5716 ImplicationChecksByTransitivity, 9.0s TimeCoverageRelationStatistics Valid=13540, Invalid=22750, Unknown=0, NotChecked=0, Total=36290 [2024-11-28 03:02:28,918 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 849 mSDsluCounter, 612 mSDsCounter, 0 mSdLazyCounter, 391 mSolverCounterSat, 112 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 849 SdHoareTripleChecker+Valid, 634 SdHoareTripleChecker+Invalid, 503 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 112 IncrementalHoareTripleChecker+Valid, 391 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2024-11-28 03:02:28,918 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [849 Valid, 634 Invalid, 503 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [112 Valid, 391 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2024-11-28 03:02:28,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 862 states. [2024-11-28 03:02:29,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 862 to 862. [2024-11-28 03:02:29,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 862 states, 669 states have (on average 1.1420029895366217) internal successors, (764), 669 states have internal predecessors, (764), 97 states have call successors, (97), 96 states have call predecessors, (97), 95 states have return successors, (96), 96 states have call predecessors, (96), 96 states have call successors, (96) [2024-11-28 03:02:29,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 862 states to 862 states and 957 transitions. [2024-11-28 03:02:29,049 INFO L78 Accepts]: Start accepts. Automaton has 862 states and 957 transitions. Word has length 433 [2024-11-28 03:02:29,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:02:29,050 INFO L471 AbstractCegarLoop]: Abstraction has 862 states and 957 transitions. [2024-11-28 03:02:29,051 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) [2024-11-28 03:02:29,051 INFO L276 IsEmpty]: Start isEmpty. Operand 862 states and 957 transitions. [2024-11-28 03:02:29,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 866 [2024-11-28 03:02:29,079 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:02:29,079 INFO L218 NwaCegarLoop]: trace histogram [95, 95, 94, 94, 94, 94, 94, 94, 94, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:02:29,090 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-28 03:02:29,280 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:02:29,280 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:02:29,280 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:02:29,281 INFO L85 PathProgramCache]: Analyzing trace with hash 495227252, now seen corresponding path program 6 times [2024-11-28 03:02:29,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:02:29,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079205267] [2024-11-28 03:02:29,281 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-28 03:02:29,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:02:31,339 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-28 03:02:31,339 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:02:58,393 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 22043 refuted. 0 times theorem prover too weak. 17488 trivial. 0 not checked. [2024-11-28 03:02:58,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:02:58,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079205267] [2024-11-28 03:02:58,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079205267] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:02:58,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1417513021] [2024-11-28 03:02:58,394 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-28 03:02:58,394 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:02:58,395 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:02:58,399 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:02:58,400 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 03:03:05,372 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-28 03:03:05,372 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:03:05,428 INFO L256 TraceCheckSpWp]: Trace formula consists of 1945 conjuncts, 191 conjuncts are in the unsatisfiable core [2024-11-28 03:03:05,447 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:03:06,930 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 39527 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:03:06,931 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:03:14,587 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 22043 refuted. 0 times theorem prover too weak. 17488 trivial. 0 not checked. [2024-11-28 03:03:14,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1417513021] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:03:14,588 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:03:14,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [133, 97, 98] total 139 [2024-11-28 03:03:14,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125543789] [2024-11-28 03:03:14,589 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:03:14,592 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 139 states [2024-11-28 03:03:14,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:03:14,597 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 139 interpolants. [2024-11-28 03:03:14,600 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6879, Invalid=12303, Unknown=0, NotChecked=0, Total=19182 [2024-11-28 03:03:14,602 INFO L87 Difference]: Start difference. First operand 862 states and 957 transitions. Second operand has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) [2024-11-28 03:03:20,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:03:20,138 INFO L93 Difference]: Finished difference Result 921 states and 1027 transitions. [2024-11-28 03:03:20,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2024-11-28 03:03:20,140 INFO L78 Accepts]: Start accepts. Automaton has has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) Word has length 865 [2024-11-28 03:03:20,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:03:20,148 INFO L225 Difference]: With dead ends: 921 [2024-11-28 03:03:20,149 INFO L226 Difference]: Without dead ends: 916 [2024-11-28 03:03:20,155 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1925 GetRequests, 1634 SyntacticMatches, 90 SemanticMatches, 201 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10247 ImplicationChecksByTransitivity, 16.5s TimeCoverageRelationStatistics Valid=15349, Invalid=25657, Unknown=0, NotChecked=0, Total=41006 [2024-11-28 03:03:20,156 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 460 mSDsluCounter, 660 mSDsCounter, 0 mSdLazyCounter, 431 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 460 SdHoareTripleChecker+Valid, 682 SdHoareTripleChecker+Invalid, 437 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 431 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2024-11-28 03:03:20,157 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [460 Valid, 682 Invalid, 437 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 431 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2024-11-28 03:03:20,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states. [2024-11-28 03:03:20,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 916. [2024-11-28 03:03:20,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 916 states, 711 states have (on average 1.1420534458509142) internal successors, (812), 711 states have internal predecessors, (812), 103 states have call successors, (103), 102 states have call predecessors, (103), 101 states have return successors, (102), 102 states have call predecessors, (102), 102 states have call successors, (102) [2024-11-28 03:03:20,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 916 states to 916 states and 1017 transitions. [2024-11-28 03:03:20,300 INFO L78 Accepts]: Start accepts. Automaton has 916 states and 1017 transitions. Word has length 865 [2024-11-28 03:03:20,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:03:20,303 INFO L471 AbstractCegarLoop]: Abstraction has 916 states and 1017 transitions. [2024-11-28 03:03:20,304 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) [2024-11-28 03:03:20,304 INFO L276 IsEmpty]: Start isEmpty. Operand 916 states and 1017 transitions. [2024-11-28 03:03:20,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 920 [2024-11-28 03:03:20,344 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:03:20,345 INFO L218 NwaCegarLoop]: trace histogram [101, 101, 100, 100, 100, 100, 100, 100, 100, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:03:20,359 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-28 03:03:20,545 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:03:20,546 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:03:20,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:03:20,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1067012436, now seen corresponding path program 7 times [2024-11-28 03:03:20,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:03:20,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579586322] [2024-11-28 03:03:20,547 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-28 03:03:20,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:03:21,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2024-11-28 03:03:21,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [78121403] [2024-11-28 03:03:21,553 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-28 03:03:21,553 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:03:21,553 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:03:21,556 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:03:21,559 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 03:03:22,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:03:22,291 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:03:22,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:03:23,157 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-28 03:03:23,159 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-28 03:03:23,160 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-28 03:03:23,184 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-28 03:03:23,363 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:03:23,366 INFO L422 BasicCegarLoop]: Path program histogram: [7, 1, 1, 1, 1] [2024-11-28 03:03:23,654 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-28 03:03:23,658 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 03:03:23 BoogieIcfgContainer [2024-11-28 03:03:23,658 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-28 03:03:23,659 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-28 03:03:23,659 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-28 03:03:23,659 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-28 03:03:23,660 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:01:49" (3/4) ... [2024-11-28 03:03:23,661 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-28 03:03:23,988 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 610. [2024-11-28 03:03:24,281 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/witness.graphml [2024-11-28 03:03:24,282 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/witness.yml [2024-11-28 03:03:24,283 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-28 03:03:24,284 INFO L158 Benchmark]: Toolchain (without parser) took 95199.43ms. Allocated memory was 117.4MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 85.7MB in the beginning and 1.3GB in the end (delta: -1.2GB). Peak memory consumption was 892.0MB. Max. memory is 16.1GB. [2024-11-28 03:03:24,284 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory was 104.0MB in the beginning and 103.9MB in the end (delta: 168.4kB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:03:24,284 INFO L158 Benchmark]: CACSL2BoogieTranslator took 345.76ms. Allocated memory is still 117.4MB. Free memory was 85.4MB in the beginning and 74.4MB in the end (delta: 11.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:03:24,285 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.25ms. Allocated memory is still 117.4MB. Free memory was 74.4MB in the beginning and 73.3MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:03:24,285 INFO L158 Benchmark]: Boogie Preprocessor took 47.89ms. Allocated memory is still 117.4MB. Free memory was 73.3MB in the beginning and 71.9MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:03:24,285 INFO L158 Benchmark]: RCFGBuilder took 382.26ms. Allocated memory is still 117.4MB. Free memory was 71.9MB in the beginning and 61.4MB in the end (delta: 10.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-28 03:03:24,286 INFO L158 Benchmark]: TraceAbstraction took 93747.01ms. Allocated memory was 117.4MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 60.8MB in the beginning and 544.9MB in the end (delta: -484.2MB). Peak memory consumption was 839.3MB. Max. memory is 16.1GB. [2024-11-28 03:03:24,286 INFO L158 Benchmark]: Witness Printer took 623.92ms. Allocated memory is still 1.4GB. Free memory was 544.9MB in the beginning and 1.3GB in the end (delta: -786.2MB). Peak memory consumption was 27.5MB. Max. memory is 16.1GB. [2024-11-28 03:03:24,288 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 167.8MB. Free memory was 104.0MB in the beginning and 103.9MB in the end (delta: 168.4kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 345.76ms. Allocated memory is still 117.4MB. Free memory was 85.4MB in the beginning and 74.4MB in the end (delta: 11.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.25ms. Allocated memory is still 117.4MB. Free memory was 74.4MB in the beginning and 73.3MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 47.89ms. Allocated memory is still 117.4MB. Free memory was 73.3MB in the beginning and 71.9MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 382.26ms. Allocated memory is still 117.4MB. Free memory was 71.9MB in the beginning and 61.4MB in the end (delta: 10.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * TraceAbstraction took 93747.01ms. Allocated memory was 117.4MB in the beginning and 1.4GB in the end (delta: 1.3GB). Free memory was 60.8MB in the beginning and 544.9MB in the end (delta: -484.2MB). Peak memory consumption was 839.3MB. Max. memory is 16.1GB. * Witness Printer took 623.92ms. Allocated memory is still 1.4GB. Free memory was 544.9MB in the beginning and 1.3GB in the end (delta: -786.2MB). Peak memory consumption was 27.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 14]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L19] int counter = 0; VAL [counter=0] [L21] int A, R; [L22] long long u, v, r; [L23] A = __VERIFIER_nondet_int() [L24] R = __VERIFIER_nondet_int() [L26] CALL assume_abort_if_not(((long long) R - 1) * ((long long) R - 1) < A) VAL [\old(cond)=1, counter=0] [L9] COND FALSE !(!cond) VAL [\old(cond)=1, counter=0] [L26] RET assume_abort_if_not(((long long) R - 1) * ((long long) R - 1) < A) VAL [A=25010003, R=5002, counter=0] [L28] CALL assume_abort_if_not(A % 2 == 1) VAL [\old(cond)=1, counter=0] [L9] COND FALSE !(!cond) VAL [\old(cond)=1, counter=0] [L28] RET assume_abort_if_not(A % 2 == 1) VAL [A=25010003, R=5002, counter=0] [L30] u = ((long long) 2 * R) + 1 [L31] v = 1 [L32] r = ((long long) R * R) - A VAL [A=25010003, counter=0, r=10001, u=10005, v=1] [L34] EXPR counter++ VAL [A=25010003, counter=1, r=10001, u=10005, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=1] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=1] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=1, r=10001, u=10005, v=1] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=1, r=10001, u=10005, v=1] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=1, r=10000, u=10005, v=3] [L34] EXPR counter++ VAL [A=25010003, counter=2, r=10000, u=10005, v=3] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=2] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=2] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=2, r=10000, u=10005, v=3] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=2, r=10000, u=10005, v=3] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=2, r=9997, u=10005, v=5] [L34] EXPR counter++ VAL [A=25010003, counter=3, r=9997, u=10005, v=5] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=3] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=3] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=3, r=9997, u=10005, v=5] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=3, r=9997, u=10005, v=5] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=3, r=9992, u=10005, v=7] [L34] EXPR counter++ VAL [A=25010003, counter=4, r=9992, u=10005, v=7] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=4] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=4] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=4, r=9992, u=10005, v=7] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=4, r=9992, u=10005, v=7] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=4, r=9985, u=10005, v=9] [L34] EXPR counter++ VAL [A=25010003, counter=5, r=9985, u=10005, v=9] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=5] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=5] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=5, r=9985, u=10005, v=9] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=5, r=9985, u=10005, v=9] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=5, r=9976, u=10005, v=11] [L34] EXPR counter++ VAL [A=25010003, counter=6, r=9976, u=10005, v=11] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=6] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=6] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=6, r=9976, u=10005, v=11] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=6, r=9976, u=10005, v=11] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=6, r=9965, u=10005, v=13] [L34] EXPR counter++ VAL [A=25010003, counter=7, r=9965, u=10005, v=13] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=7] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=7] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=7, r=9965, u=10005, v=13] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=7, r=9965, u=10005, v=13] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=7, r=9952, u=10005, v=15] [L34] EXPR counter++ VAL [A=25010003, counter=8, r=9952, u=10005, v=15] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=8] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=8] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=8, r=9952, u=10005, v=15] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=8, r=9952, u=10005, v=15] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=8, r=9937, u=10005, v=17] [L34] EXPR counter++ VAL [A=25010003, counter=9, r=9937, u=10005, v=17] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=9] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=9] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=9, r=9937, u=10005, v=17] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=9, r=9937, u=10005, v=17] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=9, r=9920, u=10005, v=19] [L34] EXPR counter++ VAL [A=25010003, counter=10, r=9920, u=10005, v=19] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=10] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=10] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=10, r=9920, u=10005, v=19] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=10, r=9920, u=10005, v=19] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=10, r=9901, u=10005, v=21] [L34] EXPR counter++ VAL [A=25010003, counter=11, r=9901, u=10005, v=21] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=11] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=11] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=11, r=9901, u=10005, v=21] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=11, r=9901, u=10005, v=21] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=11, r=9880, u=10005, v=23] [L34] EXPR counter++ VAL [A=25010003, counter=12, r=9880, u=10005, v=23] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=12] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=12] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=12, r=9880, u=10005, v=23] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=12, r=9880, u=10005, v=23] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=12, r=9857, u=10005, v=25] [L34] EXPR counter++ VAL [A=25010003, counter=13, r=9857, u=10005, v=25] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=13] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=13] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=13, r=9857, u=10005, v=25] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=13, r=9857, u=10005, v=25] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=13, r=9832, u=10005, v=27] [L34] EXPR counter++ VAL [A=25010003, counter=14, r=9832, u=10005, v=27] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=14] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=14] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=14, r=9832, u=10005, v=27] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=14, r=9832, u=10005, v=27] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=14, r=9805, u=10005, v=29] [L34] EXPR counter++ VAL [A=25010003, counter=15, r=9805, u=10005, v=29] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=15] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=15] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=15, r=9805, u=10005, v=29] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=15, r=9805, u=10005, v=29] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=15, r=9776, u=10005, v=31] [L34] EXPR counter++ VAL [A=25010003, counter=16, r=9776, u=10005, v=31] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=16] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=16] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=16, r=9776, u=10005, v=31] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=16, r=9776, u=10005, v=31] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=16, r=9745, u=10005, v=33] [L34] EXPR counter++ VAL [A=25010003, counter=17, r=9745, u=10005, v=33] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=17] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=17] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=17, r=9745, u=10005, v=33] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=17, r=9745, u=10005, v=33] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=17, r=9712, u=10005, v=35] [L34] EXPR counter++ VAL [A=25010003, counter=18, r=9712, u=10005, v=35] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=18] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=18] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=18, r=9712, u=10005, v=35] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=18, r=9712, u=10005, v=35] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=18, r=9677, u=10005, v=37] [L34] EXPR counter++ VAL [A=25010003, counter=19, r=9677, u=10005, v=37] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=19] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=19] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=19, r=9677, u=10005, v=37] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=19, r=9677, u=10005, v=37] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=19, r=9640, u=10005, v=39] [L34] EXPR counter++ VAL [A=25010003, counter=20, r=9640, u=10005, v=39] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=20] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=20] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=20, r=9640, u=10005, v=39] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=20, r=9640, u=10005, v=39] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=20, r=9601, u=10005, v=41] [L34] EXPR counter++ VAL [A=25010003, counter=21, r=9601, u=10005, v=41] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=21] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=21] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=21, r=9601, u=10005, v=41] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=21, r=9601, u=10005, v=41] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=21, r=9560, u=10005, v=43] [L34] EXPR counter++ VAL [A=25010003, counter=22, r=9560, u=10005, v=43] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=22] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=22] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=22, r=9560, u=10005, v=43] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=22, r=9560, u=10005, v=43] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=22, r=9517, u=10005, v=45] [L34] EXPR counter++ VAL [A=25010003, counter=23, r=9517, u=10005, v=45] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=23] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=23] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=23, r=9517, u=10005, v=45] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=23, r=9517, u=10005, v=45] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=23, r=9472, u=10005, v=47] [L34] EXPR counter++ VAL [A=25010003, counter=24, r=9472, u=10005, v=47] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=24] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=24] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=24, r=9472, u=10005, v=47] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=24, r=9472, u=10005, v=47] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=24, r=9425, u=10005, v=49] [L34] EXPR counter++ VAL [A=25010003, counter=25, r=9425, u=10005, v=49] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=25] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=25] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=25, r=9425, u=10005, v=49] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=25, r=9425, u=10005, v=49] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=25, r=9376, u=10005, v=51] [L34] EXPR counter++ VAL [A=25010003, counter=26, r=9376, u=10005, v=51] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=26] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=26] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=26, r=9376, u=10005, v=51] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=26, r=9376, u=10005, v=51] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=26, r=9325, u=10005, v=53] [L34] EXPR counter++ VAL [A=25010003, counter=27, r=9325, u=10005, v=53] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=27] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=27] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=27, r=9325, u=10005, v=53] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=27, r=9325, u=10005, v=53] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=27, r=9272, u=10005, v=55] [L34] EXPR counter++ VAL [A=25010003, counter=28, r=9272, u=10005, v=55] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=28] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=28] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=28, r=9272, u=10005, v=55] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=28, r=9272, u=10005, v=55] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=28, r=9217, u=10005, v=57] [L34] EXPR counter++ VAL [A=25010003, counter=29, r=9217, u=10005, v=57] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=29] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=29] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=29, r=9217, u=10005, v=57] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=29, r=9217, u=10005, v=57] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=29, r=9160, u=10005, v=59] [L34] EXPR counter++ VAL [A=25010003, counter=30, r=9160, u=10005, v=59] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=30] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=30] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=30, r=9160, u=10005, v=59] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=30, r=9160, u=10005, v=59] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=30, r=9101, u=10005, v=61] [L34] EXPR counter++ VAL [A=25010003, counter=31, r=9101, u=10005, v=61] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=31] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=31] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=31, r=9101, u=10005, v=61] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=31, r=9101, u=10005, v=61] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=31, r=9040, u=10005, v=63] [L34] EXPR counter++ VAL [A=25010003, counter=32, r=9040, u=10005, v=63] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=32] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=32] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=32, r=9040, u=10005, v=63] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=32, r=9040, u=10005, v=63] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=32, r=8977, u=10005, v=65] [L34] EXPR counter++ VAL [A=25010003, counter=33, r=8977, u=10005, v=65] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=33] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=33] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=33, r=8977, u=10005, v=65] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=33, r=8977, u=10005, v=65] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=33, r=8912, u=10005, v=67] [L34] EXPR counter++ VAL [A=25010003, counter=34, r=8912, u=10005, v=67] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=34] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=34] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=34, r=8912, u=10005, v=67] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=34, r=8912, u=10005, v=67] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=34, r=8845, u=10005, v=69] [L34] EXPR counter++ VAL [A=25010003, counter=35, r=8845, u=10005, v=69] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=35] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=35] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=35, r=8845, u=10005, v=69] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=35, r=8845, u=10005, v=69] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=35, r=8776, u=10005, v=71] [L34] EXPR counter++ VAL [A=25010003, counter=36, r=8776, u=10005, v=71] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=36] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=36] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=36, r=8776, u=10005, v=71] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=36, r=8776, u=10005, v=71] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=36, r=8705, u=10005, v=73] [L34] EXPR counter++ VAL [A=25010003, counter=37, r=8705, u=10005, v=73] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=37] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=37] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=37, r=8705, u=10005, v=73] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=37, r=8705, u=10005, v=73] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=37, r=8632, u=10005, v=75] [L34] EXPR counter++ VAL [A=25010003, counter=38, r=8632, u=10005, v=75] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=38] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=38] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=38, r=8632, u=10005, v=75] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=38, r=8632, u=10005, v=75] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=38, r=8557, u=10005, v=77] [L34] EXPR counter++ VAL [A=25010003, counter=39, r=8557, u=10005, v=77] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=39] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=39] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=39, r=8557, u=10005, v=77] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=39, r=8557, u=10005, v=77] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=39, r=8480, u=10005, v=79] [L34] EXPR counter++ VAL [A=25010003, counter=40, r=8480, u=10005, v=79] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=40] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=40] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=40, r=8480, u=10005, v=79] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=40, r=8480, u=10005, v=79] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=40, r=8401, u=10005, v=81] [L34] EXPR counter++ VAL [A=25010003, counter=41, r=8401, u=10005, v=81] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=41] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=41] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=41, r=8401, u=10005, v=81] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=41, r=8401, u=10005, v=81] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=41, r=8320, u=10005, v=83] [L34] EXPR counter++ VAL [A=25010003, counter=42, r=8320, u=10005, v=83] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=42] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=42] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=42, r=8320, u=10005, v=83] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=42, r=8320, u=10005, v=83] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=42, r=8237, u=10005, v=85] [L34] EXPR counter++ VAL [A=25010003, counter=43, r=8237, u=10005, v=85] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=43] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=43] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=43, r=8237, u=10005, v=85] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=43, r=8237, u=10005, v=85] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=43, r=8152, u=10005, v=87] [L34] EXPR counter++ VAL [A=25010003, counter=44, r=8152, u=10005, v=87] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=44] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=44] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=44, r=8152, u=10005, v=87] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=44, r=8152, u=10005, v=87] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=44, r=8065, u=10005, v=89] [L34] EXPR counter++ VAL [A=25010003, counter=45, r=8065, u=10005, v=89] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=45] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=45] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=45, r=8065, u=10005, v=89] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=45, r=8065, u=10005, v=89] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=45, r=7976, u=10005, v=91] [L34] EXPR counter++ VAL [A=25010003, counter=46, r=7976, u=10005, v=91] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=46] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=46] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=46, r=7976, u=10005, v=91] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=46, r=7976, u=10005, v=91] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=46, r=7885, u=10005, v=93] [L34] EXPR counter++ VAL [A=25010003, counter=47, r=7885, u=10005, v=93] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=47] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=47] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=47, r=7885, u=10005, v=93] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=47, r=7885, u=10005, v=93] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=47, r=7792, u=10005, v=95] [L34] EXPR counter++ VAL [A=25010003, counter=48, r=7792, u=10005, v=95] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=48] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=48] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=48, r=7792, u=10005, v=95] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=48, r=7792, u=10005, v=95] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=48, r=7697, u=10005, v=97] [L34] EXPR counter++ VAL [A=25010003, counter=49, r=7697, u=10005, v=97] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=49] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=49] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=49, r=7697, u=10005, v=97] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=49, r=7697, u=10005, v=97] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=49, r=7600, u=10005, v=99] [L34] EXPR counter++ VAL [A=25010003, counter=50, r=7600, u=10005, v=99] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=50] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=50] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=50, r=7600, u=10005, v=99] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=50, r=7600, u=10005, v=99] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=50, r=7501, u=10005, v=101] [L34] EXPR counter++ VAL [A=25010003, counter=51, r=7501, u=10005, v=101] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=51] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=51] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=51, r=7501, u=10005, v=101] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=51, r=7501, u=10005, v=101] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=51, r=7400, u=10005, v=103] [L34] EXPR counter++ VAL [A=25010003, counter=52, r=7400, u=10005, v=103] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=52] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=52] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=52, r=7400, u=10005, v=103] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=52, r=7400, u=10005, v=103] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=52, r=7297, u=10005, v=105] [L34] EXPR counter++ VAL [A=25010003, counter=53, r=7297, u=10005, v=105] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=53] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=53] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=53, r=7297, u=10005, v=105] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=53, r=7297, u=10005, v=105] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=53, r=7192, u=10005, v=107] [L34] EXPR counter++ VAL [A=25010003, counter=54, r=7192, u=10005, v=107] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=54] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=54] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=54, r=7192, u=10005, v=107] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=54, r=7192, u=10005, v=107] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=54, r=7085, u=10005, v=109] [L34] EXPR counter++ VAL [A=25010003, counter=55, r=7085, u=10005, v=109] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=55] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=55] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=55, r=7085, u=10005, v=109] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=55, r=7085, u=10005, v=109] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=55, r=6976, u=10005, v=111] [L34] EXPR counter++ VAL [A=25010003, counter=56, r=6976, u=10005, v=111] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=56] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=56] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=56, r=6976, u=10005, v=111] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=56, r=6976, u=10005, v=111] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=56, r=6865, u=10005, v=113] [L34] EXPR counter++ VAL [A=25010003, counter=57, r=6865, u=10005, v=113] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=57] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=57] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=57, r=6865, u=10005, v=113] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=57, r=6865, u=10005, v=113] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=57, r=6752, u=10005, v=115] [L34] EXPR counter++ VAL [A=25010003, counter=58, r=6752, u=10005, v=115] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=58] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=58] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=58, r=6752, u=10005, v=115] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=58, r=6752, u=10005, v=115] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=58, r=6637, u=10005, v=117] [L34] EXPR counter++ VAL [A=25010003, counter=59, r=6637, u=10005, v=117] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=59] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=59] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=59, r=6637, u=10005, v=117] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=59, r=6637, u=10005, v=117] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=59, r=6520, u=10005, v=119] [L34] EXPR counter++ VAL [A=25010003, counter=60, r=6520, u=10005, v=119] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=60] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=60] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=60, r=6520, u=10005, v=119] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=60, r=6520, u=10005, v=119] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=60, r=6401, u=10005, v=121] [L34] EXPR counter++ VAL [A=25010003, counter=61, r=6401, u=10005, v=121] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=61] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=61] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=61, r=6401, u=10005, v=121] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=61, r=6401, u=10005, v=121] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=61, r=6280, u=10005, v=123] [L34] EXPR counter++ VAL [A=25010003, counter=62, r=6280, u=10005, v=123] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=62] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=62] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=62, r=6280, u=10005, v=123] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=62, r=6280, u=10005, v=123] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=62, r=6157, u=10005, v=125] [L34] EXPR counter++ VAL [A=25010003, counter=63, r=6157, u=10005, v=125] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=63] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=63] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=63, r=6157, u=10005, v=125] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=63, r=6157, u=10005, v=125] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=63, r=6032, u=10005, v=127] [L34] EXPR counter++ VAL [A=25010003, counter=64, r=6032, u=10005, v=127] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=64] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=64] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=64, r=6032, u=10005, v=127] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=64, r=6032, u=10005, v=127] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=64, r=5905, u=10005, v=129] [L34] EXPR counter++ VAL [A=25010003, counter=65, r=5905, u=10005, v=129] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=65] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=65] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=65, r=5905, u=10005, v=129] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=65, r=5905, u=10005, v=129] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=65, r=5776, u=10005, v=131] [L34] EXPR counter++ VAL [A=25010003, counter=66, r=5776, u=10005, v=131] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=66] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=66] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=66, r=5776, u=10005, v=131] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=66, r=5776, u=10005, v=131] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=66, r=5645, u=10005, v=133] [L34] EXPR counter++ VAL [A=25010003, counter=67, r=5645, u=10005, v=133] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=67] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=67] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=67, r=5645, u=10005, v=133] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=67, r=5645, u=10005, v=133] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=67, r=5512, u=10005, v=135] [L34] EXPR counter++ VAL [A=25010003, counter=68, r=5512, u=10005, v=135] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=68] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=68] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=68, r=5512, u=10005, v=135] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=68, r=5512, u=10005, v=135] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=68, r=5377, u=10005, v=137] [L34] EXPR counter++ VAL [A=25010003, counter=69, r=5377, u=10005, v=137] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=69] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=69] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=69, r=5377, u=10005, v=137] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=69, r=5377, u=10005, v=137] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=69, r=5240, u=10005, v=139] [L34] EXPR counter++ VAL [A=25010003, counter=70, r=5240, u=10005, v=139] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=70] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=70] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=70, r=5240, u=10005, v=139] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=70, r=5240, u=10005, v=139] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=70, r=5101, u=10005, v=141] [L34] EXPR counter++ VAL [A=25010003, counter=71, r=5101, u=10005, v=141] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=71] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=71] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=71, r=5101, u=10005, v=141] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=71, r=5101, u=10005, v=141] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=71, r=4960, u=10005, v=143] [L34] EXPR counter++ VAL [A=25010003, counter=72, r=4960, u=10005, v=143] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=72] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=72] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=72, r=4960, u=10005, v=143] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=72, r=4960, u=10005, v=143] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=72, r=4817, u=10005, v=145] [L34] EXPR counter++ VAL [A=25010003, counter=73, r=4817, u=10005, v=145] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=73] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=73] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=73, r=4817, u=10005, v=145] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=73, r=4817, u=10005, v=145] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=73, r=4672, u=10005, v=147] [L34] EXPR counter++ VAL [A=25010003, counter=74, r=4672, u=10005, v=147] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=74] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=74] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=74, r=4672, u=10005, v=147] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=74, r=4672, u=10005, v=147] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=74, r=4525, u=10005, v=149] [L34] EXPR counter++ VAL [A=25010003, counter=75, r=4525, u=10005, v=149] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=75] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=75] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=75, r=4525, u=10005, v=149] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=75, r=4525, u=10005, v=149] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=75, r=4376, u=10005, v=151] [L34] EXPR counter++ VAL [A=25010003, counter=76, r=4376, u=10005, v=151] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=76] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=76] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=76, r=4376, u=10005, v=151] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=76, r=4376, u=10005, v=151] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=76, r=4225, u=10005, v=153] [L34] EXPR counter++ VAL [A=25010003, counter=77, r=4225, u=10005, v=153] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=77] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=77] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=77, r=4225, u=10005, v=153] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=77, r=4225, u=10005, v=153] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=77, r=4072, u=10005, v=155] [L34] EXPR counter++ VAL [A=25010003, counter=78, r=4072, u=10005, v=155] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=78] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=78] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=78, r=4072, u=10005, v=155] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=78, r=4072, u=10005, v=155] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=78, r=3917, u=10005, v=157] [L34] EXPR counter++ VAL [A=25010003, counter=79, r=3917, u=10005, v=157] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=79] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=79] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=79, r=3917, u=10005, v=157] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=79, r=3917, u=10005, v=157] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=79, r=3760, u=10005, v=159] [L34] EXPR counter++ VAL [A=25010003, counter=80, r=3760, u=10005, v=159] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=80] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=80] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=80, r=3760, u=10005, v=159] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=80, r=3760, u=10005, v=159] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=80, r=3601, u=10005, v=161] [L34] EXPR counter++ VAL [A=25010003, counter=81, r=3601, u=10005, v=161] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=81] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=81] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=81, r=3601, u=10005, v=161] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=81, r=3601, u=10005, v=161] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=81, r=3440, u=10005, v=163] [L34] EXPR counter++ VAL [A=25010003, counter=82, r=3440, u=10005, v=163] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=82] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=82] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=82, r=3440, u=10005, v=163] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=82, r=3440, u=10005, v=163] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=82, r=3277, u=10005, v=165] [L34] EXPR counter++ VAL [A=25010003, counter=83, r=3277, u=10005, v=165] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=83] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=83] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=83, r=3277, u=10005, v=165] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=83, r=3277, u=10005, v=165] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=83, r=3112, u=10005, v=167] [L34] EXPR counter++ VAL [A=25010003, counter=84, r=3112, u=10005, v=167] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=84] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=84] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=84, r=3112, u=10005, v=167] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=84, r=3112, u=10005, v=167] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=84, r=2945, u=10005, v=169] [L34] EXPR counter++ VAL [A=25010003, counter=85, r=2945, u=10005, v=169] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=85] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=85] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=85, r=2945, u=10005, v=169] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=85, r=2945, u=10005, v=169] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=85, r=2776, u=10005, v=171] [L34] EXPR counter++ VAL [A=25010003, counter=86, r=2776, u=10005, v=171] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=86] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=86] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=86, r=2776, u=10005, v=171] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=86, r=2776, u=10005, v=171] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=86, r=2605, u=10005, v=173] [L34] EXPR counter++ VAL [A=25010003, counter=87, r=2605, u=10005, v=173] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=87] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=87] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=87, r=2605, u=10005, v=173] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=87, r=2605, u=10005, v=173] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=87, r=2432, u=10005, v=175] [L34] EXPR counter++ VAL [A=25010003, counter=88, r=2432, u=10005, v=175] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=88] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=88] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=88, r=2432, u=10005, v=175] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=88, r=2432, u=10005, v=175] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=88, r=2257, u=10005, v=177] [L34] EXPR counter++ VAL [A=25010003, counter=89, r=2257, u=10005, v=177] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=89] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=89] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=89, r=2257, u=10005, v=177] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=89, r=2257, u=10005, v=177] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=89, r=2080, u=10005, v=179] [L34] EXPR counter++ VAL [A=25010003, counter=90, r=2080, u=10005, v=179] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=90] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=90] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=90, r=2080, u=10005, v=179] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=90, r=2080, u=10005, v=179] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=90, r=1901, u=10005, v=181] [L34] EXPR counter++ VAL [A=25010003, counter=91, r=1901, u=10005, v=181] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=91] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=91] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=91, r=1901, u=10005, v=181] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=91, r=1901, u=10005, v=181] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=91, r=1720, u=10005, v=183] [L34] EXPR counter++ VAL [A=25010003, counter=92, r=1720, u=10005, v=183] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=92] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=92] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=92, r=1720, u=10005, v=183] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=92, r=1720, u=10005, v=183] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=92, r=1537, u=10005, v=185] [L34] EXPR counter++ VAL [A=25010003, counter=93, r=1537, u=10005, v=185] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=93] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=93] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=93, r=1537, u=10005, v=185] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=93, r=1537, u=10005, v=185] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=93, r=1352, u=10005, v=187] [L34] EXPR counter++ VAL [A=25010003, counter=94, r=1352, u=10005, v=187] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=94] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=94] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=94, r=1352, u=10005, v=187] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=94, r=1352, u=10005, v=187] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=94, r=1165, u=10005, v=189] [L34] EXPR counter++ VAL [A=25010003, counter=95, r=1165, u=10005, v=189] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=95] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=95] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=95, r=1165, u=10005, v=189] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=95, r=1165, u=10005, v=189] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=95, r=976, u=10005, v=191] [L34] EXPR counter++ VAL [A=25010003, counter=96, r=976, u=10005, v=191] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=96] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=96] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=96, r=976, u=10005, v=191] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=96, r=976, u=10005, v=191] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=96, r=785, u=10005, v=193] [L34] EXPR counter++ VAL [A=25010003, counter=97, r=785, u=10005, v=193] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=97] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=97] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=97, r=785, u=10005, v=193] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=97, r=785, u=10005, v=193] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=97, r=592, u=10005, v=195] [L34] EXPR counter++ VAL [A=25010003, counter=98, r=592, u=10005, v=195] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=98] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=98] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=98, r=592, u=10005, v=195] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=98, r=592, u=10005, v=195] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=98, r=397, u=10005, v=197] [L34] EXPR counter++ VAL [A=25010003, counter=99, r=397, u=10005, v=197] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=99] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=99] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=99, r=397, u=10005, v=197] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=99, r=397, u=10005, v=197] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=99, r=200, u=10005, v=199] [L34] EXPR counter++ VAL [A=25010003, counter=100, r=200, u=10005, v=199] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=100] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=100] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=25010003, counter=100, r=200, u=10005, v=199] [L36] COND FALSE !(!(r != 0)) VAL [A=25010003, counter=100, r=200, u=10005, v=199] [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=25010003, counter=100, r=1, u=10005, v=201] [L34] EXPR counter++ VAL [A=25010003, counter=101, r=1, u=10005, v=201] [L34] COND FALSE !(counter++<100) [L48] CALL __VERIFIER_assert(((long long) 4*A) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=0, counter=101] [L12] COND TRUE !(cond) VAL [\old(cond)=0, counter=101] [L14] reach_error() VAL [\old(cond)=0, counter=101] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 25 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 93.4s, OverallIterations: 11, TraceHistogramMax: 101, PathProgramHistogramMax: 7, EmptinessCheckTime: 0.1s, AutomataDifference: 17.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1932 SdHoareTripleChecker+Valid, 3.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1931 mSDsluCounter, 2504 SdHoareTripleChecker+Invalid, 3.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2284 mSDsCounter, 195 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1354 IncrementalHoareTripleChecker+Invalid, 1549 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 195 mSolverCounterUnsat, 220 mSDtfsCounter, 1354 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 3977 GetRequests, 3304 SyntacticMatches, 92 SemanticMatches, 581 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17877 ImplicationChecksByTransitivity, 30.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=916occurred in iteration=10, InterpolantAutomatonStates: 583, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.6s AutomataMinimizationTime, 10 MinimizatonAttempts, 10 StatesRemovedByMinimization, 2 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 14.5s SatisfiabilityAnalysisTime, 56.2s InterpolantComputationTime, 5395 NumberOfCodeBlocks, 5395 NumberOfCodeBlocksAsserted, 325 NumberOfCheckSat, 5245 ConstructedInterpolants, 0 QuantifiedInterpolants, 12935 SizeOfPredicates, 179 NumberOfNonLiveVariables, 4132 ConjunctsInSsa, 392 ConjunctsInUnsatCore, 25 InterpolantComputations, 3 PerfectInterpolantSequences, 46667/155806 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-28 03:03:24,329 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a67dbeac-cf58-45be-8686-6aec35c832ba/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE