./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/config/AutomizerReach.xml -i ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-11-28 03:47:36,150 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-28 03:47:36,212 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/config/svcomp-Reach-32bit-Automizer_Default.epf [2024-11-28 03:47:36,219 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-28 03:47:36,220 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-28 03:47:36,259 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-28 03:47:36,262 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-28 03:47:36,262 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-28 03:47:36,263 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-28 03:47:36,263 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-28 03:47:36,264 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-11-28 03:47:36,264 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-11-28 03:47:36,265 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-28 03:47:36,265 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-28 03:47:36,266 INFO L153 SettingsManager]: * Use SBE=true [2024-11-28 03:47:36,266 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-28 03:47:36,266 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-11-28 03:47:36,266 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-28 03:47:36,266 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-28 03:47:36,267 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-28 03:47:36,268 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:47:36,268 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-28 03:47:36,268 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:47:36,269 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-11-28 03:47:36,269 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-11-28 03:47:36,270 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 [2024-11-28 03:47:36,610 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-28 03:47:36,618 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-28 03:47:36,620 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-28 03:47:36,622 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-28 03:47:36,622 INFO L274 PluginConnector]: CDTParser initialized [2024-11-28 03:47:36,623 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2024-11-28 03:47:39,697 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/data/61146eb3b/54095b06f13f4249a2276cb1f9415b8d/FLAG5bc09b07c [2024-11-28 03:47:39,897 INFO L384 CDTParser]: Found 1 translation units. [2024-11-28 03:47:39,898 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2024-11-28 03:47:39,920 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/data/61146eb3b/54095b06f13f4249a2276cb1f9415b8d/FLAG5bc09b07c [2024-11-28 03:47:39,945 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/data/61146eb3b/54095b06f13f4249a2276cb1f9415b8d [2024-11-28 03:47:39,948 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-28 03:47:39,950 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-28 03:47:39,952 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-28 03:47:39,952 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-28 03:47:39,957 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-28 03:47:39,957 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:47:39" (1/1) ... [2024-11-28 03:47:39,961 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5cb4527b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:39, skipping insertion in model container [2024-11-28 03:47:39,961 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 03:47:39" (1/1) ... [2024-11-28 03:47:39,975 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-28 03:47:40,144 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2024-11-28 03:47:40,163 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:47:40,173 INFO L200 MainTranslator]: Completed pre-run [2024-11-28 03:47:40,184 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2024-11-28 03:47:40,191 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-28 03:47:40,210 INFO L204 MainTranslator]: Completed translation [2024-11-28 03:47:40,210 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40 WrapperNode [2024-11-28 03:47:40,211 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-28 03:47:40,212 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-28 03:47:40,212 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-28 03:47:40,213 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-28 03:47:40,222 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,228 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,244 INFO L138 Inliner]: procedures = 14, calls = 11, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 47 [2024-11-28 03:47:40,245 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-28 03:47:40,246 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-28 03:47:40,246 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-28 03:47:40,247 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-28 03:47:40,255 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,255 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,256 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,270 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-28 03:47:40,272 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,272 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,276 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,280 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,283 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,284 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,288 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,289 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-28 03:47:40,290 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-28 03:47:40,290 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-28 03:47:40,290 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-28 03:47:40,291 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (1/1) ... [2024-11-28 03:47:40,302 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-11-28 03:47:40,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:40,327 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-11-28 03:47:40,330 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-11-28 03:47:40,358 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-28 03:47:40,358 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-11-28 03:47:40,358 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-11-28 03:47:40,359 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-28 03:47:40,359 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-28 03:47:40,359 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-28 03:47:40,359 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2024-11-28 03:47:40,359 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2024-11-28 03:47:40,423 INFO L234 CfgBuilder]: Building ICFG [2024-11-28 03:47:40,425 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-28 03:47:40,575 INFO L? ?]: Removed 6 outVars from TransFormulas that were not future-live. [2024-11-28 03:47:40,576 INFO L283 CfgBuilder]: Performing block encoding [2024-11-28 03:47:40,585 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-28 03:47:40,585 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-11-28 03:47:40,586 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:47:40 BoogieIcfgContainer [2024-11-28 03:47:40,586 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-28 03:47:40,588 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-11-28 03:47:40,588 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-11-28 03:47:40,594 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-11-28 03:47:40,594 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 28.11 03:47:39" (1/3) ... [2024-11-28 03:47:40,594 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@389a8b50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:47:40, skipping insertion in model container [2024-11-28 03:47:40,595 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 03:47:40" (2/3) ... [2024-11-28 03:47:40,596 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@389a8b50 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 28.11 03:47:40, skipping insertion in model container [2024-11-28 03:47:40,597 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:47:40" (3/3) ... [2024-11-28 03:47:40,598 INFO L128 eAbstractionObserver]: Analyzing ICFG mannadiv_unwindbound100.c [2024-11-28 03:47:40,616 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-11-28 03:47:40,618 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG mannadiv_unwindbound100.c that has 3 procedures, 25 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-11-28 03:47:40,667 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-11-28 03:47:40,683 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@43eca15a, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-11-28 03:47:40,683 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-11-28 03:47:40,687 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:47:40,693 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2024-11-28 03:47:40,693 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:40,694 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:40,694 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:40,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:40,699 INFO L85 PathProgramCache]: Analyzing trace with hash 1086166160, now seen corresponding path program 1 times [2024-11-28 03:47:40,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:40,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [843939012] [2024-11-28 03:47:40,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:40,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:40,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:40,838 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-28 03:47:40,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:40,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [843939012] [2024-11-28 03:47:40,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [843939012] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:40,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1843337175] [2024-11-28 03:47:40,839 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:40,839 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:40,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:40,842 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:40,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-11-28 03:47:40,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:40,931 INFO L256 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-11-28 03:47:40,935 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:40,947 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2024-11-28 03:47:40,949 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:47:40,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1843337175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:47:40,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:47:40,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-11-28 03:47:40,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075991924] [2024-11-28 03:47:40,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:47:40,957 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-11-28 03:47:40,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:40,977 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-28 03:47:40,979 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:47:40,981 INFO L87 Difference]: Start difference. First operand has 25 states, 17 states have (on average 1.411764705882353) internal successors, (24), 18 states have internal predecessors, (24), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) Second operand has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-28 03:47:41,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:41,002 INFO L93 Difference]: Finished difference Result 47 states and 64 transitions. [2024-11-28 03:47:41,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-28 03:47:41,004 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) Word has length 18 [2024-11-28 03:47:41,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:41,010 INFO L225 Difference]: With dead ends: 47 [2024-11-28 03:47:41,011 INFO L226 Difference]: Without dead ends: 21 [2024-11-28 03:47:41,014 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-28 03:47:41,017 INFO L435 NwaCegarLoop]: 29 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:41,020 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:47:41,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2024-11-28 03:47:41,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2024-11-28 03:47:41,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-11-28 03:47:41,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 25 transitions. [2024-11-28 03:47:41,058 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 25 transitions. Word has length 18 [2024-11-28 03:47:41,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:41,059 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 25 transitions. [2024-11-28 03:47:41,059 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 6.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 2 states have call successors, (2) [2024-11-28 03:47:41,060 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 25 transitions. [2024-11-28 03:47:41,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2024-11-28 03:47:41,062 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:41,062 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:41,071 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-11-28 03:47:41,263 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-11-28 03:47:41,263 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:41,264 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:41,264 INFO L85 PathProgramCache]: Analyzing trace with hash 1316097620, now seen corresponding path program 1 times [2024-11-28 03:47:41,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:41,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289134532] [2024-11-28 03:47:41,264 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:41,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:41,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2024-11-28 03:47:41,296 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1716666765] [2024-11-28 03:47:41,296 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:41,296 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:41,296 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:41,298 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:41,302 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-11-28 03:47:41,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:41,354 INFO L256 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 9 conjuncts are in the unsatisfiable core [2024-11-28 03:47:41,357 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:41,512 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:41,512 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:47:41,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:41,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289134532] [2024-11-28 03:47:41,513 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2024-11-28 03:47:41,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1716666765] [2024-11-28 03:47:41,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1716666765] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:47:41,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:47:41,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-28 03:47:41,514 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [864346506] [2024-11-28 03:47:41,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:47:41,514 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-11-28 03:47:41,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:41,515 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-28 03:47:41,515 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-28 03:47:41,515 INFO L87 Difference]: Start difference. First operand 21 states and 25 transitions. Second operand has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:47:41,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:41,595 INFO L93 Difference]: Finished difference Result 33 states and 40 transitions. [2024-11-28 03:47:41,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-28 03:47:41,596 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2024-11-28 03:47:41,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:41,598 INFO L225 Difference]: With dead ends: 33 [2024-11-28 03:47:41,599 INFO L226 Difference]: Without dead ends: 31 [2024-11-28 03:47:41,599 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 15 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2024-11-28 03:47:41,600 INFO L435 NwaCegarLoop]: 18 mSDtfsCounter, 5 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 69 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:41,601 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 69 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:47:41,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2024-11-28 03:47:41,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 28. [2024-11-28 03:47:41,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 19 states have (on average 1.263157894736842) internal successors, (24), 21 states have internal predecessors, (24), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:47:41,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2024-11-28 03:47:41,613 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 19 [2024-11-28 03:47:41,614 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:41,614 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2024-11-28 03:47:41,615 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:47:41,615 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2024-11-28 03:47:41,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2024-11-28 03:47:41,617 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:41,618 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:41,626 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:41,818 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:41,818 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:41,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:41,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1318004244, now seen corresponding path program 1 times [2024-11-28 03:47:41,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:41,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861368256] [2024-11-28 03:47:41,819 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:41,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:41,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:41,918 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:41,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:41,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861368256] [2024-11-28 03:47:41,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861368256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:47:41,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-28 03:47:41,919 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-11-28 03:47:41,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1144077252] [2024-11-28 03:47:41,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:47:41,919 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-11-28 03:47:41,919 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:41,920 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-28 03:47:41,920 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:47:41,920 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:47:41,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:41,936 INFO L93 Difference]: Finished difference Result 35 states and 39 transitions. [2024-11-28 03:47:41,937 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-28 03:47:41,937 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 19 [2024-11-28 03:47:41,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:41,939 INFO L225 Difference]: With dead ends: 35 [2024-11-28 03:47:41,939 INFO L226 Difference]: Without dead ends: 28 [2024-11-28 03:47:41,939 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-28 03:47:41,940 INFO L435 NwaCegarLoop]: 23 mSDtfsCounter, 5 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 57 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:41,940 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 57 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:47:41,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2024-11-28 03:47:41,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2024-11-28 03:47:41,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 19 states have (on average 1.2105263157894737) internal successors, (23), 21 states have internal predecessors, (23), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:47:41,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2024-11-28 03:47:41,947 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 19 [2024-11-28 03:47:41,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:41,947 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2024-11-28 03:47:41,947 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2024-11-28 03:47:41,948 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2024-11-28 03:47:41,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2024-11-28 03:47:41,948 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:41,949 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:41,949 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-11-28 03:47:41,949 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:41,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:41,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1691684484, now seen corresponding path program 1 times [2024-11-28 03:47:41,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:41,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816022295] [2024-11-28 03:47:41,950 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:41,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:41,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:42,289 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:42,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:42,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816022295] [2024-11-28 03:47:42,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816022295] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:42,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [102586261] [2024-11-28 03:47:42,290 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:42,290 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:42,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:42,292 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:42,301 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-11-28 03:47:42,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:42,364 INFO L256 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:47:42,365 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:42,530 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:42,530 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-11-28 03:47:42,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [102586261] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-28 03:47:42,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-11-28 03:47:42,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 11 [2024-11-28 03:47:42,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1084502291] [2024-11-28 03:47:42,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-28 03:47:42,531 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-11-28 03:47:42,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:42,532 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-11-28 03:47:42,532 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2024-11-28 03:47:42,532 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand has 6 states, 5 states have (on average 3.0) internal successors, (15), 5 states have internal predecessors, (15), 3 states have call successors, (4), 2 states have call predecessors, (4), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-28 03:47:42,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:42,603 INFO L93 Difference]: Finished difference Result 37 states and 42 transitions. [2024-11-28 03:47:42,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-11-28 03:47:42,603 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 5 states have internal predecessors, (15), 3 states have call successors, (4), 2 states have call predecessors, (4), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 25 [2024-11-28 03:47:42,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:42,604 INFO L225 Difference]: With dead ends: 37 [2024-11-28 03:47:42,605 INFO L226 Difference]: Without dead ends: 30 [2024-11-28 03:47:42,606 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 24 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=101, Unknown=0, NotChecked=0, Total=132 [2024-11-28 03:47:42,606 INFO L435 NwaCegarLoop]: 18 mSDtfsCounter, 4 mSDsluCounter, 68 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4 SdHoareTripleChecker+Valid, 86 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:42,607 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4 Valid, 86 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-11-28 03:47:42,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2024-11-28 03:47:42,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2024-11-28 03:47:42,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 20 states have (on average 1.2) internal successors, (24), 21 states have internal predecessors, (24), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2024-11-28 03:47:42,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2024-11-28 03:47:42,619 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 25 [2024-11-28 03:47:42,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:42,619 INFO L471 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2024-11-28 03:47:42,619 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 3.0) internal successors, (15), 5 states have internal predecessors, (15), 3 states have call successors, (4), 2 states have call predecessors, (4), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-11-28 03:47:42,619 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2024-11-28 03:47:42,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2024-11-28 03:47:42,620 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:42,620 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:42,629 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:42,820 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:42,821 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:42,821 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:42,821 INFO L85 PathProgramCache]: Analyzing trace with hash -147457855, now seen corresponding path program 1 times [2024-11-28 03:47:42,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:42,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084916123] [2024-11-28 03:47:42,821 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:42,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:42,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2024-11-28 03:47:42,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [952356522] [2024-11-28 03:47:42,859 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:42,859 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:42,859 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:42,865 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:42,867 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-11-28 03:47:42,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:42,921 INFO L256 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 17 conjuncts are in the unsatisfiable core [2024-11-28 03:47:42,923 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:43,107 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:43,107 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:43,223 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:43,224 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:43,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084916123] [2024-11-28 03:47:43,224 WARN L311 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2024-11-28 03:47:43,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [952356522] [2024-11-28 03:47:43,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [952356522] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:43,224 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-11-28 03:47:43,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 8 [2024-11-28 03:47:43,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [319121532] [2024-11-28 03:47:43,224 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:43,225 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 03:47:43,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:43,225 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:47:43,225 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:47:43,226 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand has 8 states, 8 states have (on average 3.125) internal successors, (25), 7 states have internal predecessors, (25), 5 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2024-11-28 03:47:43,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:43,356 INFO L93 Difference]: Finished difference Result 59 states and 75 transitions. [2024-11-28 03:47:43,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-11-28 03:47:43,357 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 7 states have internal predecessors, (25), 5 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 28 [2024-11-28 03:47:43,358 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:43,358 INFO L225 Difference]: With dead ends: 59 [2024-11-28 03:47:43,358 INFO L226 Difference]: Without dead ends: 45 [2024-11-28 03:47:43,359 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 46 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-11-28 03:47:43,361 INFO L435 NwaCegarLoop]: 21 mSDtfsCounter, 11 mSDsluCounter, 76 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 97 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:43,362 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 97 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:47:43,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2024-11-28 03:47:43,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 37. [2024-11-28 03:47:43,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 27 states have internal predecessors, (33), 6 states have call successors, (6), 4 states have call predecessors, (6), 3 states have return successors, (5), 5 states have call predecessors, (5), 5 states have call successors, (5) [2024-11-28 03:47:43,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 44 transitions. [2024-11-28 03:47:43,379 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 44 transitions. Word has length 28 [2024-11-28 03:47:43,380 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:43,380 INFO L471 AbstractCegarLoop]: Abstraction has 37 states and 44 transitions. [2024-11-28 03:47:43,380 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 7 states have internal predecessors, (25), 5 states have call successors, (6), 2 states have call predecessors, (6), 1 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2024-11-28 03:47:43,380 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 44 transitions. [2024-11-28 03:47:43,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2024-11-28 03:47:43,381 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:43,381 INFO L218 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:43,390 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:43,581 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:43,581 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:43,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:43,582 INFO L85 PathProgramCache]: Analyzing trace with hash -145551231, now seen corresponding path program 1 times [2024-11-28 03:47:43,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:43,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961894760] [2024-11-28 03:47:43,582 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:43,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:43,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:43,659 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:43,659 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:43,659 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961894760] [2024-11-28 03:47:43,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961894760] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:43,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [147375462] [2024-11-28 03:47:43,660 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:43,660 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:43,660 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:43,662 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:43,665 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-11-28 03:47:43,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:43,710 INFO L256 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 5 conjuncts are in the unsatisfiable core [2024-11-28 03:47:43,712 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:43,767 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:43,768 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:43,827 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:43,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [147375462] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:43,827 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:47:43,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 5] total 8 [2024-11-28 03:47:43,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693745768] [2024-11-28 03:47:43,828 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:43,828 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-11-28 03:47:43,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:43,829 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-11-28 03:47:43,831 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2024-11-28 03:47:43,831 INFO L87 Difference]: Start difference. First operand 37 states and 44 transitions. Second operand has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) [2024-11-28 03:47:43,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:43,930 INFO L93 Difference]: Finished difference Result 72 states and 83 transitions. [2024-11-28 03:47:43,930 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2024-11-28 03:47:43,931 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) Word has length 28 [2024-11-28 03:47:43,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:43,932 INFO L225 Difference]: With dead ends: 72 [2024-11-28 03:47:43,932 INFO L226 Difference]: Without dead ends: 67 [2024-11-28 03:47:43,932 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=70, Unknown=0, NotChecked=0, Total=110 [2024-11-28 03:47:43,934 INFO L435 NwaCegarLoop]: 23 mSDtfsCounter, 32 mSDsluCounter, 83 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 106 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:43,935 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 106 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:47:43,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2024-11-28 03:47:43,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 57. [2024-11-28 03:47:43,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 43 states have (on average 1.2093023255813953) internal successors, (52), 43 states have internal predecessors, (52), 8 states have call successors, (8), 6 states have call predecessors, (8), 5 states have return successors, (7), 7 states have call predecessors, (7), 7 states have call successors, (7) [2024-11-28 03:47:43,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 67 transitions. [2024-11-28 03:47:43,954 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 67 transitions. Word has length 28 [2024-11-28 03:47:43,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:43,954 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 67 transitions. [2024-11-28 03:47:43,954 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 4.125) internal successors, (33), 8 states have internal predecessors, (33), 5 states have call successors, (10), 4 states have call predecessors, (10), 3 states have return successors, (9), 4 states have call predecessors, (9), 4 states have call successors, (9) [2024-11-28 03:47:43,954 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 67 transitions. [2024-11-28 03:47:43,955 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2024-11-28 03:47:43,955 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:43,955 INFO L218 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:43,963 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:44,155 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2024-11-28 03:47:44,156 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:44,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:44,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1574868521, now seen corresponding path program 1 times [2024-11-28 03:47:44,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:44,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1360358125] [2024-11-28 03:47:44,156 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:44,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:44,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:44,519 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-28 03:47:44,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:44,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1360358125] [2024-11-28 03:47:44,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1360358125] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:44,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [299733564] [2024-11-28 03:47:44,520 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-28 03:47:44,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:44,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:44,522 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:44,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-11-28 03:47:44,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-28 03:47:44,587 INFO L256 TraceCheckSpWp]: Trace formula consists of 99 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-11-28 03:47:44,590 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:44,824 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2024-11-28 03:47:44,824 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:44,932 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-11-28 03:47:44,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [299733564] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:44,933 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:47:44,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 10, 7] total 15 [2024-11-28 03:47:44,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801173974] [2024-11-28 03:47:44,933 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:44,934 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-28 03:47:44,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:44,934 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-28 03:47:44,935 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=169, Unknown=0, NotChecked=0, Total=210 [2024-11-28 03:47:44,935 INFO L87 Difference]: Start difference. First operand 57 states and 67 transitions. Second operand has 15 states, 13 states have (on average 2.5384615384615383) internal successors, (33), 11 states have internal predecessors, (33), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (7), 5 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:47:45,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:45,111 INFO L93 Difference]: Finished difference Result 66 states and 76 transitions. [2024-11-28 03:47:45,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-11-28 03:47:45,111 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 13 states have (on average 2.5384615384615383) internal successors, (33), 11 states have internal predecessors, (33), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (7), 5 states have call predecessors, (7), 3 states have call successors, (7) Word has length 34 [2024-11-28 03:47:45,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:45,112 INFO L225 Difference]: With dead ends: 66 [2024-11-28 03:47:45,112 INFO L226 Difference]: Without dead ends: 60 [2024-11-28 03:47:45,113 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=218, Unknown=0, NotChecked=0, Total=272 [2024-11-28 03:47:45,113 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 15 mSDsluCounter, 133 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 155 SdHoareTripleChecker+Invalid, 111 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:45,114 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 155 Invalid, 111 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 106 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:47:45,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2024-11-28 03:47:45,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 57. [2024-11-28 03:47:45,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 43 states have (on average 1.1162790697674418) internal successors, (48), 43 states have internal predecessors, (48), 8 states have call successors, (8), 6 states have call predecessors, (8), 5 states have return successors, (7), 7 states have call predecessors, (7), 7 states have call successors, (7) [2024-11-28 03:47:45,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 63 transitions. [2024-11-28 03:47:45,137 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 63 transitions. Word has length 34 [2024-11-28 03:47:45,141 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:45,141 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 63 transitions. [2024-11-28 03:47:45,141 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 13 states have (on average 2.5384615384615383) internal successors, (33), 11 states have internal predecessors, (33), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (7), 5 states have call predecessors, (7), 3 states have call successors, (7) [2024-11-28 03:47:45,141 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 63 transitions. [2024-11-28 03:47:45,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2024-11-28 03:47:45,143 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:45,143 INFO L218 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:45,152 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2024-11-28 03:47:45,343 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable6 [2024-11-28 03:47:45,344 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:45,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:45,344 INFO L85 PathProgramCache]: Analyzing trace with hash -1700883628, now seen corresponding path program 2 times [2024-11-28 03:47:45,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:45,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637917396] [2024-11-28 03:47:45,345 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:47:45,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:45,368 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 03:47:45,368 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:45,605 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 38 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-11-28 03:47:45,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:45,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637917396] [2024-11-28 03:47:45,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637917396] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:45,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [40616285] [2024-11-28 03:47:45,605 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-11-28 03:47:45,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:45,606 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:45,610 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:45,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-11-28 03:47:45,674 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-11-28 03:47:45,674 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:45,675 INFO L256 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-11-28 03:47:45,677 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:45,787 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 62 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:45,787 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:45,968 INFO L134 CoverageAnalysis]: Checked inductivity of 74 backedges. 8 proven. 38 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2024-11-28 03:47:45,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [40616285] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:45,969 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:47:45,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 8] total 15 [2024-11-28 03:47:45,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634939313] [2024-11-28 03:47:45,969 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:45,969 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2024-11-28 03:47:45,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:45,970 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2024-11-28 03:47:45,970 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=129, Unknown=0, NotChecked=0, Total=210 [2024-11-28 03:47:45,971 INFO L87 Difference]: Start difference. First operand 57 states and 63 transitions. Second operand has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-11-28 03:47:46,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:46,220 INFO L93 Difference]: Finished difference Result 116 states and 133 transitions. [2024-11-28 03:47:46,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2024-11-28 03:47:46,220 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) Word has length 55 [2024-11-28 03:47:46,221 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:46,222 INFO L225 Difference]: With dead ends: 116 [2024-11-28 03:47:46,222 INFO L226 Difference]: Without dead ends: 111 [2024-11-28 03:47:46,223 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=184, Invalid=322, Unknown=0, NotChecked=0, Total=506 [2024-11-28 03:47:46,223 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 43 mSDsluCounter, 118 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 43 SdHoareTripleChecker+Valid, 140 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:46,224 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [43 Valid, 140 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-11-28 03:47:46,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2024-11-28 03:47:46,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2024-11-28 03:47:46,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 85 states have (on average 1.1294117647058823) internal successors, (96), 85 states have internal predecessors, (96), 14 states have call successors, (14), 12 states have call predecessors, (14), 11 states have return successors, (13), 13 states have call predecessors, (13), 13 states have call successors, (13) [2024-11-28 03:47:46,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 123 transitions. [2024-11-28 03:47:46,254 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 123 transitions. Word has length 55 [2024-11-28 03:47:46,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:46,254 INFO L471 AbstractCegarLoop]: Abstraction has 111 states and 123 transitions. [2024-11-28 03:47:46,255 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 4.533333333333333) internal successors, (68), 15 states have internal predecessors, (68), 11 states have call successors, (19), 7 states have call predecessors, (19), 6 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-11-28 03:47:46,255 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 123 transitions. [2024-11-28 03:47:46,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2024-11-28 03:47:46,259 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:46,259 INFO L218 NwaCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:46,270 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:46,464 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable7 [2024-11-28 03:47:46,464 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:46,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:46,464 INFO L85 PathProgramCache]: Analyzing trace with hash 592653108, now seen corresponding path program 3 times [2024-11-28 03:47:46,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:46,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22076945] [2024-11-28 03:47:46,465 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-28 03:47:46,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:46,523 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-28 03:47:46,523 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:47,520 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 245 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2024-11-28 03:47:47,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:47,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22076945] [2024-11-28 03:47:47,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [22076945] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:47,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [57585738] [2024-11-28 03:47:47,521 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2024-11-28 03:47:47,521 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:47,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:47,525 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:47,527 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-11-28 03:47:47,642 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2024-11-28 03:47:47,643 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:47,645 INFO L256 TraceCheckSpWp]: Trace formula consists of 295 conjuncts, 23 conjuncts are in the unsatisfiable core [2024-11-28 03:47:47,653 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:47,850 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 425 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:47,850 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:48,392 INFO L134 CoverageAnalysis]: Checked inductivity of 449 backedges. 20 proven. 245 refuted. 0 times theorem prover too weak. 184 trivial. 0 not checked. [2024-11-28 03:47:48,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [57585738] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:48,393 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:47:48,393 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 13, 14] total 33 [2024-11-28 03:47:48,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2036619254] [2024-11-28 03:47:48,393 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:48,394 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2024-11-28 03:47:48,394 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:48,396 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2024-11-28 03:47:48,396 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=615, Unknown=0, NotChecked=0, Total=1056 [2024-11-28 03:47:48,397 INFO L87 Difference]: Start difference. First operand 111 states and 123 transitions. Second operand has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) [2024-11-28 03:47:49,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:49,012 INFO L93 Difference]: Finished difference Result 224 states and 259 transitions. [2024-11-28 03:47:49,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2024-11-28 03:47:49,013 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) Word has length 109 [2024-11-28 03:47:49,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:49,015 INFO L225 Difference]: With dead ends: 224 [2024-11-28 03:47:49,015 INFO L226 Difference]: Without dead ends: 219 [2024-11-28 03:47:49,016 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 251 GetRequests, 206 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 238 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=796, Invalid=1366, Unknown=0, NotChecked=0, Total=2162 [2024-11-28 03:47:49,017 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 124 mSDsluCounter, 178 mSDsCounter, 0 mSdLazyCounter, 96 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 124 SdHoareTripleChecker+Valid, 200 SdHoareTripleChecker+Invalid, 108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 96 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:49,017 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [124 Valid, 200 Invalid, 108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 96 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-11-28 03:47:49,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2024-11-28 03:47:49,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 219. [2024-11-28 03:47:49,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219 states, 169 states have (on average 1.136094674556213) internal successors, (192), 169 states have internal predecessors, (192), 26 states have call successors, (26), 24 states have call predecessors, (26), 23 states have return successors, (25), 25 states have call predecessors, (25), 25 states have call successors, (25) [2024-11-28 03:47:49,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 243 transitions. [2024-11-28 03:47:49,067 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 243 transitions. Word has length 109 [2024-11-28 03:47:49,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:49,068 INFO L471 AbstractCegarLoop]: Abstraction has 219 states and 243 transitions. [2024-11-28 03:47:49,068 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 4.424242424242424) internal successors, (146), 33 states have internal predecessors, (146), 23 states have call successors, (37), 13 states have call predecessors, (37), 12 states have return successors, (36), 22 states have call predecessors, (36), 22 states have call successors, (36) [2024-11-28 03:47:49,068 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 243 transitions. [2024-11-28 03:47:49,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 218 [2024-11-28 03:47:49,074 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:49,074 INFO L218 NwaCegarLoop]: trace histogram [23, 23, 22, 22, 22, 22, 22, 22, 22, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:49,085 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2024-11-28 03:47:49,274 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:49,275 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:49,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:49,276 INFO L85 PathProgramCache]: Analyzing trace with hash 1359241972, now seen corresponding path program 4 times [2024-11-28 03:47:49,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:49,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251772526] [2024-11-28 03:47:49,276 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-28 03:47:49,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:49,394 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-28 03:47:49,394 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:51,170 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 1199 refuted. 0 times theorem prover too weak. 928 trivial. 0 not checked. [2024-11-28 03:47:51,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:47:51,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251772526] [2024-11-28 03:47:51,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251772526] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:47:51,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1693695401] [2024-11-28 03:47:51,171 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2024-11-28 03:47:51,171 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:51,171 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:47:51,172 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:47:51,174 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-11-28 03:47:51,322 INFO L229 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2024-11-28 03:47:51,322 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:47:51,326 INFO L256 TraceCheckSpWp]: Trace formula consists of 571 conjuncts, 47 conjuncts are in the unsatisfiable core [2024-11-28 03:47:51,334 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:47:51,729 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 2123 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:47:51,729 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:47:52,980 INFO L134 CoverageAnalysis]: Checked inductivity of 2171 backedges. 44 proven. 1199 refuted. 0 times theorem prover too weak. 928 trivial. 0 not checked. [2024-11-28 03:47:52,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1693695401] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:47:52,980 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:47:52,980 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 25, 26] total 52 [2024-11-28 03:47:52,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [65524091] [2024-11-28 03:47:52,981 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:47:52,983 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 52 states [2024-11-28 03:47:52,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:47:52,986 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2024-11-28 03:47:52,987 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1230, Invalid=1422, Unknown=0, NotChecked=0, Total=2652 [2024-11-28 03:47:52,988 INFO L87 Difference]: Start difference. First operand 219 states and 243 transitions. Second operand has 52 states, 52 states have (on average 5.173076923076923) internal successors, (269), 52 states have internal predecessors, (269), 48 states have call successors, (73), 25 states have call predecessors, (73), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) [2024-11-28 03:47:54,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:47:54,879 INFO L93 Difference]: Finished difference Result 440 states and 511 transitions. [2024-11-28 03:47:54,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2024-11-28 03:47:54,881 INFO L78 Accepts]: Start accepts. Automaton has has 52 states, 52 states have (on average 5.173076923076923) internal successors, (269), 52 states have internal predecessors, (269), 48 states have call successors, (73), 25 states have call predecessors, (73), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) Word has length 217 [2024-11-28 03:47:54,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:47:54,886 INFO L225 Difference]: With dead ends: 440 [2024-11-28 03:47:54,886 INFO L226 Difference]: Without dead ends: 435 [2024-11-28 03:47:54,894 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 503 GetRequests, 409 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1380 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=3364, Invalid=5756, Unknown=0, NotChecked=0, Total=9120 [2024-11-28 03:47:54,896 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 420 mSDsluCounter, 314 mSDsCounter, 0 mSdLazyCounter, 189 mSolverCounterSat, 52 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 420 SdHoareTripleChecker+Valid, 336 SdHoareTripleChecker+Invalid, 241 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 52 IncrementalHoareTripleChecker+Valid, 189 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-11-28 03:47:54,897 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [420 Valid, 336 Invalid, 241 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [52 Valid, 189 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-11-28 03:47:54,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states. [2024-11-28 03:47:54,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2024-11-28 03:47:54,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 337 states have (on average 1.13946587537092) internal successors, (384), 337 states have internal predecessors, (384), 50 states have call successors, (50), 48 states have call predecessors, (50), 47 states have return successors, (49), 49 states have call predecessors, (49), 49 states have call successors, (49) [2024-11-28 03:47:54,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 483 transitions. [2024-11-28 03:47:54,969 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 483 transitions. Word has length 217 [2024-11-28 03:47:54,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:47:54,971 INFO L471 AbstractCegarLoop]: Abstraction has 435 states and 483 transitions. [2024-11-28 03:47:54,972 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 52 states, 52 states have (on average 5.173076923076923) internal successors, (269), 52 states have internal predecessors, (269), 48 states have call successors, (73), 25 states have call predecessors, (73), 24 states have return successors, (72), 47 states have call predecessors, (72), 47 states have call successors, (72) [2024-11-28 03:47:54,972 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 483 transitions. [2024-11-28 03:47:54,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 434 [2024-11-28 03:47:54,984 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:47:54,984 INFO L218 NwaCegarLoop]: trace histogram [47, 47, 46, 46, 46, 46, 46, 46, 46, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:47:54,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-11-28 03:47:55,185 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:47:55,185 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:47:55,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:47:55,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1200550516, now seen corresponding path program 5 times [2024-11-28 03:47:55,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:47:55,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785490151] [2024-11-28 03:47:55,187 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-28 03:47:55,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:47:55,666 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-28 03:47:55,666 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:48:01,177 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 5267 refuted. 0 times theorem prover too weak. 4144 trivial. 0 not checked. [2024-11-28 03:48:01,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:48:01,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785490151] [2024-11-28 03:48:01,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785490151] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:48:01,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1167709660] [2024-11-28 03:48:01,178 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2024-11-28 03:48:01,178 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:01,179 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:48:01,181 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:48:01,185 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-11-28 03:48:01,619 INFO L229 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2024-11-28 03:48:01,619 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:48:01,624 INFO L256 TraceCheckSpWp]: Trace formula consists of 1123 conjuncts, 95 conjuncts are in the unsatisfiable core [2024-11-28 03:48:01,633 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:48:02,237 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 9407 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:48:02,237 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:48:05,822 INFO L134 CoverageAnalysis]: Checked inductivity of 9503 backedges. 92 proven. 5267 refuted. 0 times theorem prover too weak. 4144 trivial. 0 not checked. [2024-11-28 03:48:05,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1167709660] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:48:05,822 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:48:05,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 49, 50] total 99 [2024-11-28 03:48:05,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [869685554] [2024-11-28 03:48:05,823 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:48:05,824 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 99 states [2024-11-28 03:48:05,824 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:48:05,827 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2024-11-28 03:48:05,830 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=4658, Invalid=5044, Unknown=0, NotChecked=0, Total=9702 [2024-11-28 03:48:05,831 INFO L87 Difference]: Start difference. First operand 435 states and 483 transitions. Second operand has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) [2024-11-28 03:48:11,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:48:11,565 INFO L93 Difference]: Finished difference Result 872 states and 1015 transitions. [2024-11-28 03:48:11,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2024-11-28 03:48:11,566 INFO L78 Accepts]: Start accepts. Automaton has has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) Word has length 433 [2024-11-28 03:48:11,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:48:11,570 INFO L225 Difference]: With dead ends: 872 [2024-11-28 03:48:11,570 INFO L226 Difference]: Without dead ends: 867 [2024-11-28 03:48:11,577 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1007 GetRequests, 818 SyntacticMatches, 0 SemanticMatches, 189 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5716 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=13540, Invalid=22750, Unknown=0, NotChecked=0, Total=36290 [2024-11-28 03:48:11,578 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 961 mSDsluCounter, 616 mSDsCounter, 0 mSdLazyCounter, 391 mSolverCounterSat, 105 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 961 SdHoareTripleChecker+Valid, 638 SdHoareTripleChecker+Invalid, 496 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 105 IncrementalHoareTripleChecker+Valid, 391 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-28 03:48:11,578 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [961 Valid, 638 Invalid, 496 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [105 Valid, 391 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-28 03:48:11,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 867 states. [2024-11-28 03:48:11,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 867 to 867. [2024-11-28 03:48:11,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 867 states, 673 states have (on average 1.1411589895988112) internal successors, (768), 673 states have internal predecessors, (768), 98 states have call successors, (98), 96 states have call predecessors, (98), 95 states have return successors, (97), 97 states have call predecessors, (97), 97 states have call successors, (97) [2024-11-28 03:48:11,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 867 states to 867 states and 963 transitions. [2024-11-28 03:48:11,652 INFO L78 Accepts]: Start accepts. Automaton has 867 states and 963 transitions. Word has length 433 [2024-11-28 03:48:11,653 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:48:11,653 INFO L471 AbstractCegarLoop]: Abstraction has 867 states and 963 transitions. [2024-11-28 03:48:11,654 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 99 states, 99 states have (on average 5.353535353535354) internal successors, (530), 99 states have internal predecessors, (530), 95 states have call successors, (145), 49 states have call predecessors, (145), 48 states have return successors, (144), 94 states have call predecessors, (144), 94 states have call successors, (144) [2024-11-28 03:48:11,654 INFO L276 IsEmpty]: Start isEmpty. Operand 867 states and 963 transitions. [2024-11-28 03:48:11,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 866 [2024-11-28 03:48:11,679 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:48:11,680 INFO L218 NwaCegarLoop]: trace histogram [95, 95, 94, 94, 94, 94, 94, 94, 94, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:48:11,691 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-11-28 03:48:11,880 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:11,880 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:48:11,881 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:48:11,881 INFO L85 PathProgramCache]: Analyzing trace with hash 495227252, now seen corresponding path program 6 times [2024-11-28 03:48:11,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:48:11,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167300155] [2024-11-28 03:48:11,881 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-28 03:48:11,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:48:12,854 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-28 03:48:12,855 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:48:35,561 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 22043 refuted. 0 times theorem prover too weak. 17488 trivial. 0 not checked. [2024-11-28 03:48:35,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-28 03:48:35,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167300155] [2024-11-28 03:48:35,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167300155] provided 0 perfect and 1 imperfect interpolant sequences [2024-11-28 03:48:35,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [955140549] [2024-11-28 03:48:35,562 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2024-11-28 03:48:35,563 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:35,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:48:35,568 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:48:35,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-11-28 03:48:36,848 INFO L229 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2024-11-28 03:48:36,848 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-11-28 03:48:36,859 INFO L256 TraceCheckSpWp]: Trace formula consists of 2227 conjuncts, 191 conjuncts are in the unsatisfiable core [2024-11-28 03:48:36,881 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-11-28 03:48:37,944 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 39527 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2024-11-28 03:48:37,944 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-11-28 03:48:44,080 INFO L134 CoverageAnalysis]: Checked inductivity of 39719 backedges. 188 proven. 22043 refuted. 0 times theorem prover too weak. 17488 trivial. 0 not checked. [2024-11-28 03:48:44,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [955140549] provided 0 perfect and 2 imperfect interpolant sequences [2024-11-28 03:48:44,081 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-11-28 03:48:44,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [133, 97, 98] total 139 [2024-11-28 03:48:44,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901054431] [2024-11-28 03:48:44,081 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-11-28 03:48:44,083 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 139 states [2024-11-28 03:48:44,084 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-28 03:48:44,087 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 139 interpolants. [2024-11-28 03:48:44,089 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6879, Invalid=12303, Unknown=0, NotChecked=0, Total=19182 [2024-11-28 03:48:44,090 INFO L87 Difference]: Start difference. First operand 867 states and 963 transitions. Second operand has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) [2024-11-28 03:48:48,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-28 03:48:48,210 INFO L93 Difference]: Finished difference Result 926 states and 1033 transitions. [2024-11-28 03:48:48,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2024-11-28 03:48:48,211 INFO L78 Accepts]: Start accepts. Automaton has has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) Word has length 865 [2024-11-28 03:48:48,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-11-28 03:48:48,224 INFO L225 Difference]: With dead ends: 926 [2024-11-28 03:48:48,226 INFO L226 Difference]: Without dead ends: 921 [2024-11-28 03:48:48,233 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1925 GetRequests, 1634 SyntacticMatches, 90 SemanticMatches, 201 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10247 ImplicationChecksByTransitivity, 14.0s TimeCoverageRelationStatistics Valid=15349, Invalid=25657, Unknown=0, NotChecked=0, Total=41006 [2024-11-28 03:48:48,234 INFO L435 NwaCegarLoop]: 22 mSDtfsCounter, 502 mSDsluCounter, 654 mSDsCounter, 0 mSdLazyCounter, 442 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 502 SdHoareTripleChecker+Valid, 676 SdHoareTripleChecker+Invalid, 445 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 442 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-11-28 03:48:48,234 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [502 Valid, 676 Invalid, 445 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 442 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-11-28 03:48:48,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 921 states. [2024-11-28 03:48:48,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 921 to 921. [2024-11-28 03:48:48,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 921 states, 715 states have (on average 1.1412587412587412) internal successors, (816), 715 states have internal predecessors, (816), 104 states have call successors, (104), 102 states have call predecessors, (104), 101 states have return successors, (103), 103 states have call predecessors, (103), 103 states have call successors, (103) [2024-11-28 03:48:48,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 921 states to 921 states and 1023 transitions. [2024-11-28 03:48:48,340 INFO L78 Accepts]: Start accepts. Automaton has 921 states and 1023 transitions. Word has length 865 [2024-11-28 03:48:48,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-11-28 03:48:48,343 INFO L471 AbstractCegarLoop]: Abstraction has 921 states and 1023 transitions. [2024-11-28 03:48:48,344 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 139 states, 139 states have (on average 5.539568345323741) internal successors, (770), 139 states have internal predecessors, (770), 101 states have call successors, (200), 97 states have call predecessors, (200), 96 states have return successors, (199), 100 states have call predecessors, (199), 100 states have call successors, (199) [2024-11-28 03:48:48,344 INFO L276 IsEmpty]: Start isEmpty. Operand 921 states and 1023 transitions. [2024-11-28 03:48:48,381 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 920 [2024-11-28 03:48:48,381 INFO L210 NwaCegarLoop]: Found error trace [2024-11-28 03:48:48,381 INFO L218 NwaCegarLoop]: trace histogram [101, 101, 100, 100, 100, 100, 100, 100, 100, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-28 03:48:48,397 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-11-28 03:48:48,582 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:48,582 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-11-28 03:48:48,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-28 03:48:48,583 INFO L85 PathProgramCache]: Analyzing trace with hash 1067012436, now seen corresponding path program 7 times [2024-11-28 03:48:48,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-28 03:48:48,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003424389] [2024-11-28 03:48:48,583 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-28 03:48:48,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-28 03:48:49,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2024-11-28 03:48:49,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2122851101] [2024-11-28 03:48:49,436 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2024-11-28 03:48:49,436 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:49,436 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 [2024-11-28 03:48:49,438 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-11-28 03:48:49,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2024-11-28 03:48:50,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:48:50,004 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-28 03:48:50,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-28 03:48:50,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-28 03:48:50,651 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-11-28 03:48:50,652 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-11-28 03:48:50,669 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2024-11-28 03:48:50,854 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-11-28 03:48:50,857 INFO L422 BasicCegarLoop]: Path program histogram: [7, 1, 1, 1, 1, 1, 1] [2024-11-28 03:48:51,081 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-11-28 03:48:51,086 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 28.11 03:48:51 BoogieIcfgContainer [2024-11-28 03:48:51,086 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-11-28 03:48:51,087 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-28 03:48:51,087 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-28 03:48:51,087 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-28 03:48:51,088 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 03:47:40" (3/4) ... [2024-11-28 03:48:51,089 INFO L140 WitnessPrinter]: Generating witness for reachability counterexample [2024-11-28 03:48:51,359 INFO L129 tionWitnessGenerator]: Generated YAML witness of length 610. [2024-11-28 03:48:51,675 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/witness.graphml [2024-11-28 03:48:51,676 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/witness.yml [2024-11-28 03:48:51,676 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-28 03:48:51,679 INFO L158 Benchmark]: Toolchain (without parser) took 71726.99ms. Allocated memory was 117.4MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 92.1MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 395.3MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,679 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 117.4MB. Free memory is still 71.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:48:51,679 INFO L158 Benchmark]: CACSL2BoogieTranslator took 259.58ms. Allocated memory is still 117.4MB. Free memory was 91.9MB in the beginning and 80.8MB in the end (delta: 11.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,679 INFO L158 Benchmark]: Boogie Procedure Inliner took 32.95ms. Allocated memory is still 117.4MB. Free memory was 80.8MB in the beginning and 79.7MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. [2024-11-28 03:48:51,680 INFO L158 Benchmark]: Boogie Preprocessor took 43.36ms. Allocated memory is still 117.4MB. Free memory was 79.7MB in the beginning and 78.5MB in the end (delta: 1.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,680 INFO L158 Benchmark]: RCFGBuilder took 296.38ms. Allocated memory is still 117.4MB. Free memory was 78.5MB in the beginning and 68.6MB in the end (delta: 9.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,680 INFO L158 Benchmark]: TraceAbstraction took 70497.73ms. Allocated memory was 117.4MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 68.1MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 319.8MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,680 INFO L158 Benchmark]: Witness Printer took 589.59ms. Allocated memory is still 1.6GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 50.3MB). Peak memory consumption was 50.3MB. Max. memory is 16.1GB. [2024-11-28 03:48:51,684 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 117.4MB. Free memory is still 71.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 259.58ms. Allocated memory is still 117.4MB. Free memory was 91.9MB in the beginning and 80.8MB in the end (delta: 11.1MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 32.95ms. Allocated memory is still 117.4MB. Free memory was 80.8MB in the beginning and 79.7MB in the end (delta: 1.1MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 43.36ms. Allocated memory is still 117.4MB. Free memory was 79.7MB in the beginning and 78.5MB in the end (delta: 1.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 296.38ms. Allocated memory is still 117.4MB. Free memory was 78.5MB in the beginning and 68.6MB in the end (delta: 9.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * TraceAbstraction took 70497.73ms. Allocated memory was 117.4MB in the beginning and 1.6GB in the end (delta: 1.5GB). Free memory was 68.1MB in the beginning and 1.2GB in the end (delta: -1.1GB). Peak memory consumption was 319.8MB. Max. memory is 16.1GB. * Witness Printer took 589.59ms. Allocated memory is still 1.6GB. Free memory was 1.2GB in the beginning and 1.2GB in the end (delta: 50.3MB). Peak memory consumption was 50.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 18]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L22] int counter = 0; VAL [counter=0] [L24] int x1, x2; [L25] int y1, y2, y3; [L26] x1 = __VERIFIER_nondet_int() [L27] x2 = __VERIFIER_nondet_int() [L29] CALL assume_abort_if_not(x1 >= 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) VAL [\old(cond)=1, counter=0] [L29] RET assume_abort_if_not(x1 >= 0) VAL [counter=0, x1=101, x2=1] [L30] CALL assume_abort_if_not(x2 != 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) VAL [\old(cond)=1, counter=0] [L30] RET assume_abort_if_not(x2 != 0) VAL [counter=0, x1=101, x2=1] [L32] y1 = 0 [L33] y2 = 0 [L34] y3 = x1 VAL [counter=0, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] EXPR counter++ VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=1] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=1] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=1, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] EXPR counter++ VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=2] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=2] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=2, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] EXPR counter++ VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=3] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=3] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=3, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] EXPR counter++ VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=4] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=4] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=4, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] EXPR counter++ VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=5] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=5] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=5, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] EXPR counter++ VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=6] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=6] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=6, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] EXPR counter++ VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=7] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=7] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=7, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] EXPR counter++ VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=8] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=8] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=8, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] EXPR counter++ VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=9] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=9] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=9, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] EXPR counter++ VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=10] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=10] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=10, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] EXPR counter++ VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=11] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=11] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=11, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] EXPR counter++ VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=12] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=12] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=12, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] EXPR counter++ VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=13] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=13] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=13, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] EXPR counter++ VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=14] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=14] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=14, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] EXPR counter++ VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=15] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=15] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=15, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] EXPR counter++ VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=16] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=16] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=16, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] EXPR counter++ VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=17] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=17] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=17, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] EXPR counter++ VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=18] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=18] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=18, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] EXPR counter++ VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=19] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=19] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=19, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] EXPR counter++ VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=20] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=20] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=20, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] EXPR counter++ VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=21] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=21] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=21, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] EXPR counter++ VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=22] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=22] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=22, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] EXPR counter++ VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=23] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=23] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=23, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] EXPR counter++ VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=24] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=24] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=24, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] EXPR counter++ VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=25] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=25] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=25, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] EXPR counter++ VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=26] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=26] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=26, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] EXPR counter++ VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=27] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=27] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=27, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] EXPR counter++ VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=28] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=28] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=28, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] EXPR counter++ VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=29] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=29] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=29, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] EXPR counter++ VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=30] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=30] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=30, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] EXPR counter++ VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=31] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=31] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=31, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] EXPR counter++ VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=32] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=32] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=32, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] EXPR counter++ VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=33] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=33] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=33, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] EXPR counter++ VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=34] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=34] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=34, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] EXPR counter++ VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=35] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=35] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=35, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] EXPR counter++ VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=36] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=36] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=36, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] EXPR counter++ VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=37] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=37] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=37, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] EXPR counter++ VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=38] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=38] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=38, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] EXPR counter++ VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=39] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=39] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=39, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] EXPR counter++ VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=40] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=40] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=40, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] EXPR counter++ VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=41] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=41] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=41, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] EXPR counter++ VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=42] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=42] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=42, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] EXPR counter++ VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=43] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=43] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=43, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] EXPR counter++ VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=44] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=44] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=44, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] EXPR counter++ VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=45] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=45] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=45, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] EXPR counter++ VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=46] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=46] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=46, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] EXPR counter++ VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=47] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=47] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=47, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] EXPR counter++ VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=48] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=48] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=48, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] EXPR counter++ VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=49] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=49] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=49, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] EXPR counter++ VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=50] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=50] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=50, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] EXPR counter++ VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=51] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=51] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=51, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] EXPR counter++ VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=52] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=52] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=52, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] EXPR counter++ VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=53] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=53] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=53, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] EXPR counter++ VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=54] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=54] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=54, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] EXPR counter++ VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=55] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=55] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=55, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] EXPR counter++ VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=56] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=56] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=56, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] EXPR counter++ VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=57] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=57] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=57, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] EXPR counter++ VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=58] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=58] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=58, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] EXPR counter++ VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=59] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=59] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=59, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] EXPR counter++ VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=60] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=60] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=60, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] EXPR counter++ VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=61] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=61] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=61, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] EXPR counter++ VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=62] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=62] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=62, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] EXPR counter++ VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=63] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=63] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=63, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] EXPR counter++ VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=64] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=64] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=64, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] EXPR counter++ VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=65] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=65] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=65, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] EXPR counter++ VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=66] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=66] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=66, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] EXPR counter++ VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=67] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=67] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=67, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] EXPR counter++ VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=68] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=68] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=68, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] EXPR counter++ VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=69] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=69] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=69, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] EXPR counter++ VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=70] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=70] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=70, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] EXPR counter++ VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=71] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=71] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=71, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] EXPR counter++ VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=72] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=72] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=72, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] EXPR counter++ VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=73] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=73] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=73, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] EXPR counter++ VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=74] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=74] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=74, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] EXPR counter++ VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=75] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=75] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=75, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] EXPR counter++ VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=76] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=76] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=76, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] EXPR counter++ VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=77] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=77] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=77, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] EXPR counter++ VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=78] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=78] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=78, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] EXPR counter++ VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=79] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=79] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=79, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] EXPR counter++ VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=80] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=80] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=80, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] EXPR counter++ VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=81] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=81] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=81, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] EXPR counter++ VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=82] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=82] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=82, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] EXPR counter++ VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=83] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=83] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=83, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] EXPR counter++ VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=84] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=84] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=84, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] EXPR counter++ VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=85] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=85] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=85, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] EXPR counter++ VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=86] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=86] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=86, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] EXPR counter++ VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=87] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=87] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=87, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] EXPR counter++ VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=88] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=88] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=88, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] EXPR counter++ VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=89] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=89] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=89, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] EXPR counter++ VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=90] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=90] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=90, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] EXPR counter++ VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=91] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=91] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=91, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] EXPR counter++ VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=92] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=92] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=92, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] EXPR counter++ VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=93] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=93] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=93, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] EXPR counter++ VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=94] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=94] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=94, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] EXPR counter++ VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=95] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=95] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=95, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] EXPR counter++ VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=96] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=96] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=96, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] EXPR counter++ VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=97] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=97] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=97, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] EXPR counter++ VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=98] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=98] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=98, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] EXPR counter++ VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=99] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=99] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=99, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] EXPR counter++ VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=100] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, counter=100] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L39] COND FALSE !(!(y3 != 0)) VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=100, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] EXPR counter++ VAL [counter=101, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] COND FALSE !(counter++<100) [L50] CALL __VERIFIER_assert(y1*x2 + y2 == x1) VAL [\old(cond)=0, counter=101] [L16] COND TRUE !(cond) VAL [\old(cond)=0, counter=101] [L18] reach_error() VAL [\old(cond)=0, counter=101] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 25 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 70.2s, OverallIterations: 13, TraceHistogramMax: 101, PathProgramHistogramMax: 7, EmptinessCheckTime: 0.1s, AutomataDifference: 13.4s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2125 SdHoareTripleChecker+Valid, 2.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2122 mSDsluCounter, 2589 SdHoareTripleChecker+Invalid, 1.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2325 mSDsCounter, 192 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1437 IncrementalHoareTripleChecker+Invalid, 1629 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 192 mSolverCounterUnsat, 264 mSDtfsCounter, 1437 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4082 GetRequests, 3392 SyntacticMatches, 92 SemanticMatches, 598 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17699 ImplicationChecksByTransitivity, 26.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=921occurred in iteration=12, InterpolantAutomatonStates: 601, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 12 MinimizatonAttempts, 25 StatesRemovedByMinimization, 5 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 4.7s SatisfiabilityAnalysisTime, 47.3s InterpolantComputationTime, 5519 NumberOfCodeBlocks, 5519 NumberOfCodeBlocksAsserted, 329 NumberOfCheckSat, 5374 ConstructedInterpolants, 0 QuantifiedInterpolants, 13183 SizeOfPredicates, 182 NumberOfNonLiveVariables, 4850 ConjunctsInSsa, 433 ConjunctsInUnsatCore, 29 InterpolantComputations, 4 PerfectInterpolantSequences, 46716/155866 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2024-11-28 03:48:51,723 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d9c4862d-6023-4f85-b063-ca3889e52000/bin/uautomizer-verify-aQ6SnzHsRB/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE