./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash d628f3524885345eb9e2318f2d0dbb026e233c3bcc51319b2ad8fc1a71d35580 --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 11:55:14,496 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 11:55:14,554 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Termination-64bit-Automizer_Default.epf [2024-12-02 11:55:14,559 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 11:55:14,559 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 11:55:14,581 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 11:55:14,582 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 11:55:14,582 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 11:55:14,582 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 11:55:14,583 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 11:55:14,583 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 11:55:14,583 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 11:55:14,583 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 11:55:14,583 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-12-02 11:55:14,583 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-12-02 11:55:14,583 INFO L153 SettingsManager]: * Use old map elimination=false [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-12-02 11:55:14,584 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-12-02 11:55:14,584 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 11:55:14,585 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 11:55:14,585 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL_NO_AM [2024-12-02 11:55:14,585 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-12-02 11:55:14,585 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d628f3524885345eb9e2318f2d0dbb026e233c3bcc51319b2ad8fc1a71d35580 [2024-12-02 11:55:14,834 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 11:55:14,843 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 11:55:14,846 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 11:55:14,847 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 11:55:14,847 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 11:55:14,849 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i [2024-12-02 11:55:17,633 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/data/43c26c7ca/040233e539014871a877c8710d6a0637/FLAG926b5befa [2024-12-02 11:55:17,869 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 11:55:17,870 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/sv-benchmarks/c/termination-memory-alloca/java_Sequence-alloca.i [2024-12-02 11:55:17,881 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/data/43c26c7ca/040233e539014871a877c8710d6a0637/FLAG926b5befa [2024-12-02 11:55:17,895 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/data/43c26c7ca/040233e539014871a877c8710d6a0637 [2024-12-02 11:55:17,897 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 11:55:17,899 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 11:55:17,900 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 11:55:17,900 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 11:55:17,904 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 11:55:17,905 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:55:17" (1/1) ... [2024-12-02 11:55:17,906 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2792a07a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:17, skipping insertion in model container [2024-12-02 11:55:17,906 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:55:17" (1/1) ... [2024-12-02 11:55:17,933 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 11:55:18,142 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:55:18,153 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 11:55:18,183 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:55:18,204 INFO L204 MainTranslator]: Completed translation [2024-12-02 11:55:18,205 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18 WrapperNode [2024-12-02 11:55:18,205 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 11:55:18,206 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 11:55:18,206 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 11:55:18,206 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 11:55:18,212 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,220 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,236 INFO L138 Inliner]: procedures = 109, calls = 25, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 54 [2024-12-02 11:55:18,236 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 11:55:18,237 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 11:55:18,237 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 11:55:18,237 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 11:55:18,245 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,245 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,247 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,257 INFO L175 MemorySlicer]: Split 14 memory accesses to 3 slices as follows [4, 4, 6]. 43 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0, 0, 0]. The 7 writes are split as follows [2, 2, 3]. [2024-12-02 11:55:18,257 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,257 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,261 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,261 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,263 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,264 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,265 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,266 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 11:55:18,267 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 11:55:18,267 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 11:55:18,267 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 11:55:18,268 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (1/1) ... [2024-12-02 11:55:18,273 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:18,284 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:18,296 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:18,298 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2024-12-02 11:55:18,322 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 11:55:18,322 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 11:55:18,409 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 11:55:18,410 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 11:55:18,514 INFO L? ?]: Removed 9 outVars from TransFormulas that were not future-live. [2024-12-02 11:55:18,514 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 11:55:18,522 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 11:55:18,522 INFO L312 CfgBuilder]: Removed 2 assume(true) statements. [2024-12-02 11:55:18,522 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:55:18 BoogieIcfgContainer [2024-12-02 11:55:18,522 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 11:55:18,523 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-12-02 11:55:18,523 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-12-02 11:55:18,528 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-12-02 11:55:18,529 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-12-02 11:55:18,529 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.12 11:55:17" (1/3) ... [2024-12-02 11:55:18,530 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4faae2ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.12 11:55:18, skipping insertion in model container [2024-12-02 11:55:18,530 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-12-02 11:55:18,530 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:55:18" (2/3) ... [2024-12-02 11:55:18,530 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4faae2ad and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.12 11:55:18, skipping insertion in model container [2024-12-02 11:55:18,530 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-12-02 11:55:18,530 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:55:18" (3/3) ... [2024-12-02 11:55:18,531 INFO L363 chiAutomizerObserver]: Analyzing ICFG java_Sequence-alloca.i [2024-12-02 11:55:18,576 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-12-02 11:55:18,576 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-12-02 11:55:18,576 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-12-02 11:55:18,576 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-12-02 11:55:18,576 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-12-02 11:55:18,577 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-12-02 11:55:18,577 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-12-02 11:55:18,577 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-12-02 11:55:18,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:18,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-12-02 11:55:18,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:18,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:18,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-12-02 11:55:18,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:18,601 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-12-02 11:55:18,601 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:18,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2024-12-02 11:55:18,602 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:18,602 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:18,602 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2024-12-02 11:55:18,602 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:18,609 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" [2024-12-02 11:55:18,609 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" [2024-12-02 11:55:18,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:18,614 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2024-12-02 11:55:18,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:18,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574056114] [2024-12-02 11:55:18,621 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:18,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:18,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,732 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:18,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:18,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:18,767 INFO L85 PathProgramCache]: Analyzing trace with hash 35849, now seen corresponding path program 1 times [2024-12-02 11:55:18,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:18,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63863335] [2024-12-02 11:55:18,767 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:18,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:18,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,781 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:18,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,791 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:18,792 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:18,793 INFO L85 PathProgramCache]: Analyzing trace with hash 28694791, now seen corresponding path program 1 times [2024-12-02 11:55:18,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:18,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713181928] [2024-12-02 11:55:18,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:18,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:18,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,825 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:18,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:18,846 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:19,396 INFO L204 LassoAnalysis]: Preferences: [2024-12-02 11:55:19,397 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2024-12-02 11:55:19,397 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2024-12-02 11:55:19,397 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2024-12-02 11:55:19,397 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2024-12-02 11:55:19,397 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:19,397 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2024-12-02 11:55:19,397 INFO L131 ssoRankerPreferences]: Path of dumped script: [2024-12-02 11:55:19,398 INFO L132 ssoRankerPreferences]: Filename of dumped script: java_Sequence-alloca.i_Iteration1_Lasso [2024-12-02 11:55:19,398 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2024-12-02 11:55:19,398 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2024-12-02 11:55:19,411 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,425 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,429 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,438 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,441 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,444 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,446 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:19,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2024-12-02 11:55:20,149 INFO L259 LassoAnalysis]: Preprocessing complete. [2024-12-02 11:55:20,153 INFO L451 LassoAnalysis]: Using template 'affine'. [2024-12-02 11:55:20,155 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,155 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,157 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,159 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2024-12-02 11:55:20,160 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,173 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,173 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,174 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,174 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,174 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,179 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,179 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,181 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,187 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2024-12-02 11:55:20,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,187 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,189 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,189 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2024-12-02 11:55:20,191 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,202 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,202 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,202 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,202 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,202 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,203 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,203 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,205 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,210 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2024-12-02 11:55:20,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,210 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,212 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,213 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2024-12-02 11:55:20,214 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,225 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,225 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,225 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,225 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,225 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,226 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,226 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,227 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,233 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2024-12-02 11:55:20,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,233 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,235 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2024-12-02 11:55:20,237 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,250 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,250 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,250 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,250 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,250 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,250 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,250 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,252 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,260 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2024-12-02 11:55:20,260 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,260 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,262 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2024-12-02 11:55:20,265 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,277 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,278 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,278 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,278 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,281 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,281 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,286 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,294 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2024-12-02 11:55:20,294 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,295 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,296 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,297 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2024-12-02 11:55:20,298 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,309 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,309 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,309 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,310 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,312 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,312 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,316 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,322 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2024-12-02 11:55:20,322 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,322 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,324 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,325 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2024-12-02 11:55:20,326 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,338 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,338 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,338 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,338 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,340 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,341 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,344 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,350 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2024-12-02 11:55:20,351 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,351 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,352 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,353 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2024-12-02 11:55:20,354 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,365 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,365 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,365 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,365 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,365 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,366 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,366 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,367 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,372 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2024-12-02 11:55:20,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,375 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2024-12-02 11:55:20,377 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,388 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,388 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,388 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,388 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,388 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,389 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,389 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,390 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,395 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2024-12-02 11:55:20,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,395 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,397 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,397 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2024-12-02 11:55:20,399 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,410 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,410 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,410 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,410 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,410 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,410 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,411 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,412 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,418 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2024-12-02 11:55:20,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,418 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,420 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2024-12-02 11:55:20,422 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,434 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,434 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,434 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,434 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,437 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,437 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,441 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,448 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2024-12-02 11:55:20,449 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,450 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2024-12-02 11:55:20,453 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,463 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,463 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2024-12-02 11:55:20,464 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,464 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,464 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,464 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2024-12-02 11:55:20,464 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2024-12-02 11:55:20,466 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,473 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2024-12-02 11:55:20,473 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,474 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,475 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2024-12-02 11:55:20,477 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,491 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,491 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,491 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,491 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,496 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,496 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,502 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,510 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2024-12-02 11:55:20,510 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,512 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,512 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2024-12-02 11:55:20,514 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,528 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,528 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,528 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,528 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,531 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,531 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,538 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,546 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2024-12-02 11:55:20,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,546 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,548 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,549 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2024-12-02 11:55:20,551 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,563 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,563 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,563 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,563 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,565 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,565 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,569 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2024-12-02 11:55:20,577 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2024-12-02 11:55:20,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,578 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,579 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2024-12-02 11:55:20,582 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2024-12-02 11:55:20,595 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2024-12-02 11:55:20,595 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2024-12-02 11:55:20,596 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2024-12-02 11:55:20,596 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2024-12-02 11:55:20,600 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2024-12-02 11:55:20,600 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2024-12-02 11:55:20,608 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2024-12-02 11:55:20,621 INFO L443 ModelExtractionUtils]: Simplification made 5 calls to the SMT solver. [2024-12-02 11:55:20,623 INFO L444 ModelExtractionUtils]: 3 out of 10 variables were initially zero. Simplification set additionally 4 variables to zero. [2024-12-02 11:55:20,624 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-12-02 11:55:20,624 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:20,626 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-12-02 11:55:20,628 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2024-12-02 11:55:20,628 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2024-12-02 11:55:20,640 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2024-12-02 11:55:20,641 INFO L474 LassoAnalysis]: Proved termination. [2024-12-02 11:55:20,641 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select (select #memory_int#1 ULTIMATE.start_main_~i~0#1.base) ULTIMATE.start_main_~i~0#1.offset)_1) = -2*v_rep(select (select #memory_int#1 ULTIMATE.start_main_~i~0#1.base) ULTIMATE.start_main_~i~0#1.offset)_1 + 199 Supporting invariants [] [2024-12-02 11:55:20,646 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2024-12-02 11:55:20,694 INFO L156 tatePredicateManager]: 16 out of 16 supporting invariants were superfluous and have been removed [2024-12-02 11:55:20,700 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #memory_int#1 [2024-12-02 11:55:20,701 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#memory_int#1,GLOBAL] [2024-12-02 11:55:20,701 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array ArrayAccessExpression[IdentifierExpression[#memory_int#1,GLOBAL],[IdentifierExpression[~i~0!base,]]] [2024-12-02 11:55:20,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:20,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:20,741 INFO L256 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 2 conjuncts are in the unsatisfiable core [2024-12-02 11:55:20,742 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:20,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:20,762 INFO L256 TraceCheckSpWp]: Trace formula consists of 27 conjuncts, 7 conjuncts are in the unsatisfiable core [2024-12-02 11:55:20,763 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:20,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-12-02 11:55:20,839 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2024-12-02 11:55:20,840 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:20,910 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.3333333333333333) internal successors, (16), 12 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 30 states and 37 transitions. Complement of second has 10 states. [2024-12-02 11:55:20,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 6 states 1 stem states 3 non-accepting loop states 1 accepting loop states [2024-12-02 11:55:20,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:20,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 23 transitions. [2024-12-02 11:55:20,922 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 2 letters. Loop has 3 letters. [2024-12-02 11:55:20,923 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-12-02 11:55:20,923 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 5 letters. Loop has 3 letters. [2024-12-02 11:55:20,923 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-12-02 11:55:20,923 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 6 states and 23 transitions. Stem has 2 letters. Loop has 6 letters. [2024-12-02 11:55:20,923 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2024-12-02 11:55:20,924 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 37 transitions. [2024-12-02 11:55:20,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:20,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 11 states and 13 transitions. [2024-12-02 11:55:20,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2024-12-02 11:55:20,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:20,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 13 transitions. [2024-12-02 11:55:20,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:20,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-12-02 11:55:20,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 13 transitions. [2024-12-02 11:55:20,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2024-12-02 11:55:20,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.1818181818181819) internal successors, (13), 10 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:20,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 13 transitions. [2024-12-02 11:55:20,951 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-12-02 11:55:20,951 INFO L425 stractBuchiCegarLoop]: Abstraction has 11 states and 13 transitions. [2024-12-02 11:55:20,951 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-12-02 11:55:20,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 13 transitions. [2024-12-02 11:55:20,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:20,952 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:20,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:20,952 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2024-12-02 11:55:20,952 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:20,952 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:20,952 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:20,953 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:20,953 INFO L85 PathProgramCache]: Analyzing trace with hash 28694857, now seen corresponding path program 1 times [2024-12-02 11:55:20,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:20,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690685844] [2024-12-02 11:55:20,953 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:20,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:20,993 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2024-12-02 11:55:20,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:21,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:21,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690685844] [2024-12-02 11:55:21,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690685844] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:21,130 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [729330511] [2024-12-02 11:55:21,130 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:21,130 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:21,130 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:21,132 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:21,133 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2024-12-02 11:55:21,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:21,192 INFO L256 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 4 conjuncts are in the unsatisfiable core [2024-12-02 11:55:21,193 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:21,212 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:21,230 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:21,252 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [729330511] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:21,252 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:21,252 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2024-12-02 11:55:21,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1611700964] [2024-12-02 11:55:21,253 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:21,254 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:21,255 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:21,255 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 1 times [2024-12-02 11:55:21,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:21,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71034620] [2024-12-02 11:55:21,255 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:21,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:21,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:21,264 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:21,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:21,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:21,370 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:21,371 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 11:55:21,372 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:55:21,373 INFO L87 Difference]: Start difference. First operand 11 states and 13 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 1.4285714285714286) internal successors, (10), 7 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:21,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:21,422 INFO L93 Difference]: Finished difference Result 18 states and 19 transitions. [2024-12-02 11:55:21,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 19 transitions. [2024-12-02 11:55:21,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:21,424 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 16 states and 17 transitions. [2024-12-02 11:55:21,424 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:21,424 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:21,424 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 17 transitions. [2024-12-02 11:55:21,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:21,425 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16 states and 17 transitions. [2024-12-02 11:55:21,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 17 transitions. [2024-12-02 11:55:21,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 14. [2024-12-02 11:55:21,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 13 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:21,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2024-12-02 11:55:21,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 15 transitions. [2024-12-02 11:55:21,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:55:21,427 INFO L425 stractBuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2024-12-02 11:55:21,427 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-12-02 11:55:21,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 15 transitions. [2024-12-02 11:55:21,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:21,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:21,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:21,429 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 1, 1, 1, 1] [2024-12-02 11:55:21,429 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:21,429 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:21,429 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:21,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:21,429 INFO L85 PathProgramCache]: Analyzing trace with hash -885219383, now seen corresponding path program 1 times [2024-12-02 11:55:21,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:21,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652143750] [2024-12-02 11:55:21,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:21,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:21,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:21,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:21,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652143750] [2024-12-02 11:55:21,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652143750] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:21,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1245270583] [2024-12-02 11:55:21,792 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:21,792 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:21,792 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:21,794 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:21,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2024-12-02 11:55:21,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:21,876 INFO L256 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 10 conjuncts are in the unsatisfiable core [2024-12-02 11:55:21,878 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:21,885 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:21,906 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-12-02 11:55:21,920 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:21,930 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-12-02 11:55:21,935 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:22,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1245270583] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:22,001 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:22,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 6, 6] total 13 [2024-12-02 11:55:22,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [751712757] [2024-12-02 11:55:22,001 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:22,001 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:22,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:22,002 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 2 times [2024-12-02 11:55:22,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:22,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [340575649] [2024-12-02 11:55:22,002 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:22,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:22,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:22,009 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:22,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:22,013 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:22,093 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:22,093 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 11:55:22,093 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=94, Unknown=0, NotChecked=0, Total=156 [2024-12-02 11:55:22,094 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:22,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:22,176 INFO L93 Difference]: Finished difference Result 32 states and 33 transitions. [2024-12-02 11:55:22,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 33 transitions. [2024-12-02 11:55:22,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:22,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 28 states and 29 transitions. [2024-12-02 11:55:22,178 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:22,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:22,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 29 transitions. [2024-12-02 11:55:22,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:22,178 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 29 transitions. [2024-12-02 11:55:22,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 29 transitions. [2024-12-02 11:55:22,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 26. [2024-12-02 11:55:22,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.0384615384615385) internal successors, (27), 25 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:22,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2024-12-02 11:55:22,180 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 27 transitions. [2024-12-02 11:55:22,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2024-12-02 11:55:22,181 INFO L425 stractBuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2024-12-02 11:55:22,181 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-12-02 11:55:22,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 27 transitions. [2024-12-02 11:55:22,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:22,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:22,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:22,183 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 6, 6, 1, 1, 1, 1] [2024-12-02 11:55:22,183 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:22,183 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:22,183 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:22,183 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:22,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1505391415, now seen corresponding path program 2 times [2024-12-02 11:55:22,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:22,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126246682] [2024-12-02 11:55:22,183 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:22,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:22,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:22,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:22,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1126246682] [2024-12-02 11:55:22,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1126246682] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:22,992 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1806307305] [2024-12-02 11:55:22,992 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:22,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:22,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:22,994 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:22,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2024-12-02 11:55:23,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:23,083 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 11:55:23,088 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:23,092 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:23,109 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-12-02 11:55:23,120 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:23,135 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:23,148 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:23,166 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:23,180 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:23,189 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-12-02 11:55:23,193 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:23,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1806307305] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:23,354 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:23,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 10, 10] total 25 [2024-12-02 11:55:23,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071172548] [2024-12-02 11:55:23,354 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:23,354 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:23,355 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:23,355 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 3 times [2024-12-02 11:55:23,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:23,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [79060625] [2024-12-02 11:55:23,355 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:23,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:23,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:23,362 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:23,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:23,366 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:23,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:23,450 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2024-12-02 11:55:23,451 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=250, Invalid=350, Unknown=0, NotChecked=0, Total=600 [2024-12-02 11:55:23,451 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 2.28) internal successors, (57), 25 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:23,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:23,682 INFO L93 Difference]: Finished difference Result 60 states and 61 transitions. [2024-12-02 11:55:23,682 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 61 transitions. [2024-12-02 11:55:23,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:23,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 52 states and 53 transitions. [2024-12-02 11:55:23,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:23,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:23,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 53 transitions. [2024-12-02 11:55:23,685 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:23,685 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 53 transitions. [2024-12-02 11:55:23,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 53 transitions. [2024-12-02 11:55:23,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 50. [2024-12-02 11:55:23,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.02) internal successors, (51), 49 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:23,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2024-12-02 11:55:23,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 51 transitions. [2024-12-02 11:55:23,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2024-12-02 11:55:23,689 INFO L425 stractBuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2024-12-02 11:55:23,689 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-12-02 11:55:23,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 51 transitions. [2024-12-02 11:55:23,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:23,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:23,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:23,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 14, 14, 1, 1, 1, 1] [2024-12-02 11:55:23,692 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:23,692 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:23,692 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:23,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:23,692 INFO L85 PathProgramCache]: Analyzing trace with hash 2091181769, now seen corresponding path program 3 times [2024-12-02 11:55:23,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:23,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551281502] [2024-12-02 11:55:23,693 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:23,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:23,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:25,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:25,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551281502] [2024-12-02 11:55:25,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551281502] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:25,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1722213065] [2024-12-02 11:55:25,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:25,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:25,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:25,795 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:25,795 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2024-12-02 11:55:25,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:25,930 INFO L256 TraceCheckSpWp]: Trace formula consists of 430 conjuncts, 46 conjuncts are in the unsatisfiable core [2024-12-02 11:55:25,938 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:25,942 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:25,957 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-12-02 11:55:25,968 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:25,980 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:25,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,010 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,026 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,038 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,051 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,063 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,076 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,088 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,104 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,117 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,129 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:26,135 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-12-02 11:55:26,138 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:26,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1722213065] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:26,671 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:26,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 18, 18] total 49 [2024-12-02 11:55:26,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [511887420] [2024-12-02 11:55:26,671 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:26,672 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:26,672 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:26,672 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 4 times [2024-12-02 11:55:26,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:26,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340330383] [2024-12-02 11:55:26,672 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:26,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:26,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:26,677 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:26,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:26,681 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:26,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:26,762 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2024-12-02 11:55:26,763 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1010, Invalid=1342, Unknown=0, NotChecked=0, Total=2352 [2024-12-02 11:55:26,763 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 2.4693877551020407) internal successors, (121), 49 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:27,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:27,307 INFO L93 Difference]: Finished difference Result 116 states and 117 transitions. [2024-12-02 11:55:27,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 116 states and 117 transitions. [2024-12-02 11:55:27,309 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:27,310 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 116 states to 100 states and 101 transitions. [2024-12-02 11:55:27,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:27,310 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:27,310 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 101 transitions. [2024-12-02 11:55:27,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:27,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 101 transitions. [2024-12-02 11:55:27,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 101 transitions. [2024-12-02 11:55:27,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 98. [2024-12-02 11:55:27,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.010204081632653) internal successors, (99), 97 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:27,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 99 transitions. [2024-12-02 11:55:27,314 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 99 transitions. [2024-12-02 11:55:27,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2024-12-02 11:55:27,315 INFO L425 stractBuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2024-12-02 11:55:27,315 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-12-02 11:55:27,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 99 transitions. [2024-12-02 11:55:27,316 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:27,316 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:27,316 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:27,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 30, 30, 1, 1, 1, 1] [2024-12-02 11:55:27,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:27,318 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:27,318 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:27,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:27,318 INFO L85 PathProgramCache]: Analyzing trace with hash 1033476809, now seen corresponding path program 4 times [2024-12-02 11:55:27,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:27,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845640330] [2024-12-02 11:55:27,318 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:27,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:27,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:32,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:32,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845640330] [2024-12-02 11:55:32,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845640330] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:32,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1092240784] [2024-12-02 11:55:32,119 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:32,119 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:32,119 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:32,120 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:32,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2024-12-02 11:55:32,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:32,296 INFO L256 TraceCheckSpWp]: Trace formula consists of 830 conjuncts, 94 conjuncts are in the unsatisfiable core [2024-12-02 11:55:32,306 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:32,308 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:32,319 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-12-02 11:55:32,326 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,335 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,343 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,351 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,360 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,368 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,382 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,389 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,397 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,405 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,412 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,419 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,426 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,433 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,441 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,449 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,456 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,463 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,471 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,479 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,488 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,497 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,505 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,514 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,521 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,529 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,537 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,545 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:32,553 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-12-02 11:55:32,555 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:33,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1092240784] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:33,989 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:33,989 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 34, 34] total 97 [2024-12-02 11:55:33,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783297002] [2024-12-02 11:55:33,990 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:33,990 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:33,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:33,990 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 5 times [2024-12-02 11:55:33,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:33,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037325302] [2024-12-02 11:55:33,991 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:33,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:33,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:33,995 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:33,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:33,998 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:34,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:34,066 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2024-12-02 11:55:34,069 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=4066, Invalid=5246, Unknown=0, NotChecked=0, Total=9312 [2024-12-02 11:55:34,069 INFO L87 Difference]: Start difference. First operand 98 states and 99 transitions. cyclomatic complexity: 3 Second operand has 97 states, 97 states have (on average 2.5670103092783507) internal successors, (249), 97 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:35,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:35,482 INFO L93 Difference]: Finished difference Result 228 states and 229 transitions. [2024-12-02 11:55:35,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228 states and 229 transitions. [2024-12-02 11:55:35,485 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:35,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228 states to 196 states and 197 transitions. [2024-12-02 11:55:35,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:35,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:35,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 197 transitions. [2024-12-02 11:55:35,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:35,486 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 197 transitions. [2024-12-02 11:55:35,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 197 transitions. [2024-12-02 11:55:35,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2024-12-02 11:55:35,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 194 states, 194 states have (on average 1.0051546391752577) internal successors, (195), 193 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:35,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 195 transitions. [2024-12-02 11:55:35,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 194 states and 195 transitions. [2024-12-02 11:55:35,495 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 126 states. [2024-12-02 11:55:35,496 INFO L425 stractBuchiCegarLoop]: Abstraction has 194 states and 195 transitions. [2024-12-02 11:55:35,496 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-12-02 11:55:35,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 194 states and 195 transitions. [2024-12-02 11:55:35,497 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:35,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:35,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:35,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [63, 62, 62, 1, 1, 1, 1] [2024-12-02 11:55:35,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:35,501 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:35,501 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:35,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:35,502 INFO L85 PathProgramCache]: Analyzing trace with hash -1470430519, now seen corresponding path program 5 times [2024-12-02 11:55:35,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:35,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438528771] [2024-12-02 11:55:35,502 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:35,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:35,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:51,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace [2024-12-02 11:55:51,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438528771] [2024-12-02 11:55:51,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438528771] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:55:51,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [613969473] [2024-12-02 11:55:51,858 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:51,858 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:55:51,858 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:55:51,860 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:55:51,861 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_6de23ed1-5508-4588-9727-44d439a93d30/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2024-12-02 11:55:52,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:55:52,153 INFO L256 TraceCheckSpWp]: Trace formula consists of 1630 conjuncts, 190 conjuncts are in the unsatisfiable core [2024-12-02 11:55:52,169 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:55:52,171 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 7 [2024-12-02 11:55:52,180 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 3 [2024-12-02 11:55:52,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,195 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,202 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,210 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,215 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,221 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,227 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,234 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,241 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,249 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,264 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,272 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,279 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,287 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,294 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,301 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,309 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,317 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,325 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,331 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,337 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,345 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,352 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,359 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,368 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,376 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,384 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,393 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,402 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,410 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,418 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,425 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,433 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,439 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,447 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,454 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,462 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,471 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,479 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,487 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,495 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,503 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,511 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,519 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,528 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,536 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,545 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,553 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,561 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,567 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,573 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,578 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,584 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,590 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,598 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,606 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,613 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,621 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,630 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,637 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 13 [2024-12-02 11:55:52,641 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 7 [2024-12-02 11:55:52,643 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:55:56,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [613969473] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:55:56,387 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:55:56,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [129, 66, 66] total 167 [2024-12-02 11:55:56,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1101415194] [2024-12-02 11:55:56,388 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:55:56,388 INFO L752 eck$LassoCheckResult]: stem already infeasible [2024-12-02 11:55:56,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:56,389 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 6 times [2024-12-02 11:55:56,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:56,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648791817] [2024-12-02 11:55:56,389 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:56,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:56,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:56,392 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:56,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:56,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:55:56,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM [2024-12-02 11:55:56,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 167 interpolants. [2024-12-02 11:55:56,455 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11707, Invalid=16015, Unknown=0, NotChecked=0, Total=27722 [2024-12-02 11:55:56,455 INFO L87 Difference]: Start difference. First operand 194 states and 195 transitions. cyclomatic complexity: 3 Second operand has 167 states, 167 states have (on average 2.5748502994011977) internal successors, (430), 167 states have internal predecessors, (430), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:59,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:55:59,399 INFO L93 Difference]: Finished difference Result 348 states and 349 transitions. [2024-12-02 11:55:59,399 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 349 transitions. [2024-12-02 11:55:59,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:59,403 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 310 states and 311 transitions. [2024-12-02 11:55:59,403 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2024-12-02 11:55:59,403 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2024-12-02 11:55:59,403 INFO L73 IsDeterministic]: Start isDeterministic. Operand 310 states and 311 transitions. [2024-12-02 11:55:59,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2024-12-02 11:55:59,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 310 states and 311 transitions. [2024-12-02 11:55:59,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states and 311 transitions. [2024-12-02 11:55:59,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 308. [2024-12-02 11:55:59,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 308 states, 308 states have (on average 1.0032467532467533) internal successors, (309), 307 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-12-02 11:55:59,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 309 transitions. [2024-12-02 11:55:59,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 308 states and 309 transitions. [2024-12-02 11:55:59,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2024-12-02 11:55:59,416 INFO L425 stractBuchiCegarLoop]: Abstraction has 308 states and 309 transitions. [2024-12-02 11:55:59,416 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-12-02 11:55:59,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 308 states and 309 transitions. [2024-12-02 11:55:59,417 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2024-12-02 11:55:59,417 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-12-02 11:55:59,417 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-12-02 11:55:59,422 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [101, 100, 100, 1, 1, 1, 1] [2024-12-02 11:55:59,422 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2024-12-02 11:55:59,422 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc2#1.base, main_#t~malloc2#1.offset, main_#t~malloc3#1.base, main_#t~malloc3#1.offset, main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~mem5#1, main_#t~mem6#1, main_#t~mem7#1, main_#t~post8#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem11#1, main_#t~mem12#1, main_~i~0#1.base, main_~i~0#1.offset, main_~j~0#1.base, main_~j~0#1.offset, main_~c~0#1.base, main_~c~0#1.offset;call main_#t~malloc2#1.base, main_#t~malloc2#1.offset := #Ultimate.allocOnStack(4);main_~i~0#1.base, main_~i~0#1.offset := main_#t~malloc2#1.base, main_#t~malloc2#1.offset;call main_#t~malloc3#1.base, main_#t~malloc3#1.offset := #Ultimate.allocOnStack(4);main_~j~0#1.base, main_~j~0#1.offset := main_#t~malloc3#1.base, main_#t~malloc3#1.offset;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnStack(4);main_~c~0#1.base, main_~c~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;call write~int#2(0, main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#1(0, main_~i~0#1.base, main_~i~0#1.offset, 4);" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume main_#t~mem5#1 < 100;havoc main_#t~mem5#1;" "call main_#t~mem6#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem6#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem7#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);main_#t~post8#1 := main_#t~mem7#1;call write~int#1(1 + main_#t~post8#1, main_~i~0#1.base, main_~i~0#1.offset, 4);havoc main_#t~mem7#1;havoc main_#t~post8#1;" "call main_#t~mem5#1 := read~int#1(main_~i~0#1.base, main_~i~0#1.offset, 4);" "assume !(main_#t~mem5#1 < 100);havoc main_#t~mem5#1;" "call write~int#0(5, main_~j~0#1.base, main_~j~0#1.offset, 4);" [2024-12-02 11:55:59,422 INFO L749 eck$LassoCheckResult]: Loop: "call main_#t~mem9#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);" "assume main_#t~mem9#1 < 21;havoc main_#t~mem9#1;" "call main_#t~mem10#1 := read~int#2(main_~c~0#1.base, main_~c~0#1.offset, 4);call write~int#2(1 + main_#t~mem10#1, main_~c~0#1.base, main_~c~0#1.offset, 4);call main_#t~mem11#1 := read~int#0(main_~j~0#1.base, main_~j~0#1.offset, 4);call write~int#0(3 + main_#t~mem11#1, main_~j~0#1.base, main_~j~0#1.offset, 4);havoc main_#t~mem11#1;" [2024-12-02 11:55:59,422 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:55:59,423 INFO L85 PathProgramCache]: Analyzing trace with hash 1507507785, now seen corresponding path program 6 times [2024-12-02 11:55:59,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:55:59,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547903020] [2024-12-02 11:55:59,423 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:55:59,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:55:59,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:55:59,737 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:55:59,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:56:00,067 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:56:00,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:56:00,068 INFO L85 PathProgramCache]: Analyzing trace with hash 50744, now seen corresponding path program 7 times [2024-12-02 11:56:00,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:56:00,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474633562] [2024-12-02 11:56:00,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:56:00,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:56:00,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:56:00,073 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:56:00,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:56:00,077 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace [2024-12-02 11:56:00,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:56:00,078 INFO L85 PathProgramCache]: Analyzing trace with hash 1986396912, now seen corresponding path program 1 times [2024-12-02 11:56:00,078 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM [2024-12-02 11:56:00,078 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208086119] [2024-12-02 11:56:00,078 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:56:00,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:56:00,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:56:00,458 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:56:00,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:56:00,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace