./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit
--------------------------------------------------------------------------------
Checking for termination
Using default analysis
Version d790fecc
Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )
--witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f
--- Real Ultimate output ---
This is Ultimate 0.3.0-dev-d790fec
[2024-12-02 06:15:09,533 INFO L188 SettingsManager]: Resetting all preferences to default values...
[2024-12-02 06:15:09,595 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Termination-32bit-Automizer_Default.epf
[2024-12-02 06:15:09,600 WARN L101 SettingsManager]: Preference file contains the following unknown settings:
[2024-12-02 06:15:09,600 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2024-12-02 06:15:09,623 INFO L130 SettingsManager]: Preferences different from defaults after loading the file:
[2024-12-02 06:15:09,623 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2024-12-02 06:15:09,624 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2024-12-02 06:15:09,624 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2024-12-02 06:15:09,624 INFO L153 SettingsManager]: * Use memory slicer=true
[2024-12-02 06:15:09,624 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2024-12-02 06:15:09,624 INFO L153 SettingsManager]: * Create parallel compositions if possible=false
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Use SBE=true
[2024-12-02 06:15:09,625 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Use old map elimination=false
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES
[2024-12-02 06:15:09,625 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME
[2024-12-02 06:15:09,625 INFO L153 SettingsManager]: * sizeof long=4
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * sizeof POINTER=4
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Check division by zero=IGNORE
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * sizeof long double=12
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Check if freed pointer was valid=false
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2024-12-02 06:15:09,626 INFO L153 SettingsManager]: * Use constant arrays=true
[2024-12-02 06:15:09,627 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults:
[2024-12-02 06:15:09,627 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements
[2024-12-02 06:15:09,627 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2024-12-02 06:15:09,627 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL_NO_AM
[2024-12-02 06:15:09,627 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2024-12-02 06:15:09,627 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f
[2024-12-02 06:15:09,884 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp
[2024-12-02 06:15:09,897 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2024-12-02 06:15:09,900 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2024-12-02 06:15:09,901 INFO L270 PluginConnector]: Initializing CDTParser...
[2024-12-02 06:15:09,902 INFO L274 PluginConnector]: CDTParser initialized
[2024-12-02 06:15:09,903 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/systemc/transmitter.05.cil.c
[2024-12-02 06:15:12,615 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/data/4da824f23/050bbcdbcff541d2981faa06aeed5816/FLAG0957719fd
[2024-12-02 06:15:12,812 INFO L384 CDTParser]: Found 1 translation units.
[2024-12-02 06:15:12,813 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/sv-benchmarks/c/systemc/transmitter.05.cil.c
[2024-12-02 06:15:12,822 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/data/4da824f23/050bbcdbcff541d2981faa06aeed5816/FLAG0957719fd
[2024-12-02 06:15:12,833 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/data/4da824f23/050bbcdbcff541d2981faa06aeed5816
[2024-12-02 06:15:12,835 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2024-12-02 06:15:12,836 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements.
[2024-12-02 06:15:12,837 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2024-12-02 06:15:12,837 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator...
[2024-12-02 06:15:12,842 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized
[2024-12-02 06:15:12,842 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:15:12" (1/1) ...
[2024-12-02 06:15:12,843 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@34782211 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:12, skipping insertion in model container
[2024-12-02 06:15:12,844 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 06:15:12" (1/1) ...
[2024-12-02 06:15:12,866 INFO L175 MainTranslator]: Built tables and reachable declarations
[2024-12-02 06:15:13,051 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-12-02 06:15:13,063 INFO L200 MainTranslator]: Completed pre-run
[2024-12-02 06:15:13,099 INFO L210 PostProcessor]: Analyzing one entry point: main
[2024-12-02 06:15:13,114 INFO L204 MainTranslator]: Completed translation
[2024-12-02 06:15:13,114 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13 WrapperNode
[2024-12-02 06:15:13,114 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2024-12-02 06:15:13,115 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2024-12-02 06:15:13,115 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner...
[2024-12-02 06:15:13,115 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized
[2024-12-02 06:15:13,120 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,126 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,161 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1232
[2024-12-02 06:15:13,162 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2024-12-02 06:15:13,162 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2024-12-02 06:15:13,162 INFO L270 PluginConnector]: Initializing Boogie Preprocessor...
[2024-12-02 06:15:13,162 INFO L274 PluginConnector]: Boogie Preprocessor initialized
[2024-12-02 06:15:13,171 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,171 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,175 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,191 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2024-12-02 06:15:13,191 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,191 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,203 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,205 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,216 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,218 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,221 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,226 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2024-12-02 06:15:13,227 INFO L112 PluginConnector]: ------------------------RCFGBuilder----------------------------
[2024-12-02 06:15:13,227 INFO L270 PluginConnector]: Initializing RCFGBuilder...
[2024-12-02 06:15:13,227 INFO L274 PluginConnector]: RCFGBuilder initialized
[2024-12-02 06:15:13,228 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (1/1) ...
[2024-12-02 06:15:13,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2024-12-02 06:15:13,246 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:13,260 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2024-12-02 06:15:13,262 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2024-12-02 06:15:13,287 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2024-12-02 06:15:13,287 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0
[2024-12-02 06:15:13,287 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2024-12-02 06:15:13,287 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2024-12-02 06:15:13,364 INFO L234 CfgBuilder]: Building ICFG
[2024-12-02 06:15:13,366 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation
[2024-12-02 06:15:14,152 INFO L? ?]: Removed 228 outVars from TransFormulas that were not future-live.
[2024-12-02 06:15:14,153 INFO L283 CfgBuilder]: Performing block encoding
[2024-12-02 06:15:14,173 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2024-12-02 06:15:14,174 INFO L312 CfgBuilder]: Removed 18 assume(true) statements.
[2024-12-02 06:15:14,174 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:15:14 BoogieIcfgContainer
[2024-12-02 06:15:14,174 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder----------------------------
[2024-12-02 06:15:14,175 INFO L112 PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2024-12-02 06:15:14,175 INFO L270 PluginConnector]: Initializing BuchiAutomizer...
[2024-12-02 06:15:14,181 INFO L274 PluginConnector]: BuchiAutomizer initialized
[2024-12-02 06:15:14,181 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-12-02 06:15:14,182 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 02.12 06:15:12" (1/3) ...
[2024-12-02 06:15:14,182 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15fb76a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.12 06:15:14, skipping insertion in model container
[2024-12-02 06:15:14,182 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-12-02 06:15:14,183 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 06:15:13" (2/3) ...
[2024-12-02 06:15:14,183 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15fb76a8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 02.12 06:15:14, skipping insertion in model container
[2024-12-02 06:15:14,183 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2024-12-02 06:15:14,183 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:15:14" (3/3) ...
[2024-12-02 06:15:14,184 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c
[2024-12-02 06:15:14,232 INFO L300 stractBuchiCegarLoop]: Interprodecural is true
[2024-12-02 06:15:14,232 INFO L301 stractBuchiCegarLoop]: Hoare is None
[2024-12-02 06:15:14,232 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2024-12-02 06:15:14,233 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2024-12-02 06:15:14,233 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2024-12-02 06:15:14,233 INFO L305 stractBuchiCegarLoop]: Difference is false
[2024-12-02 06:15:14,233 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2024-12-02 06:15:14,233 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2024-12-02 06:15:14,240 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 503 states, 502 states have (on average 1.5358565737051793) internal successors, (771), 502 states have internal predecessors, (771), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:14,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 422
[2024-12-02 06:15:14,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:14,271 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:14,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:14,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:14,280 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============
[2024-12-02 06:15:14,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 503 states, 502 states have (on average 1.5358565737051793) internal successors, (771), 502 states have internal predecessors, (771), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:14,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 422
[2024-12-02 06:15:14,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:14,293 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:14,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:14,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:14,302 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:14,303 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:14,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:14,309 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times
[2024-12-02 06:15:14,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:14,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010896603]
[2024-12-02 06:15:14,315 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:14,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:14,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:14,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:14,504 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1010896603]
[2024-12-02 06:15:14,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1010896603] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:14,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1227527715]
[2024-12-02 06:15:14,505 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:14,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:14,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:14,507 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:14,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process
[2024-12-02 06:15:14,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:14,606 INFO L256 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:14,610 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:14,703 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:14,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1227527715] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:14,791 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:14,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4
[2024-12-02 06:15:14,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454706165]
[2024-12-02 06:15:14,793 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:14,796 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:14,797 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:14,797 INFO L85 PathProgramCache]: Analyzing trace with hash -506614783, now seen corresponding path program 1 times
[2024-12-02 06:15:14,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:14,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114465779]
[2024-12-02 06:15:14,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:14,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:14,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:14,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:14,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114465779]
[2024-12-02 06:15:14,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114465779] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:14,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1584948130]
[2024-12-02 06:15:14,837 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:14,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:14,838 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:14,839 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:14,844 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process
[2024-12-02 06:15:14,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:14,924 INFO L256 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 1 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:14,926 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:14,931 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:14,937 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1584948130] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:14,937 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:14,937 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2
[2024-12-02 06:15:14,937 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851322751]
[2024-12-02 06:15:14,938 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:14,938 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:14,939 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:14,963 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-12-02 06:15:14,964 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-12-02 06:15:14,966 INFO L87 Difference]: Start difference. First operand has 503 states, 502 states have (on average 1.5358565737051793) internal successors, (771), 502 states have internal predecessors, (771), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 28.25) internal successors, (113), 4 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:15,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:15,092 INFO L93 Difference]: Finished difference Result 873 states and 1291 transitions.
[2024-12-02 06:15:15,093 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 873 states and 1291 transitions.
[2024-12-02 06:15:15,102 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 783
[2024-12-02 06:15:15,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 873 states to 861 states and 1279 transitions.
[2024-12-02 06:15:15,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 861
[2024-12-02 06:15:15,117 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 861
[2024-12-02 06:15:15,117 INFO L73 IsDeterministic]: Start isDeterministic. Operand 861 states and 1279 transitions.
[2024-12-02 06:15:15,122 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:15,122 INFO L218 hiAutomatonCegarLoop]: Abstraction has 861 states and 1279 transitions.
[2024-12-02 06:15:15,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 861 states and 1279 transitions.
[2024-12-02 06:15:15,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 861 to 860.
[2024-12-02 06:15:15,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 860 states, 860 states have (on average 1.486046511627907) internal successors, (1278), 859 states have internal predecessors, (1278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:15,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 860 states to 860 states and 1278 transitions.
[2024-12-02 06:15:15,177 INFO L240 hiAutomatonCegarLoop]: Abstraction has 860 states and 1278 transitions.
[2024-12-02 06:15:15,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:15,182 INFO L425 stractBuchiCegarLoop]: Abstraction has 860 states and 1278 transitions.
[2024-12-02 06:15:15,182 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============
[2024-12-02 06:15:15,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 860 states and 1278 transitions.
[2024-12-02 06:15:15,188 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 782
[2024-12-02 06:15:15,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:15,189 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:15,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:15,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:15,191 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:15,191 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:15,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:15,192 INFO L85 PathProgramCache]: Analyzing trace with hash 381623753, now seen corresponding path program 1 times
[2024-12-02 06:15:15,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:15,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622844047]
[2024-12-02 06:15:15,192 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:15,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,258 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:15,259 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622844047]
[2024-12-02 06:15:15,259 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622844047] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:15,259 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [381715043]
[2024-12-02 06:15:15,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:15,259 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:15,262 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:15,263 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process
[2024-12-02 06:15:15,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,345 INFO L256 TraceCheckSpWp]: Trace formula consists of 221 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:15,346 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:15,399 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:15,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [381715043] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:15,456 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:15,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4
[2024-12-02 06:15:15,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272514244]
[2024-12-02 06:15:15,456 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:15,457 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:15,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:15,457 INFO L85 PathProgramCache]: Analyzing trace with hash -1494081699, now seen corresponding path program 1 times
[2024-12-02 06:15:15,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:15,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50296634]
[2024-12-02 06:15:15,457 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:15,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:15,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50296634]
[2024-12-02 06:15:15,581 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50296634] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:15,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [519462712]
[2024-12-02 06:15:15,581 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,581 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:15,581 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:15,583 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:15,585 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process
[2024-12-02 06:15:15,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,660 INFO L256 TraceCheckSpWp]: Trace formula consists of 199 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:15,662 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:15,687 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:15,710 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [519462712] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:15,710 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:15,710 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:15,710 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050846244]
[2024-12-02 06:15:15,710 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:15,711 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:15,711 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:15,711 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-12-02 06:15:15,711 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-12-02 06:15:15,711 INFO L87 Difference]: Start difference. First operand 860 states and 1278 transitions. cyclomatic complexity: 420 Second operand has 4 states, 4 states have (on average 26.75) internal successors, (107), 4 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:15,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:15,789 INFO L93 Difference]: Finished difference Result 1543 states and 2275 transitions.
[2024-12-02 06:15:15,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1543 states and 2275 transitions.
[2024-12-02 06:15:15,797 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1460
[2024-12-02 06:15:15,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1543 states to 1543 states and 2275 transitions.
[2024-12-02 06:15:15,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1543
[2024-12-02 06:15:15,806 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1543
[2024-12-02 06:15:15,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1543 states and 2275 transitions.
[2024-12-02 06:15:15,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:15,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1543 states and 2275 transitions.
[2024-12-02 06:15:15,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1543 states and 2275 transitions.
[2024-12-02 06:15:15,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1543 to 1541.
[2024-12-02 06:15:15,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1541 states, 1541 states have (on average 1.4750162232316677) internal successors, (2273), 1540 states have internal predecessors, (2273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:15,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1541 states to 1541 states and 2273 transitions.
[2024-12-02 06:15:15,836 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1541 states and 2273 transitions.
[2024-12-02 06:15:15,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:15,837 INFO L425 stractBuchiCegarLoop]: Abstraction has 1541 states and 2273 transitions.
[2024-12-02 06:15:15,837 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============
[2024-12-02 06:15:15,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1541 states and 2273 transitions.
[2024-12-02 06:15:15,844 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1458
[2024-12-02 06:15:15,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:15,844 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:15,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:15,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:15,846 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:15,846 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:15,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:15,846 INFO L85 PathProgramCache]: Analyzing trace with hash 302986982, now seen corresponding path program 1 times
[2024-12-02 06:15:15,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:15,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91495858]
[2024-12-02 06:15:15,847 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:15,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:15,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91495858]
[2024-12-02 06:15:15,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91495858] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:15,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [599755889]
[2024-12-02 06:15:15,893 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:15,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:15,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:15,896 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:15,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process
[2024-12-02 06:15:15,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:15,967 INFO L256 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:15,968 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:16,006 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:16,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [599755889] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:16,045 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:16,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4
[2024-12-02 06:15:16,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289482287]
[2024-12-02 06:15:16,046 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:16,046 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:16,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:16,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1742435966, now seen corresponding path program 1 times
[2024-12-02 06:15:16,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:16,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313012850]
[2024-12-02 06:15:16,047 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:16,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:16,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:16,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313012850]
[2024-12-02 06:15:16,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313012850] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:16,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1339459093]
[2024-12-02 06:15:16,110 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:16,110 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:16,113 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:16,114 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process
[2024-12-02 06:15:16,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:16,193 INFO L256 TraceCheckSpWp]: Trace formula consists of 202 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:16,195 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:16,266 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:16,338 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1339459093] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:16,338 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:16,338 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:16,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196014486]
[2024-12-02 06:15:16,338 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:16,339 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:16,339 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:16,339 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-12-02 06:15:16,339 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-12-02 06:15:16,339 INFO L87 Difference]: Start difference. First operand 1541 states and 2273 transitions. cyclomatic complexity: 736 Second operand has 4 states, 4 states have (on average 23.75) internal successors, (95), 4 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:16,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:16,440 INFO L93 Difference]: Finished difference Result 2978 states and 4347 transitions.
[2024-12-02 06:15:16,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2978 states and 4347 transitions.
[2024-12-02 06:15:16,463 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2880
[2024-12-02 06:15:16,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2978 states to 2978 states and 4347 transitions.
[2024-12-02 06:15:16,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2978
[2024-12-02 06:15:16,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2978
[2024-12-02 06:15:16,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2978 states and 4347 transitions.
[2024-12-02 06:15:16,490 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:16,490 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2978 states and 4347 transitions.
[2024-12-02 06:15:16,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2978 states and 4347 transitions.
[2024-12-02 06:15:16,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2978 to 2814.
[2024-12-02 06:15:16,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2814 states, 2814 states have (on average 1.4665955934612651) internal successors, (4127), 2813 states have internal predecessors, (4127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:16,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2814 states to 2814 states and 4127 transitions.
[2024-12-02 06:15:16,557 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2814 states and 4127 transitions.
[2024-12-02 06:15:16,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:16,558 INFO L425 stractBuchiCegarLoop]: Abstraction has 2814 states and 4127 transitions.
[2024-12-02 06:15:16,558 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============
[2024-12-02 06:15:16,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2814 states and 4127 transitions.
[2024-12-02 06:15:16,574 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2716
[2024-12-02 06:15:16,575 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:16,575 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:16,576 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:16,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:16,577 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:16,577 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:16,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:16,577 INFO L85 PathProgramCache]: Analyzing trace with hash 1790214599, now seen corresponding path program 1 times
[2024-12-02 06:15:16,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:16,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882405080]
[2024-12-02 06:15:16,577 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:16,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:16,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:16,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882405080]
[2024-12-02 06:15:16,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882405080] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:16,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1746248523]
[2024-12-02 06:15:16,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,618 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:16,619 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:16,621 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:16,623 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process
[2024-12-02 06:15:16,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:16,701 INFO L256 TraceCheckSpWp]: Trace formula consists of 217 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:16,703 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:16,791 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:16,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1746248523] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:16,880 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:16,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 4
[2024-12-02 06:15:16,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [812990566]
[2024-12-02 06:15:16,881 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:16,881 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:16,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:16,882 INFO L85 PathProgramCache]: Analyzing trace with hash -118391205, now seen corresponding path program 1 times
[2024-12-02 06:15:16,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:16,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1967108824]
[2024-12-02 06:15:16,882 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:16,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:16,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:16,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1967108824]
[2024-12-02 06:15:16,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1967108824] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:16,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1524539664]
[2024-12-02 06:15:16,951 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:16,951 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:16,951 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:16,953 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:16,955 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process
[2024-12-02 06:15:17,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,030 INFO L256 TraceCheckSpWp]: Trace formula consists of 193 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:17,032 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:17,044 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:17,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1524539664] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:17,067 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:17,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:17,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736875103]
[2024-12-02 06:15:17,067 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:17,068 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:17,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:17,068 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-12-02 06:15:17,068 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2024-12-02 06:15:17,069 INFO L87 Difference]: Start difference. First operand 2814 states and 4127 transitions. cyclomatic complexity: 1321 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 4 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:17,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:17,138 INFO L93 Difference]: Finished difference Result 2814 states and 4063 transitions.
[2024-12-02 06:15:17,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2814 states and 4063 transitions.
[2024-12-02 06:15:17,159 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2716
[2024-12-02 06:15:17,175 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2814 states to 2814 states and 4063 transitions.
[2024-12-02 06:15:17,175 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2814
[2024-12-02 06:15:17,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2814
[2024-12-02 06:15:17,178 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2814 states and 4063 transitions.
[2024-12-02 06:15:17,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:17,184 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2814 states and 4063 transitions.
[2024-12-02 06:15:17,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2814 states and 4063 transitions.
[2024-12-02 06:15:17,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2814 to 2814.
[2024-12-02 06:15:17,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2814 states, 2814 states have (on average 1.4438521677327647) internal successors, (4063), 2813 states have internal predecessors, (4063), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:17,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2814 states to 2814 states and 4063 transitions.
[2024-12-02 06:15:17,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2814 states and 4063 transitions.
[2024-12-02 06:15:17,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:17,250 INFO L425 stractBuchiCegarLoop]: Abstraction has 2814 states and 4063 transitions.
[2024-12-02 06:15:17,251 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============
[2024-12-02 06:15:17,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2814 states and 4063 transitions.
[2024-12-02 06:15:17,266 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2716
[2024-12-02 06:15:17,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:17,266 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:17,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:17,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:17,268 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:17,268 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:17,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:17,268 INFO L85 PathProgramCache]: Analyzing trace with hash -947004380, now seen corresponding path program 1 times
[2024-12-02 06:15:17,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:17,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681843496]
[2024-12-02 06:15:17,269 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:17,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:17,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681843496]
[2024-12-02 06:15:17,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681843496] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:17,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [279623190]
[2024-12-02 06:15:17,308 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,308 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:17,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:17,310 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:17,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process
[2024-12-02 06:15:17,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,387 INFO L256 TraceCheckSpWp]: Trace formula consists of 215 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:17,389 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:17,420 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:17,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [279623190] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:17,460 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:17,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 2, 2] total 5
[2024-12-02 06:15:17,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [143553601]
[2024-12-02 06:15:17,460 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:17,460 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:17,460 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:17,461 INFO L85 PathProgramCache]: Analyzing trace with hash -450236201, now seen corresponding path program 1 times
[2024-12-02 06:15:17,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:17,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305569600]
[2024-12-02 06:15:17,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:17,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,502 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:17,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1305569600]
[2024-12-02 06:15:17,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1305569600] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:17,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [859344422]
[2024-12-02 06:15:17,503 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,503 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:17,503 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:17,506 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:17,507 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process
[2024-12-02 06:15:17,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,573 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:17,575 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:17,585 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:17,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [859344422] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:17,603 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:17,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:17,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695456704]
[2024-12-02 06:15:17,603 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:17,604 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:17,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:17,604 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-12-02 06:15:17,604 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20
[2024-12-02 06:15:17,604 INFO L87 Difference]: Start difference. First operand 2814 states and 4063 transitions. cyclomatic complexity: 1257 Second operand has 5 states, 5 states have (on average 22.2) internal successors, (111), 5 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:17,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:17,671 INFO L93 Difference]: Finished difference Result 2854 states and 4066 transitions.
[2024-12-02 06:15:17,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2854 states and 4066 transitions.
[2024-12-02 06:15:17,688 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2756
[2024-12-02 06:15:17,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2854 states to 2854 states and 4066 transitions.
[2024-12-02 06:15:17,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2854
[2024-12-02 06:15:17,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2854
[2024-12-02 06:15:17,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2854 states and 4066 transitions.
[2024-12-02 06:15:17,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:17,713 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2854 states and 4066 transitions.
[2024-12-02 06:15:17,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2854 states and 4066 transitions.
[2024-12-02 06:15:17,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2854 to 2814.
[2024-12-02 06:15:17,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2814 states, 2814 states have (on average 1.4264392324093818) internal successors, (4014), 2813 states have internal predecessors, (4014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:17,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2814 states to 2814 states and 4014 transitions.
[2024-12-02 06:15:17,770 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2814 states and 4014 transitions.
[2024-12-02 06:15:17,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:17,771 INFO L425 stractBuchiCegarLoop]: Abstraction has 2814 states and 4014 transitions.
[2024-12-02 06:15:17,771 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============
[2024-12-02 06:15:17,771 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2814 states and 4014 transitions.
[2024-12-02 06:15:17,780 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2716
[2024-12-02 06:15:17,780 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:17,780 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:17,781 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:17,781 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:17,781 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:17,781 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:17,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:17,781 INFO L85 PathProgramCache]: Analyzing trace with hash -87877022, now seen corresponding path program 1 times
[2024-12-02 06:15:17,782 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:17,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305161977]
[2024-12-02 06:15:17,782 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:17,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:17,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305161977]
[2024-12-02 06:15:17,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305161977] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:17,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [349967698]
[2024-12-02 06:15:17,814 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,814 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:17,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:17,816 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:17,818 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process
[2024-12-02 06:15:17,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,887 INFO L256 TraceCheckSpWp]: Trace formula consists of 210 conjuncts, 2 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:17,889 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:17,904 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:17,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [349967698] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:17,922 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:17,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 3
[2024-12-02 06:15:17,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111268863]
[2024-12-02 06:15:17,923 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:17,923 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:17,923 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:17,923 INFO L85 PathProgramCache]: Analyzing trace with hash 2079914486, now seen corresponding path program 1 times
[2024-12-02 06:15:17,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:17,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910063215]
[2024-12-02 06:15:17,923 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:17,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:17,963 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:17,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [910063215]
[2024-12-02 06:15:17,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [910063215] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:17,963 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1050102613]
[2024-12-02 06:15:17,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:17,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:17,963 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:17,965 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:17,967 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process
[2024-12-02 06:15:18,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,033 INFO L256 TraceCheckSpWp]: Trace formula consists of 184 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:18,035 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:18,045 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:18,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1050102613] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:18,066 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:18,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:18,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174236512]
[2024-12-02 06:15:18,066 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:18,066 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:18,066 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:18,067 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2024-12-02 06:15:18,067 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12
[2024-12-02 06:15:18,067 INFO L87 Difference]: Start difference. First operand 2814 states and 4014 transitions. cyclomatic complexity: 1208 Second operand has 4 states, 4 states have (on average 20.75) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:18,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:18,121 INFO L93 Difference]: Finished difference Result 2974 states and 4186 transitions.
[2024-12-02 06:15:18,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2974 states and 4186 transitions.
[2024-12-02 06:15:18,137 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2876
[2024-12-02 06:15:18,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2974 states to 2974 states and 4186 transitions.
[2024-12-02 06:15:18,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2974
[2024-12-02 06:15:18,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2974
[2024-12-02 06:15:18,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2974 states and 4186 transitions.
[2024-12-02 06:15:18,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:18,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2974 states and 4186 transitions.
[2024-12-02 06:15:18,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2974 states and 4186 transitions.
[2024-12-02 06:15:18,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2974 to 2974.
[2024-12-02 06:15:18,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2974 states, 2974 states have (on average 1.4075319435104237) internal successors, (4186), 2973 states have internal predecessors, (4186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:18,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2974 states to 2974 states and 4186 transitions.
[2024-12-02 06:15:18,226 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2974 states and 4186 transitions.
[2024-12-02 06:15:18,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states.
[2024-12-02 06:15:18,227 INFO L425 stractBuchiCegarLoop]: Abstraction has 2974 states and 4186 transitions.
[2024-12-02 06:15:18,227 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============
[2024-12-02 06:15:18,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2974 states and 4186 transitions.
[2024-12-02 06:15:18,235 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2876
[2024-12-02 06:15:18,235 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:18,235 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:18,236 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:18,236 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:18,236 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:18,236 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:18,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:18,237 INFO L85 PathProgramCache]: Analyzing trace with hash 372112350, now seen corresponding path program 1 times
[2024-12-02 06:15:18,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:18,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093950313]
[2024-12-02 06:15:18,237 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:18,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,288 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:18,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093950313]
[2024-12-02 06:15:18,288 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093950313] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:18,288 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1584837728]
[2024-12-02 06:15:18,288 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,288 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:18,288 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:18,291 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:18,308 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process
[2024-12-02 06:15:18,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,379 INFO L256 TraceCheckSpWp]: Trace formula consists of 204 conjuncts, 7 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:18,381 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:18,391 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:18,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1584837728] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:18,398 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:18,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:18,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286634421]
[2024-12-02 06:15:18,398 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:18,399 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:18,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:18,399 INFO L85 PathProgramCache]: Analyzing trace with hash -450236201, now seen corresponding path program 2 times
[2024-12-02 06:15:18,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:18,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049688131]
[2024-12-02 06:15:18,399 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:18,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:18,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049688131]
[2024-12-02 06:15:18,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049688131] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:18,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1463893343]
[2024-12-02 06:15:18,445 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,446 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:18,446 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:18,448 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:18,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process
[2024-12-02 06:15:18,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,520 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:18,522 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:18,532 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:18,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1463893343] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:18,551 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:18,551 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:18,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707672337]
[2024-12-02 06:15:18,551 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:18,552 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:18,552 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:18,552 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-12-02 06:15:18,552 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-12-02 06:15:18,552 INFO L87 Difference]: Start difference. First operand 2974 states and 4186 transitions. cyclomatic complexity: 1220 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:18,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:18,709 INFO L93 Difference]: Finished difference Result 3121 states and 4333 transitions.
[2024-12-02 06:15:18,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3121 states and 4333 transitions.
[2024-12-02 06:15:18,719 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3020
[2024-12-02 06:15:18,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3121 states to 3121 states and 4333 transitions.
[2024-12-02 06:15:18,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3121
[2024-12-02 06:15:18,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3121
[2024-12-02 06:15:18,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3121 states and 4333 transitions.
[2024-12-02 06:15:18,734 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:18,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3121 states and 4333 transitions.
[2024-12-02 06:15:18,737 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3121 states and 4333 transitions.
[2024-12-02 06:15:18,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3121 to 3121.
[2024-12-02 06:15:18,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3121 states, 3121 states have (on average 1.3883370714514578) internal successors, (4333), 3120 states have internal predecessors, (4333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:18,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3121 states to 3121 states and 4333 transitions.
[2024-12-02 06:15:18,786 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3121 states and 4333 transitions.
[2024-12-02 06:15:18,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:18,787 INFO L425 stractBuchiCegarLoop]: Abstraction has 3121 states and 4333 transitions.
[2024-12-02 06:15:18,787 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============
[2024-12-02 06:15:18,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3121 states and 4333 transitions.
[2024-12-02 06:15:18,795 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3020
[2024-12-02 06:15:18,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:18,795 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:18,796 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:18,796 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:18,796 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:18,796 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:18,796 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:18,797 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times
[2024-12-02 06:15:18,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:18,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993816882]
[2024-12-02 06:15:18,797 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:18,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:18,807 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:18,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:18,844 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:18,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:18,845 INFO L85 PathProgramCache]: Analyzing trace with hash -450236201, now seen corresponding path program 3 times
[2024-12-02 06:15:18,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:18,845 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247416483]
[2024-12-02 06:15:18,845 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:18,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,891 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:18,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [247416483]
[2024-12-02 06:15:18,891 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [247416483] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:18,891 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [842777116]
[2024-12-02 06:15:18,891 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:18,891 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:18,892 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:18,893 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:18,895 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process
[2024-12-02 06:15:18,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:18,964 INFO L256 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:18,965 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:18,973 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:18,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [842777116] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:18,994 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:18,994 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:18,994 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [661898607]
[2024-12-02 06:15:18,994 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:18,994 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:18,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:18,995 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-12-02 06:15:18,995 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-12-02 06:15:18,995 INFO L87 Difference]: Start difference. First operand 3121 states and 4333 transitions. cyclomatic complexity: 1220 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:19,056 INFO L93 Difference]: Finished difference Result 3177 states and 4389 transitions.
[2024-12-02 06:15:19,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3177 states and 4389 transitions.
[2024-12-02 06:15:19,069 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3076
[2024-12-02 06:15:19,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3177 states to 3177 states and 4389 transitions.
[2024-12-02 06:15:19,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3177
[2024-12-02 06:15:19,092 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3177
[2024-12-02 06:15:19,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3177 states and 4389 transitions.
[2024-12-02 06:15:19,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:19,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3177 states and 4389 transitions.
[2024-12-02 06:15:19,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3177 states and 4389 transitions.
[2024-12-02 06:15:19,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3177 to 3145.
[2024-12-02 06:15:19,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3145 states, 3145 states have (on average 1.3853736089030206) internal successors, (4357), 3144 states have internal predecessors, (4357), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3145 states to 3145 states and 4357 transitions.
[2024-12-02 06:15:19,158 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3145 states and 4357 transitions.
[2024-12-02 06:15:19,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:19,159 INFO L425 stractBuchiCegarLoop]: Abstraction has 3145 states and 4357 transitions.
[2024-12-02 06:15:19,159 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============
[2024-12-02 06:15:19,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3145 states and 4357 transitions.
[2024-12-02 06:15:19,167 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3044
[2024-12-02 06:15:19,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:19,167 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:19,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,168 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:19,168 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:19,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,168 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times
[2024-12-02 06:15:19,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261750463]
[2024-12-02 06:15:19,168 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,178 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:19,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,201 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:19,202 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,202 INFO L85 PathProgramCache]: Analyzing trace with hash -471620248, now seen corresponding path program 1 times
[2024-12-02 06:15:19,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297182450]
[2024-12-02 06:15:19,202 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:19,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:19,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297182450]
[2024-12-02 06:15:19,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297182450] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:19,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [979117187]
[2024-12-02 06:15:19,272 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,272 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:19,272 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:19,274 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:19,276 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process
[2024-12-02 06:15:19,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:19,349 INFO L256 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:19,351 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:19,360 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:19,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [979117187] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:19,378 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:19,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:19,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [110555073]
[2024-12-02 06:15:19,378 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:19,379 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:19,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:19,379 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-12-02 06:15:19,379 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-12-02 06:15:19,379 INFO L87 Difference]: Start difference. First operand 3145 states and 4357 transitions. cyclomatic complexity: 1220 Second operand has 5 states, 5 states have (on average 17.0) internal successors, (85), 5 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:19,515 INFO L93 Difference]: Finished difference Result 3145 states and 4308 transitions.
[2024-12-02 06:15:19,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3145 states and 4308 transitions.
[2024-12-02 06:15:19,523 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3044
[2024-12-02 06:15:19,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3145 states to 3145 states and 4308 transitions.
[2024-12-02 06:15:19,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3145
[2024-12-02 06:15:19,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3145
[2024-12-02 06:15:19,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3145 states and 4308 transitions.
[2024-12-02 06:15:19,537 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:19,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3145 states and 4308 transitions.
[2024-12-02 06:15:19,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3145 states and 4308 transitions.
[2024-12-02 06:15:19,561 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3145 to 3145.
[2024-12-02 06:15:19,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3145 states, 3145 states have (on average 1.3697933227344992) internal successors, (4308), 3144 states have internal predecessors, (4308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3145 states to 3145 states and 4308 transitions.
[2024-12-02 06:15:19,574 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3145 states and 4308 transitions.
[2024-12-02 06:15:19,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:19,575 INFO L425 stractBuchiCegarLoop]: Abstraction has 3145 states and 4308 transitions.
[2024-12-02 06:15:19,575 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============
[2024-12-02 06:15:19,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3145 states and 4308 transitions.
[2024-12-02 06:15:19,582 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3044
[2024-12-02 06:15:19,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:19,582 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:19,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,583 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:19,583 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume !(0 != stop_simulation_~tmp~2#1);stop_simulation_~__retres2~0#1 := 1;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:19,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,583 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times
[2024-12-02 06:15:19,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572187052]
[2024-12-02 06:15:19,583 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,584 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,591 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:19,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:19,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,605 INFO L85 PathProgramCache]: Analyzing trace with hash 2058530439, now seen corresponding path program 1 times
[2024-12-02 06:15:19,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467458964]
[2024-12-02 06:15:19,605 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:19,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:19,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467458964]
[2024-12-02 06:15:19,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467458964] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:19,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [244170186]
[2024-12-02 06:15:19,652 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,652 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:19,652 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:19,654 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:19,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process
[2024-12-02 06:15:19,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:19,726 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 4 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:19,727 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:19,736 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:19,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [244170186] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:19,756 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:19,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 5
[2024-12-02 06:15:19,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612499800]
[2024-12-02 06:15:19,756 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:19,756 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:19,757 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:19,757 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2024-12-02 06:15:19,757 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2024-12-02 06:15:19,757 INFO L87 Difference]: Start difference. First operand 3145 states and 4308 transitions. cyclomatic complexity: 1171 Second operand has 5 states, 5 states have (on average 17.0) internal successors, (85), 5 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:19,817 INFO L93 Difference]: Finished difference Result 3185 states and 4348 transitions.
[2024-12-02 06:15:19,818 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3185 states and 4348 transitions.
[2024-12-02 06:15:19,825 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3084
[2024-12-02 06:15:19,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3185 states to 3185 states and 4348 transitions.
[2024-12-02 06:15:19,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3185
[2024-12-02 06:15:19,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3185
[2024-12-02 06:15:19,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3185 states and 4348 transitions.
[2024-12-02 06:15:19,838 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:19,838 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3185 states and 4348 transitions.
[2024-12-02 06:15:19,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3185 states and 4348 transitions.
[2024-12-02 06:15:19,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3185 to 3169.
[2024-12-02 06:15:19,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3169 states, 3169 states have (on average 1.3669927421899652) internal successors, (4332), 3168 states have internal predecessors, (4332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:19,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3169 states to 3169 states and 4332 transitions.
[2024-12-02 06:15:19,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3169 states and 4332 transitions.
[2024-12-02 06:15:19,878 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states.
[2024-12-02 06:15:19,878 INFO L425 stractBuchiCegarLoop]: Abstraction has 3169 states and 4332 transitions.
[2024-12-02 06:15:19,879 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============
[2024-12-02 06:15:19,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3169 states and 4332 transitions.
[2024-12-02 06:15:19,886 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3068
[2024-12-02 06:15:19,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:19,886 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:19,886 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:19,887 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:19,887 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:19,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,887 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times
[2024-12-02 06:15:19,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199741935]
[2024-12-02 06:15:19,887 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,896 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:19,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:19,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:19,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:19,908 INFO L85 PathProgramCache]: Analyzing trace with hash -746439444, now seen corresponding path program 1 times
[2024-12-02 06:15:19,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:19,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715845639]
[2024-12-02 06:15:19,908 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:19,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:19,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:20,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:20,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715845639]
[2024-12-02 06:15:20,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715845639] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:20,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1931978753]
[2024-12-02 06:15:20,012 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,012 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:20,012 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:20,014 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:20,017 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process
[2024-12-02 06:15:20,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:20,088 INFO L256 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 7 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:20,089 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:20,113 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:20,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1931978753] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:20,125 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:20,125 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 8
[2024-12-02 06:15:20,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375249109]
[2024-12-02 06:15:20,125 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:20,125 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:20,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:20,126 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants.
[2024-12-02 06:15:20,126 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56
[2024-12-02 06:15:20,126 INFO L87 Difference]: Start difference. First operand 3169 states and 4332 transitions. cyclomatic complexity: 1171 Second operand has 8 states, 8 states have (on average 14.875) internal successors, (119), 8 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:20,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:20,365 INFO L93 Difference]: Finished difference Result 3205 states and 4282 transitions.
[2024-12-02 06:15:20,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3205 states and 4282 transitions.
[2024-12-02 06:15:20,377 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3104
[2024-12-02 06:15:20,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3205 states to 3205 states and 4282 transitions.
[2024-12-02 06:15:20,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3205
[2024-12-02 06:15:20,388 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3205
[2024-12-02 06:15:20,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3205 states and 4282 transitions.
[2024-12-02 06:15:20,392 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:20,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3205 states and 4282 transitions.
[2024-12-02 06:15:20,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3205 states and 4282 transitions.
[2024-12-02 06:15:20,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3205 to 3205.
[2024-12-02 06:15:20,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3205 states, 3205 states have (on average 1.33603744149766) internal successors, (4282), 3204 states have internal predecessors, (4282), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:20,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3205 states to 3205 states and 4282 transitions.
[2024-12-02 06:15:20,434 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3205 states and 4282 transitions.
[2024-12-02 06:15:20,435 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states.
[2024-12-02 06:15:20,435 INFO L425 stractBuchiCegarLoop]: Abstraction has 3205 states and 4282 transitions.
[2024-12-02 06:15:20,435 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============
[2024-12-02 06:15:20,435 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3205 states and 4282 transitions.
[2024-12-02 06:15:20,443 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3104
[2024-12-02 06:15:20,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:20,443 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:20,444 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:20,444 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:20,444 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;"
[2024-12-02 06:15:20,444 INFO L749 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume !(0 == ~E_3~0);" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0;" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume !(1 == ~E_3~0);" "assume 1 == ~E_4~0;~E_4~0 := 2;" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1;" "assume !(0 != start_simulation_~tmp___0~1#1);"
[2024-12-02 06:15:20,444 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:20,444 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times
[2024-12-02 06:15:20,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:20,445 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533823307]
[2024-12-02 06:15:20,445 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,445 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:20,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,453 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:20,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,464 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:20,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:20,464 INFO L85 PathProgramCache]: Analyzing trace with hash -643725080, now seen corresponding path program 1 times
[2024-12-02 06:15:20,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:20,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334988475]
[2024-12-02 06:15:20,465 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,465 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:20,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:20,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:20,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334988475]
[2024-12-02 06:15:20,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334988475] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:20,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [251113044]
[2024-12-02 06:15:20,499 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,499 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:20,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:20,502 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:20,504 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process
[2024-12-02 06:15:20,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:20,575 INFO L256 TraceCheckSpWp]: Trace formula consists of 189 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:20,576 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:20,664 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:20,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [251113044] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:20,752 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:20,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:20,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303752163]
[2024-12-02 06:15:20,752 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:20,752 INFO L764 eck$LassoCheckResult]: loop already infeasible
[2024-12-02 06:15:20,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:20,753 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:20,753 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:20,753 INFO L87 Difference]: Start difference. First operand 3205 states and 4282 transitions. cyclomatic complexity: 1085 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:20,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:20,784 INFO L93 Difference]: Finished difference Result 4878 states and 6425 transitions.
[2024-12-02 06:15:20,784 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4878 states and 6425 transitions.
[2024-12-02 06:15:20,796 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4760
[2024-12-02 06:15:20,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4878 states to 4878 states and 6425 transitions.
[2024-12-02 06:15:20,811 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4878
[2024-12-02 06:15:20,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4878
[2024-12-02 06:15:20,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4878 states and 6425 transitions.
[2024-12-02 06:15:20,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:20,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4878 states and 6425 transitions.
[2024-12-02 06:15:20,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4878 states and 6425 transitions.
[2024-12-02 06:15:20,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4878 to 4878.
[2024-12-02 06:15:20,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4878 states, 4878 states have (on average 1.3171381713817139) internal successors, (6425), 4877 states have internal predecessors, (6425), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:20,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4878 states to 4878 states and 6425 transitions.
[2024-12-02 06:15:20,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4878 states and 6425 transitions.
[2024-12-02 06:15:20,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:20,913 INFO L425 stractBuchiCegarLoop]: Abstraction has 4878 states and 6425 transitions.
[2024-12-02 06:15:20,913 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============
[2024-12-02 06:15:20,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4878 states and 6425 transitions.
[2024-12-02 06:15:20,923 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4760
[2024-12-02 06:15:20,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:20,923 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:20,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:20,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:20,924 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:20,924 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:20,924 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:20,925 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 1 times
[2024-12-02 06:15:20,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:20,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122530575]
[2024-12-02 06:15:20,925 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:20,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,935 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:20,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:20,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:20,956 INFO L85 PathProgramCache]: Analyzing trace with hash -874408162, now seen corresponding path program 1 times
[2024-12-02 06:15:20,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:20,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125795769]
[2024-12-02 06:15:20,956 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:20,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,960 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:20,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:20,963 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:20,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:20,964 INFO L85 PathProgramCache]: Analyzing trace with hash 424577235, now seen corresponding path program 1 times
[2024-12-02 06:15:20,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:20,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14230192]
[2024-12-02 06:15:20,964 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:20,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:20,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:21,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:21,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14230192]
[2024-12-02 06:15:21,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14230192] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:21,013 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1604844235]
[2024-12-02 06:15:21,014 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,014 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:21,014 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:21,016 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:21,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process
[2024-12-02 06:15:21,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:21,097 INFO L256 TraceCheckSpWp]: Trace formula consists of 225 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:21,098 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:21,202 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:21,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1604844235] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:21,322 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:21,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:21,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [821748789]
[2024-12-02 06:15:21,323 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:21,394 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:21,395 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:21,395 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:21,395 INFO L87 Difference]: Start difference. First operand 4878 states and 6425 transitions. cyclomatic complexity: 1559 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:21,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:21,453 INFO L93 Difference]: Finished difference Result 9114 states and 11859 transitions.
[2024-12-02 06:15:21,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9114 states and 11859 transitions.
[2024-12-02 06:15:21,473 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8884
[2024-12-02 06:15:21,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9114 states to 9114 states and 11859 transitions.
[2024-12-02 06:15:21,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9114
[2024-12-02 06:15:21,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9114
[2024-12-02 06:15:21,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9114 states and 11859 transitions.
[2024-12-02 06:15:21,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:21,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9114 states and 11859 transitions.
[2024-12-02 06:15:21,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9114 states and 11859 transitions.
[2024-12-02 06:15:21,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9114 to 8586.
[2024-12-02 06:15:21,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8586 states, 8586 states have (on average 1.307593757279292) internal successors, (11227), 8585 states have internal predecessors, (11227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:21,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8586 states to 8586 states and 11227 transitions.
[2024-12-02 06:15:21,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8586 states and 11227 transitions.
[2024-12-02 06:15:21,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:21,565 INFO L425 stractBuchiCegarLoop]: Abstraction has 8586 states and 11227 transitions.
[2024-12-02 06:15:21,565 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============
[2024-12-02 06:15:21,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8586 states and 11227 transitions.
[2024-12-02 06:15:21,581 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8356
[2024-12-02 06:15:21,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:21,581 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:21,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:21,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:21,582 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:21,582 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:21,582 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:21,582 INFO L85 PathProgramCache]: Analyzing trace with hash -297503444, now seen corresponding path program 1 times
[2024-12-02 06:15:21,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:21,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472186028]
[2024-12-02 06:15:21,583 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:21,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:21,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:21,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472186028]
[2024-12-02 06:15:21,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472186028] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:21,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1131592369]
[2024-12-02 06:15:21,605 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,605 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:21,605 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:21,607 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:21,609 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process
[2024-12-02 06:15:21,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:21,679 INFO L256 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:21,680 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:21,687 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:21,694 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1131592369] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:21,694 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:21,694 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:21,694 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909428946]
[2024-12-02 06:15:21,694 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:21,694 INFO L752 eck$LassoCheckResult]: stem already infeasible
[2024-12-02 06:15:21,694 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:21,694 INFO L85 PathProgramCache]: Analyzing trace with hash -1392489712, now seen corresponding path program 1 times
[2024-12-02 06:15:21,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:21,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615158167]
[2024-12-02 06:15:21,694 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:21,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:21,698 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:21,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:21,701 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:21,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:21,761 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:21,761 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:21,762 INFO L87 Difference]: Start difference. First operand 8586 states and 11227 transitions. cyclomatic complexity: 2653 Second operand has 3 states, 3 states have (on average 24.0) internal successors, (72), 3 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:21,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:21,779 INFO L93 Difference]: Finished difference Result 8514 states and 11130 transitions.
[2024-12-02 06:15:21,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8514 states and 11130 transitions.
[2024-12-02 06:15:21,829 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8356
[2024-12-02 06:15:21,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8514 states to 8514 states and 11130 transitions.
[2024-12-02 06:15:21,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8514
[2024-12-02 06:15:21,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8514
[2024-12-02 06:15:21,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8514 states and 11130 transitions.
[2024-12-02 06:15:21,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:21,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8514 states and 11130 transitions.
[2024-12-02 06:15:21,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8514 states and 11130 transitions.
[2024-12-02 06:15:21,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8514 to 8514.
[2024-12-02 06:15:21,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8514 states, 8514 states have (on average 1.3072586328400282) internal successors, (11130), 8513 states have internal predecessors, (11130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:21,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8514 states to 8514 states and 11130 transitions.
[2024-12-02 06:15:21,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8514 states and 11130 transitions.
[2024-12-02 06:15:21,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:21,947 INFO L425 stractBuchiCegarLoop]: Abstraction has 8514 states and 11130 transitions.
[2024-12-02 06:15:21,947 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============
[2024-12-02 06:15:21,947 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8514 states and 11130 transitions.
[2024-12-02 06:15:21,968 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8356
[2024-12-02 06:15:21,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:21,968 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:21,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:21,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:21,969 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:21,969 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume !(0 == ~t2_st~0);" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:21,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:21,970 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 2 times
[2024-12-02 06:15:21,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:21,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411215019]
[2024-12-02 06:15:21,970 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:21,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:21,980 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:21,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:21,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:21,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:21,994 INFO L85 PathProgramCache]: Analyzing trace with hash -1392489712, now seen corresponding path program 2 times
[2024-12-02 06:15:21,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:21,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110697545]
[2024-12-02 06:15:21,994 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:21,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:21,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:21,997 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:21,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:22,000 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:22,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:22,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1391960965, now seen corresponding path program 1 times
[2024-12-02 06:15:22,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:22,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703516325]
[2024-12-02 06:15:22,001 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:22,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:22,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:22,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703516325]
[2024-12-02 06:15:22,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703516325] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:22,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1717021285]
[2024-12-02 06:15:22,044 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,044 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:22,044 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:22,046 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:22,048 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process
[2024-12-02 06:15:22,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:22,122 INFO L256 TraceCheckSpWp]: Trace formula consists of 229 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:22,124 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:22,220 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:22,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1717021285] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:22,325 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:22,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:22,326 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428478582]
[2024-12-02 06:15:22,326 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:22,379 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:22,380 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:22,380 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:22,380 INFO L87 Difference]: Start difference. First operand 8514 states and 11130 transitions. cyclomatic complexity: 2628 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:22,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:22,440 INFO L93 Difference]: Finished difference Result 10487 states and 13596 transitions.
[2024-12-02 06:15:22,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10487 states and 13596 transitions.
[2024-12-02 06:15:22,473 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10127
[2024-12-02 06:15:22,500 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10487 states to 10487 states and 13596 transitions.
[2024-12-02 06:15:22,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10487
[2024-12-02 06:15:22,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10487
[2024-12-02 06:15:22,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10487 states and 13596 transitions.
[2024-12-02 06:15:22,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:22,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10487 states and 13596 transitions.
[2024-12-02 06:15:22,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10487 states and 13596 transitions.
[2024-12-02 06:15:22,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10487 to 10063.
[2024-12-02 06:15:22,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10063 states, 10063 states have (on average 1.3010036768359337) internal successors, (13092), 10062 states have internal predecessors, (13092), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:22,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10063 states to 10063 states and 13092 transitions.
[2024-12-02 06:15:22,640 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10063 states and 13092 transitions.
[2024-12-02 06:15:22,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:22,641 INFO L425 stractBuchiCegarLoop]: Abstraction has 10063 states and 13092 transitions.
[2024-12-02 06:15:22,641 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============
[2024-12-02 06:15:22,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10063 states and 13092 transitions.
[2024-12-02 06:15:22,664 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9703
[2024-12-02 06:15:22,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:22,664 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:22,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:22,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:22,666 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:22,666 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume !(0 == ~t3_st~0);" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:22,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:22,666 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 3 times
[2024-12-02 06:15:22,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:22,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242964021]
[2024-12-02 06:15:22,666 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:22,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:22,676 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:22,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:22,692 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:22,693 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:22,693 INFO L85 PathProgramCache]: Analyzing trace with hash 922532638, now seen corresponding path program 1 times
[2024-12-02 06:15:22,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:22,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685503341]
[2024-12-02 06:15:22,693 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:22,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:22,696 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:22,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:22,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:22,701 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:22,701 INFO L85 PathProgramCache]: Analyzing trace with hash 1015007827, now seen corresponding path program 1 times
[2024-12-02 06:15:22,701 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:22,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099931808]
[2024-12-02 06:15:22,701 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:22,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:22,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:22,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099931808]
[2024-12-02 06:15:22,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099931808] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:22,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1246398267]
[2024-12-02 06:15:22,741 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:22,741 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:22,741 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:22,743 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:22,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process
[2024-12-02 06:15:22,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:22,824 INFO L256 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:22,826 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:22,942 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:23,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1246398267] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:23,062 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:23,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:23,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [845250758]
[2024-12-02 06:15:23,063 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:23,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:23,133 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:23,133 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:23,133 INFO L87 Difference]: Start difference. First operand 10063 states and 13092 transitions. cyclomatic complexity: 3041 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:23,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:23,204 INFO L93 Difference]: Finished difference Result 12833 states and 16549 transitions.
[2024-12-02 06:15:23,204 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12833 states and 16549 transitions.
[2024-12-02 06:15:23,244 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12169
[2024-12-02 06:15:23,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12833 states to 12833 states and 16549 transitions.
[2024-12-02 06:15:23,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12833
[2024-12-02 06:15:23,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12833
[2024-12-02 06:15:23,291 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12833 states and 16549 transitions.
[2024-12-02 06:15:23,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:23,297 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12833 states and 16549 transitions.
[2024-12-02 06:15:23,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12833 states and 16549 transitions.
[2024-12-02 06:15:23,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12833 to 12393.
[2024-12-02 06:15:23,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12393 states, 12393 states have (on average 1.2945211006213184) internal successors, (16043), 12392 states have internal predecessors, (16043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:23,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12393 states to 12393 states and 16043 transitions.
[2024-12-02 06:15:23,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12393 states and 16043 transitions.
[2024-12-02 06:15:23,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:23,463 INFO L425 stractBuchiCegarLoop]: Abstraction has 12393 states and 16043 transitions.
[2024-12-02 06:15:23,463 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============
[2024-12-02 06:15:23,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12393 states and 16043 transitions.
[2024-12-02 06:15:23,488 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11729
[2024-12-02 06:15:23,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:23,488 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:23,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:23,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:23,490 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:23,490 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume !(0 == ~t4_st~0);" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:23,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:23,490 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 4 times
[2024-12-02 06:15:23,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:23,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747416302]
[2024-12-02 06:15:23,490 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:23,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:23,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:23,501 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:23,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:23,515 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:23,515 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:23,515 INFO L85 PathProgramCache]: Analyzing trace with hash 1622403984, now seen corresponding path program 1 times
[2024-12-02 06:15:23,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:23,516 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751846624]
[2024-12-02 06:15:23,516 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:23,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:23,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:23,519 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:23,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:23,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:23,524 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:23,524 INFO L85 PathProgramCache]: Analyzing trace with hash 296747397, now seen corresponding path program 1 times
[2024-12-02 06:15:23,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:23,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1536922985]
[2024-12-02 06:15:23,524 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:23,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:23,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:23,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:23,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1536922985]
[2024-12-02 06:15:23,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1536922985] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:23,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [457531849]
[2024-12-02 06:15:23,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:23,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:23,560 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:23,563 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:23,564 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process
[2024-12-02 06:15:23,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:23,642 INFO L256 TraceCheckSpWp]: Trace formula consists of 237 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:23,644 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:23,757 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:23,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [457531849] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:23,875 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:23,875 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 3
[2024-12-02 06:15:23,875 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021417661]
[2024-12-02 06:15:23,875 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:23,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:23,946 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:23,946 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:23,946 INFO L87 Difference]: Start difference. First operand 12393 states and 16043 transitions. cyclomatic complexity: 3662 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:24,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:24,027 INFO L93 Difference]: Finished difference Result 21861 states and 28198 transitions.
[2024-12-02 06:15:24,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21861 states and 28198 transitions.
[2024-12-02 06:15:24,147 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 20611
[2024-12-02 06:15:24,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21861 states to 21861 states and 28198 transitions.
[2024-12-02 06:15:24,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21861
[2024-12-02 06:15:24,224 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21861
[2024-12-02 06:15:24,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21861 states and 28198 transitions.
[2024-12-02 06:15:24,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:24,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21861 states and 28198 transitions.
[2024-12-02 06:15:24,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21861 states and 28198 transitions.
[2024-12-02 06:15:24,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21861 to 20680.
[2024-12-02 06:15:24,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20680 states, 20680 states have (on average 1.2974371373307543) internal successors, (26831), 20679 states have internal predecessors, (26831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:24,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20680 states to 20680 states and 26831 transitions.
[2024-12-02 06:15:24,540 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20680 states and 26831 transitions.
[2024-12-02 06:15:24,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:24,541 INFO L425 stractBuchiCegarLoop]: Abstraction has 20680 states and 26831 transitions.
[2024-12-02 06:15:24,541 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============
[2024-12-02 06:15:24,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20680 states and 26831 transitions.
[2024-12-02 06:15:24,616 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 19460
[2024-12-02 06:15:24,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:24,617 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:24,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:24,618 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:24,618 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:24,618 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume !(0 == ~t5_st~0);"
[2024-12-02 06:15:24,618 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:24,618 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 5 times
[2024-12-02 06:15:24,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:24,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [211480001]
[2024-12-02 06:15:24,619 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:24,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:24,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:24,630 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:24,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:24,646 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:24,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:24,647 INFO L85 PathProgramCache]: Analyzing trace with hash 51851038, now seen corresponding path program 1 times
[2024-12-02 06:15:24,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:24,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1963319533]
[2024-12-02 06:15:24,647 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:24,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:24,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:24,651 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:24,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:24,656 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:24,656 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:24,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1701157843, now seen corresponding path program 1 times
[2024-12-02 06:15:24,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:24,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507425558]
[2024-12-02 06:15:24,657 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:24,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:24,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:24,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL_NO_AM found an infeasible trace
[2024-12-02 06:15:24,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507425558]
[2024-12-02 06:15:24,702 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507425558] provided 0 perfect and 1 imperfect interpolant sequences
[2024-12-02 06:15:24,702 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [152774752]
[2024-12-02 06:15:24,702 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:24,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true
[2024-12-02 06:15:24,702 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3
[2024-12-02 06:15:24,704 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null)
[2024-12-02 06:15:24,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process
[2024-12-02 06:15:24,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat
[2024-12-02 06:15:24,789 INFO L256 TraceCheckSpWp]: Trace formula consists of 241 conjuncts, 3 conjuncts are in the unsatisfiable core
[2024-12-02 06:15:24,791 INFO L279 TraceCheckSpWp]: Computing forward predicates...
[2024-12-02 06:15:24,956 INFO L312 TraceCheckSpWp]: Computing backward predicates...
[2024-12-02 06:15:25,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [152774752] provided 0 perfect and 2 imperfect interpolant sequences
[2024-12-02 06:15:25,077 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences.
[2024-12-02 06:15:25,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [2, 2, 2] total 2
[2024-12-02 06:15:25,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1380106698]
[2024-12-02 06:15:25,077 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton
[2024-12-02 06:15:25,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL_NO_AM
[2024-12-02 06:15:25,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2024-12-02 06:15:25,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2024-12-02 06:15:25,155 INFO L87 Difference]: Start difference. First operand 20680 states and 26831 transitions. cyclomatic complexity: 6163 Second operand has 3 states, 2 states have (on average 46.5) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:25,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization.
[2024-12-02 06:15:25,283 INFO L93 Difference]: Finished difference Result 37845 states and 48757 transitions.
[2024-12-02 06:15:25,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37845 states and 48757 transitions.
[2024-12-02 06:15:25,394 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 35483
[2024-12-02 06:15:25,446 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37845 states to 37845 states and 48757 transitions.
[2024-12-02 06:15:25,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37845
[2024-12-02 06:15:25,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37845
[2024-12-02 06:15:25,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37845 states and 48757 transitions.
[2024-12-02 06:15:25,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2024-12-02 06:15:25,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37845 states and 48757 transitions.
[2024-12-02 06:15:25,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37845 states and 48757 transitions.
[2024-12-02 06:15:25,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37845 to 37845.
[2024-12-02 06:15:25,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37845 states, 37845 states have (on average 1.2883339939225789) internal successors, (48757), 37844 states have internal predecessors, (48757), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2024-12-02 06:15:25,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37845 states to 37845 states and 48757 transitions.
[2024-12-02 06:15:25,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37845 states and 48757 transitions.
[2024-12-02 06:15:25,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states.
[2024-12-02 06:15:25,898 INFO L425 stractBuchiCegarLoop]: Abstraction has 37845 states and 48757 transitions.
[2024-12-02 06:15:25,898 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============
[2024-12-02 06:15:25,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37845 states and 48757 transitions.
[2024-12-02 06:15:25,942 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 35483
[2024-12-02 06:15:25,942 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2024-12-02 06:15:25,942 INFO L119 BuchiIsEmpty]: Starting construction of run
[2024-12-02 06:15:25,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:25,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2024-12-02 06:15:25,943 INFO L747 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;"
[2024-12-02 06:15:25,943 INFO L749 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" "assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp_ndt_3~0#1);" "havoc eval_~tmp_ndt_3~0#1;" "assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp_ndt_4~0#1);" "havoc eval_~tmp_ndt_4~0#1;" "assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp_ndt_5~0#1);" "havoc eval_~tmp_ndt_5~0#1;" "assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp_ndt_6~0#1);" "havoc eval_~tmp_ndt_6~0#1;"
[2024-12-02 06:15:25,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:25,943 INFO L85 PathProgramCache]: Analyzing trace with hash -926716884, now seen corresponding path program 6 times
[2024-12-02 06:15:25,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:25,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46836682]
[2024-12-02 06:15:25,943 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:25,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:25,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,951 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:25,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,963 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:25,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:25,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1710756937, now seen corresponding path program 1 times
[2024-12-02 06:15:25,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:25,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418149356]
[2024-12-02 06:15:25,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:25,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:25,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,966 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:25,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:25,969 INFO L157 PredicateUnifier]: Initialized classic predicate unifier
[2024-12-02 06:15:25,969 INFO L85 PathProgramCache]: Analyzing trace with hash -1569849556, now seen corresponding path program 1 times
[2024-12-02 06:15:25,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL_NO_AM
[2024-12-02 06:15:25,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1204590359]
[2024-12-02 06:15:25,970 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2024-12-02 06:15:25,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2024-12-02 06:15:25,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,977 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:25,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:25,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL_NO_AM found a feasible trace
[2024-12-02 06:15:27,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:27,229 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2024-12-02 06:15:27,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat
[2024-12-02 06:15:27,369 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 02.12 06:15:27 BoogieIcfgContainer
[2024-12-02 06:15:27,369 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2024-12-02 06:15:27,370 INFO L112 PluginConnector]: ------------------------Witness Printer----------------------------
[2024-12-02 06:15:27,370 INFO L270 PluginConnector]: Initializing Witness Printer...
[2024-12-02 06:15:27,370 INFO L274 PluginConnector]: Witness Printer initialized
[2024-12-02 06:15:27,371 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 06:15:14" (3/4) ...
[2024-12-02 06:15:27,373 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample
[2024-12-02 06:15:27,460 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/witness.graphml
[2024-12-02 06:15:27,460 INFO L131 PluginConnector]: ------------------------ END Witness Printer----------------------------
[2024-12-02 06:15:27,461 INFO L158 Benchmark]: Toolchain (without parser) took 14625.03ms. Allocated memory was 142.6MB in the beginning and 1.1GB in the end (delta: 922.7MB). Free memory was 116.9MB in the beginning and 568.9MB in the end (delta: -452.0MB). Peak memory consumption was 465.9MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,461 INFO L158 Benchmark]: CDTParser took 0.33ms. Allocated memory is still 142.6MB. Free memory was 83.6MB in the beginning and 83.4MB in the end (delta: 146.8kB). There was no memory consumed. Max. memory is 16.1GB.
[2024-12-02 06:15:27,462 INFO L158 Benchmark]: CACSL2BoogieTranslator took 277.62ms. Allocated memory is still 142.6MB. Free memory was 116.9MB in the beginning and 101.2MB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,462 INFO L158 Benchmark]: Boogie Procedure Inliner took 46.66ms. Allocated memory is still 142.6MB. Free memory was 101.0MB in the beginning and 96.7MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB.
[2024-12-02 06:15:27,462 INFO L158 Benchmark]: Boogie Preprocessor took 64.05ms. Allocated memory is still 142.6MB. Free memory was 96.7MB in the beginning and 91.3MB in the end (delta: 5.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,462 INFO L158 Benchmark]: RCFGBuilder took 947.28ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 82.8MB in the end (delta: 8.5MB). Peak memory consumption was 49.3MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,463 INFO L158 Benchmark]: BuchiAutomizer took 13194.17ms. Allocated memory was 142.6MB in the beginning and 1.1GB in the end (delta: 922.7MB). Free memory was 82.8MB in the beginning and 581.4MB in the end (delta: -498.6MB). Peak memory consumption was 425.0MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,463 INFO L158 Benchmark]: Witness Printer took 90.32ms. Allocated memory is still 1.1GB. Free memory was 581.4MB in the beginning and 568.9MB in the end (delta: 12.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2024-12-02 06:15:27,465 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] #######################
--- Results ---
* Results from de.uni_freiburg.informatik.ultimate.core:
- StatisticsResult: Toolchain Benchmarks
Benchmark results are:
* CDTParser took 0.33ms. Allocated memory is still 142.6MB. Free memory was 83.6MB in the beginning and 83.4MB in the end (delta: 146.8kB). There was no memory consumed. Max. memory is 16.1GB.
* CACSL2BoogieTranslator took 277.62ms. Allocated memory is still 142.6MB. Free memory was 116.9MB in the beginning and 101.2MB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
* Boogie Procedure Inliner took 46.66ms. Allocated memory is still 142.6MB. Free memory was 101.0MB in the beginning and 96.7MB in the end (delta: 4.2MB). There was no memory consumed. Max. memory is 16.1GB.
* Boogie Preprocessor took 64.05ms. Allocated memory is still 142.6MB. Free memory was 96.7MB in the beginning and 91.3MB in the end (delta: 5.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
* RCFGBuilder took 947.28ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 82.8MB in the end (delta: 8.5MB). Peak memory consumption was 49.3MB. Max. memory is 16.1GB.
* BuchiAutomizer took 13194.17ms. Allocated memory was 142.6MB in the beginning and 1.1GB in the end (delta: 922.7MB). Free memory was 82.8MB in the beginning and 581.4MB in the end (delta: -498.6MB). Peak memory consumption was 425.0MB. Max. memory is 16.1GB.
* Witness Printer took 90.32ms. Allocated memory is still 1.1GB. Free memory was 581.4MB in the beginning and 568.9MB in the end (delta: 12.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
* Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
- StatisticsResult: Constructed decomposition of program
Your program was decomposed into 18 terminating modules (18 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.18 modules have a trivial ranking function, the largest among these consists of 8 locations. The remainder module has 37845 locations.
- StatisticsResult: Timing statistics
BüchiAutomizer plugin needed 13.0s and 19 iterations. TraceHistogramMax:1. Analysis of lassos took 8.0s. Construction of modules took 0.7s. Büchi inclusion checks took 3.7s. Highest rank in rank-based complementation 0. Minimization of det autom 18. Minimization of nondet autom 0. Automata minimization 1.8s AutomataMinimizationTime, 18 MinimizatonAttempts, 2828 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.9s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 13479 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 13479 mSDsluCounter, 29986 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 17128 mSDsCounter, 311 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 984 IncrementalHoareTripleChecker+Invalid, 1295 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 311 mSolverCounterUnsat, 12858 mSDtfsCounter, 984 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc5 concLT0 SILN1 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s
- TerminationAnalysisResult: Nontermination possible
Buchi Automizer proved that your program is nonterminating for some inputs
- LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution.
Nontermination argument in form of an infinite program execution.
Stem:
[L25] int m_pc = 0;
[L26] int t1_pc = 0;
[L27] int t2_pc = 0;
[L28] int t3_pc = 0;
[L29] int t4_pc = 0;
[L30] int t5_pc = 0;
[L31] int m_st ;
[L32] int t1_st ;
[L33] int t2_st ;
[L34] int t3_st ;
[L35] int t4_st ;
[L36] int t5_st ;
[L37] int m_i ;
[L38] int t1_i ;
[L39] int t2_i ;
[L40] int t3_i ;
[L41] int t4_i ;
[L42] int t5_i ;
[L43] int M_E = 2;
[L44] int T1_E = 2;
[L45] int T2_E = 2;
[L46] int T3_E = 2;
[L47] int T4_E = 2;
[L48] int T5_E = 2;
[L49] int E_1 = 2;
[L50] int E_2 = 2;
[L51] int E_3 = 2;
[L52] int E_4 = 2;
[L53] int E_5 = 2;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0]
[L945] int __retres1 ;
[L949] CALL init_model()
[L856] m_i = 1
[L857] t1_i = 1
[L858] t2_i = 1
[L859] t3_i = 1
[L860] t4_i = 1
[L861] t5_i = 1
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L949] RET init_model()
[L950] CALL start_simulation()
[L886] int kernel_st ;
[L887] int tmp ;
[L888] int tmp___0 ;
[L892] kernel_st = 0
[L893] FCALL update_channels()
[L894] CALL init_threads()
[L401] COND TRUE m_i == 1
[L402] m_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L406] COND TRUE t1_i == 1
[L407] t1_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L411] COND TRUE t2_i == 1
[L412] t2_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L416] COND TRUE t3_i == 1
[L417] t3_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L421] COND TRUE t4_i == 1
[L422] t4_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L426] COND TRUE t5_i == 1
[L427] t5_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L894] RET init_threads()
[L895] CALL fire_delta_events()
[L586] COND FALSE !(M_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L591] COND FALSE !(T1_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L596] COND FALSE !(T2_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L601] COND FALSE !(T3_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L606] COND FALSE !(T4_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L611] COND FALSE !(T5_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L616] COND FALSE !(E_1 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L621] COND FALSE !(E_2 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L626] COND FALSE !(E_3 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L631] COND FALSE !(E_4 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L636] COND FALSE !(E_5 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L895] RET fire_delta_events()
[L896] CALL activate_threads()
[L709] int tmp ;
[L710] int tmp___0 ;
[L711] int tmp___1 ;
[L712] int tmp___2 ;
[L713] int tmp___3 ;
[L714] int tmp___4 ;
[L718] CALL, EXPR is_master_triggered()
[L276] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L279] COND FALSE !(m_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L289] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L291] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L718] RET, EXPR is_master_triggered()
[L718] tmp = is_master_triggered()
[L720] COND FALSE !(\read(tmp))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726] CALL, EXPR is_transmit1_triggered()
[L295] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L298] COND FALSE !(t1_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L308] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L310] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726] RET, EXPR is_transmit1_triggered()
[L726] tmp___0 = is_transmit1_triggered()
[L728] COND FALSE !(\read(tmp___0))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734] CALL, EXPR is_transmit2_triggered()
[L314] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L317] COND FALSE !(t2_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L327] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L329] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734] RET, EXPR is_transmit2_triggered()
[L734] tmp___1 = is_transmit2_triggered()
[L736] COND FALSE !(\read(tmp___1))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742] CALL, EXPR is_transmit3_triggered()
[L333] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L336] COND FALSE !(t3_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L346] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L348] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742] RET, EXPR is_transmit3_triggered()
[L742] tmp___2 = is_transmit3_triggered()
[L744] COND FALSE !(\read(tmp___2))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750] CALL, EXPR is_transmit4_triggered()
[L352] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L355] COND FALSE !(t4_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L365] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L367] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750] RET, EXPR is_transmit4_triggered()
[L750] tmp___3 = is_transmit4_triggered()
[L752] COND FALSE !(\read(tmp___3))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758] CALL, EXPR is_transmit5_triggered()
[L371] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L374] COND FALSE !(t5_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L384] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L386] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758] RET, EXPR is_transmit5_triggered()
[L758] tmp___4 = is_transmit5_triggered()
[L760] COND FALSE !(\read(tmp___4))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L896] RET activate_threads()
[L897] CALL reset_delta_events()
[L649] COND FALSE !(M_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L654] COND FALSE !(T1_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L659] COND FALSE !(T2_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L664] COND FALSE !(T3_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L669] COND FALSE !(T4_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L674] COND FALSE !(T5_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L679] COND FALSE !(E_1 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L684] COND FALSE !(E_2 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L689] COND FALSE !(E_3 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L694] COND FALSE !(E_4 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L699] COND FALSE !(E_5 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L897] RET reset_delta_events()
[L903] kernel_st = 1
[L904] CALL eval()
[L477] int tmp ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
Loop:
[L484] CALL, EXPR exists_runnable_thread()
[L436] int __retres1 ;
[L439] COND TRUE m_st == 0
[L440] __retres1 = 1
[L472] return (__retres1);
[L484] RET, EXPR exists_runnable_thread()
[L484] tmp = exists_runnable_thread()
[L486] COND TRUE \read(tmp)
[L491] COND TRUE m_st == 0
[L492] int tmp_ndt_1;
[L493] tmp_ndt_1 = __VERIFIER_nondet_int()
[L494] COND FALSE !(\read(tmp_ndt_1))
[L505] COND TRUE t1_st == 0
[L506] int tmp_ndt_2;
[L507] tmp_ndt_2 = __VERIFIER_nondet_int()
[L508] COND FALSE !(\read(tmp_ndt_2))
[L519] COND TRUE t2_st == 0
[L520] int tmp_ndt_3;
[L521] tmp_ndt_3 = __VERIFIER_nondet_int()
[L522] COND FALSE !(\read(tmp_ndt_3))
[L533] COND TRUE t3_st == 0
[L534] int tmp_ndt_4;
[L535] tmp_ndt_4 = __VERIFIER_nondet_int()
[L536] COND FALSE !(\read(tmp_ndt_4))
[L547] COND TRUE t4_st == 0
[L548] int tmp_ndt_5;
[L549] tmp_ndt_5 = __VERIFIER_nondet_int()
[L550] COND FALSE !(\read(tmp_ndt_5))
[L561] COND TRUE t5_st == 0
[L562] int tmp_ndt_6;
[L563] tmp_ndt_6 = __VERIFIER_nondet_int()
[L564] COND FALSE !(\read(tmp_ndt_6))
End of lasso representation.
- StatisticsResult: NonterminationArgumentStatistics
Fixpoint
- NonterminatingLassoResult [Line: 1]: Nonterminating execution
Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25] int m_pc = 0;
[L26] int t1_pc = 0;
[L27] int t2_pc = 0;
[L28] int t3_pc = 0;
[L29] int t4_pc = 0;
[L30] int t5_pc = 0;
[L31] int m_st ;
[L32] int t1_st ;
[L33] int t2_st ;
[L34] int t3_st ;
[L35] int t4_st ;
[L36] int t5_st ;
[L37] int m_i ;
[L38] int t1_i ;
[L39] int t2_i ;
[L40] int t3_i ;
[L41] int t4_i ;
[L42] int t5_i ;
[L43] int M_E = 2;
[L44] int T1_E = 2;
[L45] int T2_E = 2;
[L46] int T3_E = 2;
[L47] int T4_E = 2;
[L48] int T5_E = 2;
[L49] int E_1 = 2;
[L50] int E_2 = 2;
[L51] int E_3 = 2;
[L52] int E_4 = 2;
[L53] int E_5 = 2;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0]
[L945] int __retres1 ;
[L949] CALL init_model()
[L856] m_i = 1
[L857] t1_i = 1
[L858] t2_i = 1
[L859] t3_i = 1
[L860] t4_i = 1
[L861] t5_i = 1
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L949] RET init_model()
[L950] CALL start_simulation()
[L886] int kernel_st ;
[L887] int tmp ;
[L888] int tmp___0 ;
[L892] kernel_st = 0
[L893] FCALL update_channels()
[L894] CALL init_threads()
[L401] COND TRUE m_i == 1
[L402] m_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L406] COND TRUE t1_i == 1
[L407] t1_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L411] COND TRUE t2_i == 1
[L412] t2_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L416] COND TRUE t3_i == 1
[L417] t3_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L421] COND TRUE t4_i == 1
[L422] t4_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L426] COND TRUE t5_i == 1
[L427] t5_st = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L894] RET init_threads()
[L895] CALL fire_delta_events()
[L586] COND FALSE !(M_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L591] COND FALSE !(T1_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L596] COND FALSE !(T2_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L601] COND FALSE !(T3_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L606] COND FALSE !(T4_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L611] COND FALSE !(T5_E == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L616] COND FALSE !(E_1 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L621] COND FALSE !(E_2 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L626] COND FALSE !(E_3 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L631] COND FALSE !(E_4 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L636] COND FALSE !(E_5 == 0)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L895] RET fire_delta_events()
[L896] CALL activate_threads()
[L709] int tmp ;
[L710] int tmp___0 ;
[L711] int tmp___1 ;
[L712] int tmp___2 ;
[L713] int tmp___3 ;
[L714] int tmp___4 ;
[L718] CALL, EXPR is_master_triggered()
[L276] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L279] COND FALSE !(m_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L289] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L291] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L718] RET, EXPR is_master_triggered()
[L718] tmp = is_master_triggered()
[L720] COND FALSE !(\read(tmp))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726] CALL, EXPR is_transmit1_triggered()
[L295] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L298] COND FALSE !(t1_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L308] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L310] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L726] RET, EXPR is_transmit1_triggered()
[L726] tmp___0 = is_transmit1_triggered()
[L728] COND FALSE !(\read(tmp___0))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734] CALL, EXPR is_transmit2_triggered()
[L314] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L317] COND FALSE !(t2_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L327] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L329] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L734] RET, EXPR is_transmit2_triggered()
[L734] tmp___1 = is_transmit2_triggered()
[L736] COND FALSE !(\read(tmp___1))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742] CALL, EXPR is_transmit3_triggered()
[L333] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L336] COND FALSE !(t3_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L346] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L348] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L742] RET, EXPR is_transmit3_triggered()
[L742] tmp___2 = is_transmit3_triggered()
[L744] COND FALSE !(\read(tmp___2))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750] CALL, EXPR is_transmit4_triggered()
[L352] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L355] COND FALSE !(t4_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L365] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L367] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L750] RET, EXPR is_transmit4_triggered()
[L750] tmp___3 = is_transmit4_triggered()
[L752] COND FALSE !(\read(tmp___3))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758] CALL, EXPR is_transmit5_triggered()
[L371] int __retres1 ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L374] COND FALSE !(t5_pc == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L384] __retres1 = 0
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L386] return (__retres1);
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L758] RET, EXPR is_transmit5_triggered()
[L758] tmp___4 = is_transmit5_triggered()
[L760] COND FALSE !(\read(tmp___4))
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L896] RET activate_threads()
[L897] CALL reset_delta_events()
[L649] COND FALSE !(M_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L654] COND FALSE !(T1_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L659] COND FALSE !(T2_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L664] COND FALSE !(T3_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L669] COND FALSE !(T4_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L674] COND FALSE !(T5_E == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L679] COND FALSE !(E_1 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L684] COND FALSE !(E_2 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L689] COND FALSE !(E_3 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L694] COND FALSE !(E_4 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L699] COND FALSE !(E_5 == 1)
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
[L897] RET reset_delta_events()
[L903] kernel_st = 1
[L904] CALL eval()
[L477] int tmp ;
VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0]
Loop:
[L484] CALL, EXPR exists_runnable_thread()
[L436] int __retres1 ;
[L439] COND TRUE m_st == 0
[L440] __retres1 = 1
[L472] return (__retres1);
[L484] RET, EXPR exists_runnable_thread()
[L484] tmp = exists_runnable_thread()
[L486] COND TRUE \read(tmp)
[L491] COND TRUE m_st == 0
[L492] int tmp_ndt_1;
[L493] tmp_ndt_1 = __VERIFIER_nondet_int()
[L494] COND FALSE !(\read(tmp_ndt_1))
[L505] COND TRUE t1_st == 0
[L506] int tmp_ndt_2;
[L507] tmp_ndt_2 = __VERIFIER_nondet_int()
[L508] COND FALSE !(\read(tmp_ndt_2))
[L519] COND TRUE t2_st == 0
[L520] int tmp_ndt_3;
[L521] tmp_ndt_3 = __VERIFIER_nondet_int()
[L522] COND FALSE !(\read(tmp_ndt_3))
[L533] COND TRUE t3_st == 0
[L534] int tmp_ndt_4;
[L535] tmp_ndt_4 = __VERIFIER_nondet_int()
[L536] COND FALSE !(\read(tmp_ndt_4))
[L547] COND TRUE t4_st == 0
[L548] int tmp_ndt_5;
[L549] tmp_ndt_5 = __VERIFIER_nondet_int()
[L550] COND FALSE !(\read(tmp_ndt_5))
[L561] COND TRUE t5_st == 0
[L562] int tmp_ndt_6;
[L563] tmp_ndt_6 = __VERIFIER_nondet_int()
[L564] COND FALSE !(\read(tmp_ndt_6))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2024-12-02 06:15:27,483 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Ended with exit code 0
[2024-12-02 06:15:27,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Ended with exit code 0
[2024-12-02 06:15:27,879 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Ended with exit code 0
[2024-12-02 06:15:28,084 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0
[2024-12-02 06:15:28,279 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Ended with exit code 0
[2024-12-02 06:15:28,479 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0
[2024-12-02 06:15:28,680 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Ended with exit code 0
[2024-12-02 06:15:28,880 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0
[2024-12-02 06:15:29,080 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0
[2024-12-02 06:15:29,280 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0
[2024-12-02 06:15:29,480 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0
[2024-12-02 06:15:29,681 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0
[2024-12-02 06:15:29,881 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0
[2024-12-02 06:15:30,081 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0
[2024-12-02 06:15:30,281 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0
[2024-12-02 06:15:30,484 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0
[2024-12-02 06:15:30,682 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0
[2024-12-02 06:15:30,882 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0
[2024-12-02 06:15:31,087 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0
[2024-12-02 06:15:31,283 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0
[2024-12-02 06:15:31,482 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0
[2024-12-02 06:15:31,683 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0
[2024-12-02 06:15:31,883 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0
[2024-12-02 06:15:32,083 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0
[2024-12-02 06:15:32,283 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0
[2024-12-02 06:15:32,484 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a8e6bac9-62c2-4d6d-adbe-916f54134f0f/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0
Received shutdown request...
--- End real Ultimate output ---
Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)