./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version d790fecc Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 52aaa0332eefa406b14bf0040bc722ffbb83771cf03ec10c7d17ac8a4e45d63a --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 11:22:48,291 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 11:22:48,344 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Default.epf [2024-12-02 11:22:48,348 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 11:22:48,348 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 11:22:48,368 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 11:22:48,369 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 11:22:48,369 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 11:22:48,369 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 11:22:48,369 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 11:22:48,370 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 11:22:48,370 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 11:22:48,370 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 11:22:48,370 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 11:22:48,370 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 11:22:48,370 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 11:22:48,371 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 11:22:48,371 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:22:48,372 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 11:22:48,372 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:22:48,373 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 11:22:48,373 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 52aaa0332eefa406b14bf0040bc722ffbb83771cf03ec10c7d17ac8a4e45d63a [2024-12-02 11:22:48,579 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 11:22:48,587 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 11:22:48,589 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 11:22:48,590 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 11:22:48,591 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 11:22:48,592 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:22:51,210 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/e3d59661b/3c1ad21dfbe248ea98d62e3ac01b87b1/FLAG50ff6524c [2024-12-02 11:22:51,473 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 11:22:51,474 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:22:51,485 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/e3d59661b/3c1ad21dfbe248ea98d62e3ac01b87b1/FLAG50ff6524c [2024-12-02 11:22:51,787 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/e3d59661b/3c1ad21dfbe248ea98d62e3ac01b87b1 [2024-12-02 11:22:51,788 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 11:22:51,789 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 11:22:51,790 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 11:22:51,790 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 11:22:51,793 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 11:22:51,794 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:22:51" (1/1) ... [2024-12-02 11:22:51,794 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7fb1b8ca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:51, skipping insertion in model container [2024-12-02 11:22:51,794 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:22:51" (1/1) ... [2024-12-02 11:22:51,819 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 11:22:51,957 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c[1335,1348] [2024-12-02 11:22:52,122 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:22:52,131 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 11:22:52,140 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c[1335,1348] [2024-12-02 11:22:52,229 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:22:52,242 INFO L204 MainTranslator]: Completed translation [2024-12-02 11:22:52,242 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52 WrapperNode [2024-12-02 11:22:52,243 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 11:22:52,243 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 11:22:52,243 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 11:22:52,243 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 11:22:52,248 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,269 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,432 INFO L138 Inliner]: procedures = 18, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1976 [2024-12-02 11:22:52,432 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 11:22:52,433 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 11:22:52,433 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 11:22:52,433 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 11:22:52,441 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,441 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,466 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,520 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-12-02 11:22:52,520 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,520 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,561 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,568 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,578 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,595 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,603 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,637 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 11:22:52,638 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 11:22:52,638 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 11:22:52,638 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 11:22:52,639 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (1/1) ... [2024-12-02 11:22:52,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:22:52,654 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:22:52,666 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 11:22:52,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 11:22:52,692 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 11:22:52,692 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 11:22:52,692 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 11:22:52,692 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-12-02 11:22:52,692 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 11:22:52,692 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 11:22:52,892 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 11:22:52,894 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 11:22:54,856 INFO L? ?]: Removed 1091 outVars from TransFormulas that were not future-live. [2024-12-02 11:22:54,857 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 11:22:54,875 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 11:22:54,876 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-12-02 11:22:54,876 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:22:54 BoogieIcfgContainer [2024-12-02 11:22:54,876 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 11:22:54,878 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 11:22:54,878 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 11:22:54,882 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 11:22:54,882 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 11:22:51" (1/3) ... [2024-12-02 11:22:54,883 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c992f22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 11:22:54, skipping insertion in model container [2024-12-02 11:22:54,883 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:22:52" (2/3) ... [2024-12-02 11:22:54,883 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5c992f22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 11:22:54, skipping insertion in model container [2024-12-02 11:22:54,883 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:22:54" (3/3) ... [2024-12-02 11:22:54,884 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:22:54,896 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 11:22:54,897 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c that has 2 procedures, 552 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-12-02 11:22:54,946 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 11:22:54,957 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@5ae39152, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 11:22:54,957 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 11:22:54,961 INFO L276 IsEmpty]: Start isEmpty. Operand has 552 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 547 states have internal predecessors, (816), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:54,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2024-12-02 11:22:54,972 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:54,973 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:54,973 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:54,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:54,977 INFO L85 PathProgramCache]: Analyzing trace with hash 105595379, now seen corresponding path program 1 times [2024-12-02 11:22:54,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:54,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1611988277] [2024-12-02 11:22:54,983 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:54,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:55,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:55,343 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-12-02 11:22:55,344 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:55,344 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1611988277] [2024-12-02 11:22:55,344 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1611988277] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:22:55,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [420017063] [2024-12-02 11:22:55,345 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:55,345 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:22:55,345 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:22:55,347 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:22:55,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 11:22:55,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:55,796 INFO L256 TraceCheckSpWp]: Trace formula consists of 929 conjuncts, 1 conjuncts are in the unsatisfiable core [2024-12-02 11:22:55,805 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:22:55,823 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2024-12-02 11:22:55,823 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:22:55,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [420017063] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:55,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:22:55,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [2] total 2 [2024-12-02 11:22:55,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328574192] [2024-12-02 11:22:55,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:55,830 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2024-12-02 11:22:55,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:55,850 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-12-02 11:22:55,850 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 11:22:55,853 INFO L87 Difference]: Start difference. First operand has 552 states, 546 states have (on average 1.4945054945054945) internal successors, (816), 547 states have internal predecessors, (816), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:22:55,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:22:55,913 INFO L93 Difference]: Finished difference Result 999 states and 1493 transitions. [2024-12-02 11:22:55,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-12-02 11:22:55,916 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) Word has length 149 [2024-12-02 11:22:55,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:22:55,925 INFO L225 Difference]: With dead ends: 999 [2024-12-02 11:22:55,925 INFO L226 Difference]: Without dead ends: 549 [2024-12-02 11:22:55,928 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 150 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-12-02 11:22:55,930 INFO L435 NwaCegarLoop]: 817 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 0 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 817 SdHoareTripleChecker+Invalid, 0 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 0 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:22:55,931 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 817 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 0 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:22:55,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states. [2024-12-02 11:22:55,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 549. [2024-12-02 11:22:55,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 549 states, 544 states have (on average 1.4908088235294117) internal successors, (811), 544 states have internal predecessors, (811), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:55,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 549 states to 549 states and 817 transitions. [2024-12-02 11:22:55,984 INFO L78 Accepts]: Start accepts. Automaton has 549 states and 817 transitions. Word has length 149 [2024-12-02 11:22:55,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:22:55,984 INFO L471 AbstractCegarLoop]: Abstraction has 549 states and 817 transitions. [2024-12-02 11:22:55,985 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:22:55,985 INFO L276 IsEmpty]: Start isEmpty. Operand 549 states and 817 transitions. [2024-12-02 11:22:55,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2024-12-02 11:22:55,988 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:55,988 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:55,996 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 11:22:56,188 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2024-12-02 11:22:56,189 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:56,189 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:56,189 INFO L85 PathProgramCache]: Analyzing trace with hash 677396781, now seen corresponding path program 1 times [2024-12-02 11:22:56,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:56,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955616385] [2024-12-02 11:22:56,190 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:56,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:56,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:57,191 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:22:57,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:57,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955616385] [2024-12-02 11:22:57,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955616385] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:57,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:22:57,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:22:57,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874477199] [2024-12-02 11:22:57,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:57,193 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:22:57,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:57,193 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:22:57,194 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:22:57,194 INFO L87 Difference]: Start difference. First operand 549 states and 817 transitions. Second operand has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:57,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:22:57,234 INFO L93 Difference]: Finished difference Result 553 states and 821 transitions. [2024-12-02 11:22:57,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:22:57,234 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 149 [2024-12-02 11:22:57,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:22:57,237 INFO L225 Difference]: With dead ends: 553 [2024-12-02 11:22:57,237 INFO L226 Difference]: Without dead ends: 551 [2024-12-02 11:22:57,238 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:22:57,238 INFO L435 NwaCegarLoop]: 815 mSDtfsCounter, 0 mSDsluCounter, 1624 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2439 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:22:57,239 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2439 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:22:57,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2024-12-02 11:22:57,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2024-12-02 11:22:57,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 546 states have (on average 1.489010989010989) internal successors, (813), 546 states have internal predecessors, (813), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:57,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 819 transitions. [2024-12-02 11:22:57,256 INFO L78 Accepts]: Start accepts. Automaton has 551 states and 819 transitions. Word has length 149 [2024-12-02 11:22:57,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:22:57,258 INFO L471 AbstractCegarLoop]: Abstraction has 551 states and 819 transitions. [2024-12-02 11:22:57,258 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 34.25) internal successors, (137), 4 states have internal predecessors, (137), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:57,258 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 819 transitions. [2024-12-02 11:22:57,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 151 [2024-12-02 11:22:57,260 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:57,260 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:57,260 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2024-12-02 11:22:57,260 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:57,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:57,261 INFO L85 PathProgramCache]: Analyzing trace with hash -473840291, now seen corresponding path program 1 times [2024-12-02 11:22:57,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:57,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376239628] [2024-12-02 11:22:57,261 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:57,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:57,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:57,814 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:22:57,814 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:57,814 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1376239628] [2024-12-02 11:22:57,814 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1376239628] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:57,814 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:22:57,815 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:22:57,815 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904150894] [2024-12-02 11:22:57,815 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:57,815 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:22:57,815 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:57,816 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:22:57,816 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:22:57,816 INFO L87 Difference]: Start difference. First operand 551 states and 819 transitions. Second operand has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:58,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:22:58,279 INFO L93 Difference]: Finished difference Result 1371 states and 2041 transitions. [2024-12-02 11:22:58,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:22:58,280 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 150 [2024-12-02 11:22:58,280 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:22:58,282 INFO L225 Difference]: With dead ends: 1371 [2024-12-02 11:22:58,283 INFO L226 Difference]: Without dead ends: 551 [2024-12-02 11:22:58,284 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2024-12-02 11:22:58,284 INFO L435 NwaCegarLoop]: 861 mSDtfsCounter, 1618 mSDsluCounter, 1490 mSDsCounter, 0 mSdLazyCounter, 302 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1618 SdHoareTripleChecker+Valid, 2351 SdHoareTripleChecker+Invalid, 339 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 302 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:22:58,285 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1618 Valid, 2351 Invalid, 339 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 302 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:22:58,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2024-12-02 11:22:58,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 551. [2024-12-02 11:22:58,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 551 states, 546 states have (on average 1.4871794871794872) internal successors, (812), 546 states have internal predecessors, (812), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:58,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 551 states to 551 states and 818 transitions. [2024-12-02 11:22:58,299 INFO L78 Accepts]: Start accepts. Automaton has 551 states and 818 transitions. Word has length 150 [2024-12-02 11:22:58,299 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:22:58,299 INFO L471 AbstractCegarLoop]: Abstraction has 551 states and 818 transitions. [2024-12-02 11:22:58,299 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 27.6) internal successors, (138), 5 states have internal predecessors, (138), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:58,299 INFO L276 IsEmpty]: Start isEmpty. Operand 551 states and 818 transitions. [2024-12-02 11:22:58,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 152 [2024-12-02 11:22:58,301 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:58,301 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:58,301 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2024-12-02 11:22:58,301 INFO L396 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:58,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:58,302 INFO L85 PathProgramCache]: Analyzing trace with hash -1290588625, now seen corresponding path program 1 times [2024-12-02 11:22:58,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:58,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145657799] [2024-12-02 11:22:58,302 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:58,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:58,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:58,776 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:22:58,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:58,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145657799] [2024-12-02 11:22:58,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145657799] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:58,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:22:58,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:22:58,776 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025953339] [2024-12-02 11:22:58,776 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:58,777 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:22:58,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:58,778 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:22:58,778 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:22:58,778 INFO L87 Difference]: Start difference. First operand 551 states and 818 transitions. Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:58,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:22:58,823 INFO L93 Difference]: Finished difference Result 1002 states and 1487 transitions. [2024-12-02 11:22:58,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:22:58,824 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 151 [2024-12-02 11:22:58,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:22:58,827 INFO L225 Difference]: With dead ends: 1002 [2024-12-02 11:22:58,827 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:22:58,828 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:22:58,828 INFO L435 NwaCegarLoop]: 814 mSDtfsCounter, 0 mSDsluCounter, 1618 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2432 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:22:58,829 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2432 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:22:58,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:22:58,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:22:58,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4854014598540146) internal successors, (814), 548 states have internal predecessors, (814), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:58,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 820 transitions. [2024-12-02 11:22:58,846 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 820 transitions. Word has length 151 [2024-12-02 11:22:58,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:22:58,847 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 820 transitions. [2024-12-02 11:22:58,847 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 34.75) internal successors, (139), 4 states have internal predecessors, (139), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:58,847 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 820 transitions. [2024-12-02 11:22:58,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2024-12-02 11:22:58,849 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:58,849 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:58,849 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2024-12-02 11:22:58,850 INFO L396 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:58,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:58,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1843460468, now seen corresponding path program 1 times [2024-12-02 11:22:58,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:58,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69446080] [2024-12-02 11:22:58,850 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:58,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:58,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:59,347 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:22:59,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:59,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69446080] [2024-12-02 11:22:59,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69446080] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:59,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:22:59,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:22:59,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057888915] [2024-12-02 11:22:59,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:59,348 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:22:59,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:59,348 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:22:59,349 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:22:59,349 INFO L87 Difference]: Start difference. First operand 553 states and 820 transitions. Second operand has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:59,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:22:59,530 INFO L93 Difference]: Finished difference Result 1004 states and 1488 transitions. [2024-12-02 11:22:59,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:22:59,530 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 152 [2024-12-02 11:22:59,531 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:22:59,533 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:22:59,533 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:22:59,534 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:22:59,534 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 694 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 164 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 694 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 164 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 164 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:22:59,534 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [694 Valid, 1470 Invalid, 164 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 164 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:22:59,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:22:59,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:22:59,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4835766423357664) internal successors, (813), 548 states have internal predecessors, (813), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:22:59,551 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 819 transitions. [2024-12-02 11:22:59,551 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 819 transitions. Word has length 152 [2024-12-02 11:22:59,552 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:22:59,552 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 819 transitions. [2024-12-02 11:22:59,552 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 35.0) internal successors, (140), 4 states have internal predecessors, (140), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:22:59,552 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 819 transitions. [2024-12-02 11:22:59,553 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 154 [2024-12-02 11:22:59,553 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:22:59,553 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:22:59,553 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2024-12-02 11:22:59,553 INFO L396 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:22:59,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:22:59,554 INFO L85 PathProgramCache]: Analyzing trace with hash -954896960, now seen corresponding path program 1 times [2024-12-02 11:22:59,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:22:59,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082328597] [2024-12-02 11:22:59,554 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:22:59,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:22:59,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:22:59,837 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:22:59,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:22:59,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082328597] [2024-12-02 11:22:59,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082328597] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:22:59,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:22:59,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:22:59,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1409717614] [2024-12-02 11:22:59,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:22:59,838 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:22:59,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:22:59,839 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:22:59,839 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:22:59,839 INFO L87 Difference]: Start difference. First operand 553 states and 819 transitions. Second operand has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:00,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:00,001 INFO L93 Difference]: Finished difference Result 1010 states and 1494 transitions. [2024-12-02 11:23:00,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:23:00,002 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 153 [2024-12-02 11:23:00,002 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:00,005 INFO L225 Difference]: With dead ends: 1010 [2024-12-02 11:23:00,005 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:00,006 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:00,007 INFO L435 NwaCegarLoop]: 806 mSDtfsCounter, 705 mSDsluCounter, 1544 mSDsCounter, 0 mSdLazyCounter, 98 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 705 SdHoareTripleChecker+Valid, 2350 SdHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 98 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:00,007 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [705 Valid, 2350 Invalid, 100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 98 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:00,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:00,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:00,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4817518248175183) internal successors, (812), 548 states have internal predecessors, (812), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:00,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 818 transitions. [2024-12-02 11:23:00,022 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 818 transitions. Word has length 153 [2024-12-02 11:23:00,022 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:00,022 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 818 transitions. [2024-12-02 11:23:00,022 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.2) internal successors, (141), 5 states have internal predecessors, (141), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:00,022 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 818 transitions. [2024-12-02 11:23:00,024 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2024-12-02 11:23:00,024 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:00,024 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:00,024 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2024-12-02 11:23:00,024 INFO L396 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:00,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:00,025 INFO L85 PathProgramCache]: Analyzing trace with hash 690807295, now seen corresponding path program 1 times [2024-12-02 11:23:00,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:00,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744540239] [2024-12-02 11:23:00,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:00,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:00,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:00,440 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:00,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:00,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744540239] [2024-12-02 11:23:00,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744540239] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:00,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:00,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:00,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942649269] [2024-12-02 11:23:00,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:00,441 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:00,441 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:00,441 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:00,441 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:00,442 INFO L87 Difference]: Start difference. First operand 553 states and 818 transitions. Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:00,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:00,609 INFO L93 Difference]: Finished difference Result 1004 states and 1484 transitions. [2024-12-02 11:23:00,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:00,609 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 154 [2024-12-02 11:23:00,610 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:00,611 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:00,611 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:00,612 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:00,613 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 802 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 160 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 805 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 161 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 160 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:00,613 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [805 Valid, 1477 Invalid, 161 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 160 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:00,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:00,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:00,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.47992700729927) internal successors, (811), 548 states have internal predecessors, (811), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:00,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 817 transitions. [2024-12-02 11:23:00,628 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 817 transitions. Word has length 154 [2024-12-02 11:23:00,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:00,628 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 817 transitions. [2024-12-02 11:23:00,628 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:00,628 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 817 transitions. [2024-12-02 11:23:00,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2024-12-02 11:23:00,630 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:00,630 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:00,630 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2024-12-02 11:23:00,630 INFO L396 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:00,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:00,630 INFO L85 PathProgramCache]: Analyzing trace with hash -1444639353, now seen corresponding path program 1 times [2024-12-02 11:23:00,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:00,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077787511] [2024-12-02 11:23:00,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:00,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:00,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:00,922 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:00,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:00,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077787511] [2024-12-02 11:23:00,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077787511] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:00,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:00,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:00,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1543708029] [2024-12-02 11:23:00,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:00,923 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:00,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:00,924 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:00,924 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:00,924 INFO L87 Difference]: Start difference. First operand 553 states and 817 transitions. Second operand has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:01,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:01,085 INFO L93 Difference]: Finished difference Result 1004 states and 1482 transitions. [2024-12-02 11:23:01,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:01,085 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 155 [2024-12-02 11:23:01,086 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:01,087 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:01,087 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:01,087 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:01,088 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 798 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 158 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 801 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 158 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:01,088 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [801 Valid, 1477 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 158 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:01,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:01,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:01,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4781021897810218) internal successors, (810), 548 states have internal predecessors, (810), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:01,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 816 transitions. [2024-12-02 11:23:01,097 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 816 transitions. Word has length 155 [2024-12-02 11:23:01,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:01,097 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 816 transitions. [2024-12-02 11:23:01,098 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.6) internal successors, (143), 5 states have internal predecessors, (143), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:01,098 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 816 transitions. [2024-12-02 11:23:01,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2024-12-02 11:23:01,099 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:01,099 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:01,100 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2024-12-02 11:23:01,100 INFO L396 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:01,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:01,100 INFO L85 PathProgramCache]: Analyzing trace with hash 457554086, now seen corresponding path program 1 times [2024-12-02 11:23:01,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:01,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309398185] [2024-12-02 11:23:01,100 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:01,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:01,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:01,547 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:01,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:01,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309398185] [2024-12-02 11:23:01,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309398185] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:01,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:01,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:01,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [572084573] [2024-12-02 11:23:01,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:01,548 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:01,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:01,549 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:01,549 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:01,549 INFO L87 Difference]: Start difference. First operand 553 states and 816 transitions. Second operand has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:01,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:01,703 INFO L93 Difference]: Finished difference Result 1004 states and 1480 transitions. [2024-12-02 11:23:01,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:01,704 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 156 [2024-12-02 11:23:01,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:01,706 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:01,706 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:01,707 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:01,707 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 791 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 156 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 794 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 157 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 156 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:01,708 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [794 Valid, 1477 Invalid, 157 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 156 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:01,709 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:01,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:01,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4762773722627738) internal successors, (809), 548 states have internal predecessors, (809), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:01,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 815 transitions. [2024-12-02 11:23:01,723 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 815 transitions. Word has length 156 [2024-12-02 11:23:01,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:01,723 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 815 transitions. [2024-12-02 11:23:01,723 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 28.8) internal successors, (144), 5 states have internal predecessors, (144), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:01,723 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 815 transitions. [2024-12-02 11:23:01,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 158 [2024-12-02 11:23:01,725 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:01,725 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:01,725 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2024-12-02 11:23:01,725 INFO L396 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:01,726 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:01,726 INFO L85 PathProgramCache]: Analyzing trace with hash -1750596921, now seen corresponding path program 1 times [2024-12-02 11:23:01,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:01,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [682033659] [2024-12-02 11:23:01,726 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:01,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:01,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:02,128 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:02,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:02,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [682033659] [2024-12-02 11:23:02,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [682033659] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:02,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:02,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:02,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977988279] [2024-12-02 11:23:02,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:02,129 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:02,129 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:02,130 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:02,130 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:02,130 INFO L87 Difference]: Start difference. First operand 553 states and 815 transitions. Second operand has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:02,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:02,295 INFO L93 Difference]: Finished difference Result 1004 states and 1478 transitions. [2024-12-02 11:23:02,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:02,296 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 157 [2024-12-02 11:23:02,296 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:02,298 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:02,298 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:02,299 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:02,300 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 1465 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1468 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:02,301 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1468 Valid, 1470 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:02,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:02,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:02,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4744525547445255) internal successors, (808), 548 states have internal predecessors, (808), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:02,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 814 transitions. [2024-12-02 11:23:02,315 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 814 transitions. Word has length 157 [2024-12-02 11:23:02,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:02,315 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 814 transitions. [2024-12-02 11:23:02,316 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.0) internal successors, (145), 5 states have internal predecessors, (145), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:02,316 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 814 transitions. [2024-12-02 11:23:02,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2024-12-02 11:23:02,317 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:02,317 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:02,317 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2024-12-02 11:23:02,317 INFO L396 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:02,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:02,318 INFO L85 PathProgramCache]: Analyzing trace with hash -273443585, now seen corresponding path program 1 times [2024-12-02 11:23:02,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:02,318 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088471624] [2024-12-02 11:23:02,318 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:02,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:02,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:02,683 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:02,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:02,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088471624] [2024-12-02 11:23:02,683 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088471624] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:02,683 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:02,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:02,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303297524] [2024-12-02 11:23:02,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:02,684 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:02,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:02,684 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:02,684 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:02,685 INFO L87 Difference]: Start difference. First operand 553 states and 814 transitions. Second operand has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:02,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:02,846 INFO L93 Difference]: Finished difference Result 1004 states and 1476 transitions. [2024-12-02 11:23:02,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:02,847 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 158 [2024-12-02 11:23:02,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:02,849 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:02,850 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:02,850 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:02,851 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 1457 mSDsluCounter, 736 mSDsCounter, 0 mSdLazyCounter, 152 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1460 SdHoareTripleChecker+Valid, 1470 SdHoareTripleChecker+Invalid, 153 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:02,851 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1460 Valid, 1470 Invalid, 153 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 152 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:02,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:02,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:02,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4726277372262773) internal successors, (807), 548 states have internal predecessors, (807), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:02,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 813 transitions. [2024-12-02 11:23:02,867 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 813 transitions. Word has length 158 [2024-12-02 11:23:02,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:02,867 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 813 transitions. [2024-12-02 11:23:02,867 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.2) internal successors, (146), 5 states have internal predecessors, (146), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:02,868 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 813 transitions. [2024-12-02 11:23:02,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2024-12-02 11:23:02,869 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:02,869 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:02,869 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2024-12-02 11:23:02,869 INFO L396 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:02,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:02,870 INFO L85 PathProgramCache]: Analyzing trace with hash -808870848, now seen corresponding path program 1 times [2024-12-02 11:23:02,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:02,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199290276] [2024-12-02 11:23:02,870 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:02,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:02,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:03,218 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:03,218 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:03,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199290276] [2024-12-02 11:23:03,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199290276] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:03,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:03,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:03,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1015011966] [2024-12-02 11:23:03,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:03,219 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:03,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:03,219 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:03,220 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:03,220 INFO L87 Difference]: Start difference. First operand 553 states and 813 transitions. Second operand has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:03,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:03,376 INFO L93 Difference]: Finished difference Result 1004 states and 1474 transitions. [2024-12-02 11:23:03,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:03,377 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 159 [2024-12-02 11:23:03,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:03,379 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:03,379 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:03,380 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:03,381 INFO L435 NwaCegarLoop]: 734 mSDtfsCounter, 779 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 150 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 782 SdHoareTripleChecker+Valid, 1477 SdHoareTripleChecker+Invalid, 151 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 150 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:03,381 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [782 Valid, 1477 Invalid, 151 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 150 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:03,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:03,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:03,393 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4708029197080292) internal successors, (806), 548 states have internal predecessors, (806), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:03,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 812 transitions. [2024-12-02 11:23:03,396 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 812 transitions. Word has length 159 [2024-12-02 11:23:03,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:03,397 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 812 transitions. [2024-12-02 11:23:03,397 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.4) internal successors, (147), 5 states have internal predecessors, (147), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:03,397 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 812 transitions. [2024-12-02 11:23:03,399 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 161 [2024-12-02 11:23:03,399 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:03,399 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:03,399 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11 [2024-12-02 11:23:03,399 INFO L396 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:03,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:03,400 INFO L85 PathProgramCache]: Analyzing trace with hash -476571176, now seen corresponding path program 1 times [2024-12-02 11:23:03,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:03,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051247213] [2024-12-02 11:23:03,400 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:03,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:03,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:03,888 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:03,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:03,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051247213] [2024-12-02 11:23:03,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051247213] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:03,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:03,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:03,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334086443] [2024-12-02 11:23:03,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:03,889 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:03,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:03,890 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:03,890 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:03,890 INFO L87 Difference]: Start difference. First operand 553 states and 812 transitions. Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:03,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:03,999 INFO L93 Difference]: Finished difference Result 1004 states and 1472 transitions. [2024-12-02 11:23:03,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:04,000 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 160 [2024-12-02 11:23:04,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:04,002 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:04,002 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:04,003 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:04,003 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 694 mSDsluCounter, 768 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 694 SdHoareTripleChecker+Valid, 1534 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:04,003 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [694 Valid, 1534 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 84 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:04,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:04,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:04,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.468978102189781) internal successors, (805), 548 states have internal predecessors, (805), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:04,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 811 transitions. [2024-12-02 11:23:04,018 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 811 transitions. Word has length 160 [2024-12-02 11:23:04,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:04,019 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 811 transitions. [2024-12-02 11:23:04,019 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 37.0) internal successors, (148), 4 states have internal predecessors, (148), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:04,019 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 811 transitions. [2024-12-02 11:23:04,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2024-12-02 11:23:04,021 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:04,021 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:04,021 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12 [2024-12-02 11:23:04,021 INFO L396 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:04,021 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:04,021 INFO L85 PathProgramCache]: Analyzing trace with hash -431893312, now seen corresponding path program 1 times [2024-12-02 11:23:04,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:04,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693283941] [2024-12-02 11:23:04,022 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:04,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:04,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:04,342 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:04,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:04,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693283941] [2024-12-02 11:23:04,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693283941] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:04,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:04,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:04,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529759211] [2024-12-02 11:23:04,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:04,343 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:04,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:04,344 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:04,344 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:04,344 INFO L87 Difference]: Start difference. First operand 553 states and 811 transitions. Second operand has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:04,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:04,460 INFO L93 Difference]: Finished difference Result 1010 states and 1478 transitions. [2024-12-02 11:23:04,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:23:04,461 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 161 [2024-12-02 11:23:04,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:04,463 INFO L225 Difference]: With dead ends: 1010 [2024-12-02 11:23:04,463 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:04,464 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:04,465 INFO L435 NwaCegarLoop]: 798 mSDtfsCounter, 705 mSDsluCounter, 1568 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 705 SdHoareTripleChecker+Valid, 2366 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:04,465 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [705 Valid, 2366 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:04,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:04,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:04,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.467153284671533) internal successors, (804), 548 states have internal predecessors, (804), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:04,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 810 transitions. [2024-12-02 11:23:04,484 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 810 transitions. Word has length 161 [2024-12-02 11:23:04,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:04,485 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 810 transitions. [2024-12-02 11:23:04,485 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 29.8) internal successors, (149), 5 states have internal predecessors, (149), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:04,485 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 810 transitions. [2024-12-02 11:23:04,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2024-12-02 11:23:04,487 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:04,487 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:04,487 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2024-12-02 11:23:04,487 INFO L396 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:04,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:04,488 INFO L85 PathProgramCache]: Analyzing trace with hash 876306403, now seen corresponding path program 1 times [2024-12-02 11:23:04,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:04,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835283782] [2024-12-02 11:23:04,488 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:04,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:04,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:04,863 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:04,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:04,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835283782] [2024-12-02 11:23:04,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1835283782] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:04,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:04,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:04,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581795943] [2024-12-02 11:23:04,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:04,864 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:04,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:04,864 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:04,865 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:04,865 INFO L87 Difference]: Start difference. First operand 553 states and 810 transitions. Second operand has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:04,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:04,971 INFO L93 Difference]: Finished difference Result 1004 states and 1468 transitions. [2024-12-02 11:23:04,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:04,972 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 162 [2024-12-02 11:23:04,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:04,974 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:04,974 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:04,975 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:04,975 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 1487 mSDsluCounter, 768 mSDsCounter, 0 mSdLazyCounter, 80 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1490 SdHoareTripleChecker+Valid, 1534 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 80 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:04,976 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1490 Valid, 1534 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 80 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:04,977 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:04,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:04,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4653284671532847) internal successors, (803), 548 states have internal predecessors, (803), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:04,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 809 transitions. [2024-12-02 11:23:04,991 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 809 transitions. Word has length 162 [2024-12-02 11:23:04,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:04,992 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 809 transitions. [2024-12-02 11:23:04,992 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.0) internal successors, (150), 5 states have internal predecessors, (150), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:04,992 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 809 transitions. [2024-12-02 11:23:04,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 164 [2024-12-02 11:23:04,994 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:04,994 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:04,994 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2024-12-02 11:23:04,994 INFO L396 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:04,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:04,994 INFO L85 PathProgramCache]: Analyzing trace with hash -2138234105, now seen corresponding path program 1 times [2024-12-02 11:23:04,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:04,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776734758] [2024-12-02 11:23:04,995 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:04,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:05,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:05,301 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:05,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:05,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776734758] [2024-12-02 11:23:05,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776734758] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:05,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:05,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:05,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968369320] [2024-12-02 11:23:05,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:05,302 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:05,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:05,303 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:05,303 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:05,303 INFO L87 Difference]: Start difference. First operand 553 states and 809 transitions. Second operand has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:05,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:05,399 INFO L93 Difference]: Finished difference Result 1004 states and 1466 transitions. [2024-12-02 11:23:05,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:05,399 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 163 [2024-12-02 11:23:05,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:05,401 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:05,401 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:05,402 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:05,402 INFO L435 NwaCegarLoop]: 766 mSDtfsCounter, 790 mSDsluCounter, 775 mSDsCounter, 0 mSdLazyCounter, 78 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 793 SdHoareTripleChecker+Valid, 1541 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 78 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:05,402 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [793 Valid, 1541 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 78 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:05,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:05,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:05,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4635036496350364) internal successors, (802), 548 states have internal predecessors, (802), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:05,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 808 transitions. [2024-12-02 11:23:05,412 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 808 transitions. Word has length 163 [2024-12-02 11:23:05,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:05,412 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 808 transitions. [2024-12-02 11:23:05,412 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:05,412 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 808 transitions. [2024-12-02 11:23:05,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2024-12-02 11:23:05,413 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:05,414 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:05,414 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable15 [2024-12-02 11:23:05,414 INFO L396 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:05,414 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:05,414 INFO L85 PathProgramCache]: Analyzing trace with hash -1761805302, now seen corresponding path program 1 times [2024-12-02 11:23:05,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:05,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1796005053] [2024-12-02 11:23:05,414 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:05,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:05,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:05,704 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:05,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:05,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1796005053] [2024-12-02 11:23:05,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1796005053] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:05,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:05,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:05,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192985277] [2024-12-02 11:23:05,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:05,705 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:05,705 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:05,705 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:05,705 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:05,705 INFO L87 Difference]: Start difference. First operand 553 states and 808 transitions. Second operand has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:05,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:05,780 INFO L93 Difference]: Finished difference Result 1004 states and 1464 transitions. [2024-12-02 11:23:05,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:05,781 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 164 [2024-12-02 11:23:05,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:05,783 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:05,783 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:05,783 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:05,784 INFO L435 NwaCegarLoop]: 782 mSDtfsCounter, 699 mSDsluCounter, 784 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 699 SdHoareTripleChecker+Valid, 1566 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:05,784 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [699 Valid, 1566 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:05,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:05,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:05,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4598540145985401) internal successors, (800), 548 states have internal predecessors, (800), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:05,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 806 transitions. [2024-12-02 11:23:05,795 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 806 transitions. Word has length 164 [2024-12-02 11:23:05,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:05,795 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 806 transitions. [2024-12-02 11:23:05,795 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 38.0) internal successors, (152), 4 states have internal predecessors, (152), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:05,795 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 806 transitions. [2024-12-02 11:23:05,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2024-12-02 11:23:05,797 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:05,797 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:05,797 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable16 [2024-12-02 11:23:05,797 INFO L396 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:05,798 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:05,798 INFO L85 PathProgramCache]: Analyzing trace with hash -540920697, now seen corresponding path program 1 times [2024-12-02 11:23:05,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:05,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102791941] [2024-12-02 11:23:05,798 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:05,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:05,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:06,023 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:06,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:06,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102791941] [2024-12-02 11:23:06,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102791941] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:06,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:06,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:06,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [745819707] [2024-12-02 11:23:06,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:06,024 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:06,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:06,024 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:06,025 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:06,025 INFO L87 Difference]: Start difference. First operand 553 states and 806 transitions. Second operand has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:06,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:06,087 INFO L93 Difference]: Finished difference Result 1004 states and 1460 transitions. [2024-12-02 11:23:06,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:06,088 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 166 [2024-12-02 11:23:06,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:06,090 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:06,090 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:06,090 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:06,091 INFO L435 NwaCegarLoop]: 782 mSDtfsCounter, 1481 mSDsluCounter, 784 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1484 SdHoareTripleChecker+Valid, 1566 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:06,091 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1484 Valid, 1566 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:06,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:06,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:06,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4580291970802919) internal successors, (799), 548 states have internal predecessors, (799), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:06,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 805 transitions. [2024-12-02 11:23:06,106 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 805 transitions. Word has length 166 [2024-12-02 11:23:06,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:06,107 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 805 transitions. [2024-12-02 11:23:06,107 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.8) internal successors, (154), 5 states have internal predecessors, (154), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:06,107 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 805 transitions. [2024-12-02 11:23:06,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2024-12-02 11:23:06,109 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:06,109 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:06,109 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable17 [2024-12-02 11:23:06,109 INFO L396 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:06,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:06,109 INFO L85 PathProgramCache]: Analyzing trace with hash 430318257, now seen corresponding path program 1 times [2024-12-02 11:23:06,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:06,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020571409] [2024-12-02 11:23:06,110 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:06,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:06,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:06,558 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:06,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:06,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020571409] [2024-12-02 11:23:06,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020571409] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:06,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:06,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:06,558 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991052815] [2024-12-02 11:23:06,558 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:06,559 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:06,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:06,559 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:06,559 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:06,559 INFO L87 Difference]: Start difference. First operand 553 states and 805 transitions. Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:23:06,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:06,621 INFO L93 Difference]: Finished difference Result 1004 states and 1458 transitions. [2024-12-02 11:23:06,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:06,622 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 167 [2024-12-02 11:23:06,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:06,624 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:06,624 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:06,624 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:06,625 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 734 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 736 SdHoareTripleChecker+Valid, 1572 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:06,625 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [736 Valid, 1572 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:06,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:06,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:06,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4562043795620438) internal successors, (798), 548 states have internal predecessors, (798), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:06,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 804 transitions. [2024-12-02 11:23:06,640 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 804 transitions. Word has length 167 [2024-12-02 11:23:06,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:06,640 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 804 transitions. [2024-12-02 11:23:06,640 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 38.75) internal successors, (155), 4 states have internal predecessors, (155), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:23:06,640 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 804 transitions. [2024-12-02 11:23:06,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 169 [2024-12-02 11:23:06,642 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:06,642 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:06,642 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable18 [2024-12-02 11:23:06,642 INFO L396 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:06,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:06,643 INFO L85 PathProgramCache]: Analyzing trace with hash -274414691, now seen corresponding path program 1 times [2024-12-02 11:23:06,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:06,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1168876999] [2024-12-02 11:23:06,643 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:06,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:06,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:07,121 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:07,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:07,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1168876999] [2024-12-02 11:23:07,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1168876999] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:07,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:07,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:07,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173366964] [2024-12-02 11:23:07,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:07,122 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:07,122 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:07,122 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:07,122 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:07,123 INFO L87 Difference]: Start difference. First operand 553 states and 804 transitions. Second operand has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:23:07,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:07,194 INFO L93 Difference]: Finished difference Result 1004 states and 1456 transitions. [2024-12-02 11:23:07,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:07,195 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) Word has length 168 [2024-12-02 11:23:07,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:07,197 INFO L225 Difference]: With dead ends: 1004 [2024-12-02 11:23:07,197 INFO L226 Difference]: Without dead ends: 553 [2024-12-02 11:23:07,198 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:07,198 INFO L435 NwaCegarLoop]: 785 mSDtfsCounter, 732 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 734 SdHoareTripleChecker+Valid, 1572 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:07,199 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [734 Valid, 1572 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:07,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2024-12-02 11:23:07,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 553. [2024-12-02 11:23:07,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 553 states, 548 states have (on average 1.4543795620437956) internal successors, (797), 548 states have internal predecessors, (797), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:07,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 553 states to 553 states and 803 transitions. [2024-12-02 11:23:07,218 INFO L78 Accepts]: Start accepts. Automaton has 553 states and 803 transitions. Word has length 168 [2024-12-02 11:23:07,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:07,219 INFO L471 AbstractCegarLoop]: Abstraction has 553 states and 803 transitions. [2024-12-02 11:23:07,219 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 39.0) internal successors, (156), 4 states have internal predecessors, (156), 2 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 2 states have call predecessors, (3), 2 states have call successors, (3) [2024-12-02 11:23:07,219 INFO L276 IsEmpty]: Start isEmpty. Operand 553 states and 803 transitions. [2024-12-02 11:23:07,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2024-12-02 11:23:07,221 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:07,222 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:07,222 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable19 [2024-12-02 11:23:07,222 INFO L396 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:07,222 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:07,222 INFO L85 PathProgramCache]: Analyzing trace with hash 848604686, now seen corresponding path program 1 times [2024-12-02 11:23:07,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:07,223 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977812220] [2024-12-02 11:23:07,223 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:07,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:07,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:08,043 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:08,043 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:08,043 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977812220] [2024-12-02 11:23:08,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977812220] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:08,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:08,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:08,043 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958763649] [2024-12-02 11:23:08,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:08,044 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:08,044 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:08,044 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:08,044 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:08,044 INFO L87 Difference]: Start difference. First operand 553 states and 803 transitions. Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:08,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:08,285 INFO L93 Difference]: Finished difference Result 1010 states and 1462 transitions. [2024-12-02 11:23:08,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:23:08,285 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 169 [2024-12-02 11:23:08,286 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:08,287 INFO L225 Difference]: With dead ends: 1010 [2024-12-02 11:23:08,287 INFO L226 Difference]: Without dead ends: 557 [2024-12-02 11:23:08,288 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:08,289 INFO L435 NwaCegarLoop]: 793 mSDtfsCounter, 2 mSDsluCounter, 2186 mSDsCounter, 0 mSdLazyCounter, 216 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 2979 SdHoareTripleChecker+Invalid, 216 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 216 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:08,289 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 2979 Invalid, 216 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 216 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 11:23:08,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2024-12-02 11:23:08,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 555. [2024-12-02 11:23:08,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4527272727272726) internal successors, (799), 550 states have internal predecessors, (799), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:08,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 805 transitions. [2024-12-02 11:23:08,299 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 805 transitions. Word has length 169 [2024-12-02 11:23:08,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:08,300 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 805 transitions. [2024-12-02 11:23:08,300 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:08,300 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 805 transitions. [2024-12-02 11:23:08,301 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2024-12-02 11:23:08,301 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:08,301 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:08,301 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable20 [2024-12-02 11:23:08,301 INFO L396 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:08,301 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:08,302 INFO L85 PathProgramCache]: Analyzing trace with hash -2121667287, now seen corresponding path program 1 times [2024-12-02 11:23:08,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:08,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344664455] [2024-12-02 11:23:08,302 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:08,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:08,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:08,635 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:08,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:08,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344664455] [2024-12-02 11:23:08,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344664455] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:08,636 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:08,636 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:08,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762060708] [2024-12-02 11:23:08,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:08,636 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:08,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:08,637 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:08,637 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:08,637 INFO L87 Difference]: Start difference. First operand 555 states and 805 transitions. Second operand has 4 states, 4 states have (on average 39.5) internal successors, (158), 4 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:08,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:08,733 INFO L93 Difference]: Finished difference Result 1008 states and 1458 transitions. [2024-12-02 11:23:08,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:08,734 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 39.5) internal successors, (158), 4 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 170 [2024-12-02 11:23:08,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:08,736 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:08,736 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:08,737 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:08,738 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 684 mSDsluCounter, 763 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 684 SdHoareTripleChecker+Valid, 1524 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:08,738 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [684 Valid, 1524 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 76 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:08,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:08,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:08,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.450909090909091) internal successors, (798), 550 states have internal predecessors, (798), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:08,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 804 transitions. [2024-12-02 11:23:08,747 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 804 transitions. Word has length 170 [2024-12-02 11:23:08,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:08,748 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 804 transitions. [2024-12-02 11:23:08,748 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 39.5) internal successors, (158), 4 states have internal predecessors, (158), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:08,748 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 804 transitions. [2024-12-02 11:23:08,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 172 [2024-12-02 11:23:08,749 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:08,749 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:08,749 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable21 [2024-12-02 11:23:08,749 INFO L396 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:08,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:08,749 INFO L85 PathProgramCache]: Analyzing trace with hash 1629691787, now seen corresponding path program 1 times [2024-12-02 11:23:08,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:08,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406077321] [2024-12-02 11:23:08,750 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:08,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:08,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:09,096 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:09,097 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:09,097 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406077321] [2024-12-02 11:23:09,097 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406077321] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:09,097 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:09,097 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:09,097 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163528241] [2024-12-02 11:23:09,097 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:09,097 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:09,097 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:09,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:09,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:09,098 INFO L87 Difference]: Start difference. First operand 555 states and 804 transitions. Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:09,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:09,205 INFO L93 Difference]: Finished difference Result 1008 states and 1456 transitions. [2024-12-02 11:23:09,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:09,205 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 171 [2024-12-02 11:23:09,205 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:09,207 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:09,207 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:09,208 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:09,208 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 1360 mSDsluCounter, 763 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1360 SdHoareTripleChecker+Valid, 1524 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:09,208 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1360 Valid, 1524 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:09,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:09,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:09,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.449090909090909) internal successors, (797), 550 states have internal predecessors, (797), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:09,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 803 transitions. [2024-12-02 11:23:09,218 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 803 transitions. Word has length 171 [2024-12-02 11:23:09,218 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:09,218 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 803 transitions. [2024-12-02 11:23:09,218 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:09,218 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 803 transitions. [2024-12-02 11:23:09,219 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2024-12-02 11:23:09,219 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:09,219 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:09,219 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable22 [2024-12-02 11:23:09,219 INFO L396 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:09,220 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:09,220 INFO L85 PathProgramCache]: Analyzing trace with hash -649195798, now seen corresponding path program 1 times [2024-12-02 11:23:09,220 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:09,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705039012] [2024-12-02 11:23:09,220 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:09,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:09,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:09,563 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:09,563 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:09,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705039012] [2024-12-02 11:23:09,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705039012] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:09,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:09,564 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:09,564 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897532897] [2024-12-02 11:23:09,564 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:09,564 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:09,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:09,565 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:09,565 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:09,565 INFO L87 Difference]: Start difference. First operand 555 states and 803 transitions. Second operand has 5 states, 5 states have (on average 32.0) internal successors, (160), 5 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:09,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:09,669 INFO L93 Difference]: Finished difference Result 1008 states and 1454 transitions. [2024-12-02 11:23:09,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:09,670 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.0) internal successors, (160), 5 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 172 [2024-12-02 11:23:09,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:09,671 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:09,671 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:09,672 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:09,672 INFO L435 NwaCegarLoop]: 761 mSDtfsCounter, 681 mSDsluCounter, 770 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 681 SdHoareTripleChecker+Valid, 1531 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:09,672 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [681 Valid, 1531 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:09,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:09,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:09,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4472727272727273) internal successors, (796), 550 states have internal predecessors, (796), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:09,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 802 transitions. [2024-12-02 11:23:09,681 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 802 transitions. Word has length 172 [2024-12-02 11:23:09,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:09,681 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 802 transitions. [2024-12-02 11:23:09,681 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.0) internal successors, (160), 5 states have internal predecessors, (160), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:09,682 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 802 transitions. [2024-12-02 11:23:09,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2024-12-02 11:23:09,682 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:09,682 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:09,682 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable23 [2024-12-02 11:23:09,682 INFO L396 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:09,683 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:09,683 INFO L85 PathProgramCache]: Analyzing trace with hash -63304310, now seen corresponding path program 1 times [2024-12-02 11:23:09,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:09,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975893545] [2024-12-02 11:23:09,683 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:09,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:09,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:09,948 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:09,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:09,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1975893545] [2024-12-02 11:23:09,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1975893545] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:09,949 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:09,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:09,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1886995575] [2024-12-02 11:23:09,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:09,949 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:09,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:09,950 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:09,950 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:09,950 INFO L87 Difference]: Start difference. First operand 555 states and 802 transitions. Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 4 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:10,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:10,107 INFO L93 Difference]: Finished difference Result 1008 states and 1452 transitions. [2024-12-02 11:23:10,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:10,108 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 40.25) internal successors, (161), 4 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 173 [2024-12-02 11:23:10,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:10,109 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:10,109 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:10,110 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:10,110 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 666 mSDsluCounter, 724 mSDsCounter, 0 mSdLazyCounter, 148 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 666 SdHoareTripleChecker+Valid, 1446 SdHoareTripleChecker+Invalid, 148 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 148 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:10,110 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [666 Valid, 1446 Invalid, 148 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 148 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:10,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:10,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:10,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4454545454545455) internal successors, (795), 550 states have internal predecessors, (795), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:10,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 801 transitions. [2024-12-02 11:23:10,121 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 801 transitions. Word has length 173 [2024-12-02 11:23:10,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:10,121 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 801 transitions. [2024-12-02 11:23:10,122 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 40.25) internal successors, (161), 4 states have internal predecessors, (161), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:10,122 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 801 transitions. [2024-12-02 11:23:10,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2024-12-02 11:23:10,123 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:10,123 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:10,123 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable24 [2024-12-02 11:23:10,123 INFO L396 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:10,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:10,124 INFO L85 PathProgramCache]: Analyzing trace with hash 310833802, now seen corresponding path program 1 times [2024-12-02 11:23:10,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:10,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308689631] [2024-12-02 11:23:10,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:10,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:10,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:10,528 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:10,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:10,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [308689631] [2024-12-02 11:23:10,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [308689631] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:10,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:10,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:10,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105705306] [2024-12-02 11:23:10,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:10,529 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:10,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:10,530 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:10,530 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:10,531 INFO L87 Difference]: Start difference. First operand 555 states and 801 transitions. Second operand has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:10,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:10,714 INFO L93 Difference]: Finished difference Result 1008 states and 1450 transitions. [2024-12-02 11:23:10,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:10,714 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 174 [2024-12-02 11:23:10,715 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:10,717 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:10,717 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:10,718 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:10,718 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 664 mSDsluCounter, 731 mSDsCounter, 0 mSdLazyCounter, 146 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 664 SdHoareTripleChecker+Valid, 1453 SdHoareTripleChecker+Invalid, 146 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 146 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:10,718 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [664 Valid, 1453 Invalid, 146 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 146 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:10,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:10,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:10,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4436363636363636) internal successors, (794), 550 states have internal predecessors, (794), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:10,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 800 transitions. [2024-12-02 11:23:10,731 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 800 transitions. Word has length 174 [2024-12-02 11:23:10,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:10,731 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 800 transitions. [2024-12-02 11:23:10,731 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.4) internal successors, (162), 5 states have internal predecessors, (162), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:10,731 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 800 transitions. [2024-12-02 11:23:10,733 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 176 [2024-12-02 11:23:10,733 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:10,733 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:10,733 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable25 [2024-12-02 11:23:10,733 INFO L396 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:10,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:10,734 INFO L85 PathProgramCache]: Analyzing trace with hash -361759605, now seen corresponding path program 1 times [2024-12-02 11:23:10,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:10,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546961144] [2024-12-02 11:23:10,734 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:10,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:10,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:11,079 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:11,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:11,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546961144] [2024-12-02 11:23:11,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546961144] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:11,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:11,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:11,079 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1182466495] [2024-12-02 11:23:11,079 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:11,080 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:11,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:11,080 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:11,080 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:11,081 INFO L87 Difference]: Start difference. First operand 555 states and 800 transitions. Second operand has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:11,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:11,247 INFO L93 Difference]: Finished difference Result 1008 states and 1448 transitions. [2024-12-02 11:23:11,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:11,247 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 175 [2024-12-02 11:23:11,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:11,249 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:11,249 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:11,250 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:11,250 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 1318 mSDsluCounter, 724 mSDsCounter, 0 mSdLazyCounter, 144 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1318 SdHoareTripleChecker+Valid, 1446 SdHoareTripleChecker+Invalid, 144 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 144 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:11,250 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1318 Valid, 1446 Invalid, 144 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 144 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:11,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:11,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:11,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4418181818181819) internal successors, (793), 550 states have internal predecessors, (793), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:11,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 799 transitions. [2024-12-02 11:23:11,260 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 799 transitions. Word has length 175 [2024-12-02 11:23:11,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:11,260 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 799 transitions. [2024-12-02 11:23:11,260 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.6) internal successors, (163), 5 states have internal predecessors, (163), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:11,260 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 799 transitions. [2024-12-02 11:23:11,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2024-12-02 11:23:11,261 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:11,261 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:11,261 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable26 [2024-12-02 11:23:11,261 INFO L396 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:11,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:11,261 INFO L85 PathProgramCache]: Analyzing trace with hash 204745545, now seen corresponding path program 1 times [2024-12-02 11:23:11,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:11,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524258803] [2024-12-02 11:23:11,262 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:11,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:11,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:11,681 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:11,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:11,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524258803] [2024-12-02 11:23:11,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524258803] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:11,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:11,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:11,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841311566] [2024-12-02 11:23:11,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:11,682 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:11,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:11,683 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:11,683 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:11,683 INFO L87 Difference]: Start difference. First operand 555 states and 799 transitions. Second operand has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:11,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:11,828 INFO L93 Difference]: Finished difference Result 1008 states and 1446 transitions. [2024-12-02 11:23:11,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:11,829 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 176 [2024-12-02 11:23:11,829 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:11,830 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:11,830 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:11,831 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:11,831 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 662 mSDsluCounter, 731 mSDsCounter, 0 mSdLazyCounter, 142 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 662 SdHoareTripleChecker+Valid, 1453 SdHoareTripleChecker+Invalid, 142 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 142 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:11,832 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [662 Valid, 1453 Invalid, 142 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 142 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:11,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:11,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:11,843 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.44) internal successors, (792), 550 states have internal predecessors, (792), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:11,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 798 transitions. [2024-12-02 11:23:11,844 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 798 transitions. Word has length 176 [2024-12-02 11:23:11,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:11,845 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 798 transitions. [2024-12-02 11:23:11,845 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:11,845 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 798 transitions. [2024-12-02 11:23:11,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 178 [2024-12-02 11:23:11,846 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:11,846 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:11,846 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable27 [2024-12-02 11:23:11,846 INFO L396 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:11,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:11,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1282586636, now seen corresponding path program 1 times [2024-12-02 11:23:11,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:11,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068889569] [2024-12-02 11:23:11,847 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:11,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:11,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:12,323 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:12,323 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:12,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068889569] [2024-12-02 11:23:12,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068889569] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:12,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:12,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:12,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255319602] [2024-12-02 11:23:12,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:12,324 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:12,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:12,324 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:12,324 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:12,324 INFO L87 Difference]: Start difference. First operand 555 states and 798 transitions. Second operand has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:12,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:12,463 INFO L93 Difference]: Finished difference Result 1008 states and 1444 transitions. [2024-12-02 11:23:12,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:12,464 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 177 [2024-12-02 11:23:12,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:12,465 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:12,465 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:12,466 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:12,466 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 646 mSDsluCounter, 724 mSDsCounter, 0 mSdLazyCounter, 140 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 646 SdHoareTripleChecker+Valid, 1446 SdHoareTripleChecker+Invalid, 140 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 140 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:12,466 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [646 Valid, 1446 Invalid, 140 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 140 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:12,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:12,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:12,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4381818181818182) internal successors, (791), 550 states have internal predecessors, (791), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:12,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 797 transitions. [2024-12-02 11:23:12,474 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 797 transitions. Word has length 177 [2024-12-02 11:23:12,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:12,475 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 797 transitions. [2024-12-02 11:23:12,475 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 41.25) internal successors, (165), 4 states have internal predecessors, (165), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:12,475 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 797 transitions. [2024-12-02 11:23:12,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 179 [2024-12-02 11:23:12,476 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:12,476 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:12,476 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable28 [2024-12-02 11:23:12,476 INFO L396 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:12,476 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:12,476 INFO L85 PathProgramCache]: Analyzing trace with hash 77881224, now seen corresponding path program 1 times [2024-12-02 11:23:12,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:12,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415089120] [2024-12-02 11:23:12,477 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:12,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:12,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:12,797 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:12,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:12,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415089120] [2024-12-02 11:23:12,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415089120] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:12,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:12,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:12,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106482480] [2024-12-02 11:23:12,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:12,798 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:12,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:12,798 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:12,798 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:12,798 INFO L87 Difference]: Start difference. First operand 555 states and 797 transitions. Second operand has 5 states, 5 states have (on average 33.2) internal successors, (166), 5 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:12,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:12,960 INFO L93 Difference]: Finished difference Result 1008 states and 1442 transitions. [2024-12-02 11:23:12,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:12,961 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.2) internal successors, (166), 5 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 178 [2024-12-02 11:23:12,961 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:12,962 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:12,962 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:12,962 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:12,963 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 660 mSDsluCounter, 731 mSDsCounter, 0 mSdLazyCounter, 138 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 660 SdHoareTripleChecker+Valid, 1453 SdHoareTripleChecker+Invalid, 138 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 138 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:12,963 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [660 Valid, 1453 Invalid, 138 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 138 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:12,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:12,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:12,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4363636363636363) internal successors, (790), 550 states have internal predecessors, (790), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:12,975 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 796 transitions. [2024-12-02 11:23:12,975 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 796 transitions. Word has length 178 [2024-12-02 11:23:12,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:12,976 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 796 transitions. [2024-12-02 11:23:12,976 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.2) internal successors, (166), 5 states have internal predecessors, (166), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:12,976 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 796 transitions. [2024-12-02 11:23:12,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2024-12-02 11:23:12,977 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:12,977 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:12,977 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable29 [2024-12-02 11:23:12,977 INFO L396 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:12,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:12,978 INFO L85 PathProgramCache]: Analyzing trace with hash -2054770675, now seen corresponding path program 1 times [2024-12-02 11:23:12,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:12,978 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068128459] [2024-12-02 11:23:12,978 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:12,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:13,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:13,442 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:13,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:13,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068128459] [2024-12-02 11:23:13,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068128459] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:13,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:13,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:13,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306911064] [2024-12-02 11:23:13,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:13,443 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:13,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:13,444 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:13,444 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:13,444 INFO L87 Difference]: Start difference. First operand 555 states and 796 transitions. Second operand has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:13,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:13,595 INFO L93 Difference]: Finished difference Result 1008 states and 1440 transitions. [2024-12-02 11:23:13,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:13,595 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 179 [2024-12-02 11:23:13,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:13,597 INFO L225 Difference]: With dead ends: 1008 [2024-12-02 11:23:13,597 INFO L226 Difference]: Without dead ends: 555 [2024-12-02 11:23:13,597 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:13,597 INFO L435 NwaCegarLoop]: 722 mSDtfsCounter, 659 mSDsluCounter, 731 mSDsCounter, 0 mSdLazyCounter, 136 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 659 SdHoareTripleChecker+Valid, 1453 SdHoareTripleChecker+Invalid, 136 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 136 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:13,598 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [659 Valid, 1453 Invalid, 136 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 136 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:13,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 555 states. [2024-12-02 11:23:13,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 555 to 555. [2024-12-02 11:23:13,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 555 states, 550 states have (on average 1.4345454545454546) internal successors, (789), 550 states have internal predecessors, (789), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:13,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 795 transitions. [2024-12-02 11:23:13,606 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 795 transitions. Word has length 179 [2024-12-02 11:23:13,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:13,606 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 795 transitions. [2024-12-02 11:23:13,606 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.4) internal successors, (167), 5 states have internal predecessors, (167), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:13,606 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 795 transitions. [2024-12-02 11:23:13,607 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2024-12-02 11:23:13,607 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:13,607 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:13,607 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable30 [2024-12-02 11:23:13,608 INFO L396 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:13,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:13,608 INFO L85 PathProgramCache]: Analyzing trace with hash -1540677817, now seen corresponding path program 1 times [2024-12-02 11:23:13,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:13,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698267288] [2024-12-02 11:23:13,608 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:13,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:13,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:14,203 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:14,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:14,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698267288] [2024-12-02 11:23:14,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698267288] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:14,204 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:14,204 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:14,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143074971] [2024-12-02 11:23:14,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:14,204 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:14,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:14,205 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:14,205 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:14,205 INFO L87 Difference]: Start difference. First operand 555 states and 795 transitions. Second operand has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:14,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:14,527 INFO L93 Difference]: Finished difference Result 1010 states and 1441 transitions. [2024-12-02 11:23:14,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:23:14,527 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 180 [2024-12-02 11:23:14,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:14,529 INFO L225 Difference]: With dead ends: 1010 [2024-12-02 11:23:14,529 INFO L226 Difference]: Without dead ends: 557 [2024-12-02 11:23:14,529 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:14,529 INFO L435 NwaCegarLoop]: 599 mSDtfsCounter, 690 mSDsluCounter, 1184 mSDsCounter, 0 mSdLazyCounter, 583 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 690 SdHoareTripleChecker+Valid, 1783 SdHoareTripleChecker+Invalid, 583 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 583 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:14,530 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [690 Valid, 1783 Invalid, 583 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 583 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 11:23:14,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2024-12-02 11:23:14,537 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 556. [2024-12-02 11:23:14,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4337568058076224) internal successors, (790), 551 states have internal predecessors, (790), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:14,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 796 transitions. [2024-12-02 11:23:14,539 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 796 transitions. Word has length 180 [2024-12-02 11:23:14,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:14,539 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 796 transitions. [2024-12-02 11:23:14,539 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 33.6) internal successors, (168), 5 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:14,539 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 796 transitions. [2024-12-02 11:23:14,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 181 [2024-12-02 11:23:14,540 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:14,540 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:14,540 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable31 [2024-12-02 11:23:14,540 INFO L396 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:14,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:14,541 INFO L85 PathProgramCache]: Analyzing trace with hash 445710734, now seen corresponding path program 1 times [2024-12-02 11:23:14,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:14,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233557817] [2024-12-02 11:23:14,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:14,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:14,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:14,885 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:14,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:14,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233557817] [2024-12-02 11:23:14,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233557817] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:14,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:14,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:14,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [933211552] [2024-12-02 11:23:14,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:14,886 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:14,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:14,886 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:14,886 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:14,886 INFO L87 Difference]: Start difference. First operand 556 states and 796 transitions. Second operand has 4 states, 4 states have (on average 42.0) internal successors, (168), 4 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:15,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:15,056 INFO L93 Difference]: Finished difference Result 1012 states and 1442 transitions. [2024-12-02 11:23:15,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:15,057 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 42.0) internal successors, (168), 4 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 180 [2024-12-02 11:23:15,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:15,059 INFO L225 Difference]: With dead ends: 1012 [2024-12-02 11:23:15,059 INFO L226 Difference]: Without dead ends: 556 [2024-12-02 11:23:15,060 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:15,060 INFO L435 NwaCegarLoop]: 784 mSDtfsCounter, 2 mSDsluCounter, 1378 mSDsCounter, 0 mSdLazyCounter, 201 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 2162 SdHoareTripleChecker+Invalid, 201 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 201 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:15,060 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 2162 Invalid, 201 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 201 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 11:23:15,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 556 states. [2024-12-02 11:23:15,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 556 to 556. [2024-12-02 11:23:15,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 551 states have (on average 1.4319419237749547) internal successors, (789), 551 states have internal predecessors, (789), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:23:15,067 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 795 transitions. [2024-12-02 11:23:15,067 INFO L78 Accepts]: Start accepts. Automaton has 556 states and 795 transitions. Word has length 180 [2024-12-02 11:23:15,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:15,067 INFO L471 AbstractCegarLoop]: Abstraction has 556 states and 795 transitions. [2024-12-02 11:23:15,067 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 42.0) internal successors, (168), 4 states have internal predecessors, (168), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:15,067 INFO L276 IsEmpty]: Start isEmpty. Operand 556 states and 795 transitions. [2024-12-02 11:23:15,068 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2024-12-02 11:23:15,068 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:15,068 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:15,068 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable32 [2024-12-02 11:23:15,068 INFO L396 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:15,068 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:15,068 INFO L85 PathProgramCache]: Analyzing trace with hash 203821865, now seen corresponding path program 1 times [2024-12-02 11:23:15,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:15,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1456929580] [2024-12-02 11:23:15,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:15,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:15,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:15,797 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:23:15,798 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:15,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1456929580] [2024-12-02 11:23:15,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1456929580] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:15,798 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:15,798 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:23:15,798 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466096526] [2024-12-02 11:23:15,798 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:15,798 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:23:15,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:15,799 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:23:15,799 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:15,799 INFO L87 Difference]: Start difference. First operand 556 states and 795 transitions. Second operand has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:15,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:15,928 INFO L93 Difference]: Finished difference Result 1165 states and 1640 transitions. [2024-12-02 11:23:15,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:23:15,929 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 181 [2024-12-02 11:23:15,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:15,931 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:15,931 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:15,932 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:23:15,933 INFO L435 NwaCegarLoop]: 776 mSDtfsCounter, 1134 mSDsluCounter, 2322 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1137 SdHoareTripleChecker+Valid, 3098 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:15,933 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1137 Valid, 3098 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:15,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:15,957 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:15,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.399715504978663) internal successors, (984), 703 states have internal predecessors, (984), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:15,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 996 transitions. [2024-12-02 11:23:15,959 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 996 transitions. Word has length 181 [2024-12-02 11:23:15,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:15,960 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 996 transitions. [2024-12-02 11:23:15,960 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 28.166666666666668) internal successors, (169), 6 states have internal predecessors, (169), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:23:15,960 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 996 transitions. [2024-12-02 11:23:15,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 449 [2024-12-02 11:23:15,965 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:15,965 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:15,966 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable33 [2024-12-02 11:23:15,966 INFO L396 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:15,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:15,966 INFO L85 PathProgramCache]: Analyzing trace with hash -1787257894, now seen corresponding path program 1 times [2024-12-02 11:23:15,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:15,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [607957020] [2024-12-02 11:23:15,967 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:15,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:16,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:16,888 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:16,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:16,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [607957020] [2024-12-02 11:23:16,889 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [607957020] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:16,889 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:16,889 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:16,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023904446] [2024-12-02 11:23:16,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:16,889 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:16,889 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:16,890 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:16,890 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:16,890 INFO L87 Difference]: Start difference. First operand 711 states and 996 transitions. Second operand has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:17,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:17,033 INFO L93 Difference]: Finished difference Result 1165 states and 1639 transitions. [2024-12-02 11:23:17,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:17,033 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 448 [2024-12-02 11:23:17,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:17,036 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:17,036 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:17,036 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:17,037 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 724 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 134 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 727 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 135 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 134 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:17,037 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [727 Valid, 1451 Invalid, 135 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 134 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:17,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:17,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:17,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3982930298719773) internal successors, (983), 703 states have internal predecessors, (983), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:17,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 995 transitions. [2024-12-02 11:23:17,055 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 995 transitions. Word has length 448 [2024-12-02 11:23:17,056 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:17,056 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 995 transitions. [2024-12-02 11:23:17,056 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.2) internal successors, (421), 5 states have internal predecessors, (421), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:17,056 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 995 transitions. [2024-12-02 11:23:17,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 450 [2024-12-02 11:23:17,059 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:17,059 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:17,059 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable34 [2024-12-02 11:23:17,059 INFO L396 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:17,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:17,060 INFO L85 PathProgramCache]: Analyzing trace with hash 2025497410, now seen corresponding path program 1 times [2024-12-02 11:23:17,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:17,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20835097] [2024-12-02 11:23:17,060 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:17,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:17,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:17,717 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:17,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:17,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20835097] [2024-12-02 11:23:17,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20835097] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:17,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:17,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:17,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119138467] [2024-12-02 11:23:17,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:17,718 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:17,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:17,719 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:17,719 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:17,719 INFO L87 Difference]: Start difference. First operand 711 states and 995 transitions. Second operand has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:17,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:17,849 INFO L93 Difference]: Finished difference Result 1165 states and 1637 transitions. [2024-12-02 11:23:17,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:17,849 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 449 [2024-12-02 11:23:17,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:17,851 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:17,851 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:17,851 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:17,852 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 716 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 719 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 133 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:17,852 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [719 Valid, 1451 Invalid, 133 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:17,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:17,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:17,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3968705547652915) internal successors, (982), 703 states have internal predecessors, (982), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:17,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 994 transitions. [2024-12-02 11:23:17,867 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 994 transitions. Word has length 449 [2024-12-02 11:23:17,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:17,867 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 994 transitions. [2024-12-02 11:23:17,867 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.4) internal successors, (422), 5 states have internal predecessors, (422), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:17,867 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 994 transitions. [2024-12-02 11:23:17,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 451 [2024-12-02 11:23:17,869 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:17,869 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:17,869 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable35 [2024-12-02 11:23:17,869 INFO L396 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:17,869 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:17,870 INFO L85 PathProgramCache]: Analyzing trace with hash -19188593, now seen corresponding path program 1 times [2024-12-02 11:23:17,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:17,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881889794] [2024-12-02 11:23:17,870 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:17,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:18,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:18,512 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:18,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:18,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [881889794] [2024-12-02 11:23:18,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [881889794] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:18,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:18,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:18,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [514518428] [2024-12-02 11:23:18,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:18,513 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:18,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:18,513 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:18,513 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:18,514 INFO L87 Difference]: Start difference. First operand 711 states and 994 transitions. Second operand has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:18,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:18,621 INFO L93 Difference]: Finished difference Result 1165 states and 1635 transitions. [2024-12-02 11:23:18,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:18,622 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 450 [2024-12-02 11:23:18,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:18,623 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:18,623 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:18,624 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:18,624 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 708 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 130 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 711 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 131 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 130 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:18,624 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [711 Valid, 1451 Invalid, 131 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 130 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:18,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:18,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:18,634 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.395448079658606) internal successors, (981), 703 states have internal predecessors, (981), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:18,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 993 transitions. [2024-12-02 11:23:18,635 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 993 transitions. Word has length 450 [2024-12-02 11:23:18,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:18,635 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 993 transitions. [2024-12-02 11:23:18,636 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.6) internal successors, (423), 5 states have internal predecessors, (423), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:18,636 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 993 transitions. [2024-12-02 11:23:18,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 452 [2024-12-02 11:23:18,637 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:18,637 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:18,638 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable36 [2024-12-02 11:23:18,638 INFO L396 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:18,638 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:18,638 INFO L85 PathProgramCache]: Analyzing trace with hash -189619113, now seen corresponding path program 1 times [2024-12-02 11:23:18,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:18,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883198023] [2024-12-02 11:23:18,638 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:18,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:18,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:19,350 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:19,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:19,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883198023] [2024-12-02 11:23:19,351 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883198023] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:19,351 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:19,351 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:19,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1210745534] [2024-12-02 11:23:19,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:19,351 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:19,351 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:19,352 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:19,352 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:19,352 INFO L87 Difference]: Start difference. First operand 711 states and 993 transitions. Second operand has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:19,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:19,460 INFO L93 Difference]: Finished difference Result 1165 states and 1633 transitions. [2024-12-02 11:23:19,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:19,461 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 451 [2024-12-02 11:23:19,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:19,462 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:19,462 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:19,462 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:19,463 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 1277 mSDsluCounter, 723 mSDsCounter, 0 mSdLazyCounter, 128 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1280 SdHoareTripleChecker+Valid, 1444 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 128 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:19,463 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1280 Valid, 1444 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 128 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:19,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:19,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:19,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3940256045519204) internal successors, (980), 703 states have internal predecessors, (980), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:19,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 992 transitions. [2024-12-02 11:23:19,472 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 992 transitions. Word has length 451 [2024-12-02 11:23:19,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:19,472 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 992 transitions. [2024-12-02 11:23:19,472 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 84.8) internal successors, (424), 5 states have internal predecessors, (424), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:19,472 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 992 transitions. [2024-12-02 11:23:19,474 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 453 [2024-12-02 11:23:19,474 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:19,474 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:19,474 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable37 [2024-12-02 11:23:19,474 INFO L396 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:19,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:19,475 INFO L85 PathProgramCache]: Analyzing trace with hash -353435452, now seen corresponding path program 1 times [2024-12-02 11:23:19,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:19,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964149562] [2024-12-02 11:23:19,475 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:19,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:19,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:20,276 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:20,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:20,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964149562] [2024-12-02 11:23:20,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964149562] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:20,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:20,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:20,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782355520] [2024-12-02 11:23:20,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:20,277 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:20,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:20,278 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:20,278 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:20,278 INFO L87 Difference]: Start difference. First operand 711 states and 992 transitions. Second operand has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:20,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:20,390 INFO L93 Difference]: Finished difference Result 1165 states and 1631 transitions. [2024-12-02 11:23:20,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:20,391 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 452 [2024-12-02 11:23:20,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:20,393 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:20,393 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:20,394 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:20,394 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 692 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 126 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 695 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 127 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 126 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:20,394 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [695 Valid, 1451 Invalid, 127 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 126 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:20,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:20,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:20,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3926031294452348) internal successors, (979), 703 states have internal predecessors, (979), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:20,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 991 transitions. [2024-12-02 11:23:20,410 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 991 transitions. Word has length 452 [2024-12-02 11:23:20,410 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:20,410 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 991 transitions. [2024-12-02 11:23:20,410 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.0) internal successors, (425), 5 states have internal predecessors, (425), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:20,410 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 991 transitions. [2024-12-02 11:23:20,413 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 454 [2024-12-02 11:23:20,413 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:20,413 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:20,413 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable38 [2024-12-02 11:23:20,414 INFO L396 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:20,414 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:20,414 INFO L85 PathProgramCache]: Analyzing trace with hash 1715196140, now seen corresponding path program 1 times [2024-12-02 11:23:20,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:20,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [722013447] [2024-12-02 11:23:20,414 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:20,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:20,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:21,094 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:21,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:21,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [722013447] [2024-12-02 11:23:21,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [722013447] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:21,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:21,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:21,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709673118] [2024-12-02 11:23:21,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:21,095 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:21,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:21,096 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:21,096 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:21,097 INFO L87 Difference]: Start difference. First operand 711 states and 991 transitions. Second operand has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:21,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:21,210 INFO L93 Difference]: Finished difference Result 1165 states and 1629 transitions. [2024-12-02 11:23:21,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:21,210 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 453 [2024-12-02 11:23:21,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:21,211 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:21,211 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:21,212 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:21,212 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 684 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 124 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 687 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 124 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:21,212 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [687 Valid, 1451 Invalid, 125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 124 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:21,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:21,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:21,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.391180654338549) internal successors, (978), 703 states have internal predecessors, (978), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:21,222 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 990 transitions. [2024-12-02 11:23:21,222 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 990 transitions. Word has length 453 [2024-12-02 11:23:21,222 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:21,222 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 990 transitions. [2024-12-02 11:23:21,222 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.2) internal successors, (426), 5 states have internal predecessors, (426), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:21,222 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 990 transitions. [2024-12-02 11:23:21,224 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 455 [2024-12-02 11:23:21,224 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:21,224 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:21,224 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable39 [2024-12-02 11:23:21,224 INFO L396 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:21,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:21,224 INFO L85 PathProgramCache]: Analyzing trace with hash -1189986183, now seen corresponding path program 1 times [2024-12-02 11:23:21,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:21,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654363810] [2024-12-02 11:23:21,225 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:21,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:21,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:21,779 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:21,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:21,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654363810] [2024-12-02 11:23:21,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654363810] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:21,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:21,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:21,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1445395077] [2024-12-02 11:23:21,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:21,781 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:21,781 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:21,781 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:21,781 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:21,781 INFO L87 Difference]: Start difference. First operand 711 states and 990 transitions. Second operand has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:21,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:21,882 INFO L93 Difference]: Finished difference Result 1165 states and 1627 transitions. [2024-12-02 11:23:21,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:21,883 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 454 [2024-12-02 11:23:21,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:21,884 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:21,884 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:21,885 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:21,885 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 676 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 122 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 679 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 123 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 122 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:21,885 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [679 Valid, 1451 Invalid, 123 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 122 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:21,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:21,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:21,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3897581792318634) internal successors, (977), 703 states have internal predecessors, (977), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:21,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 989 transitions. [2024-12-02 11:23:21,894 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 989 transitions. Word has length 454 [2024-12-02 11:23:21,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:21,895 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 989 transitions. [2024-12-02 11:23:21,895 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.4) internal successors, (427), 5 states have internal predecessors, (427), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:21,895 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 989 transitions. [2024-12-02 11:23:21,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 456 [2024-12-02 11:23:21,896 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:21,896 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:21,896 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable40 [2024-12-02 11:23:21,896 INFO L396 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:21,897 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:21,897 INFO L85 PathProgramCache]: Analyzing trace with hash 686713089, now seen corresponding path program 1 times [2024-12-02 11:23:21,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:21,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229916132] [2024-12-02 11:23:21,897 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:21,897 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:22,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:22,472 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:22,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:22,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229916132] [2024-12-02 11:23:22,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229916132] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:22,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:22,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:22,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045171553] [2024-12-02 11:23:22,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:22,473 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:22,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:22,473 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:22,473 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:22,473 INFO L87 Difference]: Start difference. First operand 711 states and 989 transitions. Second operand has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:22,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:22,570 INFO L93 Difference]: Finished difference Result 1165 states and 1625 transitions. [2024-12-02 11:23:22,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:22,570 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 455 [2024-12-02 11:23:22,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:22,572 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:22,572 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:22,572 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:22,572 INFO L435 NwaCegarLoop]: 721 mSDtfsCounter, 668 mSDsluCounter, 730 mSDsCounter, 0 mSdLazyCounter, 120 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 671 SdHoareTripleChecker+Valid, 1451 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 120 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:22,573 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [671 Valid, 1451 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 120 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:22,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:22,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:22,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3883357041251778) internal successors, (976), 703 states have internal predecessors, (976), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:22,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 988 transitions. [2024-12-02 11:23:22,584 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 988 transitions. Word has length 455 [2024-12-02 11:23:22,584 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:22,584 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 988 transitions. [2024-12-02 11:23:22,584 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.6) internal successors, (428), 5 states have internal predecessors, (428), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:22,584 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 988 transitions. [2024-12-02 11:23:22,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 457 [2024-12-02 11:23:22,586 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:22,586 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:22,586 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable41 [2024-12-02 11:23:22,586 INFO L396 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:22,586 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:22,586 INFO L85 PathProgramCache]: Analyzing trace with hash -188533842, now seen corresponding path program 1 times [2024-12-02 11:23:22,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:22,586 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [448127703] [2024-12-02 11:23:22,586 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:22,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:22,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:23,290 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:23,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:23,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [448127703] [2024-12-02 11:23:23,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [448127703] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:23,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:23,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:23,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844836229] [2024-12-02 11:23:23,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:23,291 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:23,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:23,291 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:23,292 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:23,292 INFO L87 Difference]: Start difference. First operand 711 states and 988 transitions. Second operand has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:23,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:23,357 INFO L93 Difference]: Finished difference Result 1165 states and 1623 transitions. [2024-12-02 11:23:23,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:23,357 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 456 [2024-12-02 11:23:23,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:23,359 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:23,359 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:23,360 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:23,360 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 1182 mSDsluCounter, 747 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1185 SdHoareTripleChecker+Valid, 1492 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:23,361 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1185 Valid, 1492 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 70 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:23,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:23,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:23,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3869132290184922) internal successors, (975), 703 states have internal predecessors, (975), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:23,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 987 transitions. [2024-12-02 11:23:23,372 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 987 transitions. Word has length 456 [2024-12-02 11:23:23,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:23,372 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 987 transitions. [2024-12-02 11:23:23,372 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 85.8) internal successors, (429), 5 states have internal predecessors, (429), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:23,372 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 987 transitions. [2024-12-02 11:23:23,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 458 [2024-12-02 11:23:23,374 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:23,375 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:23,375 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable42 [2024-12-02 11:23:23,375 INFO L396 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:23,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:23,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1644342422, now seen corresponding path program 1 times [2024-12-02 11:23:23,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:23,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [24964569] [2024-12-02 11:23:23,376 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:23,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:23,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:24,059 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:24,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:24,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [24964569] [2024-12-02 11:23:24,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [24964569] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:24,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:24,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:24,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648744366] [2024-12-02 11:23:24,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:24,060 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:24,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:24,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:24,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:24,061 INFO L87 Difference]: Start difference. First operand 711 states and 987 transitions. Second operand has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:24,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:24,141 INFO L93 Difference]: Finished difference Result 1165 states and 1621 transitions. [2024-12-02 11:23:24,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:24,141 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 457 [2024-12-02 11:23:24,141 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:24,143 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:24,143 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:24,143 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:24,143 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 1166 mSDsluCounter, 747 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1169 SdHoareTripleChecker+Valid, 1492 SdHoareTripleChecker+Invalid, 69 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:24,144 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1169 Valid, 1492 Invalid, 69 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 68 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:24,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:24,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:24,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3854907539118066) internal successors, (974), 703 states have internal predecessors, (974), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:24,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 986 transitions. [2024-12-02 11:23:24,153 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 986 transitions. Word has length 457 [2024-12-02 11:23:24,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:24,153 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 986 transitions. [2024-12-02 11:23:24,154 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.0) internal successors, (430), 5 states have internal predecessors, (430), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:24,154 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 986 transitions. [2024-12-02 11:23:24,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 459 [2024-12-02 11:23:24,155 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:24,155 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:24,155 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable43 [2024-12-02 11:23:24,155 INFO L396 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:24,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:24,156 INFO L85 PathProgramCache]: Analyzing trace with hash 1436555875, now seen corresponding path program 1 times [2024-12-02 11:23:24,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:24,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539924876] [2024-12-02 11:23:24,156 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:24,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:24,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:24,744 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:24,744 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:24,744 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539924876] [2024-12-02 11:23:24,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539924876] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:24,745 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:24,745 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:24,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564698667] [2024-12-02 11:23:24,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:24,745 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:24,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:24,746 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:24,746 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:24,746 INFO L87 Difference]: Start difference. First operand 711 states and 986 transitions. Second operand has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:24,820 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:24,820 INFO L93 Difference]: Finished difference Result 1165 states and 1619 transitions. [2024-12-02 11:23:24,820 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:24,820 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 458 [2024-12-02 11:23:24,821 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:24,822 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:24,822 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:24,823 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:24,823 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 629 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 632 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:24,823 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [632 Valid, 1499 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:24,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:24,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:24,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3840682788051208) internal successors, (973), 703 states have internal predecessors, (973), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:24,832 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 985 transitions. [2024-12-02 11:23:24,832 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 985 transitions. Word has length 458 [2024-12-02 11:23:24,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:24,832 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 985 transitions. [2024-12-02 11:23:24,832 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.2) internal successors, (431), 5 states have internal predecessors, (431), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:24,833 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 985 transitions. [2024-12-02 11:23:24,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 460 [2024-12-02 11:23:24,834 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:24,834 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:24,834 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable44 [2024-12-02 11:23:24,834 INFO L396 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:24,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:24,835 INFO L85 PathProgramCache]: Analyzing trace with hash -1605313621, now seen corresponding path program 1 times [2024-12-02 11:23:24,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:24,835 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409902548] [2024-12-02 11:23:24,835 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:24,835 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:25,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:25,395 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:25,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:25,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409902548] [2024-12-02 11:23:25,395 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409902548] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:25,395 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:25,395 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:25,395 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706671840] [2024-12-02 11:23:25,395 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:25,396 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:25,396 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:25,396 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:25,396 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:25,396 INFO L87 Difference]: Start difference. First operand 711 states and 985 transitions. Second operand has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:25,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:25,459 INFO L93 Difference]: Finished difference Result 1165 states and 1617 transitions. [2024-12-02 11:23:25,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:25,460 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 459 [2024-12-02 11:23:25,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:25,462 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:25,462 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:25,463 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:25,463 INFO L435 NwaCegarLoop]: 745 mSDtfsCounter, 621 mSDsluCounter, 754 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 624 SdHoareTripleChecker+Valid, 1499 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:25,463 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [624 Valid, 1499 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:25,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:25,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:25,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3826458036984353) internal successors, (972), 703 states have internal predecessors, (972), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:25,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 984 transitions. [2024-12-02 11:23:25,473 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 984 transitions. Word has length 459 [2024-12-02 11:23:25,473 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:25,473 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 984 transitions. [2024-12-02 11:23:25,473 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.4) internal successors, (432), 5 states have internal predecessors, (432), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:25,473 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 984 transitions. [2024-12-02 11:23:25,475 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 461 [2024-12-02 11:23:25,475 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:25,475 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:25,475 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable45 [2024-12-02 11:23:25,475 INFO L396 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:25,475 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:25,475 INFO L85 PathProgramCache]: Analyzing trace with hash -1083755368, now seen corresponding path program 1 times [2024-12-02 11:23:25,476 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:25,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020620541] [2024-12-02 11:23:25,476 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:25,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:25,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:26,103 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:26,103 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:26,103 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020620541] [2024-12-02 11:23:26,103 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020620541] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:26,103 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:26,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:26,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [492037268] [2024-12-02 11:23:26,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:26,104 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:26,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:26,104 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:26,104 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:26,104 INFO L87 Difference]: Start difference. First operand 711 states and 984 transitions. Second operand has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:26,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:26,155 INFO L93 Difference]: Finished difference Result 1165 states and 1615 transitions. [2024-12-02 11:23:26,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:26,156 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 460 [2024-12-02 11:23:26,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:26,157 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:26,157 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:26,158 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:26,158 INFO L435 NwaCegarLoop]: 757 mSDtfsCounter, 1111 mSDsluCounter, 759 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1114 SdHoareTripleChecker+Valid, 1516 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:26,158 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1114 Valid, 1516 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:26,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:26,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:26,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3812233285917497) internal successors, (971), 703 states have internal predecessors, (971), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:26,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 983 transitions. [2024-12-02 11:23:26,168 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 983 transitions. Word has length 460 [2024-12-02 11:23:26,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:26,168 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 983 transitions. [2024-12-02 11:23:26,168 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.6) internal successors, (433), 5 states have internal predecessors, (433), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:26,168 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 983 transitions. [2024-12-02 11:23:26,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 462 [2024-12-02 11:23:26,169 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:26,170 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:26,170 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable46 [2024-12-02 11:23:26,170 INFO L396 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:26,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:26,170 INFO L85 PathProgramCache]: Analyzing trace with hash 2085697088, now seen corresponding path program 1 times [2024-12-02 11:23:26,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:26,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455883364] [2024-12-02 11:23:26,170 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:26,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:26,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:26,950 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:26,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:26,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455883364] [2024-12-02 11:23:26,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455883364] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:26,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:26,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:26,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735131367] [2024-12-02 11:23:26,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:26,951 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:26,951 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:26,952 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:26,952 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:26,952 INFO L87 Difference]: Start difference. First operand 711 states and 983 transitions. Second operand has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:27,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:27,010 INFO L93 Difference]: Finished difference Result 1165 states and 1613 transitions. [2024-12-02 11:23:27,011 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:27,011 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 461 [2024-12-02 11:23:27,011 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:27,013 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:27,013 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:27,014 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:27,014 INFO L435 NwaCegarLoop]: 757 mSDtfsCounter, 1095 mSDsluCounter, 759 mSDsCounter, 0 mSdLazyCounter, 36 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1098 SdHoareTripleChecker+Valid, 1516 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 36 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:27,014 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1098 Valid, 1516 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 36 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:27,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:27,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:27,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.379800853485064) internal successors, (970), 703 states have internal predecessors, (970), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:27,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 982 transitions. [2024-12-02 11:23:27,039 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 982 transitions. Word has length 461 [2024-12-02 11:23:27,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:27,039 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 982 transitions. [2024-12-02 11:23:27,039 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 86.8) internal successors, (434), 5 states have internal predecessors, (434), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:27,039 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 982 transitions. [2024-12-02 11:23:27,044 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 463 [2024-12-02 11:23:27,044 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:27,044 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:27,044 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable47 [2024-12-02 11:23:27,045 INFO L396 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:27,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:27,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1106690637, now seen corresponding path program 1 times [2024-12-02 11:23:27,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:27,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324965477] [2024-12-02 11:23:27,045 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:27,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:27,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:27,725 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:27,725 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:27,725 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324965477] [2024-12-02 11:23:27,725 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324965477] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:27,725 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:27,725 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:27,725 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427264051] [2024-12-02 11:23:27,725 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:27,726 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:27,726 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:27,726 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:27,726 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:27,726 INFO L87 Difference]: Start difference. First operand 711 states and 982 transitions. Second operand has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:27,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:27,969 INFO L93 Difference]: Finished difference Result 1165 states and 1611 transitions. [2024-12-02 11:23:27,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:27,969 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 462 [2024-12-02 11:23:27,970 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:27,971 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:27,971 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:27,971 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:27,971 INFO L435 NwaCegarLoop]: 578 mSDtfsCounter, 583 mSDsluCounter, 587 mSDsCounter, 0 mSdLazyCounter, 392 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 586 SdHoareTripleChecker+Valid, 1165 SdHoareTripleChecker+Invalid, 393 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 392 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:27,971 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [586 Valid, 1165 Invalid, 393 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 392 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 11:23:27,972 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:27,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:27,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3783783783783783) internal successors, (969), 703 states have internal predecessors, (969), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:27,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 981 transitions. [2024-12-02 11:23:27,981 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 981 transitions. Word has length 462 [2024-12-02 11:23:27,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:27,981 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 981 transitions. [2024-12-02 11:23:27,981 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.0) internal successors, (435), 5 states have internal predecessors, (435), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:27,981 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 981 transitions. [2024-12-02 11:23:27,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 464 [2024-12-02 11:23:27,983 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:27,983 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:27,983 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable48 [2024-12-02 11:23:27,983 INFO L396 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:27,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:27,983 INFO L85 PathProgramCache]: Analyzing trace with hash 941358165, now seen corresponding path program 1 times [2024-12-02 11:23:27,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:27,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1665318693] [2024-12-02 11:23:27,984 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:27,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:28,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:29,063 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:29,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:29,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1665318693] [2024-12-02 11:23:29,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1665318693] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:29,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:29,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:29,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822419313] [2024-12-02 11:23:29,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:29,064 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:29,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:29,064 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:29,064 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:29,064 INFO L87 Difference]: Start difference. First operand 711 states and 981 transitions. Second operand has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:29,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:29,110 INFO L93 Difference]: Finished difference Result 1165 states and 1609 transitions. [2024-12-02 11:23:29,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:29,110 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 463 [2024-12-02 11:23:29,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:29,111 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:29,111 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:29,112 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:29,112 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 496 mSDsluCounter, 758 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 496 SdHoareTripleChecker+Valid, 1514 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:29,112 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [496 Valid, 1514 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:29,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:29,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:29,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3769559032716927) internal successors, (968), 703 states have internal predecessors, (968), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:29,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 980 transitions. [2024-12-02 11:23:29,123 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 980 transitions. Word has length 463 [2024-12-02 11:23:29,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:29,123 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 980 transitions. [2024-12-02 11:23:29,124 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 109.0) internal successors, (436), 4 states have internal predecessors, (436), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:29,124 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 980 transitions. [2024-12-02 11:23:29,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 465 [2024-12-02 11:23:29,126 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:29,126 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:29,126 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable49 [2024-12-02 11:23:29,126 INFO L396 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:29,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:29,127 INFO L85 PathProgramCache]: Analyzing trace with hash 2059983743, now seen corresponding path program 1 times [2024-12-02 11:23:29,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:29,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11823457] [2024-12-02 11:23:29,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:29,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:29,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:30,166 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:30,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:30,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11823457] [2024-12-02 11:23:30,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11823457] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:30,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:30,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:30,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2244020] [2024-12-02 11:23:30,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:30,167 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:30,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:30,167 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:30,167 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:30,167 INFO L87 Difference]: Start difference. First operand 711 states and 980 transitions. Second operand has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:30,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:30,236 INFO L93 Difference]: Finished difference Result 1165 states and 1607 transitions. [2024-12-02 11:23:30,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:30,237 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 464 [2024-12-02 11:23:30,237 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:30,238 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:30,238 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:30,239 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:30,239 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 655 mSDsluCounter, 750 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 655 SdHoareTripleChecker+Valid, 1491 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:30,239 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [655 Valid, 1491 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 62 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:30,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:30,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:30,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3755334281650071) internal successors, (967), 703 states have internal predecessors, (967), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:30,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 979 transitions. [2024-12-02 11:23:30,248 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 979 transitions. Word has length 464 [2024-12-02 11:23:30,248 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:30,249 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 979 transitions. [2024-12-02 11:23:30,249 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.4) internal successors, (437), 5 states have internal predecessors, (437), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:30,249 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 979 transitions. [2024-12-02 11:23:30,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 466 [2024-12-02 11:23:30,250 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:30,250 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:30,251 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable50 [2024-12-02 11:23:30,251 INFO L396 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:30,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:30,251 INFO L85 PathProgramCache]: Analyzing trace with hash 2072196053, now seen corresponding path program 1 times [2024-12-02 11:23:30,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:30,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328292746] [2024-12-02 11:23:30,251 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:30,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:30,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:31,531 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:31,531 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:31,531 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328292746] [2024-12-02 11:23:31,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328292746] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:31,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:31,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:31,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323880072] [2024-12-02 11:23:31,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:31,532 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:31,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:31,532 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:31,532 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:31,532 INFO L87 Difference]: Start difference. First operand 711 states and 979 transitions. Second operand has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:31,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:31,618 INFO L93 Difference]: Finished difference Result 1165 states and 1605 transitions. [2024-12-02 11:23:31,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:31,619 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 465 [2024-12-02 11:23:31,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:31,620 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:31,620 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:31,620 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:31,621 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 654 mSDsluCounter, 750 mSDsCounter, 0 mSdLazyCounter, 60 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 654 SdHoareTripleChecker+Valid, 1491 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 60 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:31,621 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [654 Valid, 1491 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 60 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:31,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:31,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:31,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3741109530583215) internal successors, (966), 703 states have internal predecessors, (966), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:31,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 978 transitions. [2024-12-02 11:23:31,630 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 978 transitions. Word has length 465 [2024-12-02 11:23:31,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:31,631 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 978 transitions. [2024-12-02 11:23:31,631 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.6) internal successors, (438), 5 states have internal predecessors, (438), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:31,631 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 978 transitions. [2024-12-02 11:23:31,632 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 467 [2024-12-02 11:23:31,632 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:31,633 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:31,633 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable51 [2024-12-02 11:23:31,633 INFO L396 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:31,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:31,633 INFO L85 PathProgramCache]: Analyzing trace with hash 512722894, now seen corresponding path program 1 times [2024-12-02 11:23:31,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:31,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686415520] [2024-12-02 11:23:31,634 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:31,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:32,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:32,728 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:32,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:32,729 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686415520] [2024-12-02 11:23:32,729 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686415520] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:32,729 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:32,729 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:32,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053342161] [2024-12-02 11:23:32,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:32,729 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:32,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:32,729 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:32,729 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:32,730 INFO L87 Difference]: Start difference. First operand 711 states and 978 transitions. Second operand has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:32,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:32,795 INFO L93 Difference]: Finished difference Result 1165 states and 1603 transitions. [2024-12-02 11:23:32,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:32,795 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 466 [2024-12-02 11:23:32,795 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:32,796 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:32,796 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:32,797 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:32,797 INFO L435 NwaCegarLoop]: 741 mSDtfsCounter, 505 mSDsluCounter, 743 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 505 SdHoareTripleChecker+Valid, 1484 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:32,797 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [505 Valid, 1484 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:32,797 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:32,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:32,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.372688477951636) internal successors, (965), 703 states have internal predecessors, (965), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:32,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 977 transitions. [2024-12-02 11:23:32,806 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 977 transitions. Word has length 466 [2024-12-02 11:23:32,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:32,806 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 977 transitions. [2024-12-02 11:23:32,806 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 109.75) internal successors, (439), 4 states have internal predecessors, (439), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:32,807 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 977 transitions. [2024-12-02 11:23:32,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 468 [2024-12-02 11:23:32,808 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:32,808 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:32,808 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable52 [2024-12-02 11:23:32,808 INFO L396 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:32,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:32,809 INFO L85 PathProgramCache]: Analyzing trace with hash 861938758, now seen corresponding path program 1 times [2024-12-02 11:23:32,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:32,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [112415910] [2024-12-02 11:23:32,809 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:32,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:33,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:33,876 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:33,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:33,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [112415910] [2024-12-02 11:23:33,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [112415910] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:33,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:33,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:33,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671386875] [2024-12-02 11:23:33,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:33,877 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:33,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:33,877 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:33,877 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:33,877 INFO L87 Difference]: Start difference. First operand 711 states and 977 transitions. Second operand has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:34,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:34,008 INFO L93 Difference]: Finished difference Result 1165 states and 1601 transitions. [2024-12-02 11:23:34,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:34,008 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 467 [2024-12-02 11:23:34,008 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:34,009 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:34,009 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:34,010 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:34,010 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 637 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 118 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 637 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 118 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 118 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:34,010 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [637 Valid, 1429 Invalid, 118 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 118 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:34,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:34,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:34,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3712660028449501) internal successors, (964), 703 states have internal predecessors, (964), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:34,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 976 transitions. [2024-12-02 11:23:34,020 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 976 transitions. Word has length 467 [2024-12-02 11:23:34,020 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:34,020 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 976 transitions. [2024-12-02 11:23:34,020 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.0) internal successors, (440), 5 states have internal predecessors, (440), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:34,020 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 976 transitions. [2024-12-02 11:23:34,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 469 [2024-12-02 11:23:34,021 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:34,022 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:34,022 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable53 [2024-12-02 11:23:34,022 INFO L396 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:34,022 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:34,022 INFO L85 PathProgramCache]: Analyzing trace with hash 1901367216, now seen corresponding path program 1 times [2024-12-02 11:23:34,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:34,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530979084] [2024-12-02 11:23:34,022 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:34,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:34,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:35,099 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:35,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:35,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [530979084] [2024-12-02 11:23:35,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [530979084] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:35,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:35,100 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:35,100 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1834819387] [2024-12-02 11:23:35,100 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:35,101 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:35,101 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:35,101 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:35,101 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:35,101 INFO L87 Difference]: Start difference. First operand 711 states and 976 transitions. Second operand has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:35,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:35,222 INFO L93 Difference]: Finished difference Result 1165 states and 1599 transitions. [2024-12-02 11:23:35,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:35,222 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 468 [2024-12-02 11:23:35,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:35,223 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:35,223 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:35,224 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:35,224 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 1202 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1202 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 116 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:35,224 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1202 Valid, 1422 Invalid, 116 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 116 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:35,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:35,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:35,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3698435277382646) internal successors, (963), 703 states have internal predecessors, (963), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:35,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 975 transitions. [2024-12-02 11:23:35,233 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 975 transitions. Word has length 468 [2024-12-02 11:23:35,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:35,233 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 975 transitions. [2024-12-02 11:23:35,233 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.2) internal successors, (441), 5 states have internal predecessors, (441), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:35,233 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 975 transitions. [2024-12-02 11:23:35,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 470 [2024-12-02 11:23:35,235 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:35,235 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:35,235 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable54 [2024-12-02 11:23:35,235 INFO L396 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:35,236 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:35,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1536682647, now seen corresponding path program 1 times [2024-12-02 11:23:35,236 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:35,236 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1312683966] [2024-12-02 11:23:35,236 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:35,236 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:35,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:36,602 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:36,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:36,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1312683966] [2024-12-02 11:23:36,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1312683966] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:36,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:36,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:36,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827789536] [2024-12-02 11:23:36,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:36,604 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:36,604 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:36,604 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:36,605 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:36,605 INFO L87 Difference]: Start difference. First operand 711 states and 975 transitions. Second operand has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:36,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:36,708 INFO L93 Difference]: Finished difference Result 1165 states and 1597 transitions. [2024-12-02 11:23:36,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:36,709 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 469 [2024-12-02 11:23:36,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:36,710 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:36,710 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:36,710 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:36,711 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 558 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 114 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 558 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 114 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:36,711 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [558 Valid, 1422 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 114 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:36,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:36,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:36,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.368421052631579) internal successors, (962), 703 states have internal predecessors, (962), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:36,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 974 transitions. [2024-12-02 11:23:36,723 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 974 transitions. Word has length 469 [2024-12-02 11:23:36,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:36,723 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 974 transitions. [2024-12-02 11:23:36,723 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 110.5) internal successors, (442), 4 states have internal predecessors, (442), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:36,723 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 974 transitions. [2024-12-02 11:23:36,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 471 [2024-12-02 11:23:36,725 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:36,725 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:36,725 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable55 [2024-12-02 11:23:36,725 INFO L396 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:36,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:36,725 INFO L85 PathProgramCache]: Analyzing trace with hash 1546007711, now seen corresponding path program 1 times [2024-12-02 11:23:36,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:36,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242621334] [2024-12-02 11:23:36,725 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:36,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:37,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:37,829 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:37,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:37,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242621334] [2024-12-02 11:23:37,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242621334] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:37,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:37,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:37,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [548919129] [2024-12-02 11:23:37,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:37,830 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:37,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:37,830 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:37,830 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:37,830 INFO L87 Difference]: Start difference. First operand 711 states and 974 transitions. Second operand has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:37,950 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:37,950 INFO L93 Difference]: Finished difference Result 1165 states and 1595 transitions. [2024-12-02 11:23:37,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:37,951 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 470 [2024-12-02 11:23:37,951 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:37,952 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:37,952 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:37,952 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:37,953 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 634 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 634 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:37,953 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [634 Valid, 1429 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 112 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:37,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:37,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:37,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3669985775248934) internal successors, (961), 703 states have internal predecessors, (961), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:37,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 973 transitions. [2024-12-02 11:23:37,963 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 973 transitions. Word has length 470 [2024-12-02 11:23:37,963 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:37,963 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 973 transitions. [2024-12-02 11:23:37,963 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.6) internal successors, (443), 5 states have internal predecessors, (443), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:37,963 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 973 transitions. [2024-12-02 11:23:37,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 472 [2024-12-02 11:23:37,964 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:37,964 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:37,965 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable56 [2024-12-02 11:23:37,965 INFO L396 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:37,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:37,965 INFO L85 PathProgramCache]: Analyzing trace with hash 916407912, now seen corresponding path program 1 times [2024-12-02 11:23:37,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:37,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884591822] [2024-12-02 11:23:37,965 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:37,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:38,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:39,031 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:39,032 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:39,032 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884591822] [2024-12-02 11:23:39,032 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884591822] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:39,032 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:39,032 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:39,032 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [388678241] [2024-12-02 11:23:39,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:39,032 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:39,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:39,032 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:39,033 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:39,033 INFO L87 Difference]: Start difference. First operand 711 states and 973 transitions. Second operand has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:39,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:39,161 INFO L93 Difference]: Finished difference Result 1165 states and 1593 transitions. [2024-12-02 11:23:39,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:39,162 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 471 [2024-12-02 11:23:39,162 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:39,163 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:39,163 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:39,164 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:39,164 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 633 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 110 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 633 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 110 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:39,164 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [633 Valid, 1429 Invalid, 110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 110 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:39,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:39,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:39,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3655761024182076) internal successors, (960), 703 states have internal predecessors, (960), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:39,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 972 transitions. [2024-12-02 11:23:39,173 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 972 transitions. Word has length 471 [2024-12-02 11:23:39,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:39,174 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 972 transitions. [2024-12-02 11:23:39,174 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 88.8) internal successors, (444), 5 states have internal predecessors, (444), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:39,174 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 972 transitions. [2024-12-02 11:23:39,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 473 [2024-12-02 11:23:39,175 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:39,175 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:39,176 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable57 [2024-12-02 11:23:39,176 INFO L396 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:39,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:39,176 INFO L85 PathProgramCache]: Analyzing trace with hash -426939378, now seen corresponding path program 1 times [2024-12-02 11:23:39,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:39,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429570346] [2024-12-02 11:23:39,176 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:39,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:39,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:40,264 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:40,264 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:40,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429570346] [2024-12-02 11:23:40,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429570346] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:40,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:40,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:40,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540425180] [2024-12-02 11:23:40,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:40,264 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:40,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:40,265 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:40,265 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:40,265 INFO L87 Difference]: Start difference. First operand 711 states and 972 transitions. Second operand has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:40,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:40,375 INFO L93 Difference]: Finished difference Result 1165 states and 1591 transitions. [2024-12-02 11:23:40,376 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:40,376 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 472 [2024-12-02 11:23:40,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:40,377 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:40,377 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:40,378 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:40,378 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 632 mSDsluCounter, 719 mSDsCounter, 0 mSdLazyCounter, 108 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 632 SdHoareTripleChecker+Valid, 1429 SdHoareTripleChecker+Invalid, 108 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 108 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:40,378 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [632 Valid, 1429 Invalid, 108 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 108 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:40,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:40,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:40,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.364153627311522) internal successors, (959), 703 states have internal predecessors, (959), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:40,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 971 transitions. [2024-12-02 11:23:40,387 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 971 transitions. Word has length 472 [2024-12-02 11:23:40,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:40,387 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 971 transitions. [2024-12-02 11:23:40,387 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 89.0) internal successors, (445), 5 states have internal predecessors, (445), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:40,387 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 971 transitions. [2024-12-02 11:23:40,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 474 [2024-12-02 11:23:40,389 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:40,389 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:40,389 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable58 [2024-12-02 11:23:40,389 INFO L396 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:40,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:40,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1135077305, now seen corresponding path program 1 times [2024-12-02 11:23:40,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:40,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [531091807] [2024-12-02 11:23:40,390 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:40,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:40,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:41,459 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:41,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:41,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [531091807] [2024-12-02 11:23:41,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [531091807] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:41,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:41,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2024-12-02 11:23:41,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044016172] [2024-12-02 11:23:41,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:41,459 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:23:41,459 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:41,460 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:23:41,460 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-12-02 11:23:41,460 INFO L87 Difference]: Start difference. First operand 711 states and 971 transitions. Second operand has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:41,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:41,565 INFO L93 Difference]: Finished difference Result 1165 states and 1589 transitions. [2024-12-02 11:23:41,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:23:41,566 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 473 [2024-12-02 11:23:41,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:41,567 INFO L225 Difference]: With dead ends: 1165 [2024-12-02 11:23:41,567 INFO L226 Difference]: Without dead ends: 711 [2024-12-02 11:23:41,567 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:41,568 INFO L435 NwaCegarLoop]: 710 mSDtfsCounter, 522 mSDsluCounter, 712 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 522 SdHoareTripleChecker+Valid, 1422 SdHoareTripleChecker+Invalid, 106 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:41,568 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [522 Valid, 1422 Invalid, 106 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 106 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:41,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2024-12-02 11:23:41,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 711. [2024-12-02 11:23:41,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 711 states, 703 states have (on average 1.3627311522048364) internal successors, (958), 703 states have internal predecessors, (958), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:23:41,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 711 states to 711 states and 970 transitions. [2024-12-02 11:23:41,577 INFO L78 Accepts]: Start accepts. Automaton has 711 states and 970 transitions. Word has length 473 [2024-12-02 11:23:41,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:41,577 INFO L471 AbstractCegarLoop]: Abstraction has 711 states and 970 transitions. [2024-12-02 11:23:41,577 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 111.5) internal successors, (446), 4 states have internal predecessors, (446), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:41,577 INFO L276 IsEmpty]: Start isEmpty. Operand 711 states and 970 transitions. [2024-12-02 11:23:41,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 475 [2024-12-02 11:23:41,579 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:41,579 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:41,579 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable59 [2024-12-02 11:23:41,579 INFO L396 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:41,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:41,580 INFO L85 PathProgramCache]: Analyzing trace with hash 1287685629, now seen corresponding path program 1 times [2024-12-02 11:23:41,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:41,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628136119] [2024-12-02 11:23:41,580 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:41,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:42,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:43,161 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 114 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:43,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:43,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628136119] [2024-12-02 11:23:43,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628136119] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:43,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:43,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:23:43,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538623147] [2024-12-02 11:23:43,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:43,162 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:23:43,162 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:43,163 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:23:43,163 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:43,163 INFO L87 Difference]: Start difference. First operand 711 states and 970 transitions. Second operand has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:43,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:43,568 INFO L93 Difference]: Finished difference Result 1683 states and 2299 transitions. [2024-12-02 11:23:43,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:23:43,568 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 474 [2024-12-02 11:23:43,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:43,570 INFO L225 Difference]: With dead ends: 1683 [2024-12-02 11:23:43,571 INFO L226 Difference]: Without dead ends: 1229 [2024-12-02 11:23:43,571 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:43,571 INFO L435 NwaCegarLoop]: 674 mSDtfsCounter, 697 mSDsluCounter, 2151 mSDsCounter, 0 mSdLazyCounter, 578 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 700 SdHoareTripleChecker+Valid, 2825 SdHoareTripleChecker+Invalid, 586 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 578 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:43,572 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [700 Valid, 2825 Invalid, 586 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 578 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 11:23:43,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1229 states. [2024-12-02 11:23:43,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1229 to 1121. [2024-12-02 11:23:43,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1121 states, 1110 states have (on average 1.3567567567567567) internal successors, (1506), 1110 states have internal predecessors, (1506), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 11:23:43,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1121 states to 1121 states and 1524 transitions. [2024-12-02 11:23:43,598 INFO L78 Accepts]: Start accepts. Automaton has 1121 states and 1524 transitions. Word has length 474 [2024-12-02 11:23:43,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:43,598 INFO L471 AbstractCegarLoop]: Abstraction has 1121 states and 1524 transitions. [2024-12-02 11:23:43,598 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 74.5) internal successors, (447), 6 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:43,598 INFO L276 IsEmpty]: Start isEmpty. Operand 1121 states and 1524 transitions. [2024-12-02 11:23:43,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 476 [2024-12-02 11:23:43,603 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:43,603 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:43,603 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable60 [2024-12-02 11:23:43,603 INFO L396 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:43,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:43,603 INFO L85 PathProgramCache]: Analyzing trace with hash -642634531, now seen corresponding path program 1 times [2024-12-02 11:23:43,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:43,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885290597] [2024-12-02 11:23:43,604 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:43,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:44,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:45,249 INFO L134 CoverageAnalysis]: Checked inductivity of 174 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 128 trivial. 0 not checked. [2024-12-02 11:23:45,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:45,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885290597] [2024-12-02 11:23:45,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885290597] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:45,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:45,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 11:23:45,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577827490] [2024-12-02 11:23:45,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:45,250 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 11:23:45,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:45,251 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 11:23:45,251 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:45,251 INFO L87 Difference]: Start difference. First operand 1121 states and 1524 transitions. Second operand has 7 states, 7 states have (on average 54.714285714285715) internal successors, (383), 7 states have internal predecessors, (383), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:45,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:45,487 INFO L93 Difference]: Finished difference Result 2301 states and 3126 transitions. [2024-12-02 11:23:45,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 11:23:45,487 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 54.714285714285715) internal successors, (383), 7 states have internal predecessors, (383), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 475 [2024-12-02 11:23:45,487 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:45,489 INFO L225 Difference]: With dead ends: 2301 [2024-12-02 11:23:45,489 INFO L226 Difference]: Without dead ends: 1133 [2024-12-02 11:23:45,490 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2024-12-02 11:23:45,490 INFO L435 NwaCegarLoop]: 739 mSDtfsCounter, 824 mSDsluCounter, 2779 mSDsCounter, 0 mSdLazyCounter, 290 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 827 SdHoareTripleChecker+Valid, 3518 SdHoareTripleChecker+Invalid, 298 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 290 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:45,490 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [827 Valid, 3518 Invalid, 298 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 290 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2024-12-02 11:23:45,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1133 states. [2024-12-02 11:23:45,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1133 to 1127. [2024-12-02 11:23:45,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1127 states, 1116 states have (on average 1.3521505376344085) internal successors, (1509), 1116 states have internal predecessors, (1509), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 11:23:45,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1127 states to 1127 states and 1527 transitions. [2024-12-02 11:23:45,506 INFO L78 Accepts]: Start accepts. Automaton has 1127 states and 1527 transitions. Word has length 475 [2024-12-02 11:23:45,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:45,506 INFO L471 AbstractCegarLoop]: Abstraction has 1127 states and 1527 transitions. [2024-12-02 11:23:45,506 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 54.714285714285715) internal successors, (383), 7 states have internal predecessors, (383), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:45,506 INFO L276 IsEmpty]: Start isEmpty. Operand 1127 states and 1527 transitions. [2024-12-02 11:23:45,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 478 [2024-12-02 11:23:45,509 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:45,509 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:45,509 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable61 [2024-12-02 11:23:45,509 INFO L396 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:45,509 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:45,510 INFO L85 PathProgramCache]: Analyzing trace with hash 18182357, now seen corresponding path program 1 times [2024-12-02 11:23:45,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:45,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195405053] [2024-12-02 11:23:45,510 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:45,510 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:46,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:47,312 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 109 proven. 0 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2024-12-02 11:23:47,312 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:47,312 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195405053] [2024-12-02 11:23:47,312 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195405053] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:47,312 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:47,312 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:23:47,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274544408] [2024-12-02 11:23:47,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:47,313 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:23:47,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:47,313 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:23:47,314 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:47,314 INFO L87 Difference]: Start difference. First operand 1127 states and 1527 transitions. Second operand has 5 states, 5 states have (on average 89.4) internal successors, (447), 5 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:47,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:47,352 INFO L93 Difference]: Finished difference Result 2058 states and 2741 transitions. [2024-12-02 11:23:47,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:23:47,352 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 89.4) internal successors, (447), 5 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 477 [2024-12-02 11:23:47,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:47,354 INFO L225 Difference]: With dead ends: 2058 [2024-12-02 11:23:47,354 INFO L226 Difference]: Without dead ends: 1364 [2024-12-02 11:23:47,355 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:23:47,355 INFO L435 NwaCegarLoop]: 755 mSDtfsCounter, 19 mSDsluCounter, 2256 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 3011 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:47,355 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 3011 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 32 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:23:47,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1364 states. [2024-12-02 11:23:47,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1364 to 1358. [2024-12-02 11:23:47,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1358 states, 1347 states have (on average 1.311804008908686) internal successors, (1767), 1347 states have internal predecessors, (1767), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 11:23:47,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1358 states to 1358 states and 1785 transitions. [2024-12-02 11:23:47,371 INFO L78 Accepts]: Start accepts. Automaton has 1358 states and 1785 transitions. Word has length 477 [2024-12-02 11:23:47,371 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:47,371 INFO L471 AbstractCegarLoop]: Abstraction has 1358 states and 1785 transitions. [2024-12-02 11:23:47,372 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 89.4) internal successors, (447), 5 states have internal predecessors, (447), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:47,372 INFO L276 IsEmpty]: Start isEmpty. Operand 1358 states and 1785 transitions. [2024-12-02 11:23:47,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 480 [2024-12-02 11:23:47,373 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:47,374 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:47,374 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable62 [2024-12-02 11:23:47,374 INFO L396 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:47,374 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:47,374 INFO L85 PathProgramCache]: Analyzing trace with hash -378391989, now seen corresponding path program 1 times [2024-12-02 11:23:47,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:47,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519307433] [2024-12-02 11:23:47,374 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:47,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:48,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:49,076 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 116 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:23:49,076 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:49,076 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1519307433] [2024-12-02 11:23:49,076 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1519307433] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:49,076 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:49,076 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:23:49,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22600593] [2024-12-02 11:23:49,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:49,077 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:23:49,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:49,077 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:23:49,077 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:23:49,077 INFO L87 Difference]: Start difference. First operand 1358 states and 1785 transitions. Second operand has 6 states, 6 states have (on average 75.33333333333333) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:49,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:49,544 INFO L93 Difference]: Finished difference Result 1914 states and 2523 transitions. [2024-12-02 11:23:49,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:23:49,544 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 75.33333333333333) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 479 [2024-12-02 11:23:49,545 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:49,547 INFO L225 Difference]: With dead ends: 1914 [2024-12-02 11:23:49,547 INFO L226 Difference]: Without dead ends: 1381 [2024-12-02 11:23:49,547 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:49,548 INFO L435 NwaCegarLoop]: 567 mSDtfsCounter, 1334 mSDsluCounter, 1678 mSDsCounter, 0 mSdLazyCounter, 791 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1337 SdHoareTripleChecker+Valid, 2245 SdHoareTripleChecker+Invalid, 791 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 791 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:49,548 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1337 Valid, 2245 Invalid, 791 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 791 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:23:49,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1381 states. [2024-12-02 11:23:49,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1381 to 1359. [2024-12-02 11:23:49,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1359 states, 1348 states have (on average 1.311572700296736) internal successors, (1768), 1348 states have internal predecessors, (1768), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 11:23:49,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1359 states to 1359 states and 1786 transitions. [2024-12-02 11:23:49,566 INFO L78 Accepts]: Start accepts. Automaton has 1359 states and 1786 transitions. Word has length 479 [2024-12-02 11:23:49,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:49,566 INFO L471 AbstractCegarLoop]: Abstraction has 1359 states and 1786 transitions. [2024-12-02 11:23:49,566 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 75.33333333333333) internal successors, (452), 6 states have internal predecessors, (452), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:49,566 INFO L276 IsEmpty]: Start isEmpty. Operand 1359 states and 1786 transitions. [2024-12-02 11:23:49,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 480 [2024-12-02 11:23:49,568 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:49,569 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:49,569 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable63 [2024-12-02 11:23:49,569 INFO L396 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:49,569 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:49,569 INFO L85 PathProgramCache]: Analyzing trace with hash 667839828, now seen corresponding path program 1 times [2024-12-02 11:23:49,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:49,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083065985] [2024-12-02 11:23:49,569 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:49,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:50,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:51,358 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2024-12-02 11:23:51,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:51,358 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083065985] [2024-12-02 11:23:51,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083065985] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:51,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:51,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 11:23:51,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190520985] [2024-12-02 11:23:51,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:51,358 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 11:23:51,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:51,359 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 11:23:51,359 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2024-12-02 11:23:51,359 INFO L87 Difference]: Start difference. First operand 1359 states and 1786 transitions. Second operand has 8 states, 8 states have (on average 46.25) internal successors, (370), 8 states have internal predecessors, (370), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:51,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:51,517 INFO L93 Difference]: Finished difference Result 3086 states and 4038 transitions. [2024-12-02 11:23:51,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 11:23:51,518 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 46.25) internal successors, (370), 8 states have internal predecessors, (370), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 479 [2024-12-02 11:23:51,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:51,521 INFO L225 Difference]: With dead ends: 3086 [2024-12-02 11:23:51,521 INFO L226 Difference]: Without dead ends: 2371 [2024-12-02 11:23:51,522 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:23:51,522 INFO L435 NwaCegarLoop]: 1820 mSDtfsCounter, 1103 mSDsluCounter, 9310 mSDsCounter, 0 mSdLazyCounter, 180 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1106 SdHoareTripleChecker+Valid, 11130 SdHoareTripleChecker+Invalid, 180 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 180 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:51,522 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1106 Valid, 11130 Invalid, 180 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 180 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:23:51,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2371 states. [2024-12-02 11:23:51,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2371 to 1428. [2024-12-02 11:23:51,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1428 states, 1414 states have (on average 1.3154172560113153) internal successors, (1860), 1414 states have internal predecessors, (1860), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:23:51,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1428 states to 1428 states and 1884 transitions. [2024-12-02 11:23:51,545 INFO L78 Accepts]: Start accepts. Automaton has 1428 states and 1884 transitions. Word has length 479 [2024-12-02 11:23:51,545 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:51,545 INFO L471 AbstractCegarLoop]: Abstraction has 1428 states and 1884 transitions. [2024-12-02 11:23:51,545 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 46.25) internal successors, (370), 8 states have internal predecessors, (370), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:23:51,545 INFO L276 IsEmpty]: Start isEmpty. Operand 1428 states and 1884 transitions. [2024-12-02 11:23:51,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 481 [2024-12-02 11:23:51,547 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:51,547 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:51,547 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable64 [2024-12-02 11:23:51,547 INFO L396 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:51,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:51,547 INFO L85 PathProgramCache]: Analyzing trace with hash 949589088, now seen corresponding path program 1 times [2024-12-02 11:23:51,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:51,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321586877] [2024-12-02 11:23:51,548 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:51,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:52,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:53,192 INFO L134 CoverageAnalysis]: Checked inductivity of 176 backedges. 19 proven. 0 refuted. 0 times theorem prover too weak. 157 trivial. 0 not checked. [2024-12-02 11:23:53,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:53,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321586877] [2024-12-02 11:23:53,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321586877] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:53,192 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:53,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 11:23:53,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951105353] [2024-12-02 11:23:53,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:53,192 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 11:23:53,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:53,192 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 11:23:53,193 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:53,193 INFO L87 Difference]: Start difference. First operand 1428 states and 1884 transitions. Second operand has 7 states, 7 states have (on average 51.57142857142857) internal successors, (361), 7 states have internal predecessors, (361), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-12-02 11:23:53,623 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:53,623 INFO L93 Difference]: Finished difference Result 2646 states and 3467 transitions. [2024-12-02 11:23:53,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:23:53,623 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 51.57142857142857) internal successors, (361), 7 states have internal predecessors, (361), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) Word has length 480 [2024-12-02 11:23:53,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:53,627 INFO L225 Difference]: With dead ends: 2646 [2024-12-02 11:23:53,627 INFO L226 Difference]: Without dead ends: 1444 [2024-12-02 11:23:53,628 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-12-02 11:23:53,628 INFO L435 NwaCegarLoop]: 560 mSDtfsCounter, 749 mSDsluCounter, 1680 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 751 SdHoareTripleChecker+Valid, 2240 SdHoareTripleChecker+Invalid, 812 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:53,628 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [751 Valid, 2240 Invalid, 812 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:23:53,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1444 states. [2024-12-02 11:23:53,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1444 to 1436. [2024-12-02 11:23:53,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1436 states, 1422 states have (on average 1.310829817158931) internal successors, (1864), 1422 states have internal predecessors, (1864), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:23:53,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1436 states to 1436 states and 1888 transitions. [2024-12-02 11:23:53,662 INFO L78 Accepts]: Start accepts. Automaton has 1436 states and 1888 transitions. Word has length 480 [2024-12-02 11:23:53,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:53,662 INFO L471 AbstractCegarLoop]: Abstraction has 1436 states and 1888 transitions. [2024-12-02 11:23:53,662 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 51.57142857142857) internal successors, (361), 7 states have internal predecessors, (361), 2 states have call successors, (4), 1 states have call predecessors, (4), 1 states have return successors, (4), 2 states have call predecessors, (4), 2 states have call successors, (4) [2024-12-02 11:23:53,662 INFO L276 IsEmpty]: Start isEmpty. Operand 1436 states and 1888 transitions. [2024-12-02 11:23:53,665 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 483 [2024-12-02 11:23:53,665 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:53,666 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:53,666 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable65 [2024-12-02 11:23:53,666 INFO L396 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:53,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:53,666 INFO L85 PathProgramCache]: Analyzing trace with hash 1975318442, now seen corresponding path program 1 times [2024-12-02 11:23:53,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:53,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1449503335] [2024-12-02 11:23:53,666 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:53,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:54,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:55,317 INFO L134 CoverageAnalysis]: Checked inductivity of 177 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 149 trivial. 0 not checked. [2024-12-02 11:23:55,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:55,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1449503335] [2024-12-02 11:23:55,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1449503335] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:23:55,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:23:55,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2024-12-02 11:23:55,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1959960875] [2024-12-02 11:23:55,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:23:55,318 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 11:23:55,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:23:55,318 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 11:23:55,319 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:23:55,319 INFO L87 Difference]: Start difference. First operand 1436 states and 1888 transitions. Second operand has 7 states, 7 states have (on average 52.857142857142854) internal successors, (370), 7 states have internal predecessors, (370), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 11:23:55,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:23:55,739 INFO L93 Difference]: Finished difference Result 2614 states and 3409 transitions. [2024-12-02 11:23:55,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:23:55,740 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 52.857142857142854) internal successors, (370), 7 states have internal predecessors, (370), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 482 [2024-12-02 11:23:55,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:23:55,741 INFO L225 Difference]: With dead ends: 2614 [2024-12-02 11:23:55,741 INFO L226 Difference]: Without dead ends: 1452 [2024-12-02 11:23:55,742 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2024-12-02 11:23:55,742 INFO L435 NwaCegarLoop]: 559 mSDtfsCounter, 1421 mSDsluCounter, 1670 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1422 SdHoareTripleChecker+Valid, 2229 SdHoareTripleChecker+Invalid, 813 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:23:55,743 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1422 Valid, 2229 Invalid, 813 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:23:55,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1452 states. [2024-12-02 11:23:55,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1452 to 1444. [2024-12-02 11:23:55,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1444 states, 1430 states have (on average 1.3062937062937063) internal successors, (1868), 1430 states have internal predecessors, (1868), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:23:55,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1444 states to 1444 states and 1892 transitions. [2024-12-02 11:23:55,775 INFO L78 Accepts]: Start accepts. Automaton has 1444 states and 1892 transitions. Word has length 482 [2024-12-02 11:23:55,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:23:55,775 INFO L471 AbstractCegarLoop]: Abstraction has 1444 states and 1892 transitions. [2024-12-02 11:23:55,775 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 52.857142857142854) internal successors, (370), 7 states have internal predecessors, (370), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 11:23:55,775 INFO L276 IsEmpty]: Start isEmpty. Operand 1444 states and 1892 transitions. [2024-12-02 11:23:55,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 485 [2024-12-02 11:23:55,778 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:23:55,778 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:23:55,779 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable66 [2024-12-02 11:23:55,779 INFO L396 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:23:55,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:23:55,779 INFO L85 PathProgramCache]: Analyzing trace with hash 529239552, now seen corresponding path program 1 times [2024-12-02 11:23:55,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:23:55,779 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147379804] [2024-12-02 11:23:55,779 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:55,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:23:56,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:57,685 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 98 proven. 4 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-12-02 11:23:57,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:23:57,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [147379804] [2024-12-02 11:23:57,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [147379804] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:23:57,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1053304726] [2024-12-02 11:23:57,686 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:23:57,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:23:57,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:23:57,688 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:23:57,688 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2024-12-02 11:23:59,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:23:59,988 INFO L256 TraceCheckSpWp]: Trace formula consists of 2970 conjuncts, 22 conjuncts are in the unsatisfiable core [2024-12-02 11:24:00,001 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:24:00,996 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 130 proven. 4 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2024-12-02 11:24:00,996 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:24:01,981 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 98 proven. 4 refuted. 0 times theorem prover too weak. 76 trivial. 0 not checked. [2024-12-02 11:24:01,981 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1053304726] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:24:01,981 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:24:01,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 13 [2024-12-02 11:24:01,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419053873] [2024-12-02 11:24:01,981 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:24:01,982 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2024-12-02 11:24:01,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:01,983 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2024-12-02 11:24:01,983 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2024-12-02 11:24:01,983 INFO L87 Difference]: Start difference. First operand 1444 states and 1892 transitions. Second operand has 13 states, 13 states have (on average 60.84615384615385) internal successors, (791), 13 states have internal predecessors, (791), 3 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 11:24:02,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:02,700 INFO L93 Difference]: Finished difference Result 2652 states and 3450 transitions. [2024-12-02 11:24:02,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 11:24:02,701 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 60.84615384615385) internal successors, (791), 13 states have internal predecessors, (791), 3 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) Word has length 484 [2024-12-02 11:24:02,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:02,703 INFO L225 Difference]: With dead ends: 2652 [2024-12-02 11:24:02,703 INFO L226 Difference]: Without dead ends: 1452 [2024-12-02 11:24:02,704 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 979 GetRequests, 964 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=212, Unknown=0, NotChecked=0, Total=272 [2024-12-02 11:24:02,705 INFO L435 NwaCegarLoop]: 559 mSDtfsCounter, 837 mSDsluCounter, 3332 mSDsCounter, 0 mSdLazyCounter, 1421 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 837 SdHoareTripleChecker+Valid, 3891 SdHoareTripleChecker+Invalid, 1422 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1421 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:02,705 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [837 Valid, 3891 Invalid, 1422 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1421 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 11:24:02,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1452 states. [2024-12-02 11:24:02,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1452 to 1448. [2024-12-02 11:24:02,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1448 states, 1434 states have (on average 1.3054393305439331) internal successors, (1872), 1434 states have internal predecessors, (1872), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:24:02,725 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1448 states to 1448 states and 1896 transitions. [2024-12-02 11:24:02,726 INFO L78 Accepts]: Start accepts. Automaton has 1448 states and 1896 transitions. Word has length 484 [2024-12-02 11:24:02,726 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:02,726 INFO L471 AbstractCegarLoop]: Abstraction has 1448 states and 1896 transitions. [2024-12-02 11:24:02,726 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 60.84615384615385) internal successors, (791), 13 states have internal predecessors, (791), 3 states have call successors, (10), 2 states have call predecessors, (10), 2 states have return successors, (10), 3 states have call predecessors, (10), 3 states have call successors, (10) [2024-12-02 11:24:02,726 INFO L276 IsEmpty]: Start isEmpty. Operand 1448 states and 1896 transitions. [2024-12-02 11:24:02,728 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 487 [2024-12-02 11:24:02,728 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:02,728 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:02,745 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2024-12-02 11:24:02,929 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable67 [2024-12-02 11:24:02,929 INFO L396 AbstractCegarLoop]: === Iteration 69 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:02,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:02,929 INFO L85 PathProgramCache]: Analyzing trace with hash 805295154, now seen corresponding path program 1 times [2024-12-02 11:24:02,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:02,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [487713180] [2024-12-02 11:24:02,929 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:02,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:04,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:05,806 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2024-12-02 11:24:05,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:05,806 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [487713180] [2024-12-02 11:24:05,806 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [487713180] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:05,806 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:05,806 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 11:24:05,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239634372] [2024-12-02 11:24:05,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:05,807 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 11:24:05,807 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:05,808 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 11:24:05,808 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2024-12-02 11:24:05,808 INFO L87 Difference]: Start difference. First operand 1448 states and 1896 transitions. Second operand has 8 states, 8 states have (on average 44.125) internal successors, (353), 8 states have internal predecessors, (353), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:06,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:06,447 INFO L93 Difference]: Finished difference Result 2748 states and 3572 transitions. [2024-12-02 11:24:06,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 11:24:06,447 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 44.125) internal successors, (353), 8 states have internal predecessors, (353), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 486 [2024-12-02 11:24:06,447 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:06,449 INFO L225 Difference]: With dead ends: 2748 [2024-12-02 11:24:06,449 INFO L226 Difference]: Without dead ends: 1466 [2024-12-02 11:24:06,449 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2024-12-02 11:24:06,450 INFO L435 NwaCegarLoop]: 561 mSDtfsCounter, 891 mSDsluCounter, 2372 mSDsCounter, 0 mSdLazyCounter, 1058 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 897 SdHoareTripleChecker+Valid, 2933 SdHoareTripleChecker+Invalid, 1059 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 1058 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:06,450 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [897 Valid, 2933 Invalid, 1059 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 1058 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2024-12-02 11:24:06,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2024-12-02 11:24:06,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1463. [2024-12-02 11:24:06,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1463 states, 1449 states have (on average 1.3022774327122153) internal successors, (1887), 1449 states have internal predecessors, (1887), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:24:06,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1463 states to 1463 states and 1911 transitions. [2024-12-02 11:24:06,470 INFO L78 Accepts]: Start accepts. Automaton has 1463 states and 1911 transitions. Word has length 486 [2024-12-02 11:24:06,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:06,470 INFO L471 AbstractCegarLoop]: Abstraction has 1463 states and 1911 transitions. [2024-12-02 11:24:06,470 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 44.125) internal successors, (353), 8 states have internal predecessors, (353), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:06,470 INFO L276 IsEmpty]: Start isEmpty. Operand 1463 states and 1911 transitions. [2024-12-02 11:24:06,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 488 [2024-12-02 11:24:06,472 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:06,472 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:06,472 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable68 [2024-12-02 11:24:06,472 INFO L396 AbstractCegarLoop]: === Iteration 70 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:06,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:06,473 INFO L85 PathProgramCache]: Analyzing trace with hash -576410301, now seen corresponding path program 1 times [2024-12-02 11:24:06,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:06,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824784050] [2024-12-02 11:24:06,473 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:06,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:07,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:08,380 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2024-12-02 11:24:08,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:08,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824784050] [2024-12-02 11:24:08,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824784050] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:08,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:08,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:24:08,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052130868] [2024-12-02 11:24:08,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:08,381 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:08,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:08,382 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:08,382 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:08,382 INFO L87 Difference]: Start difference. First operand 1463 states and 1911 transitions. Second operand has 6 states, 6 states have (on average 59.0) internal successors, (354), 6 states have internal predecessors, (354), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:08,835 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:08,835 INFO L93 Difference]: Finished difference Result 2735 states and 3551 transitions. [2024-12-02 11:24:08,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:24:08,835 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 59.0) internal successors, (354), 6 states have internal predecessors, (354), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 487 [2024-12-02 11:24:08,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:08,837 INFO L225 Difference]: With dead ends: 2735 [2024-12-02 11:24:08,837 INFO L226 Difference]: Without dead ends: 1471 [2024-12-02 11:24:08,838 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:24:08,838 INFO L435 NwaCegarLoop]: 559 mSDtfsCounter, 702 mSDsluCounter, 1670 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 705 SdHoareTripleChecker+Valid, 2229 SdHoareTripleChecker+Invalid, 810 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:08,838 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [705 Valid, 2229 Invalid, 810 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:24:08,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1471 states. [2024-12-02 11:24:08,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1471 to 1458. [2024-12-02 11:24:08,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1458 states, 1444 states have (on average 1.3033240997229918) internal successors, (1882), 1444 states have internal predecessors, (1882), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:24:08,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1458 states to 1458 states and 1906 transitions. [2024-12-02 11:24:08,858 INFO L78 Accepts]: Start accepts. Automaton has 1458 states and 1906 transitions. Word has length 487 [2024-12-02 11:24:08,858 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:08,858 INFO L471 AbstractCegarLoop]: Abstraction has 1458 states and 1906 transitions. [2024-12-02 11:24:08,858 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 59.0) internal successors, (354), 6 states have internal predecessors, (354), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:08,858 INFO L276 IsEmpty]: Start isEmpty. Operand 1458 states and 1906 transitions. [2024-12-02 11:24:08,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 489 [2024-12-02 11:24:08,860 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:08,860 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:08,860 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable69 [2024-12-02 11:24:08,860 INFO L396 AbstractCegarLoop]: === Iteration 71 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:08,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:08,860 INFO L85 PathProgramCache]: Analyzing trace with hash 119022720, now seen corresponding path program 1 times [2024-12-02 11:24:08,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:08,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [263240305] [2024-12-02 11:24:08,861 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:08,861 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:09,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:10,832 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 124 trivial. 0 not checked. [2024-12-02 11:24:10,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:10,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [263240305] [2024-12-02 11:24:10,832 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [263240305] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:10,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:10,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2024-12-02 11:24:10,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407969773] [2024-12-02 11:24:10,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:10,833 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 11:24:10,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:10,833 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 11:24:10,833 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2024-12-02 11:24:10,833 INFO L87 Difference]: Start difference. First operand 1458 states and 1906 transitions. Second operand has 8 states, 8 states have (on average 50.0) internal successors, (400), 8 states have internal predecessors, (400), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:24:11,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:11,572 INFO L93 Difference]: Finished difference Result 3648 states and 4711 transitions. [2024-12-02 11:24:11,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-12-02 11:24:11,573 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 50.0) internal successors, (400), 8 states have internal predecessors, (400), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 488 [2024-12-02 11:24:11,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:11,575 INFO L225 Difference]: With dead ends: 3648 [2024-12-02 11:24:11,575 INFO L226 Difference]: Without dead ends: 2618 [2024-12-02 11:24:11,576 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2024-12-02 11:24:11,576 INFO L435 NwaCegarLoop]: 1104 mSDtfsCounter, 1292 mSDsluCounter, 4769 mSDsCounter, 0 mSdLazyCounter, 1381 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1295 SdHoareTripleChecker+Valid, 5873 SdHoareTripleChecker+Invalid, 1381 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1381 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:11,576 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1295 Valid, 5873 Invalid, 1381 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1381 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2024-12-02 11:24:11,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2618 states. [2024-12-02 11:24:11,626 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2618 to 2610. [2024-12-02 11:24:11,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2610 states, 2590 states have (on average 1.2934362934362935) internal successors, (3350), 2590 states have internal predecessors, (3350), 18 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 18 states have call predecessors, (18), 18 states have call successors, (18) [2024-12-02 11:24:11,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2610 states to 2610 states and 3386 transitions. [2024-12-02 11:24:11,630 INFO L78 Accepts]: Start accepts. Automaton has 2610 states and 3386 transitions. Word has length 488 [2024-12-02 11:24:11,630 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:11,630 INFO L471 AbstractCegarLoop]: Abstraction has 2610 states and 3386 transitions. [2024-12-02 11:24:11,630 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 50.0) internal successors, (400), 8 states have internal predecessors, (400), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:24:11,630 INFO L276 IsEmpty]: Start isEmpty. Operand 2610 states and 3386 transitions. [2024-12-02 11:24:11,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2024-12-02 11:24:11,633 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:11,633 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:11,633 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable70 [2024-12-02 11:24:11,633 INFO L396 AbstractCegarLoop]: === Iteration 72 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:11,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:11,634 INFO L85 PathProgramCache]: Analyzing trace with hash -450841632, now seen corresponding path program 1 times [2024-12-02 11:24:11,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:11,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480205782] [2024-12-02 11:24:11,634 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:11,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:12,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:13,620 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 31 proven. 0 refuted. 0 times theorem prover too weak. 150 trivial. 0 not checked. [2024-12-02 11:24:13,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:13,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480205782] [2024-12-02 11:24:13,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480205782] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:13,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:13,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:24:13,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271621001] [2024-12-02 11:24:13,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:13,621 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:13,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:13,622 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:13,622 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:13,622 INFO L87 Difference]: Start difference. First operand 2610 states and 3386 transitions. Second operand has 6 states, 6 states have (on average 62.833333333333336) internal successors, (377), 6 states have internal predecessors, (377), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 11:24:14,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:14,083 INFO L93 Difference]: Finished difference Result 2620 states and 3394 transitions. [2024-12-02 11:24:14,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:24:14,083 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 62.833333333333336) internal successors, (377), 6 states have internal predecessors, (377), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 490 [2024-12-02 11:24:14,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:14,085 INFO L225 Difference]: With dead ends: 2620 [2024-12-02 11:24:14,085 INFO L226 Difference]: Without dead ends: 1466 [2024-12-02 11:24:14,086 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:24:14,087 INFO L435 NwaCegarLoop]: 559 mSDtfsCounter, 681 mSDsluCounter, 1670 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 682 SdHoareTripleChecker+Valid, 2229 SdHoareTripleChecker+Invalid, 810 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:14,087 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [682 Valid, 2229 Invalid, 810 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 810 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:24:14,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1466 states. [2024-12-02 11:24:14,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1466 to 1462. [2024-12-02 11:24:14,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1462 states, 1448 states have (on average 1.3024861878453038) internal successors, (1886), 1448 states have internal predecessors, (1886), 12 states have call successors, (12), 1 states have call predecessors, (12), 1 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2024-12-02 11:24:14,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1462 states to 1462 states and 1910 transitions. [2024-12-02 11:24:14,121 INFO L78 Accepts]: Start accepts. Automaton has 1462 states and 1910 transitions. Word has length 490 [2024-12-02 11:24:14,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:14,121 INFO L471 AbstractCegarLoop]: Abstraction has 1462 states and 1910 transitions. [2024-12-02 11:24:14,121 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 62.833333333333336) internal successors, (377), 6 states have internal predecessors, (377), 2 states have call successors, (5), 1 states have call predecessors, (5), 1 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2024-12-02 11:24:14,121 INFO L276 IsEmpty]: Start isEmpty. Operand 1462 states and 1910 transitions. [2024-12-02 11:24:14,123 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2024-12-02 11:24:14,123 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:14,124 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:14,124 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable71 [2024-12-02 11:24:14,124 INFO L396 AbstractCegarLoop]: === Iteration 73 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:14,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:14,124 INFO L85 PathProgramCache]: Analyzing trace with hash -1627327692, now seen corresponding path program 1 times [2024-12-02 11:24:14,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:14,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822865839] [2024-12-02 11:24:14,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:14,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:15,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:17,003 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 4 proven. 117 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:17,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:17,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822865839] [2024-12-02 11:24:17,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822865839] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:24:17,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1196772470] [2024-12-02 11:24:17,003 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:17,003 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:17,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:24:17,004 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:24:17,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 11:24:19,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:19,155 INFO L256 TraceCheckSpWp]: Trace formula consists of 2976 conjuncts, 24 conjuncts are in the unsatisfiable core [2024-12-02 11:24:19,162 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:24:19,379 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 115 proven. 6 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:19,379 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:24:19,716 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 121 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:19,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1196772470] provided 1 perfect and 1 imperfect interpolant sequences [2024-12-02 11:24:19,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2024-12-02 11:24:19,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [11, 8] total 22 [2024-12-02 11:24:19,716 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1778353658] [2024-12-02 11:24:19,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:19,717 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2024-12-02 11:24:19,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:19,717 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2024-12-02 11:24:19,717 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=410, Unknown=0, NotChecked=0, Total=462 [2024-12-02 11:24:19,717 INFO L87 Difference]: Start difference. First operand 1462 states and 1910 transitions. Second operand has 7 states, 7 states have (on average 66.14285714285714) internal successors, (463), 7 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:19,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:19,849 INFO L93 Difference]: Finished difference Result 2540 states and 3327 transitions. [2024-12-02 11:24:19,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2024-12-02 11:24:19,849 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 66.14285714285714) internal successors, (463), 7 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 490 [2024-12-02 11:24:19,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:19,851 INFO L225 Difference]: With dead ends: 2540 [2024-12-02 11:24:19,851 INFO L226 Difference]: Without dead ends: 2000 [2024-12-02 11:24:19,851 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 992 GetRequests, 970 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=491, Unknown=0, NotChecked=0, Total=552 [2024-12-02 11:24:19,852 INFO L435 NwaCegarLoop]: 1342 mSDtfsCounter, 485 mSDsluCounter, 6098 mSDsCounter, 0 mSdLazyCounter, 74 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 485 SdHoareTripleChecker+Valid, 7440 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 74 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:19,852 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [485 Valid, 7440 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 74 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:24:19,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2000 states. [2024-12-02 11:24:19,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2000 to 1701. [2024-12-02 11:24:19,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1701 states, 1684 states have (on average 1.2885985748218527) internal successors, (2170), 1684 states have internal predecessors, (2170), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 11:24:19,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1701 states to 1701 states and 2200 transitions. [2024-12-02 11:24:19,876 INFO L78 Accepts]: Start accepts. Automaton has 1701 states and 2200 transitions. Word has length 490 [2024-12-02 11:24:19,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:19,876 INFO L471 AbstractCegarLoop]: Abstraction has 1701 states and 2200 transitions. [2024-12-02 11:24:19,877 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 66.14285714285714) internal successors, (463), 7 states have internal predecessors, (463), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:19,877 INFO L276 IsEmpty]: Start isEmpty. Operand 1701 states and 2200 transitions. [2024-12-02 11:24:19,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 491 [2024-12-02 11:24:19,879 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:19,879 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:19,895 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 11:24:20,079 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable72,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:20,079 INFO L396 AbstractCegarLoop]: === Iteration 74 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:20,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:20,080 INFO L85 PathProgramCache]: Analyzing trace with hash -1891471355, now seen corresponding path program 1 times [2024-12-02 11:24:20,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:20,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305246146] [2024-12-02 11:24:20,080 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:20,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:20,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:20,838 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 82 proven. 0 refuted. 0 times theorem prover too weak. 98 trivial. 0 not checked. [2024-12-02 11:24:20,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:20,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305246146] [2024-12-02 11:24:20,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305246146] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:20,838 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:20,838 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:24:20,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347448758] [2024-12-02 11:24:20,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:20,839 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:20,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:20,839 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:20,839 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:20,839 INFO L87 Difference]: Start difference. First operand 1701 states and 2200 transitions. Second operand has 6 states, 6 states have (on average 71.5) internal successors, (429), 6 states have internal predecessors, (429), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:20,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:20,878 INFO L93 Difference]: Finished difference Result 2953 states and 3820 transitions. [2024-12-02 11:24:20,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-12-02 11:24:20,879 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 71.5) internal successors, (429), 6 states have internal predecessors, (429), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 490 [2024-12-02 11:24:20,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:20,881 INFO L225 Difference]: With dead ends: 2953 [2024-12-02 11:24:20,881 INFO L226 Difference]: Without dead ends: 1773 [2024-12-02 11:24:20,882 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:20,882 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 16 mSDsluCounter, 2256 mSDsCounter, 0 mSdLazyCounter, 23 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 3012 SdHoareTripleChecker+Invalid, 25 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 23 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:20,882 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 3012 Invalid, 25 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 23 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:24:20,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1773 states. [2024-12-02 11:24:20,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1773 to 1773. [2024-12-02 11:24:20,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1773 states, 1756 states have (on average 1.29498861047836) internal successors, (2274), 1756 states have internal predecessors, (2274), 15 states have call successors, (15), 1 states have call predecessors, (15), 1 states have return successors, (15), 15 states have call predecessors, (15), 15 states have call successors, (15) [2024-12-02 11:24:20,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1773 states to 1773 states and 2304 transitions. [2024-12-02 11:24:20,906 INFO L78 Accepts]: Start accepts. Automaton has 1773 states and 2304 transitions. Word has length 490 [2024-12-02 11:24:20,906 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:20,906 INFO L471 AbstractCegarLoop]: Abstraction has 1773 states and 2304 transitions. [2024-12-02 11:24:20,906 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 71.5) internal successors, (429), 6 states have internal predecessors, (429), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:24:20,906 INFO L276 IsEmpty]: Start isEmpty. Operand 1773 states and 2304 transitions. [2024-12-02 11:24:20,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 492 [2024-12-02 11:24:20,908 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:20,908 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:20,908 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable73 [2024-12-02 11:24:20,908 INFO L396 AbstractCegarLoop]: === Iteration 75 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:20,908 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:20,909 INFO L85 PathProgramCache]: Analyzing trace with hash -2088324177, now seen corresponding path program 1 times [2024-12-02 11:24:20,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:20,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042462952] [2024-12-02 11:24:20,909 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:20,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:22,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:24,241 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 4 proven. 117 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:24,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:24,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042462952] [2024-12-02 11:24:24,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042462952] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:24:24,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [708691738] [2024-12-02 11:24:24,241 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:24,241 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:24,242 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:24:24,243 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:24:24,244 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2024-12-02 11:24:26,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:26,635 INFO L256 TraceCheckSpWp]: Trace formula consists of 2979 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 11:24:26,643 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:24:26,876 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 151 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2024-12-02 11:24:26,876 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:24:26,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [708691738] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:26,877 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:24:26,877 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [11] total 17 [2024-12-02 11:24:26,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1358858247] [2024-12-02 11:24:26,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:26,877 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2024-12-02 11:24:26,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:26,878 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2024-12-02 11:24:26,878 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2024-12-02 11:24:26,878 INFO L87 Difference]: Start difference. First operand 1773 states and 2304 transitions. Second operand has 8 states, 8 states have (on average 58.0) internal successors, (464), 8 states have internal predecessors, (464), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:27,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:27,488 INFO L93 Difference]: Finished difference Result 3959 states and 5166 transitions. [2024-12-02 11:24:27,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2024-12-02 11:24:27,489 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 58.0) internal successors, (464), 8 states have internal predecessors, (464), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 491 [2024-12-02 11:24:27,489 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:27,492 INFO L225 Difference]: With dead ends: 3959 [2024-12-02 11:24:27,492 INFO L226 Difference]: Without dead ends: 2905 [2024-12-02 11:24:27,494 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 503 GetRequests, 486 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2024-12-02 11:24:27,494 INFO L435 NwaCegarLoop]: 565 mSDtfsCounter, 1288 mSDsluCounter, 2669 mSDsCounter, 0 mSdLazyCounter, 1163 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1294 SdHoareTripleChecker+Valid, 3234 SdHoareTripleChecker+Invalid, 1163 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 1163 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:27,494 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1294 Valid, 3234 Invalid, 1163 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 1163 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 11:24:27,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2905 states. [2024-12-02 11:24:27,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2905 to 2367. [2024-12-02 11:24:27,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2367 states, 2341 states have (on average 1.2789406236651004) internal successors, (2994), 2341 states have internal predecessors, (2994), 24 states have call successors, (24), 1 states have call predecessors, (24), 1 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2024-12-02 11:24:27,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2367 states to 2367 states and 3042 transitions. [2024-12-02 11:24:27,554 INFO L78 Accepts]: Start accepts. Automaton has 2367 states and 3042 transitions. Word has length 491 [2024-12-02 11:24:27,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:27,554 INFO L471 AbstractCegarLoop]: Abstraction has 2367 states and 3042 transitions. [2024-12-02 11:24:27,555 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 58.0) internal successors, (464), 8 states have internal predecessors, (464), 2 states have call successors, (6), 2 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:27,555 INFO L276 IsEmpty]: Start isEmpty. Operand 2367 states and 3042 transitions. [2024-12-02 11:24:27,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 493 [2024-12-02 11:24:27,559 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:27,559 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:27,582 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2024-12-02 11:24:27,760 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable74,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:27,760 INFO L396 AbstractCegarLoop]: === Iteration 76 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:27,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:27,760 INFO L85 PathProgramCache]: Analyzing trace with hash 2097905472, now seen corresponding path program 1 times [2024-12-02 11:24:27,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:27,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627094223] [2024-12-02 11:24:27,760 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:27,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:29,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:31,028 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 142 trivial. 0 not checked. [2024-12-02 11:24:31,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:31,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627094223] [2024-12-02 11:24:31,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627094223] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:31,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:31,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2024-12-02 11:24:31,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [565950800] [2024-12-02 11:24:31,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:31,028 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 11:24:31,028 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:31,029 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 11:24:31,029 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2024-12-02 11:24:31,029 INFO L87 Difference]: Start difference. First operand 2367 states and 3042 transitions. Second operand has 10 states, 10 states have (on average 38.6) internal successors, (386), 10 states have internal predecessors, (386), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:24:31,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:31,480 INFO L93 Difference]: Finished difference Result 4534 states and 5809 transitions. [2024-12-02 11:24:31,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2024-12-02 11:24:31,480 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 38.6) internal successors, (386), 10 states have internal predecessors, (386), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 492 [2024-12-02 11:24:31,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:31,482 INFO L225 Difference]: With dead ends: 4534 [2024-12-02 11:24:31,482 INFO L226 Difference]: Without dead ends: 3115 [2024-12-02 11:24:31,484 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=155, Unknown=0, NotChecked=0, Total=210 [2024-12-02 11:24:31,484 INFO L435 NwaCegarLoop]: 1175 mSDtfsCounter, 2396 mSDsluCounter, 7039 mSDsCounter, 0 mSdLazyCounter, 506 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2401 SdHoareTripleChecker+Valid, 8214 SdHoareTripleChecker+Invalid, 514 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 506 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:31,484 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [2401 Valid, 8214 Invalid, 514 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 506 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2024-12-02 11:24:31,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3115 states. [2024-12-02 11:24:31,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3115 to 2455. [2024-12-02 11:24:31,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2455 states, 2425 states have (on average 1.28) internal successors, (3104), 2425 states have internal predecessors, (3104), 28 states have call successors, (28), 1 states have call predecessors, (28), 1 states have return successors, (28), 28 states have call predecessors, (28), 28 states have call successors, (28) [2024-12-02 11:24:31,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2455 states to 2455 states and 3160 transitions. [2024-12-02 11:24:31,523 INFO L78 Accepts]: Start accepts. Automaton has 2455 states and 3160 transitions. Word has length 492 [2024-12-02 11:24:31,523 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:31,523 INFO L471 AbstractCegarLoop]: Abstraction has 2455 states and 3160 transitions. [2024-12-02 11:24:31,523 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 38.6) internal successors, (386), 10 states have internal predecessors, (386), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:24:31,523 INFO L276 IsEmpty]: Start isEmpty. Operand 2455 states and 3160 transitions. [2024-12-02 11:24:31,525 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 493 [2024-12-02 11:24:31,525 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:31,525 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:31,526 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable75 [2024-12-02 11:24:31,526 INFO L396 AbstractCegarLoop]: === Iteration 77 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:31,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:31,526 INFO L85 PathProgramCache]: Analyzing trace with hash 2004667808, now seen corresponding path program 1 times [2024-12-02 11:24:31,526 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:31,526 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929684222] [2024-12-02 11:24:31,526 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:31,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:32,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:34,220 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 86 proven. 17 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2024-12-02 11:24:34,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:34,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [929684222] [2024-12-02 11:24:34,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [929684222] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:24:34,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1809581606] [2024-12-02 11:24:34,220 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:34,220 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:34,221 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:24:34,222 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:24:34,223 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 11:24:37,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:37,552 INFO L256 TraceCheckSpWp]: Trace formula consists of 2982 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 11:24:37,558 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:24:37,608 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 57 proven. 0 refuted. 0 times theorem prover too weak. 123 trivial. 0 not checked. [2024-12-02 11:24:37,608 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:24:37,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1809581606] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:37,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:24:37,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [9] total 13 [2024-12-02 11:24:37,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1526791344] [2024-12-02 11:24:37,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:37,609 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:37,609 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:37,609 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:37,609 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2024-12-02 11:24:37,609 INFO L87 Difference]: Start difference. First operand 2455 states and 3160 transitions. Second operand has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 11:24:37,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:37,706 INFO L93 Difference]: Finished difference Result 4491 states and 5748 transitions. [2024-12-02 11:24:37,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:24:37,706 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) Word has length 492 [2024-12-02 11:24:37,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:37,708 INFO L225 Difference]: With dead ends: 4491 [2024-12-02 11:24:37,708 INFO L226 Difference]: Without dead ends: 2455 [2024-12-02 11:24:37,709 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 489 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2024-12-02 11:24:37,710 INFO L435 NwaCegarLoop]: 756 mSDtfsCounter, 0 mSDsluCounter, 3005 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3761 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:37,710 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3761 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:24:37,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2455 states. [2024-12-02 11:24:37,742 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2455 to 2455. [2024-12-02 11:24:37,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2455 states, 2425 states have (on average 1.2758762886597939) internal successors, (3094), 2425 states have internal predecessors, (3094), 28 states have call successors, (28), 1 states have call predecessors, (28), 1 states have return successors, (28), 28 states have call predecessors, (28), 28 states have call successors, (28) [2024-12-02 11:24:37,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2455 states to 2455 states and 3150 transitions. [2024-12-02 11:24:37,746 INFO L78 Accepts]: Start accepts. Automaton has 2455 states and 3150 transitions. Word has length 492 [2024-12-02 11:24:37,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:37,746 INFO L471 AbstractCegarLoop]: Abstraction has 2455 states and 3150 transitions. [2024-12-02 11:24:37,746 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 75.4) internal successors, (377), 6 states have internal predecessors, (377), 3 states have call successors, (5), 2 states have call predecessors, (5), 3 states have return successors, (5), 2 states have call predecessors, (5), 3 states have call successors, (5) [2024-12-02 11:24:37,746 INFO L276 IsEmpty]: Start isEmpty. Operand 2455 states and 3150 transitions. [2024-12-02 11:24:37,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 493 [2024-12-02 11:24:37,749 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:37,749 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:37,775 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 11:24:37,949 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable76,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:37,950 INFO L396 AbstractCegarLoop]: === Iteration 78 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:37,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:37,950 INFO L85 PathProgramCache]: Analyzing trace with hash -1570240767, now seen corresponding path program 1 times [2024-12-02 11:24:37,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:37,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1990814363] [2024-12-02 11:24:37,950 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:37,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:38,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:39,776 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 122 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:39,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:39,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1990814363] [2024-12-02 11:24:39,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1990814363] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:39,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:39,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:24:39,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165259467] [2024-12-02 11:24:39,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:39,777 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:39,777 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:39,778 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:39,778 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:39,778 INFO L87 Difference]: Start difference. First operand 2455 states and 3150 transitions. Second operand has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:40,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:40,332 INFO L93 Difference]: Finished difference Result 3527 states and 4556 transitions. [2024-12-02 11:24:40,333 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:24:40,333 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 492 [2024-12-02 11:24:40,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:40,335 INFO L225 Difference]: With dead ends: 3527 [2024-12-02 11:24:40,335 INFO L226 Difference]: Without dead ends: 2712 [2024-12-02 11:24:40,335 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:24:40,336 INFO L435 NwaCegarLoop]: 565 mSDtfsCounter, 1282 mSDsluCounter, 1645 mSDsCounter, 0 mSdLazyCounter, 774 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1285 SdHoareTripleChecker+Valid, 2210 SdHoareTripleChecker+Invalid, 777 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 774 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:40,336 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1285 Valid, 2210 Invalid, 777 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 774 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2024-12-02 11:24:40,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2712 states. [2024-12-02 11:24:40,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2712 to 1992. [2024-12-02 11:24:40,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1992 states, 1966 states have (on average 1.2919633774160733) internal successors, (2540), 1966 states have internal predecessors, (2540), 24 states have call successors, (24), 1 states have call predecessors, (24), 1 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2024-12-02 11:24:40,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1992 states to 1992 states and 2588 transitions. [2024-12-02 11:24:40,367 INFO L78 Accepts]: Start accepts. Automaton has 1992 states and 2588 transitions. Word has length 492 [2024-12-02 11:24:40,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:40,367 INFO L471 AbstractCegarLoop]: Abstraction has 1992 states and 2588 transitions. [2024-12-02 11:24:40,367 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 77.5) internal successors, (465), 6 states have internal predecessors, (465), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:40,367 INFO L276 IsEmpty]: Start isEmpty. Operand 1992 states and 2588 transitions. [2024-12-02 11:24:40,370 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-12-02 11:24:40,370 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:40,370 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:40,370 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable77 [2024-12-02 11:24:40,370 INFO L396 AbstractCegarLoop]: === Iteration 79 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:40,370 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:40,370 INFO L85 PathProgramCache]: Analyzing trace with hash 1313996521, now seen corresponding path program 1 times [2024-12-02 11:24:40,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:40,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1118519691] [2024-12-02 11:24:40,371 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:40,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:40,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:41,146 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 42 proven. 0 refuted. 0 times theorem prover too weak. 140 trivial. 0 not checked. [2024-12-02 11:24:41,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:41,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1118519691] [2024-12-02 11:24:41,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1118519691] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:24:41,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:24:41,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:24:41,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676067937] [2024-12-02 11:24:41,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:24:41,147 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:24:41,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:24:41,148 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:24:41,148 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:41,148 INFO L87 Difference]: Start difference. First operand 1992 states and 2588 transitions. Second operand has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:41,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:24:41,566 INFO L93 Difference]: Finished difference Result 3427 states and 4418 transitions. [2024-12-02 11:24:41,566 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:24:41,567 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 493 [2024-12-02 11:24:41,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:24:41,568 INFO L225 Difference]: With dead ends: 3427 [2024-12-02 11:24:41,568 INFO L226 Difference]: Without dead ends: 2024 [2024-12-02 11:24:41,569 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:24:41,569 INFO L435 NwaCegarLoop]: 569 mSDtfsCounter, 716 mSDsluCounter, 1687 mSDsCounter, 0 mSdLazyCounter, 790 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 716 SdHoareTripleChecker+Valid, 2256 SdHoareTripleChecker+Invalid, 791 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 790 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:24:41,569 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [716 Valid, 2256 Invalid, 791 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 790 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:24:41,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2024 states. [2024-12-02 11:24:41,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2024 to 2008. [2024-12-02 11:24:41,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2008 states, 1982 states have (on average 1.289606458123108) internal successors, (2556), 1982 states have internal predecessors, (2556), 24 states have call successors, (24), 1 states have call predecessors, (24), 1 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2024-12-02 11:24:41,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2008 states to 2008 states and 2604 transitions. [2024-12-02 11:24:41,599 INFO L78 Accepts]: Start accepts. Automaton has 2008 states and 2604 transitions. Word has length 493 [2024-12-02 11:24:41,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:24:41,599 INFO L471 AbstractCegarLoop]: Abstraction has 2008 states and 2604 transitions. [2024-12-02 11:24:41,600 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 64.83333333333333) internal successors, (389), 6 states have internal predecessors, (389), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:24:41,600 INFO L276 IsEmpty]: Start isEmpty. Operand 2008 states and 2604 transitions. [2024-12-02 11:24:41,602 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 494 [2024-12-02 11:24:41,602 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:24:41,602 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:24:41,602 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable78 [2024-12-02 11:24:41,602 INFO L396 AbstractCegarLoop]: === Iteration 80 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:24:41,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:24:41,602 INFO L85 PathProgramCache]: Analyzing trace with hash 43422583, now seen corresponding path program 1 times [2024-12-02 11:24:41,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:24:41,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080503090] [2024-12-02 11:24:41,602 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:41,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:24:43,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:44,995 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 4 proven. 117 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:44,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:24:44,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080503090] [2024-12-02 11:24:44,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080503090] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:24:44,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1562477200] [2024-12-02 11:24:44,996 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:24:44,996 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:24:44,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:24:44,997 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:24:44,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2024-12-02 11:24:47,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:24:47,643 INFO L256 TraceCheckSpWp]: Trace formula consists of 2985 conjuncts, 144 conjuncts are in the unsatisfiable core [2024-12-02 11:24:47,657 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:24:51,779 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 82 proven. 39 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:24:51,779 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:25:03,470 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 80 proven. 41 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:25:03,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1562477200] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:25:03,470 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:25:03,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 26, 29] total 62 [2024-12-02 11:25:03,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862171308] [2024-12-02 11:25:03,470 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:25:03,471 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 62 states [2024-12-02 11:25:03,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:25:03,472 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2024-12-02 11:25:03,472 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=3385, Unknown=0, NotChecked=0, Total=3782 [2024-12-02 11:25:03,472 INFO L87 Difference]: Start difference. First operand 2008 states and 2604 transitions. Second operand has 62 states, 62 states have (on average 21.0) internal successors, (1302), 62 states have internal predecessors, (1302), 10 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-12-02 11:25:50,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:25:50,721 INFO L93 Difference]: Finished difference Result 17546 states and 22666 transitions. [2024-12-02 11:25:50,721 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 261 states. [2024-12-02 11:25:50,721 INFO L78 Accepts]: Start accepts. Automaton has has 62 states, 62 states have (on average 21.0) internal successors, (1302), 62 states have internal predecessors, (1302), 10 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) Word has length 493 [2024-12-02 11:25:50,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:25:50,729 INFO L225 Difference]: With dead ends: 17546 [2024-12-02 11:25:50,729 INFO L226 Difference]: Without dead ends: 16119 [2024-12-02 11:25:50,735 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1244 GetRequests, 935 SyntacticMatches, 0 SemanticMatches, 309 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33847 ImplicationChecksByTransitivity, 16.4s TimeCoverageRelationStatistics Valid=11473, Invalid=84937, Unknown=0, NotChecked=0, Total=96410 [2024-12-02 11:25:50,736 INFO L435 NwaCegarLoop]: 2846 mSDtfsCounter, 25018 mSDsluCounter, 92324 mSDsCounter, 0 mSdLazyCounter, 54250 mSolverCounterSat, 142 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 26.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25020 SdHoareTripleChecker+Valid, 95170 SdHoareTripleChecker+Invalid, 54392 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.3s SdHoareTripleChecker+Time, 142 IncrementalHoareTripleChecker+Valid, 54250 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 29.7s IncrementalHoareTripleChecker+Time [2024-12-02 11:25:50,736 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [25020 Valid, 95170 Invalid, 54392 Unknown, 0 Unchecked, 0.3s Time], IncrementalHoareTripleChecker [142 Valid, 54250 Invalid, 0 Unknown, 0 Unchecked, 29.7s Time] [2024-12-02 11:25:50,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16119 states. [2024-12-02 11:25:50,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16119 to 5396. [2024-12-02 11:25:50,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5396 states, 5330 states have (on average 1.2928705440900563) internal successors, (6891), 5330 states have internal predecessors, (6891), 64 states have call successors, (64), 1 states have call predecessors, (64), 1 states have return successors, (64), 64 states have call predecessors, (64), 64 states have call successors, (64) [2024-12-02 11:25:50,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5396 states to 5396 states and 7019 transitions. [2024-12-02 11:25:50,850 INFO L78 Accepts]: Start accepts. Automaton has 5396 states and 7019 transitions. Word has length 493 [2024-12-02 11:25:50,851 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:25:50,851 INFO L471 AbstractCegarLoop]: Abstraction has 5396 states and 7019 transitions. [2024-12-02 11:25:50,851 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 62 states, 62 states have (on average 21.0) internal successors, (1302), 62 states have internal predecessors, (1302), 10 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 10 states have call predecessors, (18), 10 states have call successors, (18) [2024-12-02 11:25:50,851 INFO L276 IsEmpty]: Start isEmpty. Operand 5396 states and 7019 transitions. [2024-12-02 11:25:50,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 495 [2024-12-02 11:25:50,856 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:25:50,857 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:25:50,881 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2024-12-02 11:25:51,057 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable79 [2024-12-02 11:25:51,057 INFO L396 AbstractCegarLoop]: === Iteration 81 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:25:51,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:25:51,058 INFO L85 PathProgramCache]: Analyzing trace with hash -50932220, now seen corresponding path program 1 times [2024-12-02 11:25:51,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:25:51,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464622840] [2024-12-02 11:25:51,058 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:25:51,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:25:52,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:25:53,642 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 43 proven. 0 refuted. 0 times theorem prover too weak. 137 trivial. 0 not checked. [2024-12-02 11:25:53,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:25:53,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [464622840] [2024-12-02 11:25:53,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [464622840] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:25:53,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:25:53,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 11:25:53,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [654094228] [2024-12-02 11:25:53,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:25:53,643 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 11:25:53,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:25:53,644 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 11:25:53,644 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:25:53,644 INFO L87 Difference]: Start difference. First operand 5396 states and 7019 transitions. Second operand has 9 states, 9 states have (on average 43.888888888888886) internal successors, (395), 9 states have internal predecessors, (395), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:25:54,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:25:54,969 INFO L93 Difference]: Finished difference Result 14127 states and 18241 transitions. [2024-12-02 11:25:54,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-12-02 11:25:54,969 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 43.888888888888886) internal successors, (395), 9 states have internal predecessors, (395), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 494 [2024-12-02 11:25:54,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:25:54,974 INFO L225 Difference]: With dead ends: 14127 [2024-12-02 11:25:54,974 INFO L226 Difference]: Without dead ends: 9754 [2024-12-02 11:25:54,977 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=58, Invalid=152, Unknown=0, NotChecked=0, Total=210 [2024-12-02 11:25:54,978 INFO L435 NwaCegarLoop]: 897 mSDtfsCounter, 1904 mSDsluCounter, 4092 mSDsCounter, 0 mSdLazyCounter, 2011 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1905 SdHoareTripleChecker+Valid, 4989 SdHoareTripleChecker+Invalid, 2016 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 2011 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:25:54,978 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1905 Valid, 4989 Invalid, 2016 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 2011 Invalid, 0 Unknown, 0 Unchecked, 1.1s Time] [2024-12-02 11:25:54,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9754 states. [2024-12-02 11:25:55,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9754 to 6240. [2024-12-02 11:25:55,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6240 states, 6150 states have (on average 1.2973983739837398) internal successors, (7979), 6150 states have internal predecessors, (7979), 88 states have call successors, (88), 1 states have call predecessors, (88), 1 states have return successors, (88), 88 states have call predecessors, (88), 88 states have call successors, (88) [2024-12-02 11:25:55,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6240 states to 6240 states and 8155 transitions. [2024-12-02 11:25:55,098 INFO L78 Accepts]: Start accepts. Automaton has 6240 states and 8155 transitions. Word has length 494 [2024-12-02 11:25:55,098 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:25:55,098 INFO L471 AbstractCegarLoop]: Abstraction has 6240 states and 8155 transitions. [2024-12-02 11:25:55,098 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 43.888888888888886) internal successors, (395), 9 states have internal predecessors, (395), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:25:55,098 INFO L276 IsEmpty]: Start isEmpty. Operand 6240 states and 8155 transitions. [2024-12-02 11:25:55,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 495 [2024-12-02 11:25:55,102 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:25:55,102 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:25:55,102 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable80 [2024-12-02 11:25:55,102 INFO L396 AbstractCegarLoop]: === Iteration 82 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:25:55,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:25:55,103 INFO L85 PathProgramCache]: Analyzing trace with hash 867682820, now seen corresponding path program 1 times [2024-12-02 11:25:55,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:25:55,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2043089657] [2024-12-02 11:25:55,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:25:55,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:25:57,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:25:59,607 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 85 proven. 35 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:25:59,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:25:59,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2043089657] [2024-12-02 11:25:59,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2043089657] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:25:59,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [915719873] [2024-12-02 11:25:59,608 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:25:59,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:25:59,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:25:59,609 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:25:59,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2024-12-02 11:26:03,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:26:03,316 INFO L256 TraceCheckSpWp]: Trace formula consists of 2986 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 11:26:03,322 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:26:03,365 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 75 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2024-12-02 11:26:03,366 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:26:03,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [915719873] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:26:03,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:26:03,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [12] total 16 [2024-12-02 11:26:03,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875591977] [2024-12-02 11:26:03,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:26:03,366 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:26:03,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:26:03,367 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:26:03,367 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=197, Unknown=0, NotChecked=0, Total=240 [2024-12-02 11:26:03,367 INFO L87 Difference]: Start difference. First operand 6240 states and 8155 transitions. Second operand has 6 states, 5 states have (on average 78.4) internal successors, (392), 6 states have internal predecessors, (392), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:26:03,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:26:03,517 INFO L93 Difference]: Finished difference Result 11553 states and 15074 transitions. [2024-12-02 11:26:03,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:26:03,517 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 78.4) internal successors, (392), 6 states have internal predecessors, (392), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 494 [2024-12-02 11:26:03,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:26:03,522 INFO L225 Difference]: With dead ends: 11553 [2024-12-02 11:26:03,522 INFO L226 Difference]: Without dead ends: 6240 [2024-12-02 11:26:03,526 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 506 GetRequests, 492 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=197, Unknown=0, NotChecked=0, Total=240 [2024-12-02 11:26:03,526 INFO L435 NwaCegarLoop]: 755 mSDtfsCounter, 0 mSDsluCounter, 3001 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3756 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:26:03,526 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3756 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:26:03,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6240 states. [2024-12-02 11:26:03,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6240 to 6240. [2024-12-02 11:26:03,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6240 states, 6150 states have (on average 1.2895934959349593) internal successors, (7931), 6150 states have internal predecessors, (7931), 88 states have call successors, (88), 1 states have call predecessors, (88), 1 states have return successors, (88), 88 states have call predecessors, (88), 88 states have call successors, (88) [2024-12-02 11:26:03,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6240 states to 6240 states and 8107 transitions. [2024-12-02 11:26:03,637 INFO L78 Accepts]: Start accepts. Automaton has 6240 states and 8107 transitions. Word has length 494 [2024-12-02 11:26:03,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:26:03,637 INFO L471 AbstractCegarLoop]: Abstraction has 6240 states and 8107 transitions. [2024-12-02 11:26:03,638 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 78.4) internal successors, (392), 6 states have internal predecessors, (392), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:26:03,638 INFO L276 IsEmpty]: Start isEmpty. Operand 6240 states and 8107 transitions. [2024-12-02 11:26:03,642 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-12-02 11:26:03,642 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:26:03,642 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:26:03,663 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2024-12-02 11:26:03,843 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable81,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:26:03,843 INFO L396 AbstractCegarLoop]: === Iteration 83 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:26:03,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:26:03,843 INFO L85 PathProgramCache]: Analyzing trace with hash 1722128552, now seen corresponding path program 1 times [2024-12-02 11:26:03,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:26:03,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144601419] [2024-12-02 11:26:03,843 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:26:03,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:26:05,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:26:06,641 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 121 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:26:06,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:26:06,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [144601419] [2024-12-02 11:26:06,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [144601419] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:26:06,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:26:06,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2024-12-02 11:26:06,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953951071] [2024-12-02 11:26:06,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:26:06,642 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2024-12-02 11:26:06,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:26:06,643 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2024-12-02 11:26:06,643 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:26:06,643 INFO L87 Difference]: Start difference. First operand 6240 states and 8107 transitions. Second operand has 9 states, 9 states have (on average 52.111111111111114) internal successors, (469), 9 states have internal predecessors, (469), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:26:07,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:26:07,815 INFO L93 Difference]: Finished difference Result 14047 states and 18136 transitions. [2024-12-02 11:26:07,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2024-12-02 11:26:07,815 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 52.111111111111114) internal successors, (469), 9 states have internal predecessors, (469), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) Word has length 496 [2024-12-02 11:26:07,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:26:07,821 INFO L225 Difference]: With dead ends: 14047 [2024-12-02 11:26:07,822 INFO L226 Difference]: Without dead ends: 9754 [2024-12-02 11:26:07,825 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2024-12-02 11:26:07,825 INFO L435 NwaCegarLoop]: 898 mSDtfsCounter, 1844 mSDsluCounter, 4095 mSDsCounter, 0 mSdLazyCounter, 1932 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1845 SdHoareTripleChecker+Valid, 4993 SdHoareTripleChecker+Invalid, 1936 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 1932 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:26:07,825 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [1845 Valid, 4993 Invalid, 1936 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 1932 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2024-12-02 11:26:07,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9754 states. [2024-12-02 11:26:07,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9754 to 8259. [2024-12-02 11:26:07,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8259 states, 8169 states have (on average 1.2650263190108948) internal successors, (10334), 8169 states have internal predecessors, (10334), 88 states have call successors, (88), 1 states have call predecessors, (88), 1 states have return successors, (88), 88 states have call predecessors, (88), 88 states have call successors, (88) [2024-12-02 11:26:07,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8259 states to 8259 states and 10510 transitions. [2024-12-02 11:26:07,949 INFO L78 Accepts]: Start accepts. Automaton has 8259 states and 10510 transitions. Word has length 496 [2024-12-02 11:26:07,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:26:07,949 INFO L471 AbstractCegarLoop]: Abstraction has 8259 states and 10510 transitions. [2024-12-02 11:26:07,949 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 52.111111111111114) internal successors, (469), 9 states have internal predecessors, (469), 3 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 3 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:26:07,949 INFO L276 IsEmpty]: Start isEmpty. Operand 8259 states and 10510 transitions. [2024-12-02 11:26:07,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-12-02 11:26:07,954 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:26:07,954 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:26:07,955 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable82 [2024-12-02 11:26:07,955 INFO L396 AbstractCegarLoop]: === Iteration 84 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:26:07,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:26:07,955 INFO L85 PathProgramCache]: Analyzing trace with hash -251285079, now seen corresponding path program 1 times [2024-12-02 11:26:07,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:26:07,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088577952] [2024-12-02 11:26:07,955 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:26:07,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:26:10,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:26:12,932 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 85 proven. 34 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:26:12,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:26:12,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088577952] [2024-12-02 11:26:12,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088577952] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:26:12,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [926746999] [2024-12-02 11:26:12,932 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:26:12,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:26:12,932 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:26:12,934 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:26:12,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2024-12-02 11:26:16,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:26:16,711 INFO L256 TraceCheckSpWp]: Trace formula consists of 2992 conjuncts, 121 conjuncts are in the unsatisfiable core [2024-12-02 11:26:16,724 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:26:18,484 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 99 proven. 35 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-12-02 11:26:18,484 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:26:20,516 INFO L134 CoverageAnalysis]: Checked inductivity of 179 backedges. 109 proven. 25 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-12-02 11:26:20,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [926746999] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:26:20,516 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:26:20,516 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 24, 19] total 50 [2024-12-02 11:26:20,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137924555] [2024-12-02 11:26:20,516 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:26:20,517 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2024-12-02 11:26:20,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:26:20,518 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2024-12-02 11:26:20,519 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=2179, Unknown=0, NotChecked=0, Total=2450 [2024-12-02 11:26:20,519 INFO L87 Difference]: Start difference. First operand 8259 states and 10510 transitions. Second operand has 50 states, 47 states have (on average 26.574468085106382) internal successors, (1249), 50 states have internal predecessors, (1249), 9 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 8 states have call predecessors, (18), 9 states have call successors, (18) [2024-12-02 11:26:58,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:26:58,628 INFO L93 Difference]: Finished difference Result 162767 states and 207836 transitions. [2024-12-02 11:26:58,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 333 states. [2024-12-02 11:26:58,629 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 47 states have (on average 26.574468085106382) internal successors, (1249), 50 states have internal predecessors, (1249), 9 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 8 states have call predecessors, (18), 9 states have call successors, (18) Word has length 496 [2024-12-02 11:26:58,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:26:58,719 INFO L225 Difference]: With dead ends: 162767 [2024-12-02 11:26:58,719 INFO L226 Difference]: Without dead ends: 155579 [2024-12-02 11:26:58,739 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1317 GetRequests, 957 SyntacticMatches, 0 SemanticMatches, 360 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 51788 ImplicationChecksByTransitivity, 8.8s TimeCoverageRelationStatistics Valid=7289, Invalid=123393, Unknown=0, NotChecked=0, Total=130682 [2024-12-02 11:26:58,739 INFO L435 NwaCegarLoop]: 3325 mSDtfsCounter, 54442 mSDsluCounter, 98402 mSDsCounter, 0 mSdLazyCounter, 58121 mSolverCounterSat, 79 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 20.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 54453 SdHoareTripleChecker+Valid, 101727 SdHoareTripleChecker+Invalid, 58200 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.3s SdHoareTripleChecker+Time, 79 IncrementalHoareTripleChecker+Valid, 58121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 24.3s IncrementalHoareTripleChecker+Time [2024-12-02 11:26:58,739 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [54453 Valid, 101727 Invalid, 58200 Unknown, 0 Unchecked, 0.3s Time], IncrementalHoareTripleChecker [79 Valid, 58121 Invalid, 0 Unknown, 0 Unchecked, 24.3s Time] [2024-12-02 11:26:58,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155579 states. [2024-12-02 11:26:59,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155579 to 15663. [2024-12-02 11:26:59,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15663 states, 15329 states have (on average 1.2657055254745906) internal successors, (19402), 15329 states have internal predecessors, (19402), 332 states have call successors, (332), 1 states have call predecessors, (332), 1 states have return successors, (332), 332 states have call predecessors, (332), 332 states have call successors, (332) [2024-12-02 11:26:59,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15663 states to 15663 states and 20066 transitions. [2024-12-02 11:26:59,654 INFO L78 Accepts]: Start accepts. Automaton has 15663 states and 20066 transitions. Word has length 496 [2024-12-02 11:26:59,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:26:59,655 INFO L471 AbstractCegarLoop]: Abstraction has 15663 states and 20066 transitions. [2024-12-02 11:26:59,655 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 47 states have (on average 26.574468085106382) internal successors, (1249), 50 states have internal predecessors, (1249), 9 states have call successors, (18), 1 states have call predecessors, (18), 2 states have return successors, (18), 8 states have call predecessors, (18), 9 states have call successors, (18) [2024-12-02 11:26:59,655 INFO L276 IsEmpty]: Start isEmpty. Operand 15663 states and 20066 transitions. [2024-12-02 11:26:59,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-12-02 11:26:59,666 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:26:59,666 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:26:59,688 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2024-12-02 11:26:59,867 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable83 [2024-12-02 11:26:59,867 INFO L396 AbstractCegarLoop]: === Iteration 85 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:26:59,867 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:26:59,867 INFO L85 PathProgramCache]: Analyzing trace with hash -69450588, now seen corresponding path program 1 times [2024-12-02 11:26:59,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:26:59,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893926515] [2024-12-02 11:26:59,868 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:26:59,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:27:02,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:04,620 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 2 proven. 121 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:04,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:27:04,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893926515] [2024-12-02 11:27:04,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893926515] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:27:04,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1351473249] [2024-12-02 11:27:04,620 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:04,620 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:27:04,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:27:04,621 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:27:04,622 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2024-12-02 11:27:08,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:08,462 INFO L256 TraceCheckSpWp]: Trace formula consists of 2992 conjuncts, 106 conjuncts are in the unsatisfiable core [2024-12-02 11:27:08,471 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:27:10,107 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 155 proven. 4 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2024-12-02 11:27:10,107 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:27:12,463 INFO L134 CoverageAnalysis]: Checked inductivity of 183 backedges. 85 proven. 38 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:12,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1351473249] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:27:12,463 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:27:12,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 17, 14] total 40 [2024-12-02 11:27:12,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273905103] [2024-12-02 11:27:12,464 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:27:12,464 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 40 states [2024-12-02 11:27:12,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:27:12,465 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2024-12-02 11:27:12,465 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=177, Invalid=1383, Unknown=0, NotChecked=0, Total=1560 [2024-12-02 11:27:12,465 INFO L87 Difference]: Start difference. First operand 15663 states and 20066 transitions. Second operand has 40 states, 40 states have (on average 32.75) internal successors, (1310), 40 states have internal predecessors, (1310), 7 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) [2024-12-02 11:27:20,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:27:20,191 INFO L93 Difference]: Finished difference Result 53191 states and 68053 transitions. [2024-12-02 11:27:20,192 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2024-12-02 11:27:20,192 INFO L78 Accepts]: Start accepts. Automaton has has 40 states, 40 states have (on average 32.75) internal successors, (1310), 40 states have internal predecessors, (1310), 7 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) Word has length 496 [2024-12-02 11:27:20,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:27:20,218 INFO L225 Difference]: With dead ends: 53191 [2024-12-02 11:27:20,218 INFO L226 Difference]: Without dead ends: 41234 [2024-12-02 11:27:20,224 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1056 GetRequests, 967 SyntacticMatches, 1 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1839 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=991, Invalid=7019, Unknown=0, NotChecked=0, Total=8010 [2024-12-02 11:27:20,224 INFO L435 NwaCegarLoop]: 1084 mSDtfsCounter, 4786 mSDsluCounter, 25401 mSDsCounter, 0 mSdLazyCounter, 12078 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 4.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 4795 SdHoareTripleChecker+Valid, 26485 SdHoareTripleChecker+Invalid, 12099 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 12078 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 5.2s IncrementalHoareTripleChecker+Time [2024-12-02 11:27:20,225 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [4795 Valid, 26485 Invalid, 12099 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [21 Valid, 12078 Invalid, 0 Unknown, 0 Unchecked, 5.2s Time] [2024-12-02 11:27:20,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41234 states. [2024-12-02 11:27:21,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41234 to 32451. [2024-12-02 11:27:21,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32451 states, 31689 states have (on average 1.2602164789043517) internal successors, (39935), 31689 states have internal predecessors, (39935), 760 states have call successors, (760), 1 states have call predecessors, (760), 1 states have return successors, (760), 760 states have call predecessors, (760), 760 states have call successors, (760) [2024-12-02 11:27:21,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32451 states to 32451 states and 41455 transitions. [2024-12-02 11:27:21,193 INFO L78 Accepts]: Start accepts. Automaton has 32451 states and 41455 transitions. Word has length 496 [2024-12-02 11:27:21,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:27:21,193 INFO L471 AbstractCegarLoop]: Abstraction has 32451 states and 41455 transitions. [2024-12-02 11:27:21,194 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 40 states, 40 states have (on average 32.75) internal successors, (1310), 40 states have internal predecessors, (1310), 7 states have call successors, (18), 2 states have call predecessors, (18), 2 states have return successors, (18), 7 states have call predecessors, (18), 7 states have call successors, (18) [2024-12-02 11:27:21,194 INFO L276 IsEmpty]: Start isEmpty. Operand 32451 states and 41455 transitions. [2024-12-02 11:27:21,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 497 [2024-12-02 11:27:21,281 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:27:21,281 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:27:21,300 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2024-12-02 11:27:21,481 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable84,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:27:21,482 INFO L396 AbstractCegarLoop]: === Iteration 86 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:27:21,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:27:21,482 INFO L85 PathProgramCache]: Analyzing trace with hash -385011260, now seen corresponding path program 1 times [2024-12-02 11:27:21,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:27:21,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355737524] [2024-12-02 11:27:21,482 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:21,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:27:21,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:22,260 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 84 proven. 0 refuted. 0 times theorem prover too weak. 96 trivial. 0 not checked. [2024-12-02 11:27:22,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:27:22,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355737524] [2024-12-02 11:27:22,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355737524] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:27:22,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:27:22,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-12-02 11:27:22,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741388297] [2024-12-02 11:27:22,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:27:22,261 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2024-12-02 11:27:22,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:27:22,261 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-12-02 11:27:22,261 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:27:22,262 INFO L87 Difference]: Start difference. First operand 32451 states and 41455 transitions. Second operand has 5 states, 5 states have (on average 87.8) internal successors, (439), 5 states have internal predecessors, (439), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:27:23,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:27:23,060 INFO L93 Difference]: Finished difference Result 60135 states and 76805 transitions. [2024-12-02 11:27:23,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:27:23,061 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 87.8) internal successors, (439), 5 states have internal predecessors, (439), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 496 [2024-12-02 11:27:23,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:27:23,096 INFO L225 Difference]: With dead ends: 60135 [2024-12-02 11:27:23,096 INFO L226 Difference]: Without dead ends: 31419 [2024-12-02 11:27:23,112 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2024-12-02 11:27:23,112 INFO L435 NwaCegarLoop]: 755 mSDtfsCounter, 0 mSDsluCounter, 1500 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 2255 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:27:23,112 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 2255 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:27:23,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31419 states. [2024-12-02 11:27:24,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31419 to 31419. [2024-12-02 11:27:24,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31419 states, 30657 states have (on average 1.2565808787552597) internal successors, (38523), 30657 states have internal predecessors, (38523), 760 states have call successors, (760), 1 states have call predecessors, (760), 1 states have return successors, (760), 760 states have call predecessors, (760), 760 states have call successors, (760) [2024-12-02 11:27:24,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31419 states to 31419 states and 40043 transitions. [2024-12-02 11:27:24,416 INFO L78 Accepts]: Start accepts. Automaton has 31419 states and 40043 transitions. Word has length 496 [2024-12-02 11:27:24,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:27:24,416 INFO L471 AbstractCegarLoop]: Abstraction has 31419 states and 40043 transitions. [2024-12-02 11:27:24,416 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 87.8) internal successors, (439), 5 states have internal predecessors, (439), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:27:24,416 INFO L276 IsEmpty]: Start isEmpty. Operand 31419 states and 40043 transitions. [2024-12-02 11:27:24,465 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2024-12-02 11:27:24,465 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:27:24,466 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:27:24,466 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable85 [2024-12-02 11:27:24,466 INFO L396 AbstractCegarLoop]: === Iteration 87 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:27:24,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:27:24,467 INFO L85 PathProgramCache]: Analyzing trace with hash 509746003, now seen corresponding path program 1 times [2024-12-02 11:27:24,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:27:24,467 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182428046] [2024-12-02 11:27:24,467 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:24,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:27:24,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:25,904 INFO L134 CoverageAnalysis]: Checked inductivity of 178 backedges. 118 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:25,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:27:25,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182428046] [2024-12-02 11:27:25,904 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182428046] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:27:25,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-12-02 11:27:25,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2024-12-02 11:27:25,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035605205] [2024-12-02 11:27:25,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:27:25,905 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:27:25,905 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:27:25,905 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:27:25,905 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2024-12-02 11:27:25,905 INFO L87 Difference]: Start difference. First operand 31419 states and 40043 transitions. Second operand has 6 states, 6 states have (on average 78.33333333333333) internal successors, (470), 6 states have internal predecessors, (470), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:27:26,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:27:26,949 INFO L93 Difference]: Finished difference Result 57189 states and 72904 transitions. [2024-12-02 11:27:26,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:27:26,950 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 78.33333333333333) internal successors, (470), 6 states have internal predecessors, (470), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) Word has length 497 [2024-12-02 11:27:26,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:27:26,982 INFO L225 Difference]: With dead ends: 57189 [2024-12-02 11:27:26,983 INFO L226 Difference]: Without dead ends: 39592 [2024-12-02 11:27:27,000 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2024-12-02 11:27:27,000 INFO L435 NwaCegarLoop]: 1312 mSDtfsCounter, 537 mSDsluCounter, 4677 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 537 SdHoareTripleChecker+Valid, 5989 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:27:27,001 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [537 Valid, 5989 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:27:27,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39592 states. [2024-12-02 11:27:28,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39592 to 32355. [2024-12-02 11:27:28,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32355 states, 31509 states have (on average 1.2539591862642419) internal successors, (39511), 31509 states have internal predecessors, (39511), 844 states have call successors, (844), 1 states have call predecessors, (844), 1 states have return successors, (844), 844 states have call predecessors, (844), 844 states have call successors, (844) [2024-12-02 11:27:28,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32355 states to 32355 states and 41199 transitions. [2024-12-02 11:27:28,096 INFO L78 Accepts]: Start accepts. Automaton has 32355 states and 41199 transitions. Word has length 497 [2024-12-02 11:27:28,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:27:28,096 INFO L471 AbstractCegarLoop]: Abstraction has 32355 states and 41199 transitions. [2024-12-02 11:27:28,096 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 78.33333333333333) internal successors, (470), 6 states have internal predecessors, (470), 2 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 2 states have call predecessors, (6), 2 states have call successors, (6) [2024-12-02 11:27:28,096 INFO L276 IsEmpty]: Start isEmpty. Operand 32355 states and 41199 transitions. [2024-12-02 11:27:28,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 498 [2024-12-02 11:27:28,121 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:27:28,122 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:27:28,122 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable86 [2024-12-02 11:27:28,122 INFO L396 AbstractCegarLoop]: === Iteration 88 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:27:28,122 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:27:28,122 INFO L85 PathProgramCache]: Analyzing trace with hash -971369405, now seen corresponding path program 1 times [2024-12-02 11:27:28,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:27:28,123 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988940926] [2024-12-02 11:27:28,123 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:28,123 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:27:30,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:33,291 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 39 proven. 82 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:33,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:27:33,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988940926] [2024-12-02 11:27:33,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988940926] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:27:33,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [873316263] [2024-12-02 11:27:33,292 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:33,292 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:27:33,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:27:33,294 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:27:33,294 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2024-12-02 11:27:36,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:36,885 INFO L256 TraceCheckSpWp]: Trace formula consists of 2993 conjuncts, 11 conjuncts are in the unsatisfiable core [2024-12-02 11:27:36,890 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:27:36,936 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 156 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2024-12-02 11:27:36,936 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:27:36,936 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [873316263] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:27:36,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:27:36,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [12] total 16 [2024-12-02 11:27:36,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [877891160] [2024-12-02 11:27:36,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:27:36,937 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2024-12-02 11:27:36,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:27:36,938 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2024-12-02 11:27:36,938 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2024-12-02 11:27:36,938 INFO L87 Difference]: Start difference. First operand 32355 states and 41199 transitions. Second operand has 6 states, 5 states have (on average 94.4) internal successors, (472), 6 states have internal predecessors, (472), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:27:37,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:27:37,830 INFO L93 Difference]: Finished difference Result 60042 states and 76417 transitions. [2024-12-02 11:27:37,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2024-12-02 11:27:37,830 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 5 states have (on average 94.4) internal successors, (472), 6 states have internal predecessors, (472), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 497 [2024-12-02 11:27:37,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:27:37,856 INFO L225 Difference]: With dead ends: 60042 [2024-12-02 11:27:37,856 INFO L226 Difference]: Without dead ends: 32355 [2024-12-02 11:27:37,875 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 509 GetRequests, 495 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=206, Unknown=0, NotChecked=0, Total=240 [2024-12-02 11:27:37,876 INFO L435 NwaCegarLoop]: 754 mSDtfsCounter, 0 mSDsluCounter, 2997 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 3751 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2024-12-02 11:27:37,876 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 3751 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2024-12-02 11:27:37,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32355 states. [2024-12-02 11:27:38,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32355 to 32355. [2024-12-02 11:27:38,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32355 states, 31509 states have (on average 1.250975911644292) internal successors, (39417), 31509 states have internal predecessors, (39417), 844 states have call successors, (844), 1 states have call predecessors, (844), 1 states have return successors, (844), 844 states have call predecessors, (844), 844 states have call successors, (844) [2024-12-02 11:27:38,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32355 states to 32355 states and 41105 transitions. [2024-12-02 11:27:38,901 INFO L78 Accepts]: Start accepts. Automaton has 32355 states and 41105 transitions. Word has length 497 [2024-12-02 11:27:38,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:27:38,901 INFO L471 AbstractCegarLoop]: Abstraction has 32355 states and 41105 transitions. [2024-12-02 11:27:38,901 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 5 states have (on average 94.4) internal successors, (472), 6 states have internal predecessors, (472), 3 states have call successors, (6), 2 states have call predecessors, (6), 3 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:27:38,902 INFO L276 IsEmpty]: Start isEmpty. Operand 32355 states and 41105 transitions. [2024-12-02 11:27:38,926 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 499 [2024-12-02 11:27:38,926 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:27:38,926 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:27:38,947 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2024-12-02 11:27:39,126 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable87,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:27:39,127 INFO L396 AbstractCegarLoop]: === Iteration 89 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:27:39,127 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:27:39,127 INFO L85 PathProgramCache]: Analyzing trace with hash -1936033725, now seen corresponding path program 1 times [2024-12-02 11:27:39,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:27:39,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [156105445] [2024-12-02 11:27:39,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:39,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:27:41,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:45,142 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 4 proven. 117 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:45,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-12-02 11:27:45,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [156105445] [2024-12-02 11:27:45,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [156105445] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:27:45,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [533583287] [2024-12-02 11:27:45,142 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:27:45,142 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:27:45,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:27:45,144 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:27:45,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2024-12-02 11:27:50,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:27:50,180 INFO L256 TraceCheckSpWp]: Trace formula consists of 2996 conjuncts, 129 conjuncts are in the unsatisfiable core [2024-12-02 11:27:50,190 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:27:56,205 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 2 proven. 119 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:27:56,205 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:28:04,820 INFO L134 CoverageAnalysis]: Checked inductivity of 181 backedges. 37 proven. 84 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2024-12-02 11:28:04,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [533583287] provided 0 perfect and 2 imperfect interpolant sequences [2024-12-02 11:28:04,820 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2024-12-02 11:28:04,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 26, 17] total 51 [2024-12-02 11:28:04,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612468646] [2024-12-02 11:28:04,820 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2024-12-02 11:28:04,821 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 51 states [2024-12-02 11:28:04,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-12-02 11:28:04,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2024-12-02 11:28:04,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=401, Invalid=2149, Unknown=0, NotChecked=0, Total=2550 [2024-12-02 11:28:04,822 INFO L87 Difference]: Start difference. First operand 32355 states and 41105 transitions. Second operand has 51 states, 51 states have (on average 27.392156862745097) internal successors, (1397), 51 states have internal predecessors, (1397), 8 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 8 states have call predecessors, (18), 8 states have call successors, (18) [2024-12-02 11:28:14,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:28:14,852 INFO L93 Difference]: Finished difference Result 85376 states and 108187 transitions. [2024-12-02 11:28:14,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2024-12-02 11:28:14,853 INFO L78 Accepts]: Start accepts. Automaton has has 51 states, 51 states have (on average 27.392156862745097) internal successors, (1397), 51 states have internal predecessors, (1397), 8 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 8 states have call predecessors, (18), 8 states have call successors, (18) Word has length 498 [2024-12-02 11:28:14,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:28:14,900 INFO L225 Difference]: With dead ends: 85376 [2024-12-02 11:28:14,900 INFO L226 Difference]: Without dead ends: 66843 [2024-12-02 11:28:14,920 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 1054 GetRequests, 960 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2270 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1343, Invalid=7777, Unknown=0, NotChecked=0, Total=9120 [2024-12-02 11:28:14,920 INFO L435 NwaCegarLoop]: 942 mSDtfsCounter, 7890 mSDsluCounter, 22089 mSDsCounter, 0 mSdLazyCounter, 14012 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7901 SdHoareTripleChecker+Valid, 23031 SdHoareTripleChecker+Invalid, 14028 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 14012 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 6.8s IncrementalHoareTripleChecker+Time [2024-12-02 11:28:14,920 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7901 Valid, 23031 Invalid, 14028 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [16 Valid, 14012 Invalid, 0 Unknown, 0 Unchecked, 6.8s Time] [2024-12-02 11:28:14,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66843 states. [2024-12-02 11:28:16,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66843 to 32311. [2024-12-02 11:28:16,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32311 states, 31465 states have (on average 1.2501827427300174) internal successors, (39337), 31465 states have internal predecessors, (39337), 844 states have call successors, (844), 1 states have call predecessors, (844), 1 states have return successors, (844), 844 states have call predecessors, (844), 844 states have call successors, (844) [2024-12-02 11:28:16,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32311 states to 32311 states and 41025 transitions. [2024-12-02 11:28:16,096 INFO L78 Accepts]: Start accepts. Automaton has 32311 states and 41025 transitions. Word has length 498 [2024-12-02 11:28:16,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:28:16,096 INFO L471 AbstractCegarLoop]: Abstraction has 32311 states and 41025 transitions. [2024-12-02 11:28:16,096 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 51 states, 51 states have (on average 27.392156862745097) internal successors, (1397), 51 states have internal predecessors, (1397), 8 states have call successors, (18), 1 states have call predecessors, (18), 1 states have return successors, (18), 8 states have call predecessors, (18), 8 states have call successors, (18) [2024-12-02 11:28:16,097 INFO L276 IsEmpty]: Start isEmpty. Operand 32311 states and 41025 transitions. [2024-12-02 11:28:16,119 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 499 [2024-12-02 11:28:16,120 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:28:16,120 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:28:16,150 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2024-12-02 11:28:16,320 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable88,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:28:16,320 INFO L396 AbstractCegarLoop]: === Iteration 90 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:28:16,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:28:16,321 INFO L85 PathProgramCache]: Analyzing trace with hash -373273150, now seen corresponding path program 1 times [2024-12-02 11:28:16,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-12-02 11:28:16,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983492504] [2024-12-02 11:28:16,321 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:28:16,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-12-02 11:28:20,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:28:20,697 INFO L357 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-12-02 11:28:24,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-12-02 11:28:24,859 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-12-02 11:28:24,859 INFO L340 BasicCegarLoop]: Counterexample is feasible [2024-12-02 11:28:24,860 INFO L782 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2024-12-02 11:28:24,861 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable89 [2024-12-02 11:28:24,863 INFO L422 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:28:25,081 INFO L170 ceAbstractionStarter]: Computing trace abstraction results [2024-12-02 11:28:25,083 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.12 11:28:25 BoogieIcfgContainer [2024-12-02 11:28:25,083 INFO L131 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2024-12-02 11:28:25,083 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-12-02 11:28:25,084 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-12-02 11:28:25,084 INFO L274 PluginConnector]: Witness Printer initialized [2024-12-02 11:28:25,084 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:22:54" (3/4) ... [2024-12-02 11:28:25,086 INFO L149 WitnessPrinter]: No result that supports witness generation found [2024-12-02 11:28:25,086 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-12-02 11:28:25,087 INFO L158 Benchmark]: Toolchain (without parser) took 333297.60ms. Allocated memory was 142.6MB in the beginning and 3.2GB in the end (delta: 3.0GB). Free memory was 115.8MB in the beginning and 2.1GB in the end (delta: -2.0GB). Peak memory consumption was 1.0GB. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 82.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: CACSL2BoogieTranslator took 452.73ms. Allocated memory is still 142.6MB. Free memory was 115.6MB in the beginning and 78.9MB in the end (delta: 36.8MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: Boogie Procedure Inliner took 188.91ms. Allocated memory is still 142.6MB. Free memory was 78.9MB in the beginning and 87.8MB in the end (delta: -8.9MB). Peak memory consumption was 51.8MB. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: Boogie Preprocessor took 204.75ms. Allocated memory is still 142.6MB. Free memory was 87.8MB in the beginning and 66.8MB in the end (delta: 21.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: RCFGBuilder took 2238.07ms. Allocated memory was 142.6MB in the beginning and 285.2MB in the end (delta: 142.6MB). Free memory was 66.8MB in the beginning and 164.3MB in the end (delta: -97.5MB). Peak memory consumption was 137.7MB. Max. memory is 16.1GB. [2024-12-02 11:28:25,087 INFO L158 Benchmark]: TraceAbstraction took 330205.22ms. Allocated memory was 285.2MB in the beginning and 3.2GB in the end (delta: 2.9GB). Free memory was 161.9MB in the beginning and 2.1GB in the end (delta: -2.0GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2024-12-02 11:28:25,088 INFO L158 Benchmark]: Witness Printer took 2.94ms. Allocated memory is still 3.2GB. Free memory was 2.1GB in the beginning and 2.1GB in the end (delta: 4.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 11:28:25,089 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 142.6MB. Free memory is still 82.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 452.73ms. Allocated memory is still 142.6MB. Free memory was 115.6MB in the beginning and 78.9MB in the end (delta: 36.8MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 188.91ms. Allocated memory is still 142.6MB. Free memory was 78.9MB in the beginning and 87.8MB in the end (delta: -8.9MB). Peak memory consumption was 51.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 204.75ms. Allocated memory is still 142.6MB. Free memory was 87.8MB in the beginning and 66.8MB in the end (delta: 21.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * RCFGBuilder took 2238.07ms. Allocated memory was 142.6MB in the beginning and 285.2MB in the end (delta: 142.6MB). Free memory was 66.8MB in the beginning and 164.3MB in the end (delta: -97.5MB). Peak memory consumption was 137.7MB. Max. memory is 16.1GB. * TraceAbstraction took 330205.22ms. Allocated memory was 285.2MB in the beginning and 3.2GB in the end (delta: 2.9GB). Free memory was 161.9MB in the beginning and 2.1GB in the end (delta: -2.0GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. * Witness Printer took 2.94ms. Allocated memory is still 3.2GB. Free memory was 2.1GB in the beginning and 2.1GB in the end (delta: 4.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 22]: Unable to prove that a call to reach_error is unreachable Unable to prove that a call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 390, overapproximation of bitwiseOr at line 165, overapproximation of bitwiseOr at line 146, overapproximation of bitwiseAnd at line 655, overapproximation of bitwiseAnd at line 130, overapproximation of bitwiseAnd at line 230, overapproximation of bitwiseAnd at line 166, overapproximation of bitwiseAnd at line 272, overapproximation of bitwiseAnd at line 222, overapproximation of bitwiseAnd at line 541, overapproximation of bitwiseAnd at line 296, overapproximation of bitwiseAnd at line 126, overapproximation of bitwiseAnd at line 254, overapproximation of bitwiseAnd at line 242, overapproximation of bitwiseAnd at line 465, overapproximation of bitwiseAnd at line 767, overapproximation of bitwiseAnd at line 617, overapproximation of bitwiseAnd at line 693, overapproximation of bitwiseAnd at line 278, overapproximation of bitwiseAnd at line 290, overapproximation of bitwiseAnd at line 302, overapproximation of bitwiseAnd at line 522, overapproximation of bitwiseAnd at line 284, overapproximation of bitwiseAnd at line 484, overapproximation of bitwiseAnd at line 636, overapproximation of bitwiseAnd at line 266, overapproximation of bitwiseAnd at line 248, overapproximation of bitwiseAnd at line 560, overapproximation of bitwiseAnd at line 579, overapproximation of bitwiseAnd at line 503, overapproximation of bitwiseAnd at line 399. Possible FailurePath: [L27] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L28] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L30] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 128); [L31] const SORT_3 msb_SORT_3 = (SORT_3)1 << (128 - 1); [L33] const SORT_11 mask_SORT_11 = (SORT_11)-1 >> (sizeof(SORT_11) * 8 - 6); [L34] const SORT_11 msb_SORT_11 = (SORT_11)1 << (6 - 1); [L36] const SORT_13 mask_SORT_13 = (SORT_13)-1 >> (sizeof(SORT_13) * 8 - 5); [L37] const SORT_13 msb_SORT_13 = (SORT_13)1 << (5 - 1); [L39] const SORT_19 mask_SORT_19 = (SORT_19)-1 >> (sizeof(SORT_19) * 8 - 4); [L40] const SORT_19 msb_SORT_19 = (SORT_19)1 << (4 - 1); [L42] const SORT_60 mask_SORT_60 = (SORT_60)-1 >> (sizeof(SORT_60) * 8 - 3); [L43] const SORT_60 msb_SORT_60 = (SORT_60)1 << (3 - 1); [L45] const SORT_81 mask_SORT_81 = (SORT_81)-1 >> (sizeof(SORT_81) * 8 - 2); [L46] const SORT_81 msb_SORT_81 = (SORT_81)1 << (2 - 1); [L48] const SORT_13 var_15 = 16; [L49] const SORT_19 var_20 = 15; [L50] const SORT_19 var_25 = 14; [L51] const SORT_19 var_30 = 13; [L52] const SORT_19 var_35 = 12; [L53] const SORT_19 var_40 = 11; [L54] const SORT_19 var_45 = 10; [L55] const SORT_19 var_50 = 9; [L56] const SORT_19 var_55 = 8; [L57] const SORT_60 var_61 = 7; [L58] const SORT_60 var_66 = 6; [L59] const SORT_60 var_71 = 5; [L60] const SORT_60 var_76 = 4; [L61] const SORT_81 var_82 = 3; [L62] const SORT_81 var_87 = 2; [L63] const SORT_1 var_92 = 1; [L64] const SORT_13 var_105 = 17; [L65] const SORT_11 var_122 = 0; [L66] const SORT_1 var_152 = 0; [L67] const SORT_3 var_373 = 0; [L69] SORT_1 input_2; [L70] SORT_3 input_4; [L71] SORT_1 input_5; [L72] SORT_1 input_6; [L73] SORT_1 input_7; [L74] SORT_1 input_8; [L75] SORT_3 input_9; [L76] SORT_1 input_150; [L78] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L78] SORT_3 state_10 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L79] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L79] SORT_11 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L80] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L80] SORT_3 state_18 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L81] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L81] SORT_3 state_24 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L82] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L82] SORT_3 state_29 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L83] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L83] SORT_3 state_34 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L84] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L84] SORT_3 state_39 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L85] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L85] SORT_3 state_44 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L86] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L86] SORT_3 state_49 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L87] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L87] SORT_3 state_54 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L88] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L88] SORT_3 state_59 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L89] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L89] SORT_3 state_65 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L90] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L90] SORT_3 state_70 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L91] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L91] SORT_3 state_75 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L92] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L92] SORT_3 state_80 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L93] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L93] SORT_3 state_86 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L94] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L94] SORT_3 state_91 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L95] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L95] SORT_3 state_96 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L96] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L96] SORT_11 state_101 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L97] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L97] SORT_1 state_109 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L98] SORT_1 state_110 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L99] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L99] SORT_11 state_113 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L100] EXPR __VERIFIER_nondet_uint128() & mask_SORT_3 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L100] SORT_3 state_128 = __VERIFIER_nondet_uint128() & mask_SORT_3; [L101] EXPR __VERIFIER_nondet_uchar() & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L101] SORT_1 state_132 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L102] EXPR __VERIFIER_nondet_uchar() & mask_SORT_11 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L102] SORT_11 state_185 = __VERIFIER_nondet_uchar() & mask_SORT_11; [L104] SORT_1 init_133_arg_1 = var_92; [L105] state_132 = init_133_arg_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L108] input_2 = __VERIFIER_nondet_uchar() [L109] input_4 = __VERIFIER_nondet_uint128() [L110] input_5 = __VERIFIER_nondet_uchar() [L111] input_6 = __VERIFIER_nondet_uchar() [L112] input_7 = __VERIFIER_nondet_uchar() [L113] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L113] input_7 = input_7 & mask_SORT_1 [L114] input_8 = __VERIFIER_nondet_uchar() [L115] input_9 = __VERIFIER_nondet_uint128() [L116] input_150 = __VERIFIER_nondet_uchar() [L118] SORT_1 var_134_arg_0 = input_7; [L119] SORT_1 var_134_arg_1 = state_132; [L120] SORT_1 var_134 = var_134_arg_0 == var_134_arg_1; [L121] SORT_1 var_135_arg_0 = var_92; [L122] SORT_1 var_135 = ~var_135_arg_0; [L123] SORT_1 var_136_arg_0 = var_134; [L124] SORT_1 var_136_arg_1 = var_135; VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_136_arg_0=0, var_136_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] EXPR var_136_arg_0 | var_136_arg_1 VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L126] EXPR var_136 & mask_SORT_1 VAL [input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L126] var_136 = var_136 & mask_SORT_1 [L127] SORT_1 constr_137_arg_0 = var_136; VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L128] CALL assume_abort_if_not(constr_137_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L128] RET assume_abort_if_not(constr_137_arg_0) VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] SORT_13 var_106_arg_0 = var_105; VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_106_arg_0=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L130] EXPR var_106_arg_0 & mask_SORT_13 VAL [constr_137_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L130] var_106_arg_0 = var_106_arg_0 & mask_SORT_13 [L131] SORT_11 var_106 = var_106_arg_0; [L132] SORT_11 var_107_arg_0 = state_101; [L133] SORT_11 var_107_arg_1 = var_106; [L134] SORT_1 var_107 = var_107_arg_0 == var_107_arg_1; [L135] SORT_1 var_138_arg_0 = var_107; [L136] SORT_1 var_138 = ~var_138_arg_0; [L137] SORT_1 var_139_arg_0 = input_6; [L138] SORT_1 var_139 = ~var_139_arg_0; [L139] SORT_1 var_140_arg_0 = var_138; [L140] SORT_1 var_140_arg_1 = var_139; VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_140_arg_0=-1, var_140_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L141] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L141] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L142] SORT_1 var_141_arg_0 = var_92; [L143] SORT_1 var_141 = ~var_141_arg_0; [L144] SORT_1 var_142_arg_0 = var_140; [L145] SORT_1 var_142_arg_1 = var_141; VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_142_arg_0=255, var_142_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L147] EXPR var_142 & mask_SORT_1 VAL [constr_137_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L147] var_142 = var_142 & mask_SORT_1 [L148] SORT_1 constr_143_arg_0 = var_142; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L149] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L149] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L150] SORT_11 var_102_arg_0 = state_101; [L151] SORT_1 var_102 = var_102_arg_0 != 0; [L152] SORT_1 var_103_arg_0 = var_102; [L153] SORT_1 var_103 = ~var_103_arg_0; [L154] SORT_1 var_144_arg_0 = var_103; [L155] SORT_1 var_144 = ~var_144_arg_0; [L156] SORT_1 var_145_arg_0 = input_5; [L157] SORT_1 var_145 = ~var_145_arg_0; [L158] SORT_1 var_146_arg_0 = var_144; [L159] SORT_1 var_146_arg_1 = var_145; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_146_arg_0=-256, var_146_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L160] EXPR var_146_arg_0 | var_146_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L160] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L161] SORT_1 var_147_arg_0 = var_92; [L162] SORT_1 var_147 = ~var_147_arg_0; [L163] SORT_1 var_148_arg_0 = var_146; [L164] SORT_1 var_148_arg_1 = var_147; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_148_arg_0=255, var_148_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] EXPR var_148_arg_0 | var_148_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] SORT_1 var_148 = var_148_arg_0 | var_148_arg_1; [L166] EXPR var_148 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L166] var_148 = var_148 & mask_SORT_1 [L167] SORT_1 constr_149_arg_0 = var_148; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L168] CALL assume_abort_if_not(constr_149_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L168] RET assume_abort_if_not(constr_149_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L170] SORT_1 var_153_arg_0 = state_132; [L171] SORT_1 var_153_arg_1 = var_152; [L172] SORT_1 var_153_arg_2 = var_92; [L173] SORT_1 var_153 = var_153_arg_0 ? var_153_arg_1 : var_153_arg_2; [L174] SORT_1 var_111_arg_0 = state_110; [L175] SORT_1 var_111 = ~var_111_arg_0; [L176] SORT_1 var_112_arg_0 = state_109; [L177] SORT_1 var_112_arg_1 = var_111; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_112_arg_0=0, var_112_arg_1=-1, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L178] EXPR var_112_arg_0 & var_112_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L178] SORT_1 var_112 = var_112_arg_0 & var_112_arg_1; [L179] SORT_11 var_114_arg_0 = state_113; [L180] SORT_1 var_114 = var_114_arg_0 != 0; [L181] SORT_1 var_115_arg_0 = var_112; [L182] SORT_1 var_115_arg_1 = var_114; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115_arg_0=0, var_115_arg_1=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L183] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L183] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L184] SORT_1 var_116_arg_0 = state_109; [L185] SORT_1 var_116 = ~var_116_arg_0; [L186] SORT_1 var_117_arg_0 = input_6; [L187] SORT_1 var_117_arg_1 = var_116; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_117_arg_0=0, var_117_arg_1=-1, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L188] EXPR var_117_arg_0 & var_117_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L188] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L189] SORT_1 var_118_arg_0 = var_117; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_118_arg_0=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L190] EXPR var_118_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L190] var_118_arg_0 = var_118_arg_0 & mask_SORT_1 [L191] SORT_11 var_118 = var_118_arg_0; [L192] SORT_11 var_119_arg_0 = state_113; [L193] SORT_11 var_119_arg_1 = var_118; [L194] SORT_11 var_119 = var_119_arg_0 + var_119_arg_1; [L195] SORT_1 var_120_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_120_arg_0=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L196] EXPR var_120_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L196] var_120_arg_0 = var_120_arg_0 & mask_SORT_1 [L197] SORT_11 var_120 = var_120_arg_0; [L198] SORT_11 var_121_arg_0 = var_119; [L199] SORT_11 var_121_arg_1 = var_120; [L200] SORT_11 var_121 = var_121_arg_0 - var_121_arg_1; [L201] SORT_1 var_123_arg_0 = input_7; [L202] SORT_11 var_123_arg_1 = var_122; [L203] SORT_11 var_123_arg_2 = var_121; [L204] SORT_11 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_123=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L205] EXPR var_123 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L205] var_123 = var_123 & mask_SORT_11 [L206] SORT_11 var_124_arg_0 = var_123; [L207] SORT_1 var_124 = var_124_arg_0 != 0; [L208] SORT_1 var_125_arg_0 = var_124; [L209] SORT_1 var_125 = ~var_125_arg_0; [L210] SORT_1 var_126_arg_0 = var_115; [L211] SORT_1 var_126_arg_1 = var_125; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126_arg_0=0, var_126_arg_1=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L212] EXPR var_126_arg_0 & var_126_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L212] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L213] SORT_1 var_127_arg_0 = var_126; [L214] SORT_1 var_127 = ~var_127_arg_0; [L215] SORT_11 var_14_arg_0 = state_12; [L216] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L217] EXPR var_14 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L217] var_14 = var_14 & mask_SORT_13 [L218] SORT_13 var_97_arg_0 = var_14; [L219] SORT_1 var_97 = var_97_arg_0 != 0; [L220] SORT_1 var_98_arg_0 = var_97; [L221] SORT_1 var_98 = ~var_98_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=-1] [L222] EXPR var_98 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L222] var_98 = var_98 & mask_SORT_1 [L223] SORT_1 var_93_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_93_arg_0=1, var_98=0] [L224] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=0] [L224] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L225] SORT_13 var_93 = var_93_arg_0; [L226] SORT_13 var_94_arg_0 = var_14; [L227] SORT_13 var_94_arg_1 = var_93; [L228] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L229] SORT_81 var_88_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_88_arg_0=2, var_92=1, var_94=0, var_98=0] [L230] EXPR var_88_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_94=0, var_98=0] [L230] var_88_arg_0 = var_88_arg_0 & mask_SORT_81 [L231] SORT_13 var_88 = var_88_arg_0; [L232] SORT_13 var_89_arg_0 = var_14; [L233] SORT_13 var_89_arg_1 = var_88; [L234] SORT_1 var_89 = var_89_arg_0 == var_89_arg_1; [L235] SORT_81 var_83_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_83_arg_0=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L236] EXPR var_83_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L236] var_83_arg_0 = var_83_arg_0 & mask_SORT_81 [L237] SORT_13 var_83 = var_83_arg_0; [L238] SORT_13 var_84_arg_0 = var_14; [L239] SORT_13 var_84_arg_1 = var_83; [L240] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L241] SORT_60 var_77_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_77_arg_0=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L242] EXPR var_77_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L242] var_77_arg_0 = var_77_arg_0 & mask_SORT_60 [L243] SORT_13 var_77 = var_77_arg_0; [L244] SORT_13 var_78_arg_0 = var_14; [L245] SORT_13 var_78_arg_1 = var_77; [L246] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L247] SORT_60 var_72_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_72_arg_0=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L248] EXPR var_72_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L248] var_72_arg_0 = var_72_arg_0 & mask_SORT_60 [L249] SORT_13 var_72 = var_72_arg_0; [L250] SORT_13 var_73_arg_0 = var_14; [L251] SORT_13 var_73_arg_1 = var_72; [L252] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L253] SORT_60 var_67_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_67_arg_0=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L254] EXPR var_67_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L254] var_67_arg_0 = var_67_arg_0 & mask_SORT_60 [L255] SORT_13 var_67 = var_67_arg_0; [L256] SORT_13 var_68_arg_0 = var_14; [L257] SORT_13 var_68_arg_1 = var_67; [L258] SORT_1 var_68 = var_68_arg_0 == var_68_arg_1; [L259] SORT_60 var_62_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_62_arg_0=7, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L260] EXPR var_62_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L260] var_62_arg_0 = var_62_arg_0 & mask_SORT_60 [L261] SORT_13 var_62 = var_62_arg_0; [L262] SORT_13 var_63_arg_0 = var_14; [L263] SORT_13 var_63_arg_1 = var_62; [L264] SORT_1 var_63 = var_63_arg_0 == var_63_arg_1; [L265] SORT_19 var_56_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_56_arg_0=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L266] EXPR var_56_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L266] var_56_arg_0 = var_56_arg_0 & mask_SORT_19 [L267] SORT_13 var_56 = var_56_arg_0; [L268] SORT_13 var_57_arg_0 = var_14; [L269] SORT_13 var_57_arg_1 = var_56; [L270] SORT_1 var_57 = var_57_arg_0 == var_57_arg_1; [L271] SORT_19 var_51_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_51_arg_0=9, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L272] EXPR var_51_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L272] var_51_arg_0 = var_51_arg_0 & mask_SORT_19 [L273] SORT_13 var_51 = var_51_arg_0; [L274] SORT_13 var_52_arg_0 = var_14; [L275] SORT_13 var_52_arg_1 = var_51; [L276] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L277] SORT_19 var_46_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_46_arg_0=10, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L278] EXPR var_46_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L278] var_46_arg_0 = var_46_arg_0 & mask_SORT_19 [L279] SORT_13 var_46 = var_46_arg_0; [L280] SORT_13 var_47_arg_0 = var_14; [L281] SORT_13 var_47_arg_1 = var_46; [L282] SORT_1 var_47 = var_47_arg_0 == var_47_arg_1; [L283] SORT_19 var_41_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_41_arg_0=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L284] EXPR var_41_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L284] var_41_arg_0 = var_41_arg_0 & mask_SORT_19 [L285] SORT_13 var_41 = var_41_arg_0; [L286] SORT_13 var_42_arg_0 = var_14; [L287] SORT_13 var_42_arg_1 = var_41; [L288] SORT_1 var_42 = var_42_arg_0 == var_42_arg_1; [L289] SORT_19 var_36_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_36_arg_0=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L290] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L290] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L291] SORT_13 var_36 = var_36_arg_0; [L292] SORT_13 var_37_arg_0 = var_14; [L293] SORT_13 var_37_arg_1 = var_36; [L294] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L295] SORT_19 var_31_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_31_arg_0=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L296] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L296] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L297] SORT_13 var_31 = var_31_arg_0; [L298] SORT_13 var_32_arg_0 = var_14; [L299] SORT_13 var_32_arg_1 = var_31; [L300] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L301] SORT_19 var_26_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_26_arg_0=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L302] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L302] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L303] SORT_13 var_26 = var_26_arg_0; [L304] SORT_13 var_27_arg_0 = var_14; [L305] SORT_13 var_27_arg_1 = var_26; [L306] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L307] SORT_19 var_21_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_21_arg_0=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L308] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=0, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=0, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=0, var_92=1, var_94=0, var_98=0] [L308] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L309] SORT_13 var_21 = var_21_arg_0; [L310] SORT_13 var_22_arg_0 = var_14; [L311] SORT_13 var_22_arg_1 = var_21; [L312] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L313] SORT_13 var_16_arg_0 = var_14; [L314] SORT_13 var_16_arg_1 = var_15; [L315] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L316] SORT_1 var_17_arg_0 = var_16; [L317] SORT_3 var_17_arg_1 = state_10; [L318] SORT_3 var_17_arg_2 = input_9; [L319] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L320] SORT_1 var_23_arg_0 = var_22; [L321] SORT_3 var_23_arg_1 = state_18; [L322] SORT_3 var_23_arg_2 = var_17; [L323] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L324] SORT_1 var_28_arg_0 = var_27; [L325] SORT_3 var_28_arg_1 = state_24; [L326] SORT_3 var_28_arg_2 = var_23; [L327] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L328] SORT_1 var_33_arg_0 = var_32; [L329] SORT_3 var_33_arg_1 = state_29; [L330] SORT_3 var_33_arg_2 = var_28; [L331] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L332] SORT_1 var_38_arg_0 = var_37; [L333] SORT_3 var_38_arg_1 = state_34; [L334] SORT_3 var_38_arg_2 = var_33; [L335] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L336] SORT_1 var_43_arg_0 = var_42; [L337] SORT_3 var_43_arg_1 = state_39; [L338] SORT_3 var_43_arg_2 = var_38; [L339] SORT_3 var_43 = var_43_arg_0 ? var_43_arg_1 : var_43_arg_2; [L340] SORT_1 var_48_arg_0 = var_47; [L341] SORT_3 var_48_arg_1 = state_44; [L342] SORT_3 var_48_arg_2 = var_43; [L343] SORT_3 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L344] SORT_1 var_53_arg_0 = var_52; [L345] SORT_3 var_53_arg_1 = state_49; [L346] SORT_3 var_53_arg_2 = var_48; [L347] SORT_3 var_53 = var_53_arg_0 ? var_53_arg_1 : var_53_arg_2; [L348] SORT_1 var_58_arg_0 = var_57; [L349] SORT_3 var_58_arg_1 = state_54; [L350] SORT_3 var_58_arg_2 = var_53; [L351] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; [L352] SORT_1 var_64_arg_0 = var_63; [L353] SORT_3 var_64_arg_1 = state_59; [L354] SORT_3 var_64_arg_2 = var_58; [L355] SORT_3 var_64 = var_64_arg_0 ? var_64_arg_1 : var_64_arg_2; [L356] SORT_1 var_69_arg_0 = var_68; [L357] SORT_3 var_69_arg_1 = state_65; [L358] SORT_3 var_69_arg_2 = var_64; [L359] SORT_3 var_69 = var_69_arg_0 ? var_69_arg_1 : var_69_arg_2; [L360] SORT_1 var_74_arg_0 = var_73; [L361] SORT_3 var_74_arg_1 = state_70; [L362] SORT_3 var_74_arg_2 = var_69; [L363] SORT_3 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L364] SORT_1 var_79_arg_0 = var_78; [L365] SORT_3 var_79_arg_1 = state_75; [L366] SORT_3 var_79_arg_2 = var_74; [L367] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L368] SORT_1 var_85_arg_0 = var_84; [L369] SORT_3 var_85_arg_1 = state_80; [L370] SORT_3 var_85_arg_2 = var_79; [L371] SORT_3 var_85 = var_85_arg_0 ? var_85_arg_1 : var_85_arg_2; [L372] SORT_1 var_90_arg_0 = var_89; [L373] SORT_3 var_90_arg_1 = state_86; [L374] SORT_3 var_90_arg_2 = var_85; [L375] SORT_3 var_90 = var_90_arg_0 ? var_90_arg_1 : var_90_arg_2; [L376] SORT_1 var_95_arg_0 = var_94; [L377] SORT_3 var_95_arg_1 = state_91; [L378] SORT_3 var_95_arg_2 = var_90; [L379] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L380] SORT_1 var_99_arg_0 = var_98; [L381] SORT_3 var_99_arg_1 = state_96; [L382] SORT_3 var_99_arg_2 = var_95; [L383] SORT_3 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_99=(((unsigned __int128) 18446744073709551615U << 64) | 18446744073709551615U)] [L384] EXPR var_99 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L384] var_99 = var_99 & mask_SORT_3 [L385] SORT_3 var_129_arg_0 = state_128; [L386] SORT_3 var_129_arg_1 = var_99; [L387] SORT_1 var_129 = var_129_arg_0 == var_129_arg_1; [L388] SORT_1 var_130_arg_0 = var_127; [L389] SORT_1 var_130_arg_1 = var_129; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_130_arg_0=-1, var_130_arg_1=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L390] EXPR var_130_arg_0 | var_130_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=1, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_153=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L390] SORT_1 var_130 = var_130_arg_0 | var_130_arg_1; [L391] SORT_1 var_151_arg_0 = state_132; [L392] SORT_1 var_151_arg_1 = input_150; [L393] SORT_1 var_151_arg_2 = var_130; [L394] SORT_1 var_151 = var_151_arg_0 ? var_151_arg_1 : var_151_arg_2; [L395] SORT_1 var_154_arg_0 = var_151; [L396] SORT_1 var_154 = ~var_154_arg_0; [L397] SORT_1 var_155_arg_0 = var_153; [L398] SORT_1 var_155_arg_1 = var_154; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_155_arg_0=0, var_155_arg_1=-256, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] EXPR var_155_arg_0 & var_155_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L400] EXPR var_155 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L400] var_155 = var_155 & mask_SORT_1 [L401] SORT_1 bad_156_arg_0 = var_155; [L402] CALL __VERIFIER_assert(!(bad_156_arg_0)) [L22] COND FALSE !(!(cond)) [L402] RET __VERIFIER_assert(!(bad_156_arg_0)) [L404] SORT_11 var_186_arg_0 = state_185; [L405] SORT_13 var_186 = var_186_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L406] EXPR var_186 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L406] var_186 = var_186 & mask_SORT_13 [L407] SORT_13 var_236_arg_0 = var_186; [L408] SORT_13 var_236_arg_1 = var_15; [L409] SORT_1 var_236 = var_236_arg_0 == var_236_arg_1; [L410] SORT_1 var_237_arg_0 = input_6; [L411] SORT_1 var_237_arg_1 = var_236; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_237_arg_0=0, var_237_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L412] EXPR var_237_arg_0 & var_237_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L412] SORT_1 var_237 = var_237_arg_0 & var_237_arg_1; [L413] EXPR var_237 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L413] var_237 = var_237 & mask_SORT_1 [L414] SORT_1 var_372_arg_0 = var_237; [L415] SORT_3 var_372_arg_1 = input_4; [L416] SORT_3 var_372_arg_2 = state_10; [L417] SORT_3 var_372 = var_372_arg_0 ? var_372_arg_1 : var_372_arg_2; [L418] SORT_1 var_374_arg_0 = input_7; [L419] SORT_3 var_374_arg_1 = var_373; [L420] SORT_3 var_374_arg_2 = var_372; [L421] SORT_3 var_374 = var_374_arg_0 ? var_374_arg_1 : var_374_arg_2; [L422] SORT_3 next_375_arg_1 = var_374; [L423] SORT_1 var_160_arg_0 = input_6; [L424] SORT_1 var_160_arg_1 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_160_arg_0=0, var_160_arg_1=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L425] EXPR var_160_arg_0 | var_160_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L425] SORT_1 var_160 = var_160_arg_0 | var_160_arg_1; [L426] SORT_1 var_161_arg_0 = var_160; [L427] SORT_1 var_161_arg_1 = input_7; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161_arg_0=0, var_161_arg_1=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L428] EXPR var_161_arg_0 | var_161_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L428] SORT_1 var_161 = var_161_arg_0 | var_161_arg_1; [L429] EXPR var_161 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L429] var_161 = var_161 & mask_SORT_1 [L430] SORT_1 var_303_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_303_arg_0=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L431] EXPR var_303_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L431] var_303_arg_0 = var_303_arg_0 & mask_SORT_1 [L432] SORT_11 var_303 = var_303_arg_0; [L433] SORT_11 var_304_arg_0 = state_12; [L434] SORT_11 var_304_arg_1 = var_303; [L435] SORT_11 var_304 = var_304_arg_0 + var_304_arg_1; [L436] SORT_1 var_376_arg_0 = var_161; [L437] SORT_11 var_376_arg_1 = var_304; [L438] SORT_11 var_376_arg_2 = state_12; [L439] SORT_11 var_376 = var_376_arg_0 ? var_376_arg_1 : var_376_arg_2; [L440] SORT_1 var_377_arg_0 = input_7; [L441] SORT_11 var_377_arg_1 = var_122; [L442] SORT_11 var_377_arg_2 = var_376; [L443] SORT_11 var_377 = var_377_arg_0 ? var_377_arg_1 : var_377_arg_2; [L444] SORT_11 next_378_arg_1 = var_377; [L445] SORT_19 var_229_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_229_arg_0=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L446] EXPR var_229_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L446] var_229_arg_0 = var_229_arg_0 & mask_SORT_19 [L447] SORT_13 var_229 = var_229_arg_0; [L448] SORT_13 var_230_arg_0 = var_186; [L449] SORT_13 var_230_arg_1 = var_229; [L450] SORT_1 var_230 = var_230_arg_0 == var_230_arg_1; [L451] SORT_1 var_231_arg_0 = input_6; [L452] SORT_1 var_231_arg_1 = var_230; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_231_arg_0=0, var_231_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L453] EXPR var_231_arg_0 & var_231_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L453] SORT_1 var_231 = var_231_arg_0 & var_231_arg_1; [L454] EXPR var_231 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L454] var_231 = var_231 & mask_SORT_1 [L455] SORT_1 var_379_arg_0 = var_231; [L456] SORT_3 var_379_arg_1 = input_4; [L457] SORT_3 var_379_arg_2 = state_18; [L458] SORT_3 var_379 = var_379_arg_0 ? var_379_arg_1 : var_379_arg_2; [L459] SORT_1 var_380_arg_0 = input_7; [L460] SORT_3 var_380_arg_1 = var_373; [L461] SORT_3 var_380_arg_2 = var_379; [L462] SORT_3 var_380 = var_380_arg_0 ? var_380_arg_1 : var_380_arg_2; [L463] SORT_3 next_381_arg_1 = var_380; [L464] SORT_19 var_222_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_222_arg_0=14, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L465] EXPR var_222_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L465] var_222_arg_0 = var_222_arg_0 & mask_SORT_19 [L466] SORT_13 var_222 = var_222_arg_0; [L467] SORT_13 var_223_arg_0 = var_186; [L468] SORT_13 var_223_arg_1 = var_222; [L469] SORT_1 var_223 = var_223_arg_0 == var_223_arg_1; [L470] SORT_1 var_224_arg_0 = input_6; [L471] SORT_1 var_224_arg_1 = var_223; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_224_arg_0=0, var_224_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L472] EXPR var_224_arg_0 & var_224_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L472] SORT_1 var_224 = var_224_arg_0 & var_224_arg_1; [L473] EXPR var_224 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L473] var_224 = var_224 & mask_SORT_1 [L474] SORT_1 var_382_arg_0 = var_224; [L475] SORT_3 var_382_arg_1 = input_4; [L476] SORT_3 var_382_arg_2 = state_24; [L477] SORT_3 var_382 = var_382_arg_0 ? var_382_arg_1 : var_382_arg_2; [L478] SORT_1 var_383_arg_0 = input_7; [L479] SORT_3 var_383_arg_1 = var_373; [L480] SORT_3 var_383_arg_2 = var_382; [L481] SORT_3 var_383 = var_383_arg_0 ? var_383_arg_1 : var_383_arg_2; [L482] SORT_3 next_384_arg_1 = var_383; [L483] SORT_19 var_215_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_215_arg_0=13, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L484] EXPR var_215_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L484] var_215_arg_0 = var_215_arg_0 & mask_SORT_19 [L485] SORT_13 var_215 = var_215_arg_0; [L486] SORT_13 var_216_arg_0 = var_186; [L487] SORT_13 var_216_arg_1 = var_215; [L488] SORT_1 var_216 = var_216_arg_0 == var_216_arg_1; [L489] SORT_1 var_217_arg_0 = input_6; [L490] SORT_1 var_217_arg_1 = var_216; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_217_arg_0=0, var_217_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L491] EXPR var_217_arg_0 & var_217_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L491] SORT_1 var_217 = var_217_arg_0 & var_217_arg_1; [L492] EXPR var_217 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L492] var_217 = var_217 & mask_SORT_1 [L493] SORT_1 var_385_arg_0 = var_217; [L494] SORT_3 var_385_arg_1 = input_4; [L495] SORT_3 var_385_arg_2 = state_29; [L496] SORT_3 var_385 = var_385_arg_0 ? var_385_arg_1 : var_385_arg_2; [L497] SORT_1 var_386_arg_0 = input_7; [L498] SORT_3 var_386_arg_1 = var_373; [L499] SORT_3 var_386_arg_2 = var_385; [L500] SORT_3 var_386 = var_386_arg_0 ? var_386_arg_1 : var_386_arg_2; [L501] SORT_3 next_387_arg_1 = var_386; [L502] SORT_19 var_208_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_208_arg_0=12, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L503] EXPR var_208_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L503] var_208_arg_0 = var_208_arg_0 & mask_SORT_19 [L504] SORT_13 var_208 = var_208_arg_0; [L505] SORT_13 var_209_arg_0 = var_186; [L506] SORT_13 var_209_arg_1 = var_208; [L507] SORT_1 var_209 = var_209_arg_0 == var_209_arg_1; [L508] SORT_1 var_210_arg_0 = input_6; [L509] SORT_1 var_210_arg_1 = var_209; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_210_arg_0=0, var_210_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L510] EXPR var_210_arg_0 & var_210_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L510] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L511] EXPR var_210 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L511] var_210 = var_210 & mask_SORT_1 [L512] SORT_1 var_388_arg_0 = var_210; [L513] SORT_3 var_388_arg_1 = input_4; [L514] SORT_3 var_388_arg_2 = state_34; [L515] SORT_3 var_388 = var_388_arg_0 ? var_388_arg_1 : var_388_arg_2; [L516] SORT_1 var_389_arg_0 = input_7; [L517] SORT_3 var_389_arg_1 = var_373; [L518] SORT_3 var_389_arg_2 = var_388; [L519] SORT_3 var_389 = var_389_arg_0 ? var_389_arg_1 : var_389_arg_2; [L520] SORT_3 next_390_arg_1 = var_389; [L521] SORT_19 var_201_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_201_arg_0=11, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L522] EXPR var_201_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L522] var_201_arg_0 = var_201_arg_0 & mask_SORT_19 [L523] SORT_13 var_201 = var_201_arg_0; [L524] SORT_13 var_202_arg_0 = var_186; [L525] SORT_13 var_202_arg_1 = var_201; [L526] SORT_1 var_202 = var_202_arg_0 == var_202_arg_1; [L527] SORT_1 var_203_arg_0 = input_6; [L528] SORT_1 var_203_arg_1 = var_202; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_203_arg_0=0, var_203_arg_1=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L529] EXPR var_203_arg_0 & var_203_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L529] SORT_1 var_203 = var_203_arg_0 & var_203_arg_1; [L530] EXPR var_203 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L530] var_203 = var_203 & mask_SORT_1 [L531] SORT_1 var_391_arg_0 = var_203; [L532] SORT_3 var_391_arg_1 = input_4; [L533] SORT_3 var_391_arg_2 = state_39; [L534] SORT_3 var_391 = var_391_arg_0 ? var_391_arg_1 : var_391_arg_2; [L535] SORT_1 var_392_arg_0 = input_7; [L536] SORT_3 var_392_arg_1 = var_373; [L537] SORT_3 var_392_arg_2 = var_391; [L538] SORT_3 var_392 = var_392_arg_0 ? var_392_arg_1 : var_392_arg_2; [L539] SORT_3 next_393_arg_1 = var_392; [L540] SORT_19 var_194_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_194_arg_0=10, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L541] EXPR var_194_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L541] var_194_arg_0 = var_194_arg_0 & mask_SORT_19 [L542] SORT_13 var_194 = var_194_arg_0; [L543] SORT_13 var_195_arg_0 = var_186; [L544] SORT_13 var_195_arg_1 = var_194; [L545] SORT_1 var_195 = var_195_arg_0 == var_195_arg_1; [L546] SORT_1 var_196_arg_0 = input_6; [L547] SORT_1 var_196_arg_1 = var_195; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_196_arg_0=0, var_196_arg_1=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L548] EXPR var_196_arg_0 & var_196_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L548] SORT_1 var_196 = var_196_arg_0 & var_196_arg_1; [L549] EXPR var_196 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L549] var_196 = var_196 & mask_SORT_1 [L550] SORT_1 var_394_arg_0 = var_196; [L551] SORT_3 var_394_arg_1 = input_4; [L552] SORT_3 var_394_arg_2 = state_44; [L553] SORT_3 var_394 = var_394_arg_0 ? var_394_arg_1 : var_394_arg_2; [L554] SORT_1 var_395_arg_0 = input_7; [L555] SORT_3 var_395_arg_1 = var_373; [L556] SORT_3 var_395_arg_2 = var_394; [L557] SORT_3 var_395 = var_395_arg_0 ? var_395_arg_1 : var_395_arg_2; [L558] SORT_3 next_396_arg_1 = var_395; [L559] SORT_19 var_298_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_298_arg_0=9, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L560] EXPR var_298_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L560] var_298_arg_0 = var_298_arg_0 & mask_SORT_19 [L561] SORT_13 var_298 = var_298_arg_0; [L562] SORT_13 var_299_arg_0 = var_186; [L563] SORT_13 var_299_arg_1 = var_298; [L564] SORT_1 var_299 = var_299_arg_0 == var_299_arg_1; [L565] SORT_1 var_300_arg_0 = input_6; [L566] SORT_1 var_300_arg_1 = var_299; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_300_arg_0=0, var_300_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L567] EXPR var_300_arg_0 & var_300_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L567] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L568] EXPR var_300 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L568] var_300 = var_300 & mask_SORT_1 [L569] SORT_1 var_397_arg_0 = var_300; [L570] SORT_3 var_397_arg_1 = input_4; [L571] SORT_3 var_397_arg_2 = state_49; [L572] SORT_3 var_397 = var_397_arg_0 ? var_397_arg_1 : var_397_arg_2; [L573] SORT_1 var_398_arg_0 = input_7; [L574] SORT_3 var_398_arg_1 = var_373; [L575] SORT_3 var_398_arg_2 = var_397; [L576] SORT_3 var_398 = var_398_arg_0 ? var_398_arg_1 : var_398_arg_2; [L577] SORT_3 next_399_arg_1 = var_398; [L578] SORT_19 var_291_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_291_arg_0=8, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L579] EXPR var_291_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L579] var_291_arg_0 = var_291_arg_0 & mask_SORT_19 [L580] SORT_13 var_291 = var_291_arg_0; [L581] SORT_13 var_292_arg_0 = var_186; [L582] SORT_13 var_292_arg_1 = var_291; [L583] SORT_1 var_292 = var_292_arg_0 == var_292_arg_1; [L584] SORT_1 var_293_arg_0 = input_6; [L585] SORT_1 var_293_arg_1 = var_292; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_293_arg_0=0, var_293_arg_1=1, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L586] EXPR var_293_arg_0 & var_293_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L586] SORT_1 var_293 = var_293_arg_0 & var_293_arg_1; [L587] EXPR var_293 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L587] var_293 = var_293 & mask_SORT_1 [L588] SORT_1 var_400_arg_0 = var_293; [L589] SORT_3 var_400_arg_1 = input_4; [L590] SORT_3 var_400_arg_2 = state_54; [L591] SORT_3 var_400 = var_400_arg_0 ? var_400_arg_1 : var_400_arg_2; [L592] SORT_1 var_401_arg_0 = input_7; [L593] SORT_3 var_401_arg_1 = var_373; [L594] SORT_3 var_401_arg_2 = var_400; [L595] SORT_3 var_401 = var_401_arg_0 ? var_401_arg_1 : var_401_arg_2; [L596] SORT_3 next_402_arg_1 = var_401; [L597] SORT_60 var_284_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_284_arg_0=7, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L598] EXPR var_284_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L598] var_284_arg_0 = var_284_arg_0 & mask_SORT_60 [L599] SORT_13 var_284 = var_284_arg_0; [L600] SORT_13 var_285_arg_0 = var_186; [L601] SORT_13 var_285_arg_1 = var_284; [L602] SORT_1 var_285 = var_285_arg_0 == var_285_arg_1; [L603] SORT_1 var_286_arg_0 = input_6; [L604] SORT_1 var_286_arg_1 = var_285; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_286_arg_0=0, var_286_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L605] EXPR var_286_arg_0 & var_286_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L605] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L606] EXPR var_286 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L606] var_286 = var_286 & mask_SORT_1 [L607] SORT_1 var_403_arg_0 = var_286; [L608] SORT_3 var_403_arg_1 = input_4; [L609] SORT_3 var_403_arg_2 = state_59; [L610] SORT_3 var_403 = var_403_arg_0 ? var_403_arg_1 : var_403_arg_2; [L611] SORT_1 var_404_arg_0 = input_7; [L612] SORT_3 var_404_arg_1 = var_373; [L613] SORT_3 var_404_arg_2 = var_403; [L614] SORT_3 var_404 = var_404_arg_0 ? var_404_arg_1 : var_404_arg_2; [L615] SORT_3 next_405_arg_1 = var_404; [L616] SORT_60 var_277_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_277_arg_0=6, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L617] EXPR var_277_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L617] var_277_arg_0 = var_277_arg_0 & mask_SORT_60 [L618] SORT_13 var_277 = var_277_arg_0; [L619] SORT_13 var_278_arg_0 = var_186; [L620] SORT_13 var_278_arg_1 = var_277; [L621] SORT_1 var_278 = var_278_arg_0 == var_278_arg_1; [L622] SORT_1 var_279_arg_0 = input_6; [L623] SORT_1 var_279_arg_1 = var_278; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_279_arg_0=0, var_279_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L624] EXPR var_279_arg_0 & var_279_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L624] SORT_1 var_279 = var_279_arg_0 & var_279_arg_1; [L625] EXPR var_279 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L625] var_279 = var_279 & mask_SORT_1 [L626] SORT_1 var_406_arg_0 = var_279; [L627] SORT_3 var_406_arg_1 = input_4; [L628] SORT_3 var_406_arg_2 = state_65; [L629] SORT_3 var_406 = var_406_arg_0 ? var_406_arg_1 : var_406_arg_2; [L630] SORT_1 var_407_arg_0 = input_7; [L631] SORT_3 var_407_arg_1 = var_373; [L632] SORT_3 var_407_arg_2 = var_406; [L633] SORT_3 var_407 = var_407_arg_0 ? var_407_arg_1 : var_407_arg_2; [L634] SORT_3 next_408_arg_1 = var_407; [L635] SORT_60 var_270_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_270_arg_0=5, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L636] EXPR var_270_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L636] var_270_arg_0 = var_270_arg_0 & mask_SORT_60 [L637] SORT_13 var_270 = var_270_arg_0; [L638] SORT_13 var_271_arg_0 = var_186; [L639] SORT_13 var_271_arg_1 = var_270; [L640] SORT_1 var_271 = var_271_arg_0 == var_271_arg_1; [L641] SORT_1 var_272_arg_0 = input_6; [L642] SORT_1 var_272_arg_1 = var_271; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_272_arg_0=0, var_272_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L643] EXPR var_272_arg_0 & var_272_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L643] SORT_1 var_272 = var_272_arg_0 & var_272_arg_1; [L644] EXPR var_272 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L644] var_272 = var_272 & mask_SORT_1 [L645] SORT_1 var_409_arg_0 = var_272; [L646] SORT_3 var_409_arg_1 = input_4; [L647] SORT_3 var_409_arg_2 = state_70; [L648] SORT_3 var_409 = var_409_arg_0 ? var_409_arg_1 : var_409_arg_2; [L649] SORT_1 var_410_arg_0 = input_7; [L650] SORT_3 var_410_arg_1 = var_373; [L651] SORT_3 var_410_arg_2 = var_409; [L652] SORT_3 var_410 = var_410_arg_0 ? var_410_arg_1 : var_410_arg_2; [L653] SORT_3 next_411_arg_1 = var_410; [L654] SORT_60 var_263_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_263_arg_0=4, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L655] EXPR var_263_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L655] var_263_arg_0 = var_263_arg_0 & mask_SORT_60 [L656] SORT_13 var_263 = var_263_arg_0; [L657] SORT_13 var_264_arg_0 = var_186; [L658] SORT_13 var_264_arg_1 = var_263; [L659] SORT_1 var_264 = var_264_arg_0 == var_264_arg_1; [L660] SORT_1 var_265_arg_0 = input_6; [L661] SORT_1 var_265_arg_1 = var_264; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_265_arg_0=0, var_265_arg_1=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L662] EXPR var_265_arg_0 & var_265_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L662] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L663] EXPR var_265 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L663] var_265 = var_265 & mask_SORT_1 [L664] SORT_1 var_412_arg_0 = var_265; [L665] SORT_3 var_412_arg_1 = input_4; [L666] SORT_3 var_412_arg_2 = state_75; [L667] SORT_3 var_412 = var_412_arg_0 ? var_412_arg_1 : var_412_arg_2; [L668] SORT_1 var_413_arg_0 = input_7; [L669] SORT_3 var_413_arg_1 = var_373; [L670] SORT_3 var_413_arg_2 = var_412; [L671] SORT_3 var_413 = var_413_arg_0 ? var_413_arg_1 : var_413_arg_2; [L672] SORT_3 next_414_arg_1 = var_413; [L673] SORT_81 var_256_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_256_arg_0=3, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L674] EXPR var_256_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L674] var_256_arg_0 = var_256_arg_0 & mask_SORT_81 [L675] SORT_13 var_256 = var_256_arg_0; [L676] SORT_13 var_257_arg_0 = var_186; [L677] SORT_13 var_257_arg_1 = var_256; [L678] SORT_1 var_257 = var_257_arg_0 == var_257_arg_1; [L679] SORT_1 var_258_arg_0 = input_6; [L680] SORT_1 var_258_arg_1 = var_257; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_258_arg_0=0, var_258_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L681] EXPR var_258_arg_0 & var_258_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L681] SORT_1 var_258 = var_258_arg_0 & var_258_arg_1; [L682] EXPR var_258 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L682] var_258 = var_258 & mask_SORT_1 [L683] SORT_1 var_415_arg_0 = var_258; [L684] SORT_3 var_415_arg_1 = input_4; [L685] SORT_3 var_415_arg_2 = state_80; [L686] SORT_3 var_415 = var_415_arg_0 ? var_415_arg_1 : var_415_arg_2; [L687] SORT_1 var_416_arg_0 = input_7; [L688] SORT_3 var_416_arg_1 = var_373; [L689] SORT_3 var_416_arg_2 = var_415; [L690] SORT_3 var_416 = var_416_arg_0 ? var_416_arg_1 : var_416_arg_2; [L691] SORT_3 next_417_arg_1 = var_416; [L692] SORT_81 var_249_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_249_arg_0=2, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L693] EXPR var_249_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L693] var_249_arg_0 = var_249_arg_0 & mask_SORT_81 [L694] SORT_13 var_249 = var_249_arg_0; [L695] SORT_13 var_250_arg_0 = var_186; [L696] SORT_13 var_250_arg_1 = var_249; [L697] SORT_1 var_250 = var_250_arg_0 == var_250_arg_1; [L698] SORT_1 var_251_arg_0 = input_6; [L699] SORT_1 var_251_arg_1 = var_250; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_251_arg_0=0, var_251_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L700] EXPR var_251_arg_0 & var_251_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L700] SORT_1 var_251 = var_251_arg_0 & var_251_arg_1; [L701] EXPR var_251 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L701] var_251 = var_251 & mask_SORT_1 [L702] SORT_1 var_418_arg_0 = var_251; [L703] SORT_3 var_418_arg_1 = input_4; [L704] SORT_3 var_418_arg_2 = state_86; [L705] SORT_3 var_418 = var_418_arg_0 ? var_418_arg_1 : var_418_arg_2; [L706] SORT_1 var_419_arg_0 = input_7; [L707] SORT_3 var_419_arg_1 = var_373; [L708] SORT_3 var_419_arg_2 = var_418; [L709] SORT_3 var_419 = var_419_arg_0 ? var_419_arg_1 : var_419_arg_2; [L710] SORT_3 next_420_arg_1 = var_419; [L711] SORT_1 var_242_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_242_arg_0=1, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L712] EXPR var_242_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L712] var_242_arg_0 = var_242_arg_0 & mask_SORT_1 [L713] SORT_13 var_242 = var_242_arg_0; [L714] SORT_13 var_243_arg_0 = var_186; [L715] SORT_13 var_243_arg_1 = var_242; [L716] SORT_1 var_243 = var_243_arg_0 == var_243_arg_1; [L717] SORT_1 var_244_arg_0 = input_6; [L718] SORT_1 var_244_arg_1 = var_243; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_244_arg_0=0, var_244_arg_1=0, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L719] EXPR var_244_arg_0 & var_244_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L719] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L720] EXPR var_244 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_186=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L720] var_244 = var_244 & mask_SORT_1 [L721] SORT_1 var_421_arg_0 = var_244; [L722] SORT_3 var_421_arg_1 = input_4; [L723] SORT_3 var_421_arg_2 = state_91; [L724] SORT_3 var_421 = var_421_arg_0 ? var_421_arg_1 : var_421_arg_2; [L725] SORT_1 var_422_arg_0 = input_7; [L726] SORT_3 var_422_arg_1 = var_373; [L727] SORT_3 var_422_arg_2 = var_421; [L728] SORT_3 var_422 = var_422_arg_0 ? var_422_arg_1 : var_422_arg_2; [L729] SORT_3 next_423_arg_1 = var_422; [L730] SORT_13 var_187_arg_0 = var_186; [L731] SORT_1 var_187 = var_187_arg_0 != 0; [L732] SORT_1 var_188_arg_0 = var_187; [L733] SORT_1 var_188 = ~var_188_arg_0; [L734] SORT_1 var_189_arg_0 = input_6; [L735] SORT_1 var_189_arg_1 = var_188; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_189_arg_0=0, var_189_arg_1=-1, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L736] EXPR var_189_arg_0 & var_189_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L736] SORT_1 var_189 = var_189_arg_0 & var_189_arg_1; [L737] EXPR var_189 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L737] var_189 = var_189 & mask_SORT_1 [L738] SORT_1 var_424_arg_0 = var_189; [L739] SORT_3 var_424_arg_1 = input_4; [L740] SORT_3 var_424_arg_2 = state_96; [L741] SORT_3 var_424 = var_424_arg_0 ? var_424_arg_1 : var_424_arg_2; [L742] SORT_1 var_425_arg_0 = input_7; [L743] SORT_3 var_425_arg_1 = var_373; [L744] SORT_3 var_425_arg_2 = var_424; [L745] SORT_3 var_425 = var_425_arg_0 ? var_425_arg_1 : var_425_arg_2; [L746] SORT_3 next_426_arg_1 = var_425; [L747] SORT_1 var_427_arg_0 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_427_arg_0=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L748] EXPR var_427_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_101=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L748] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L749] SORT_11 var_427 = var_427_arg_0; [L750] SORT_11 var_428_arg_0 = state_101; [L751] SORT_11 var_428_arg_1 = var_427; [L752] SORT_11 var_428 = var_428_arg_0 + var_428_arg_1; [L753] SORT_1 var_429_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_428=0, var_429_arg_0=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L754] EXPR var_429_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_428=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L754] var_429_arg_0 = var_429_arg_0 & mask_SORT_1 [L755] SORT_11 var_429 = var_429_arg_0; [L756] SORT_11 var_430_arg_0 = var_428; [L757] SORT_11 var_430_arg_1 = var_429; [L758] SORT_11 var_430 = var_430_arg_0 - var_430_arg_1; [L759] SORT_1 var_431_arg_0 = input_7; [L760] SORT_11 var_431_arg_1 = var_122; [L761] SORT_11 var_431_arg_2 = var_430; [L762] SORT_11 var_431 = var_431_arg_0 ? var_431_arg_1 : var_431_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_431=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L763] EXPR var_431 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L763] var_431 = var_431 & mask_SORT_11 [L764] SORT_11 next_432_arg_1 = var_431; [L765] SORT_1 var_333_arg_0 = state_109; [L766] SORT_1 var_333 = ~var_333_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_333=-1, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L767] EXPR var_333 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L767] var_333 = var_333 & mask_SORT_1 [L768] SORT_1 var_329_arg_0 = input_8; [L769] SORT_1 var_329_arg_1 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329_arg_0=0, var_329_arg_1=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L770] EXPR var_329_arg_0 & var_329_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L770] SORT_1 var_329 = var_329_arg_0 & var_329_arg_1; [L771] SORT_1 var_330_arg_0 = state_109; [L772] SORT_1 var_330_arg_1 = var_329; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_330_arg_0=0, var_330_arg_1=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L773] EXPR var_330_arg_0 | var_330_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L773] SORT_1 var_330 = var_330_arg_0 | var_330_arg_1; [L774] SORT_1 var_433_arg_0 = var_333; [L775] SORT_1 var_433_arg_1 = var_330; [L776] SORT_1 var_433_arg_2 = state_109; [L777] SORT_1 var_433 = var_433_arg_0 ? var_433_arg_1 : var_433_arg_2; [L778] SORT_1 var_434_arg_0 = input_7; [L779] SORT_1 var_434_arg_1 = var_152; [L780] SORT_1 var_434_arg_2 = var_433; [L781] SORT_1 var_434 = var_434_arg_0 ? var_434_arg_1 : var_434_arg_2; [L782] SORT_1 next_435_arg_1 = var_434; [L783] SORT_1 var_341_arg_0 = var_126; [L784] SORT_1 var_341_arg_1 = state_110; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_341_arg_0=0, var_341_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L785] EXPR var_341_arg_0 | var_341_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_5=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, state_109=0, state_110=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L785] SORT_1 var_341 = var_341_arg_0 | var_341_arg_1; [L786] SORT_1 var_436_arg_0 = var_92; [L787] SORT_1 var_436_arg_1 = var_341; [L788] SORT_1 var_436_arg_2 = state_110; [L789] SORT_1 var_436 = var_436_arg_0 ? var_436_arg_1 : var_436_arg_2; [L790] SORT_1 var_437_arg_0 = input_7; [L791] SORT_1 var_437_arg_1 = var_152; [L792] SORT_1 var_437_arg_2 = var_436; [L793] SORT_1 var_437 = var_437_arg_0 ? var_437_arg_1 : var_437_arg_2; [L794] SORT_1 next_438_arg_1 = var_437; [L795] SORT_1 var_353_arg_0 = input_6; [L796] SORT_1 var_353_arg_1 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_353_arg_0=0, var_353_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L797] EXPR var_353_arg_0 | var_353_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L797] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L798] SORT_1 var_354_arg_0 = var_353; [L799] SORT_1 var_354_arg_1 = input_7; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_354_arg_0=0, var_354_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L800] EXPR var_354_arg_0 | var_354_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_109=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L800] SORT_1 var_354 = var_354_arg_0 | var_354_arg_1; [L801] SORT_1 var_355_arg_0 = var_354; [L802] SORT_1 var_355_arg_1 = state_109; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_355_arg_0=0, var_355_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L803] EXPR var_355_arg_0 | var_355_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L803] SORT_1 var_355 = var_355_arg_0 | var_355_arg_1; [L804] EXPR var_355 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_113=0, state_128=0, state_185=0, var_105=17, var_122=0, var_123=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L804] var_355 = var_355 & mask_SORT_1 [L805] SORT_1 var_439_arg_0 = var_355; [L806] SORT_11 var_439_arg_1 = var_123; [L807] SORT_11 var_439_arg_2 = state_113; [L808] SORT_11 var_439 = var_439_arg_0 ? var_439_arg_1 : var_439_arg_2; [L809] SORT_1 var_440_arg_0 = input_7; [L810] SORT_11 var_440_arg_1 = var_122; [L811] SORT_11 var_440_arg_2 = var_439; [L812] SORT_11 var_440 = var_440_arg_0 ? var_440_arg_1 : var_440_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_440=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L813] EXPR var_440 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_329=0, var_333=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L813] var_440 = var_440 & mask_SORT_11 [L814] SORT_11 next_441_arg_1 = var_440; [L815] SORT_1 var_338_arg_0 = var_329; [L816] SORT_1 var_338_arg_1 = var_333; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_338_arg_0=0, var_338_arg_1=0, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L817] EXPR var_338_arg_0 & var_338_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L817] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L818] EXPR var_338 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_4=0, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_128=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L818] var_338 = var_338 & mask_SORT_1 [L819] SORT_1 var_442_arg_0 = var_338; [L820] SORT_3 var_442_arg_1 = input_4; [L821] SORT_3 var_442_arg_2 = state_128; [L822] SORT_3 var_442 = var_442_arg_0 ? var_442_arg_1 : var_442_arg_2; [L823] SORT_1 var_443_arg_0 = input_7; [L824] SORT_3 var_443_arg_1 = var_373; [L825] SORT_3 var_443_arg_2 = var_442; [L826] SORT_3 var_443 = var_443_arg_0 ? var_443_arg_1 : var_443_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_443=0, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L827] EXPR var_443 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_6=0, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L827] var_443 = var_443 & mask_SORT_3 [L828] SORT_3 next_444_arg_1 = var_443; [L829] SORT_1 next_445_arg_1 = var_152; [L830] SORT_1 var_309_arg_0 = input_6; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, next_444_arg_1=0, next_445_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_309_arg_0=0, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L831] EXPR var_309_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_7=0, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, next_375_arg_1=0, next_378_arg_1=0, next_381_arg_1=0, next_384_arg_1=0, next_387_arg_1=0, next_390_arg_1=0, next_393_arg_1=0, next_396_arg_1=0, next_399_arg_1=0, next_402_arg_1=0, next_405_arg_1=0, next_408_arg_1=0, next_411_arg_1=0, next_414_arg_1=0, next_417_arg_1=0, next_420_arg_1=0, next_423_arg_1=0, next_426_arg_1=0, next_432_arg_1=0, next_435_arg_1=0, next_438_arg_1=0, next_441_arg_1=0, next_444_arg_1=0, next_445_arg_1=0, state_185=0, var_105=17, var_122=0, var_152=0, var_15=16, var_161=0, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L831] var_309_arg_0 = var_309_arg_0 & mask_SORT_1 [L832] SORT_11 var_309 = var_309_arg_0; [L833] SORT_11 var_310_arg_0 = state_185; [L834] SORT_11 var_310_arg_1 = var_309; [L835] SORT_11 var_310 = var_310_arg_0 + var_310_arg_1; [L836] SORT_1 var_446_arg_0 = var_161; [L837] SORT_11 var_446_arg_1 = var_310; [L838] SORT_11 var_446_arg_2 = state_185; [L839] SORT_11 var_446 = var_446_arg_0 ? var_446_arg_1 : var_446_arg_2; [L840] SORT_1 var_447_arg_0 = input_7; [L841] SORT_11 var_447_arg_1 = var_122; [L842] SORT_11 var_447_arg_2 = var_446; [L843] SORT_11 var_447 = var_447_arg_0 ? var_447_arg_1 : var_447_arg_2; [L844] SORT_11 next_448_arg_1 = var_447; [L846] state_10 = next_375_arg_1 [L847] state_12 = next_378_arg_1 [L848] state_18 = next_381_arg_1 [L849] state_24 = next_384_arg_1 [L850] state_29 = next_387_arg_1 [L851] state_34 = next_390_arg_1 [L852] state_39 = next_393_arg_1 [L853] state_44 = next_396_arg_1 [L854] state_49 = next_399_arg_1 [L855] state_54 = next_402_arg_1 [L856] state_59 = next_405_arg_1 [L857] state_65 = next_408_arg_1 [L858] state_70 = next_411_arg_1 [L859] state_75 = next_414_arg_1 [L860] state_80 = next_417_arg_1 [L861] state_86 = next_420_arg_1 [L862] state_91 = next_423_arg_1 [L863] state_96 = next_426_arg_1 [L864] state_101 = next_432_arg_1 [L865] state_109 = next_435_arg_1 [L866] state_110 = next_438_arg_1 [L867] state_113 = next_441_arg_1 [L868] state_128 = next_444_arg_1 [L869] state_132 = next_445_arg_1 [L870] state_185 = next_448_arg_1 [L108] input_2 = __VERIFIER_nondet_uchar() [L109] input_4 = __VERIFIER_nondet_uint128() [L110] input_5 = __VERIFIER_nondet_uchar() [L111] input_6 = __VERIFIER_nondet_uchar() [L112] input_7 = __VERIFIER_nondet_uchar() [L113] EXPR input_7 & mask_SORT_1 VAL [mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L113] input_7 = input_7 & mask_SORT_1 [L114] input_8 = __VERIFIER_nondet_uchar() [L115] input_9 = __VERIFIER_nondet_uint128() [L116] input_150 = __VERIFIER_nondet_uchar() [L118] SORT_1 var_134_arg_0 = input_7; [L119] SORT_1 var_134_arg_1 = state_132; [L120] SORT_1 var_134 = var_134_arg_0 == var_134_arg_1; [L121] SORT_1 var_135_arg_0 = var_92; [L122] SORT_1 var_135 = ~var_135_arg_0; [L123] SORT_1 var_136_arg_0 = var_134; [L124] SORT_1 var_136_arg_1 = var_135; VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_136_arg_0=0, var_136_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] EXPR var_136_arg_0 | var_136_arg_1 VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L125] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L126] EXPR var_136 & mask_SORT_1 VAL [input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L126] var_136 = var_136 & mask_SORT_1 [L127] SORT_1 constr_137_arg_0 = var_136; VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L128] CALL assume_abort_if_not(constr_137_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L128] RET assume_abort_if_not(constr_137_arg_0) VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L129] SORT_13 var_106_arg_0 = var_105; VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_106_arg_0=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L130] EXPR var_106_arg_0 & mask_SORT_13 VAL [constr_137_arg_0=1, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L130] var_106_arg_0 = var_106_arg_0 & mask_SORT_13 [L131] SORT_11 var_106 = var_106_arg_0; [L132] SORT_11 var_107_arg_0 = state_101; [L133] SORT_11 var_107_arg_1 = var_106; [L134] SORT_1 var_107 = var_107_arg_0 == var_107_arg_1; [L135] SORT_1 var_138_arg_0 = var_107; [L136] SORT_1 var_138 = ~var_138_arg_0; [L137] SORT_1 var_139_arg_0 = input_6; [L138] SORT_1 var_139 = ~var_139_arg_0; [L139] SORT_1 var_140_arg_0 = var_138; [L140] SORT_1 var_140_arg_1 = var_139; VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_140_arg_0=-1, var_140_arg_1=-1, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L141] EXPR var_140_arg_0 | var_140_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L141] SORT_1 var_140 = var_140_arg_0 | var_140_arg_1; [L142] SORT_1 var_141_arg_0 = var_92; [L143] SORT_1 var_141 = ~var_141_arg_0; [L144] SORT_1 var_142_arg_0 = var_140; [L145] SORT_1 var_142_arg_1 = var_141; VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_142_arg_0=255, var_142_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] EXPR var_142_arg_0 | var_142_arg_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L146] SORT_1 var_142 = var_142_arg_0 | var_142_arg_1; [L147] EXPR var_142 & mask_SORT_1 VAL [constr_137_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L147] var_142 = var_142 & mask_SORT_1 [L148] SORT_1 constr_143_arg_0 = var_142; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L149] CALL assume_abort_if_not(constr_143_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L149] RET assume_abort_if_not(constr_143_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L150] SORT_11 var_102_arg_0 = state_101; [L151] SORT_1 var_102 = var_102_arg_0 != 0; [L152] SORT_1 var_103_arg_0 = var_102; [L153] SORT_1 var_103 = ~var_103_arg_0; [L154] SORT_1 var_144_arg_0 = var_103; [L155] SORT_1 var_144 = ~var_144_arg_0; [L156] SORT_1 var_145_arg_0 = input_5; [L157] SORT_1 var_145 = ~var_145_arg_0; [L158] SORT_1 var_146_arg_0 = var_144; [L159] SORT_1 var_146_arg_1 = var_145; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_146_arg_0=-256, var_146_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L160] EXPR var_146_arg_0 | var_146_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L160] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L161] SORT_1 var_147_arg_0 = var_92; [L162] SORT_1 var_147 = ~var_147_arg_0; [L163] SORT_1 var_148_arg_0 = var_146; [L164] SORT_1 var_148_arg_1 = var_147; VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_148_arg_0=254, var_148_arg_1=-2, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] EXPR var_148_arg_0 | var_148_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L165] SORT_1 var_148 = var_148_arg_0 | var_148_arg_1; [L166] EXPR var_148 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L166] var_148 = var_148 & mask_SORT_1 [L167] SORT_1 constr_149_arg_0 = var_148; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L168] CALL assume_abort_if_not(constr_149_arg_0) VAL [\old(cond)=1] [L23] COND FALSE !(!cond) VAL [\old(cond)=1] [L168] RET assume_abort_if_not(constr_149_arg_0) VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L170] SORT_1 var_153_arg_0 = state_132; [L171] SORT_1 var_153_arg_1 = var_152; [L172] SORT_1 var_153_arg_2 = var_92; [L173] SORT_1 var_153 = var_153_arg_0 ? var_153_arg_1 : var_153_arg_2; [L174] SORT_1 var_111_arg_0 = state_110; [L175] SORT_1 var_111 = ~var_111_arg_0; [L176] SORT_1 var_112_arg_0 = state_109; [L177] SORT_1 var_112_arg_1 = var_111; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_112_arg_0=0, var_112_arg_1=-1, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L178] EXPR var_112_arg_0 & var_112_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L178] SORT_1 var_112 = var_112_arg_0 & var_112_arg_1; [L179] SORT_11 var_114_arg_0 = state_113; [L180] SORT_1 var_114 = var_114_arg_0 != 0; [L181] SORT_1 var_115_arg_0 = var_112; [L182] SORT_1 var_115_arg_1 = var_114; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115_arg_0=0, var_115_arg_1=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L183] EXPR var_115_arg_0 & var_115_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L183] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L184] SORT_1 var_116_arg_0 = state_109; [L185] SORT_1 var_116 = ~var_116_arg_0; [L186] SORT_1 var_117_arg_0 = input_6; [L187] SORT_1 var_117_arg_1 = var_116; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_117_arg_0=0, var_117_arg_1=-1, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L188] EXPR var_117_arg_0 & var_117_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L188] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L189] SORT_1 var_118_arg_0 = var_117; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_118_arg_0=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L190] EXPR var_118_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L190] var_118_arg_0 = var_118_arg_0 & mask_SORT_1 [L191] SORT_11 var_118 = var_118_arg_0; [L192] SORT_11 var_119_arg_0 = state_113; [L193] SORT_11 var_119_arg_1 = var_118; [L194] SORT_11 var_119 = var_119_arg_0 + var_119_arg_1; [L195] SORT_1 var_120_arg_0 = input_5; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_120_arg_0=257, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L196] EXPR var_120_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_119=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L196] var_120_arg_0 = var_120_arg_0 & mask_SORT_1 [L197] SORT_11 var_120 = var_120_arg_0; [L198] SORT_11 var_121_arg_0 = var_119; [L199] SORT_11 var_121_arg_1 = var_120; [L200] SORT_11 var_121 = var_121_arg_0 - var_121_arg_1; [L201] SORT_1 var_123_arg_0 = input_7; [L202] SORT_11 var_123_arg_1 = var_122; [L203] SORT_11 var_123_arg_2 = var_121; [L204] SORT_11 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_123=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L205] EXPR var_123 & mask_SORT_11 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_115=0, var_122=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L205] var_123 = var_123 & mask_SORT_11 [L206] SORT_11 var_124_arg_0 = var_123; [L207] SORT_1 var_124 = var_124_arg_0 != 0; [L208] SORT_1 var_125_arg_0 = var_124; [L209] SORT_1 var_125 = ~var_125_arg_0; [L210] SORT_1 var_126_arg_0 = var_115; [L211] SORT_1 var_126_arg_1 = var_125; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126_arg_0=0, var_126_arg_1=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L212] EXPR var_126_arg_0 & var_126_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L212] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L213] SORT_1 var_127_arg_0 = var_126; [L214] SORT_1 var_127 = ~var_127_arg_0; [L215] SORT_11 var_14_arg_0 = state_12; [L216] SORT_13 var_14 = var_14_arg_0 >> 0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L217] EXPR var_14 & mask_SORT_13 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L217] var_14 = var_14 & mask_SORT_13 [L218] SORT_13 var_97_arg_0 = var_14; [L219] SORT_1 var_97 = var_97_arg_0 != 0; [L220] SORT_1 var_98_arg_0 = var_97; [L221] SORT_1 var_98 = ~var_98_arg_0; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=-1] [L222] EXPR var_98 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L222] var_98 = var_98 & mask_SORT_1 [L223] SORT_1 var_93_arg_0 = var_92; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_93_arg_0=1, var_98=1] [L224] EXPR var_93_arg_0 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_98=1] [L224] var_93_arg_0 = var_93_arg_0 & mask_SORT_1 [L225] SORT_13 var_93 = var_93_arg_0; [L226] SORT_13 var_94_arg_0 = var_14; [L227] SORT_13 var_94_arg_1 = var_93; [L228] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L229] SORT_81 var_88_arg_0 = var_87; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_88_arg_0=2, var_92=1, var_94=0, var_98=1] [L230] EXPR var_88_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_94=0, var_98=1] [L230] var_88_arg_0 = var_88_arg_0 & mask_SORT_81 [L231] SORT_13 var_88 = var_88_arg_0; [L232] SORT_13 var_89_arg_0 = var_14; [L233] SORT_13 var_89_arg_1 = var_88; [L234] SORT_1 var_89 = var_89_arg_0 == var_89_arg_1; [L235] SORT_81 var_83_arg_0 = var_82; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_83_arg_0=3, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L236] EXPR var_83_arg_0 & mask_SORT_81 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L236] var_83_arg_0 = var_83_arg_0 & mask_SORT_81 [L237] SORT_13 var_83 = var_83_arg_0; [L238] SORT_13 var_84_arg_0 = var_14; [L239] SORT_13 var_84_arg_1 = var_83; [L240] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L241] SORT_60 var_77_arg_0 = var_76; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_77_arg_0=4, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L242] EXPR var_77_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L242] var_77_arg_0 = var_77_arg_0 & mask_SORT_60 [L243] SORT_13 var_77 = var_77_arg_0; [L244] SORT_13 var_78_arg_0 = var_14; [L245] SORT_13 var_78_arg_1 = var_77; [L246] SORT_1 var_78 = var_78_arg_0 == var_78_arg_1; [L247] SORT_60 var_72_arg_0 = var_71; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_72_arg_0=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L248] EXPR var_72_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L248] var_72_arg_0 = var_72_arg_0 & mask_SORT_60 [L249] SORT_13 var_72 = var_72_arg_0; [L250] SORT_13 var_73_arg_0 = var_14; [L251] SORT_13 var_73_arg_1 = var_72; [L252] SORT_1 var_73 = var_73_arg_0 == var_73_arg_1; [L253] SORT_60 var_67_arg_0 = var_66; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_67_arg_0=6, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L254] EXPR var_67_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L254] var_67_arg_0 = var_67_arg_0 & mask_SORT_60 [L255] SORT_13 var_67 = var_67_arg_0; [L256] SORT_13 var_68_arg_0 = var_14; [L257] SORT_13 var_68_arg_1 = var_67; [L258] SORT_1 var_68 = var_68_arg_0 == var_68_arg_1; [L259] SORT_60 var_62_arg_0 = var_61; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_62_arg_0=7, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L260] EXPR var_62_arg_0 & mask_SORT_60 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L260] var_62_arg_0 = var_62_arg_0 & mask_SORT_60 [L261] SORT_13 var_62 = var_62_arg_0; [L262] SORT_13 var_63_arg_0 = var_14; [L263] SORT_13 var_63_arg_1 = var_62; [L264] SORT_1 var_63 = var_63_arg_0 == var_63_arg_1; [L265] SORT_19 var_56_arg_0 = var_55; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_56_arg_0=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L266] EXPR var_56_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L266] var_56_arg_0 = var_56_arg_0 & mask_SORT_19 [L267] SORT_13 var_56 = var_56_arg_0; [L268] SORT_13 var_57_arg_0 = var_14; [L269] SORT_13 var_57_arg_1 = var_56; [L270] SORT_1 var_57 = var_57_arg_0 == var_57_arg_1; [L271] SORT_19 var_51_arg_0 = var_50; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_51_arg_0=9, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L272] EXPR var_51_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L272] var_51_arg_0 = var_51_arg_0 & mask_SORT_19 [L273] SORT_13 var_51 = var_51_arg_0; [L274] SORT_13 var_52_arg_0 = var_14; [L275] SORT_13 var_52_arg_1 = var_51; [L276] SORT_1 var_52 = var_52_arg_0 == var_52_arg_1; [L277] SORT_19 var_46_arg_0 = var_45; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_46_arg_0=10, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L278] EXPR var_46_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L278] var_46_arg_0 = var_46_arg_0 & mask_SORT_19 [L279] SORT_13 var_46 = var_46_arg_0; [L280] SORT_13 var_47_arg_0 = var_14; [L281] SORT_13 var_47_arg_1 = var_46; [L282] SORT_1 var_47 = var_47_arg_0 == var_47_arg_1; [L283] SORT_19 var_41_arg_0 = var_40; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_41_arg_0=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L284] EXPR var_41_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L284] var_41_arg_0 = var_41_arg_0 & mask_SORT_19 [L285] SORT_13 var_41 = var_41_arg_0; [L286] SORT_13 var_42_arg_0 = var_14; [L287] SORT_13 var_42_arg_1 = var_41; [L288] SORT_1 var_42 = var_42_arg_0 == var_42_arg_1; [L289] SORT_19 var_36_arg_0 = var_35; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_36_arg_0=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L290] EXPR var_36_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L290] var_36_arg_0 = var_36_arg_0 & mask_SORT_19 [L291] SORT_13 var_36 = var_36_arg_0; [L292] SORT_13 var_37_arg_0 = var_14; [L293] SORT_13 var_37_arg_1 = var_36; [L294] SORT_1 var_37 = var_37_arg_0 == var_37_arg_1; [L295] SORT_19 var_31_arg_0 = var_30; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_31_arg_0=13, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L296] EXPR var_31_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L296] var_31_arg_0 = var_31_arg_0 & mask_SORT_19 [L297] SORT_13 var_31 = var_31_arg_0; [L298] SORT_13 var_32_arg_0 = var_14; [L299] SORT_13 var_32_arg_1 = var_31; [L300] SORT_1 var_32 = var_32_arg_0 == var_32_arg_1; [L301] SORT_19 var_26_arg_0 = var_25; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_26_arg_0=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L302] EXPR var_26_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_32=0, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L302] var_26_arg_0 = var_26_arg_0 & mask_SORT_19 [L303] SORT_13 var_26 = var_26_arg_0; [L304] SORT_13 var_27_arg_0 = var_14; [L305] SORT_13 var_27_arg_1 = var_26; [L306] SORT_1 var_27 = var_27_arg_0 == var_27_arg_1; [L307] SORT_19 var_21_arg_0 = var_20; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_21_arg_0=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L308] EXPR var_21_arg_0 & mask_SORT_19 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_14=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_27=0, var_30=13, var_32=0, var_35=12, var_373=0, var_37=1, var_40=11, var_42=0, var_45=10, var_47=0, var_50=9, var_52=0, var_55=8, var_57=1, var_61=7, var_63=0, var_66=6, var_68=0, var_71=5, var_73=1, var_76=4, var_78=0, var_82=3, var_84=0, var_87=2, var_89=1, var_92=1, var_94=0, var_98=1] [L308] var_21_arg_0 = var_21_arg_0 & mask_SORT_19 [L309] SORT_13 var_21 = var_21_arg_0; [L310] SORT_13 var_22_arg_0 = var_14; [L311] SORT_13 var_22_arg_1 = var_21; [L312] SORT_1 var_22 = var_22_arg_0 == var_22_arg_1; [L313] SORT_13 var_16_arg_0 = var_14; [L314] SORT_13 var_16_arg_1 = var_15; [L315] SORT_1 var_16 = var_16_arg_0 == var_16_arg_1; [L316] SORT_1 var_17_arg_0 = var_16; [L317] SORT_3 var_17_arg_1 = state_10; [L318] SORT_3 var_17_arg_2 = input_9; [L319] SORT_3 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L320] SORT_1 var_23_arg_0 = var_22; [L321] SORT_3 var_23_arg_1 = state_18; [L322] SORT_3 var_23_arg_2 = var_17; [L323] SORT_3 var_23 = var_23_arg_0 ? var_23_arg_1 : var_23_arg_2; [L324] SORT_1 var_28_arg_0 = var_27; [L325] SORT_3 var_28_arg_1 = state_24; [L326] SORT_3 var_28_arg_2 = var_23; [L327] SORT_3 var_28 = var_28_arg_0 ? var_28_arg_1 : var_28_arg_2; [L328] SORT_1 var_33_arg_0 = var_32; [L329] SORT_3 var_33_arg_1 = state_29; [L330] SORT_3 var_33_arg_2 = var_28; [L331] SORT_3 var_33 = var_33_arg_0 ? var_33_arg_1 : var_33_arg_2; [L332] SORT_1 var_38_arg_0 = var_37; [L333] SORT_3 var_38_arg_1 = state_34; [L334] SORT_3 var_38_arg_2 = var_33; [L335] SORT_3 var_38 = var_38_arg_0 ? var_38_arg_1 : var_38_arg_2; [L336] SORT_1 var_43_arg_0 = var_42; [L337] SORT_3 var_43_arg_1 = state_39; [L338] SORT_3 var_43_arg_2 = var_38; [L339] SORT_3 var_43 = var_43_arg_0 ? var_43_arg_1 : var_43_arg_2; [L340] SORT_1 var_48_arg_0 = var_47; [L341] SORT_3 var_48_arg_1 = state_44; [L342] SORT_3 var_48_arg_2 = var_43; [L343] SORT_3 var_48 = var_48_arg_0 ? var_48_arg_1 : var_48_arg_2; [L344] SORT_1 var_53_arg_0 = var_52; [L345] SORT_3 var_53_arg_1 = state_49; [L346] SORT_3 var_53_arg_2 = var_48; [L347] SORT_3 var_53 = var_53_arg_0 ? var_53_arg_1 : var_53_arg_2; [L348] SORT_1 var_58_arg_0 = var_57; [L349] SORT_3 var_58_arg_1 = state_54; [L350] SORT_3 var_58_arg_2 = var_53; [L351] SORT_3 var_58 = var_58_arg_0 ? var_58_arg_1 : var_58_arg_2; [L352] SORT_1 var_64_arg_0 = var_63; [L353] SORT_3 var_64_arg_1 = state_59; [L354] SORT_3 var_64_arg_2 = var_58; [L355] SORT_3 var_64 = var_64_arg_0 ? var_64_arg_1 : var_64_arg_2; [L356] SORT_1 var_69_arg_0 = var_68; [L357] SORT_3 var_69_arg_1 = state_65; [L358] SORT_3 var_69_arg_2 = var_64; [L359] SORT_3 var_69 = var_69_arg_0 ? var_69_arg_1 : var_69_arg_2; [L360] SORT_1 var_74_arg_0 = var_73; [L361] SORT_3 var_74_arg_1 = state_70; [L362] SORT_3 var_74_arg_2 = var_69; [L363] SORT_3 var_74 = var_74_arg_0 ? var_74_arg_1 : var_74_arg_2; [L364] SORT_1 var_79_arg_0 = var_78; [L365] SORT_3 var_79_arg_1 = state_75; [L366] SORT_3 var_79_arg_2 = var_74; [L367] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L368] SORT_1 var_85_arg_0 = var_84; [L369] SORT_3 var_85_arg_1 = state_80; [L370] SORT_3 var_85_arg_2 = var_79; [L371] SORT_3 var_85 = var_85_arg_0 ? var_85_arg_1 : var_85_arg_2; [L372] SORT_1 var_90_arg_0 = var_89; [L373] SORT_3 var_90_arg_1 = state_86; [L374] SORT_3 var_90_arg_2 = var_85; [L375] SORT_3 var_90 = var_90_arg_0 ? var_90_arg_1 : var_90_arg_2; [L376] SORT_1 var_95_arg_0 = var_94; [L377] SORT_3 var_95_arg_1 = state_91; [L378] SORT_3 var_95_arg_2 = var_90; [L379] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L380] SORT_1 var_99_arg_0 = var_98; [L381] SORT_3 var_99_arg_1 = state_96; [L382] SORT_3 var_99_arg_2 = var_95; [L383] SORT_3 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1, var_99=0] [L384] EXPR var_99 & mask_SORT_3 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_127=-1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L384] var_99 = var_99 & mask_SORT_3 [L385] SORT_3 var_129_arg_0 = state_128; [L386] SORT_3 var_129_arg_1 = var_99; [L387] SORT_1 var_129 = var_129_arg_0 == var_129_arg_1; [L388] SORT_1 var_130_arg_0 = var_127; [L389] SORT_1 var_130_arg_1 = var_129; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_130_arg_0=-1, var_130_arg_1=1, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L390] EXPR var_130_arg_0 | var_130_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_132=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_153=1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L390] SORT_1 var_130 = var_130_arg_0 | var_130_arg_1; [L391] SORT_1 var_151_arg_0 = state_132; [L392] SORT_1 var_151_arg_1 = input_150; [L393] SORT_1 var_151_arg_2 = var_130; [L394] SORT_1 var_151 = var_151_arg_0 ? var_151_arg_1 : var_151_arg_2; [L395] SORT_1 var_154_arg_0 = var_151; [L396] SORT_1 var_154 = ~var_154_arg_0; [L397] SORT_1 var_155_arg_0 = var_153; [L398] SORT_1 var_155_arg_1 = var_154; VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_155_arg_0=1, var_155_arg_1=-1, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] EXPR var_155_arg_0 & var_155_arg_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L399] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L400] EXPR var_155 & mask_SORT_1 VAL [constr_137_arg_0=1, constr_143_arg_0=1, constr_149_arg_0=1, input_5=257, input_6=0, input_7=1, mask_SORT_11=63, mask_SORT_13=31, mask_SORT_19=15, mask_SORT_1=1, mask_SORT_3=-1, mask_SORT_60=7, mask_SORT_81=3, state_101=0, state_109=0, state_10=0, state_110=0, state_113=0, state_128=0, state_12=0, state_185=0, state_18=0, state_24=0, state_29=0, state_34=0, state_39=0, state_44=0, state_49=0, state_54=0, state_59=0, state_65=0, state_70=0, state_75=0, state_80=0, state_86=0, state_91=0, state_96=0, var_105=17, var_122=0, var_123=0, var_126=0, var_152=0, var_15=16, var_20=15, var_25=14, var_30=13, var_35=12, var_373=0, var_40=11, var_45=10, var_50=9, var_55=8, var_61=7, var_66=6, var_71=5, var_76=4, var_82=3, var_87=2, var_92=1] [L400] var_155 = var_155 & mask_SORT_1 [L401] SORT_1 bad_156_arg_0 = var_155; [L402] CALL __VERIFIER_assert(!(bad_156_arg_0)) [L22] COND TRUE !(cond) [L22] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 2 procedures, 552 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 329.9s, OverallIterations: 90, TraceHistogramMax: 6, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.4s, AutomataDifference: 124.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 159229 SdHoareTripleChecker+Valid, 80.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 159073 mSDsluCounter, 443077 SdHoareTripleChecker+Invalid, 69.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 370206 mSDsCounter, 375 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 161868 IncrementalHoareTripleChecker+Invalid, 162243 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 375 mSolverCounterUnsat, 72871 mSDtfsCounter, 161868 mSolverCounterSat, 1.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 9373 GetRequests, 8069 SyntacticMatches, 1 SemanticMatches, 1303 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 90163 ImplicationChecksByTransitivity, 33.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=32451occurred in iteration=85, InterpolantAutomatonStates: 1129, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 8.2s AutomataMinimizationTime, 89 MinimizatonAttempts, 209569 StatesRemovedByMinimization, 26 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 2.8s SsaConstructionTime, 60.8s SatisfiabilityAnalysisTime, 103.1s InterpolantComputationTime, 37338 NumberOfCodeBlocks, 37338 NumberOfCodeBlocksAsserted, 101 NumberOfCheckSat, 39691 ConstructedInterpolants, 0 QuantifiedInterpolants, 240739 SizeOfPredicates, 60 NumberOfNonLiveVariables, 30780 ConjunctsInSsa, 600 ConjunctsInUnsatCore, 106 InterpolantComputations, 84 PerfectInterpolantSequences, 11865/13029 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available, ConComCheckerStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2024-12-02 11:28:25,128 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/AutomizerReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1 --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 52aaa0332eefa406b14bf0040bc722ffbb83771cf03ec10c7d17ac8a4e45d63a --- Real Ultimate output --- This is Ultimate 0.3.0-dev-d790fec [2024-12-02 11:28:27,188 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-12-02 11:28:27,265 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/config/svcomp-Reach-64bit-Automizer_Bitvector.epf [2024-12-02 11:28:27,271 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-12-02 11:28:27,272 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-12-02 11:28:27,295 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-12-02 11:28:27,296 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-12-02 11:28:27,296 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-12-02 11:28:27,296 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-12-02 11:28:27,297 INFO L153 SettingsManager]: * Use memory slicer=true [2024-12-02 11:28:27,297 INFO L151 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2024-12-02 11:28:27,297 INFO L153 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2024-12-02 11:28:27,297 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-12-02 11:28:27,297 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-12-02 11:28:27,297 INFO L153 SettingsManager]: * Use SBE=true [2024-12-02 11:28:27,298 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Use bitvectors instead of ints=true [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2024-12-02 11:28:27,298 INFO L153 SettingsManager]: * Use constant arrays=true [2024-12-02 11:28:27,298 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:28:27,299 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Only consider context switches at boundaries of atomic blocks=true [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * SMT solver=External_DefaultMode [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:28:27,299 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2024-12-02 11:28:27,299 INFO L153 SettingsManager]: * Compute procedure contracts=false [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopHeads [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Trace refinement strategy=FOX [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Apply one-shot large block encoding in concurrent analysis=false [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Automaton type used in concurrency analysis=PETRI_NET [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Order on configurations for Petri net unfoldings=DBO [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2024-12-02 11:28:27,300 INFO L153 SettingsManager]: * Looper check in Petri net analysis=SEMANTIC Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1 Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 52aaa0332eefa406b14bf0040bc722ffbb83771cf03ec10c7d17ac8a4e45d63a [2024-12-02 11:28:27,535 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-12-02 11:28:27,543 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-12-02 11:28:27,545 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-12-02 11:28:27,547 INFO L270 PluginConnector]: Initializing CDTParser... [2024-12-02 11:28:27,547 INFO L274 PluginConnector]: CDTParser initialized [2024-12-02 11:28:27,548 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:28:30,215 INFO L533 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/0fe97a4a1/4fd888a940a94aa6b3e05eaeac5bd23f/FLAGd38444e84 [2024-12-02 11:28:30,430 INFO L384 CDTParser]: Found 1 translation units. [2024-12-02 11:28:30,431 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:28:30,442 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/0fe97a4a1/4fd888a940a94aa6b3e05eaeac5bd23f/FLAGd38444e84 [2024-12-02 11:28:30,455 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/data/0fe97a4a1/4fd888a940a94aa6b3e05eaeac5bd23f [2024-12-02 11:28:30,458 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-12-02 11:28:30,459 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-12-02 11:28:30,460 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-12-02 11:28:30,460 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-12-02 11:28:30,464 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-12-02 11:28:30,465 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,466 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2caeeb7e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30, skipping insertion in model container [2024-12-02 11:28:30,466 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,496 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-12-02 11:28:30,640 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c[1335,1348] [2024-12-02 11:28:30,789 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:28:30,801 INFO L200 MainTranslator]: Completed pre-run [2024-12-02 11:28:30,810 WARN L250 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c[1335,1348] [2024-12-02 11:28:30,890 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-12-02 11:28:30,903 INFO L204 MainTranslator]: Completed translation [2024-12-02 11:28:30,903 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30 WrapperNode [2024-12-02 11:28:30,903 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-12-02 11:28:30,904 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-12-02 11:28:30,904 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-12-02 11:28:30,904 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-12-02 11:28:30,908 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,925 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,970 INFO L138 Inliner]: procedures = 18, calls = 11, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 912 [2024-12-02 11:28:30,971 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-12-02 11:28:30,971 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-12-02 11:28:30,971 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-12-02 11:28:30,971 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-12-02 11:28:30,980 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,980 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:30,987 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,009 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-12-02 11:28:31,010 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,010 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,029 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,031 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,034 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,038 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,042 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,049 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-12-02 11:28:31,050 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-12-02 11:28:31,050 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-12-02 11:28:31,050 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-12-02 11:28:31,051 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (1/1) ... [2024-12-02 11:28:31,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 [2024-12-02 11:28:31,067 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:28:31,076 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (exit command is (exit), workingDir is null) [2024-12-02 11:28:31,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Waiting until timeout for monitored process [2024-12-02 11:28:31,096 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-12-02 11:28:31,096 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~intINTTYPE1#0 [2024-12-02 11:28:31,096 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2024-12-02 11:28:31,097 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2024-12-02 11:28:31,097 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-12-02 11:28:31,097 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-12-02 11:28:31,281 INFO L234 CfgBuilder]: Building ICFG [2024-12-02 11:28:31,283 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2024-12-02 11:28:32,015 INFO L? ?]: Removed 271 outVars from TransFormulas that were not future-live. [2024-12-02 11:28:32,016 INFO L283 CfgBuilder]: Performing block encoding [2024-12-02 11:28:32,024 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-12-02 11:28:32,024 INFO L312 CfgBuilder]: Removed 1 assume(true) statements. [2024-12-02 11:28:32,025 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:28:32 BoogieIcfgContainer [2024-12-02 11:28:32,025 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-12-02 11:28:32,027 INFO L112 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2024-12-02 11:28:32,028 INFO L270 PluginConnector]: Initializing TraceAbstraction... [2024-12-02 11:28:32,033 INFO L274 PluginConnector]: TraceAbstraction initialized [2024-12-02 11:28:32,033 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.12 11:28:30" (1/3) ... [2024-12-02 11:28:32,033 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ac32f90 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 11:28:32, skipping insertion in model container [2024-12-02 11:28:32,034 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.12 11:28:30" (2/3) ... [2024-12-02 11:28:32,034 INFO L204 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ac32f90 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.12 11:28:32, skipping insertion in model container [2024-12-02 11:28:32,034 INFO L184 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.12 11:28:32" (3/3) ... [2024-12-02 11:28:32,035 INFO L128 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c [2024-12-02 11:28:32,050 INFO L216 ceAbstractionStarter]: Automizer settings: Hoare:LoopHeads NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2024-12-02 11:28:32,052 INFO L151 ceAbstractionStarter]: Applying trace abstraction to ICFG btor2c-lazyMod.circular_pointer_top_w128_d16_e0.c that has 2 procedures, 20 locations, 1 initial locations, 1 loop locations, and 1 error locations. [2024-12-02 11:28:32,091 INFO L332 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2024-12-02 11:28:32,099 INFO L333 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mAutomataTypeConcurrency=PETRI_NET, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopHeads, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@a66fee3, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2024-12-02 11:28:32,099 INFO L334 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2024-12-02 11:28:32,103 INFO L276 IsEmpty]: Start isEmpty. Operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2024-12-02 11:28:32,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2024-12-02 11:28:32,107 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:28:32,107 INFO L218 NwaCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-12-02 11:28:32,108 INFO L396 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:28:32,111 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:28:32,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1676994902, now seen corresponding path program 1 times [2024-12-02 11:28:32,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 11:28:32,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2030438764] [2024-12-02 11:28:32,120 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:28:32,120 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:28:32,120 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:28:32,122 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:28:32,123 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2024-12-02 11:28:32,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:28:32,508 INFO L256 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 20 conjuncts are in the unsatisfiable core [2024-12-02 11:28:32,517 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:28:32,763 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2024-12-02 11:28:32,763 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:28:32,916 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 11:28:32,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2030438764] [2024-12-02 11:28:32,917 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2030438764] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:28:32,917 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [662356790] [2024-12-02 11:28:32,917 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:28:32,917 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 11:28:32,917 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 11:28:32,925 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 11:28:32,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (3)] Waiting until timeout for monitored process [2024-12-02 11:28:33,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:28:33,591 INFO L256 TraceCheckSpWp]: Trace formula consists of 352 conjuncts, 15 conjuncts are in the unsatisfiable core [2024-12-02 11:28:33,596 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:28:33,685 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2024-12-02 11:28:33,686 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2024-12-02 11:28:33,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [662356790] provided 1 perfect and 0 imperfect interpolant sequences [2024-12-02 11:28:33,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2024-12-02 11:28:33,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [7] total 7 [2024-12-02 11:28:33,688 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888700226] [2024-12-02 11:28:33,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-12-02 11:28:33,691 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2024-12-02 11:28:33,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 11:28:33,704 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-12-02 11:28:33,705 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:28:33,706 INFO L87 Difference]: Start difference. First operand has 20 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:28:33,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:28:33,856 INFO L93 Difference]: Finished difference Result 43 states and 63 transitions. [2024-12-02 11:28:33,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-12-02 11:28:33,858 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) Word has length 23 [2024-12-02 11:28:33,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:28:33,863 INFO L225 Difference]: With dead ends: 43 [2024-12-02 11:28:33,863 INFO L226 Difference]: Without dead ends: 25 [2024-12-02 11:28:33,865 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2024-12-02 11:28:33,867 INFO L435 NwaCegarLoop]: 14 mSDtfsCounter, 0 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2024-12-02 11:28:33,868 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 38 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2024-12-02 11:28:33,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2024-12-02 11:28:33,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2024-12-02 11:28:33,889 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 6 states have call successors, (6), 1 states have call predecessors, (6), 1 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2024-12-02 11:28:33,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 30 transitions. [2024-12-02 11:28:33,893 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 30 transitions. Word has length 23 [2024-12-02 11:28:33,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:28:33,895 INFO L471 AbstractCegarLoop]: Abstraction has 25 states and 30 transitions. [2024-12-02 11:28:33,895 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 1 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 1 states have call predecessors, (3), 1 states have call successors, (3) [2024-12-02 11:28:33,895 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 30 transitions. [2024-12-02 11:28:33,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2024-12-02 11:28:33,896 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:28:33,896 INFO L218 NwaCegarLoop]: trace histogram [6, 6, 6, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2024-12-02 11:28:33,904 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2024-12-02 11:28:34,101 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (3)] Ended with exit code 0 [2024-12-02 11:28:34,297 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 11:28:34,297 INFO L396 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:28:34,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:28:34,298 INFO L85 PathProgramCache]: Analyzing trace with hash -1294995197, now seen corresponding path program 1 times [2024-12-02 11:28:34,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 11:28:34,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1776056983] [2024-12-02 11:28:34,299 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:28:34,299 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:28:34,299 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:28:34,301 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:28:34,302 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2024-12-02 11:28:34,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:28:34,762 INFO L256 TraceCheckSpWp]: Trace formula consists of 656 conjuncts, 43 conjuncts are in the unsatisfiable core [2024-12-02 11:28:34,772 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:28:35,276 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-12-02 11:28:35,276 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:28:35,430 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 11:28:35,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1776056983] [2024-12-02 11:28:35,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1776056983] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:28:35,430 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1141678949] [2024-12-02 11:28:35,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-12-02 11:28:35,430 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 11:28:35,430 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 11:28:35,432 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 11:28:35,434 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (5)] Waiting until timeout for monitored process [2024-12-02 11:28:36,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-12-02 11:28:36,532 INFO L256 TraceCheckSpWp]: Trace formula consists of 656 conjuncts, 40 conjuncts are in the unsatisfiable core [2024-12-02 11:28:36,543 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:28:36,841 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2024-12-02 11:28:36,841 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:28:36,985 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1141678949] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:28:36,985 INFO L185 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2024-12-02 11:28:36,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 10 [2024-12-02 11:28:36,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080302972] [2024-12-02 11:28:36,985 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2024-12-02 11:28:36,986 INFO L548 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2024-12-02 11:28:36,986 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy FOX [2024-12-02 11:28:36,987 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2024-12-02 11:28:36,987 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2024-12-02 11:28:36,987 INFO L87 Difference]: Start difference. First operand 25 states and 30 transitions. Second operand has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:28:37,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-12-02 11:28:37,437 INFO L93 Difference]: Finished difference Result 36 states and 44 transitions. [2024-12-02 11:28:37,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2024-12-02 11:28:37,437 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) Word has length 44 [2024-12-02 11:28:37,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2024-12-02 11:28:37,438 INFO L225 Difference]: With dead ends: 36 [2024-12-02 11:28:37,438 INFO L226 Difference]: Without dead ends: 34 [2024-12-02 11:28:37,439 INFO L434 NwaCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 83 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=47, Invalid=193, Unknown=0, NotChecked=0, Total=240 [2024-12-02 11:28:37,439 INFO L435 NwaCegarLoop]: 12 mSDtfsCounter, 7 mSDsluCounter, 64 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 139 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2024-12-02 11:28:37,440 INFO L436 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 76 Invalid, 139 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2024-12-02 11:28:37,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2024-12-02 11:28:37,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2024-12-02 11:28:37,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 23 states have internal predecessors, (24), 9 states have call successors, (9), 1 states have call predecessors, (9), 1 states have return successors, (9), 9 states have call predecessors, (9), 9 states have call successors, (9) [2024-12-02 11:28:37,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 42 transitions. [2024-12-02 11:28:37,446 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 42 transitions. Word has length 44 [2024-12-02 11:28:37,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2024-12-02 11:28:37,446 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 42 transitions. [2024-12-02 11:28:37,447 INFO L472 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 9 states have (on average 2.4444444444444446) internal successors, (22), 10 states have internal predecessors, (22), 3 states have call successors, (6), 1 states have call predecessors, (6), 2 states have return successors, (6), 2 states have call predecessors, (6), 3 states have call successors, (6) [2024-12-02 11:28:37,447 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 42 transitions. [2024-12-02 11:28:37,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2024-12-02 11:28:37,448 INFO L210 NwaCegarLoop]: Found error trace [2024-12-02 11:28:37,448 INFO L218 NwaCegarLoop]: trace histogram [9, 9, 9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1] [2024-12-02 11:28:37,456 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (5)] Ended with exit code 0 [2024-12-02 11:28:37,656 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2024-12-02 11:28:37,848 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:28:37,849 INFO L396 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2024-12-02 11:28:37,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-12-02 11:28:37,849 INFO L85 PathProgramCache]: Analyzing trace with hash 1531864950, now seen corresponding path program 2 times [2024-12-02 11:28:37,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy FOX [2024-12-02 11:28:37,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1577824255] [2024-12-02 11:28:37,850 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 11:28:37,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2024-12-02 11:28:37,850 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 [2024-12-02 11:28:37,852 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2024-12-02 11:28:37,853 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2024-12-02 11:28:38,658 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 11:28:38,658 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 11:28:38,670 INFO L256 TraceCheckSpWp]: Trace formula consists of 960 conjuncts, 88 conjuncts are in the unsatisfiable core [2024-12-02 11:28:38,681 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:28:41,954 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 12 proven. 55 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-12-02 11:28:41,954 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:28:47,067 WARN L851 $PredicateComparison]: unable to prove that (let ((.cse1 ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_1~0#1|))) (let ((.cse6 (= ((_ extract 7 0) (bvand .cse1 (_ bv254 32))) (_ bv0 8))) (.cse8 (= (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |c_ULTIMATE.start_main_~mask_SORT_13~0#1|) ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_12~0#1|)))))))) (.cse11 (= (_ bv0 8) ((_ extract 7 0) (bvand .cse1 (_ bv255 32))))) (.cse14 (= (_ bv0 8) |c_ULTIMATE.start_main_~state_132~0#1|))) (let ((.cse3 (or (forall ((|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_151_arg_1~0#1_17| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_151_arg_1~0#1_17|)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|)))) .cse1)))) .cse14)) (.cse0 ((_ zero_extend 24) |c_ULTIMATE.start_main_~state_109~0#1|)) (.cse2 (not .cse14)) (.cse10 (not .cse11)) (.cse9 (not .cse8)) (.cse5 (not .cse6)) (.cse12 (= |c_ULTIMATE.start_main_~state_128~0#1| (bvand |c_ULTIMATE.start_main_~state_96~0#1| |c_ULTIMATE.start_main_~mask_SORT_3~0#1|)))) (and (or (and (or (forall ((|v_ULTIMATE.start_main_~var_115_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_126_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv1 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_115_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_1~0#1_17|) .cse0)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_126_arg_1~0#1_17|)))))))))))))))))) .cse1)))) .cse2) .cse3) (let ((.cse4 (forall ((|v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| (_ BitVec 128))) (not (= |c_ULTIMATE.start_main_~state_128~0#1| (bvand |v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| |c_ULTIMATE.start_main_~mask_SORT_3~0#1|))))) (.cse7 (not .cse12))) (and (or (and (or .cse4 .cse5) (or .cse6 .cse7)) .cse8) (or .cse9 (and (or .cse4 .cse10) (or .cse11 .cse7)))))) (or (and .cse3 (or (forall ((|v_ULTIMATE.start_main_~var_115_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_112_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_126_arg_1~0#1_17| (_ BitVec 8)) (|v_ULTIMATE.start_main_~var_155_arg_0~0#1_19| (_ BitVec 8))) (= (_ bv0 8) ((_ extract 7 0) (bvand .cse1 ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) ((_ zero_extend 24) ((_ extract 7 0) (bvor (_ bv0 32) ((_ zero_extend 24) ((_ extract 7 0) (bvnot ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_115_arg_1~0#1_17|) ((_ zero_extend 24) ((_ extract 7 0) (bvand ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_112_arg_1~0#1_17|) .cse0)))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_126_arg_1~0#1_17|))))))))))))))) ((_ zero_extend 24) |v_ULTIMATE.start_main_~var_155_arg_0~0#1_19|)))))))) .cse2)) (let ((.cse13 (forall ((|v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| (_ BitVec 128))) (= |c_ULTIMATE.start_main_~state_128~0#1| (bvand |v_ULTIMATE.start_main_~var_99_arg_2~0#1_15| |c_ULTIMATE.start_main_~mask_SORT_3~0#1|))))) (and (or (and (or .cse13 .cse10) (or .cse11 .cse12)) .cse9) (or (and (or .cse5 .cse13) (or .cse6 .cse12)) .cse8)))))))) is different from false [2024-12-02 11:28:47,523 INFO L136 FreeRefinementEngine]: Strategy FOX found an infeasible trace [2024-12-02 11:28:47,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1577824255] [2024-12-02 11:28:47,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1577824255] provided 0 perfect and 1 imperfect interpolant sequences [2024-12-02 11:28:47,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [285448892] [2024-12-02 11:28:47,523 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2024-12-02 11:28:47,523 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2024-12-02 11:28:47,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 [2024-12-02 11:28:47,525 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2024-12-02 11:28:47,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (7)] Waiting until timeout for monitored process [2024-12-02 11:28:49,170 INFO L229 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2024-12-02 11:28:49,170 INFO L230 tOrderPrioritization]: Conjunction of SSA is unsat [2024-12-02 11:28:49,208 INFO L256 TraceCheckSpWp]: Trace formula consists of 960 conjuncts, 87 conjuncts are in the unsatisfiable core [2024-12-02 11:28:49,221 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2024-12-02 11:29:05,896 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 12 proven. 55 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2024-12-02 11:29:05,896 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2024-12-02 11:29:12,879 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1)] Ended with exit code 101 [2024-12-02 11:29:12,880 WARN L249 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) stderr output: (error "out of memory") [2024-12-02 11:29:12,880 WARN L320 FreeRefinementEngine]: Global settings require throwing the following exception [2024-12-02 11:29:12,890 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2024-12-02 11:29:13,094 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt (7)] Ended with exit code 0 [2024-12-02 11:29:13,281 WARN L453 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 -smt2 -in SMTLIB2_COMPLIANT=true,7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/cvc4 --incremental --print-success --lang smt [2024-12-02 11:29:13,282 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:281) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.smtlibutils.ManagedScript.checkSat(ManagedScript.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.MonolithicImplicationChecker.checkImplication(MonolithicImplicationChecker.java:85) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.compare(PredicateUnifier.java:842) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier$PredicateComparison.(PredicateUnifier.java:786) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:374) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:323) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:555) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:416) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeBackwardSequence(IterativePredicateTransformer.java:395) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.predicates.IterativePredicateTransformer.computeWeakestPreconditionSequence(IterativePredicateTransformer.java:267) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:325) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:181) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:160) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getOrConstruct(IpTcStrategyModuleBase.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getInterpolantComputationStatus(IpTcStrategyModuleBase.java:77) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.tryExecuteInterpolantGenerator(AutomatonFreeRefinementEngine.java:267) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.generateProof(AutomatonFreeRefinementEngine.java:148) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.executeStrategy(AutomatonFreeRefinementEngine.java:137) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.(AutomatonFreeRefinementEngine.java:85) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:82) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:317) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:407) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.startCegar(AbstractCegarLoop.java:342) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.runCegar(AbstractCegarLoop.java:324) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:428) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:314) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseSequentialProgram(TraceAbstractionStarter.java:275) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:167) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:140) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:132) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:167) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:150) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:127) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:233) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:227) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:144) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:106) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:319) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1518) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:701) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:258) ... 46 more [2024-12-02 11:29:13,286 INFO L158 Benchmark]: Toolchain (without parser) took 42827.02ms. Allocated memory was 92.3MB in the beginning and 469.8MB in the end (delta: 377.5MB). Free memory was 68.3MB in the beginning and 178.9MB in the end (delta: -110.6MB). Peak memory consumption was 268.1MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,286 INFO L158 Benchmark]: CDTParser took 0.39ms. Allocated memory is still 83.9MB. Free memory is still 48.0MB. There was no memory consumed. Max. memory is 16.1GB. [2024-12-02 11:29:13,286 INFO L158 Benchmark]: CACSL2BoogieTranslator took 443.47ms. Allocated memory is still 92.3MB. Free memory was 68.1MB in the beginning and 63.3MB in the end (delta: 4.8MB). Peak memory consumption was 31.7MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,287 INFO L158 Benchmark]: Boogie Procedure Inliner took 66.86ms. Allocated memory is still 92.3MB. Free memory was 63.3MB in the beginning and 56.3MB in the end (delta: 7.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,287 INFO L158 Benchmark]: Boogie Preprocessor took 77.79ms. Allocated memory is still 92.3MB. Free memory was 56.3MB in the beginning and 48.9MB in the end (delta: 7.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,287 INFO L158 Benchmark]: RCFGBuilder took 975.38ms. Allocated memory was 92.3MB in the beginning and 142.6MB in the end (delta: 50.3MB). Free memory was 48.9MB in the beginning and 65.9MB in the end (delta: -17.0MB). Peak memory consumption was 35.5MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,288 INFO L158 Benchmark]: TraceAbstraction took 41257.67ms. Allocated memory was 142.6MB in the beginning and 469.8MB in the end (delta: 327.2MB). Free memory was 65.4MB in the beginning and 178.9MB in the end (delta: -113.5MB). Peak memory consumption was 214.7MB. Max. memory is 16.1GB. [2024-12-02 11:29:13,290 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.39ms. Allocated memory is still 83.9MB. Free memory is still 48.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 443.47ms. Allocated memory is still 92.3MB. Free memory was 68.1MB in the beginning and 63.3MB in the end (delta: 4.8MB). Peak memory consumption was 31.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 66.86ms. Allocated memory is still 92.3MB. Free memory was 63.3MB in the beginning and 56.3MB in the end (delta: 7.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 77.79ms. Allocated memory is still 92.3MB. Free memory was 56.3MB in the beginning and 48.9MB in the end (delta: 7.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 975.38ms. Allocated memory was 92.3MB in the beginning and 142.6MB in the end (delta: 50.3MB). Free memory was 48.9MB in the beginning and 65.9MB in the end (delta: -17.0MB). Peak memory consumption was 35.5MB. Max. memory is 16.1GB. * TraceAbstraction took 41257.67ms. Allocated memory was 142.6MB in the beginning and 469.8MB in the end (delta: 327.2MB). Free memory was 65.4MB in the beginning and 178.9MB in the end (delta: -113.5MB). Peak memory consumption was 214.7MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:262) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_475562d3-b4a1-4ad6-874a-1a307800b8e1/bin/uautomizer-verify-84ZbGMXZE1/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:4000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory")